System and method for deterministic and incremental physics-aware network-on-chip generation

Abstract

To provide a method and a non-transitory computer-readable medium for generating and synthesizing a network, such as a network-on-chip (NoC), that eliminate a condition that leads to a deadlock.SOLUTION: A method is for transforming an existing deadlock-free NoC configuration, and an existing deadlock-free NoC configuration includes a plurality of existing physical segments and a set of existing permissible turns between the segments. A set of the plurality of existing physical segments and existing turns form a set of a plurality of existing routes. The method creates a new NoC configuration by creating and / or composing at least a first new connection having a source and a destination into an existing deadlock-free network-on-chip configuration. The method makes the new network-on-chip configuration deadlock-free by creating a first new deadlock-free route from the source to the destination, and preserves the existing route.SELECTED DRAWING: None

Description

[Technical field]

[0001] Technical Field The present technology is in the field of system design, and more specifically, relates to topology generation of network-on-chip (NoC) descriptions. [Background technology]

[0002] background Multiprocessor systems are implemented in systems-on-chip (SoCs) that communicate through a network-on-chip (NoC). The SoC contains instances of master (initiator) intellectual property (IP) and slave (target) IP. Transactions in the form of packets are sent from the master to one or more slaves using industry standard protocols. A master connected to the NoC sends a request transaction to the slave, using an address to select the slave. The NoC decodes the address and transports the request from the master to the slave. The slave handles the transaction and sends a response transaction, which is transported back to the master by the NoC.

[0003] For a given set of performance requirements, such as connectivity and latency between sources and destinations, frequencies of various elements, maximum area available for NoC logic, minimum throughput between sources and destinations, and location on the floorplan of elements attached to the NoC, it is a complex task to create an optimal NoC that meets all the requirements with the minimum amount of logic and wires. It is typically the job of a chip engineer or chip designer to create this optimal NoC, which is a difficult and time-consuming task. In addition to this being a difficult challenge, the design of the NoC is revised every time one of the requirements changes, such as a change in the chip floorplan or a change in the expected performance. As a result, this task needs to be re-done frequently over the design time of the chip. This process is time-consuming and results in manufacturing delays. Therefore, what is needed is a system and method for efficiently generating a NoC from a set of constraints enumerated as requirements and a set of inputs. The system needs to produce a NoC with all its elements placed on the chip's floorplan.

[0004] NoC is an example for designing a scalable communication architecture for SoC. When using NoC in a design application, it is more desirable to eliminate conditions that result in deadlocks in the network. Currently, it is known to route messages through an array of data processing nodes to facilitate multiple paths directed to a destination without causing messages to be delayed due to routing deadlocks. An important aspect in designing an application-specific NoC is more desirable deadlock-free operation with minimal power and area overhead. There are two main types of deadlocks that are known to occur in NoCs. The first type of deadlock is routing-dependent deadlock. The second type of deadlock is message-dependent deadlock.

[0005] Current problems exist during NoC synthesis of new connections in an existing NoC because it is difficult to reuse an existing topology and the production costs associated with wiring are expensive. Another problem arises when performing environmental NoC synthesis occurs after a change in the specification. For example, when a new connection is added, previous results are overwritten. Therefore, a method is needed for designing NoCs that avoids both routing-dependent and message-dependent deadlocks and that is integrated with the topology synthesis phase of the NoC design flow. By considering the deadlock avoidance problem during topology synthesis, a more desirable NoC design can be achieved compared to traditional methods where the deadlock avoidance problem is managed separately. Furthermore, there is a need to add new connections without overwriting previous results. Summary of the Invention [Means for solving the problem]

[0006] overview According to various embodiments and aspects of the present invention, a system and method for generating a network on chip (NoC) using a set of constraints and a set of steps having inputs for creating or generating the NoC with all its elements. The elements of the NoC are placed on the floor plan of the chip. An advantage of the present invention is the simplification of the design process and the work of the chip engineer or designer. The NoC generation or synthesis method has an incremental design, whereby the NoC is generated or synthesized one connection at a time. In particular, a set of nodes of source-destination pairs and each new connection is synthesized by taking as input a set of existing connections. New components including but not limited to switches and / or links may be created when synthesizing a new connection to define a network route from a source to a destination. It is within the scope of the present invention, including but not limited to, that the destination is a list of components to be traversed. Furthermore, configuring the newly created components including but not limited to clocks and / or data widths is an important aspect in synthesizing a new connection.

[0007] In one embodiment, the set of existing connections may be empty, so that the NoC is synthesized from the beginning of the process with no existing connections.

[0008] The order in which connections are implemented affects the quality of the topology. In one embodiment, the order may be determined based on multiple mathematical optimization techniques and / or heuristics. For example, the order may be determined by the area of ​​the floorplan spanned by the connections. In another example, the order may be a latency-based communication policy configured to measure the latency of arrival of packets to a destination and implement more sensitive connections with higher priority. It is within the scope of the present invention that the synthesis order is an input to a method for deterministic, incremental, physics-aware NoC topology synthesis.

[0009] A system configured to automatically generate or synthesize a deadlock-free NoC from a specification including a floorplan, which is a physical layout of a chip; technical parameters, including but not limited to wire delay and / or logic density; floorplan areas, including but not limited to module and / or clock restrictions; clock domain crossings (CDCs), which are traversals of signals in a synchronous digital circuit from a first clock domain to a second clock domain; performance requirements; and components having configurations and positions on the floorplan, connectivity requirements between the first component and the second component, and communication policies between the first component and the second component.

[0010] A method for converting an existing deadlock-free network-on-chip (NoC) configuration, the existing deadlock-free network-on-chip configuration including a plurality of existing physical segments and a set of existing turns that are allowable between the segments, the plurality of existing physical segments and the set of existing turns forming a plurality of existing routes. The method includes generating a new NoC configuration by generating and / or merging at least a first new connection into the existing deadlock-free network-on-chip configuration, the first new connection having a source and a destination, the generating creates a first new deadlock-free route from the source to the destination, such that the new network-on-chip configuration is deadlock-free, and the generating preserves the existing route.

[0011] The generating includes, for each existing route, translating the route into segments and turns; identifying one or more new connections to be combined, each of the multiple new connections having an undefined route, a source, and a destination associated therewith, the one or more new connections being identified along with a combination order; and, for each of the one or more new connections and according to the sorting, identifying a plurality of possible routes from the source to the destination for the new connection.

[0012] The possible routes include one or more of: a new incoming segment connecting the source to an existing deadlock-free NoC configuration, a new outgoing segment connecting the existing deadlock-free network-on-chip configuration to the destination, one or more new internal segments connecting existing segments of the existing deadlock-free network-on-chip configuration, whereby the one or more new internal segments connect the source to the destination, where it is not considered whether the new internal segments create a circular dependency between the segments, thereby causing a deadlock, and only the existing segments.

[0013] filtering a plurality of possible routes based on one or more criteria, the one or more criteria including a communication policy criterion based on an acceptable latency of a route from a source to a destination of the new connection and any of a plurality of user-defined criteria; selecting one of the plurality of possible routes for synthesis; and / or synthesizing the selected possible route into an existing deadlock-free network-on-chip configuration.

[0014] According to one or more embodiments of the present invention, the first new deadlock-free root includes at least one of an existing physical segment and a new physical segment.

[0015] According to one or more embodiments of the invention, generating a first new deadlock-free route from a source to a destination preserves all existing routes.

[0016] In accordance with one or more embodiments of the present invention, the generation of new deadlock-free routes is repeated incrementally.

[0017] According to one or more embodiments of the present invention, identifying a composition order includes sorting the one or more new connections according to a heuristic.

[0018] In accordance with one or more embodiments of the present invention, at least some of the existing segments are physically immutable.

[0019] In accordance with one or more embodiments of the present invention, the endpoints of at least some of the existing segments are switches. Switches are physically immutable.

[0020] In accordance with one or more embodiments of the present invention, any component is logically modifiable, causing at least one existing component to reconfigure in response to the new resulting topology.

[0021] According to one or more embodiments of the present invention, selecting one of a plurality of possible routes for synthesis includes selecting a possible route that maximizes use of an existing deadlock-free network-on-chip configuration, where the existing segments are made physically unalterable except for the ingress and egress segments, the switches are made physically unalterable, and at least one network element is made logically unalterable.

[0022] According to one or more embodiments of the present invention, selecting one of a plurality of possible routes for synthesis includes selecting a possible route that minimizes a latency of the route.

[0023] According to one or more embodiments of the present invention, selecting one of multiple possible routes for synthesis includes selecting a possible route that maximizes use of existing deadlock-free network-on-chip configurations, where existing segments are not made physically unchangeable, switches are enabled to have new connections, and existing network elements are made logically unchangeable, which includes keeping clock frequencies and other attributes unchanged.

[0024] According to one or more embodiments of the invention, selecting one of multiple possible routes for synthesis includes selecting while existing segments are not physically immutable, switches are allowed to have new connections, and existing network elements are reconfigurable.

[0025] A method for incremental synthesis and transformation of deadlock-free network-on-chip topologies includes receiving an input that is a network topology, the network topology being translated into an existing segment, reusing the existing segment in a new route, the existing segment being formed by a path between a first node and a second node, forming a split segment, recursively splitting the existing segment at any point along the path between the first node and the second node, and in response to the split, synthesizing a new route by adding a new segment and a new turn to the split segment, and routing packets from the turns of the existing segment to the new segment to generate a deadlock-free network-on-chip topology, thereby avoiding deadlocks in the network.

[0026] According to one or more embodiments of the present invention, identifying a composition order includes sorting the one or more new connections according to a heuristic.

[0027] In accordance with one or more embodiments of the present invention, at least some of the existing segments are physically immutable.

[0028] In accordance with one or more embodiments of the present invention, the endpoints of at least some of the existing segments are switches. Switches are physically immutable.

[0029] In accordance with one or more embodiments of the present invention, any component is logically modifiable, causing at least one existing component to reconfigure in response to the new resulting topology.

[0030] A non-transitory computer readable medium for storing code, which when executed by one or more processors, causes the processor to receive an input topology of a network-on-chip (NoC) to determine a source-destination pair and at least one existing connection to be selected for composition, transfer the source-destination pair to a pair of segments, transfer the at least one existing connection to the pair of existing segments, determine whether the NoC is deadlock-free, and in response to determining, if the NoC is deadlock-free, extract a pair of segments that do not have a defined route and sort them using a heuristic, input the pair of segments and the pair of existing segments to a configuration searcher, wherein the configuration searcher selects communication ports from the pair of segments and sorts the pair of existing segments. and determining a configuration for routing from a source to a destination of the source-destination pair using the communication policy, the communication policy being configured to receive user-defined parameters associated with the source-destination pair, the communication policy being configured to communicate with a configuration filtering module, the configuration filtering module being configured to output eligible configurations, causing the configuration selection module to select a final configuration to be implemented to connect the source-destination pair, causing a pair of existing segments to be connected to the pair of segments to be split at a point indicated by the final configuration, causing a new segment to be created as indicated by the final configuration, causing a corresponding turn to be activated that connects the pair of existing segments with the pair of segments, and causing a route from the source to the destination of the source-destination pair to be calculated. [Brief description of the drawings]

[0031] [Figure 1A] 1 is a logical diagram of a network-on-chip (NoC) including various elements that create the NoC. [Figure 1B] FIG. 1 shows a NoC in which elements are arranged on a network floorplan. [Figure 2A] FIG. 2 illustrates a method for generating an NoC description based on a set of constraints according to various aspects and embodiments of the present invention. [Figure 2B]FIG. 2 is a block diagram of a NoC synthesis tool in accordance with various aspects and embodiments of the present invention. [Diagram 3] FIG. 2 is a graphical representation of a chip floorplan with locations of occlusion areas and interfaces with a NoC in accordance with various aspects and embodiments of the present invention. [Figure 4] FIG. 2 illustrates a connectivity table for a NoC according to various aspects and embodiments of the present invention. [Diagram 5] FIG. 1 illustrates a scenario table with throughput definitions for read and write transactions in accordance with various aspects and embodiments of the present invention. [Figure 6] FIG. 1 illustrates the creation of a network with three traffic classes in accordance with various aspects and embodiments of the present invention. [Figure 7] 7 illustrates a decomposition of the network of FIG. 6 using mergers and splitters in accordance with various aspects and embodiments of the present invention. [Figure 8] FIG. 7 illustrates a roadmap in a floorplan of one master of the network of FIG. 6 in accordance with various aspects and embodiments of the present invention. [Figure 9] FIG. 7 illustrates a roadmap in a floorplan of one slave of the network of FIG. 6 in accordance with various aspects and embodiments of the present invention. [Figure 10] FIG. 9 illustrates the decomposition of a main node splitter into a cascade of splitters physically distributed along the roadmap of FIG. 8 in accordance with various aspects and embodiments of the present invention. [Figure 11] FIG. 10 illustrates a decomposition of a main node merger into a cascade of physically distributed mergers along the roadmap of FIG. 9 in accordance with various aspects and embodiments of the present invention. [Figure 12] FIG. 2 illustrates an example of two closely merged nodes in accordance with various aspects and embodiments of the present invention. [Figure 13] FIG. 2 illustrates a NoC topology on a floorplan having a deadlock-free network of segments and turns in accordance with various aspects and embodiments of the present invention. [Figure 14A] FIG. 2 illustrates a NoC topology on a floorplan having divided segments "S"-"D" in accordance with various aspects and embodiments of the present invention. [Figure 14B] FIG. 1 illustrates a NoC topology on a floorplan with a partitioned segment "S" to "D" updated to use two new sub-segments "S" to "N" and "N" to "D" in accordance with various aspects and embodiments of the present invention. [Figure 14C] FIG. 2 illustrates a NoC topology on a floorplan having sub-segments "N" and "S" that are merged into a split segment in accordance with various aspects and embodiments of the present invention. [Figure 14D] FIG. 2 illustrates a NoC topology on a floorplan having a sub-segment represented by a channel between node "N" and node "S" that is branched into a split segment in accordance with various aspects and embodiments of the present invention. [Figure 15] 1 is a flowchart illustrating a method for single-connection NoC topology synthesis processing in accordance with various aspects and embodiments of the present invention. [Figure 16A] 1 illustrates a NoC topology on a floorplan having a requirement to connect node "S" to node "D" in accordance with various aspects and embodiments of the present invention. [Figure 16B] A diagram illustrating a NoC topology on a floorplan with incremental synthesis results of a routing configuration from "S" to "D" having a new incoming segment, a new internal segment, and an existing outgoing segment in accordance with various aspects and embodiments of the present invention. [Figure 17A] FIG. 17 illustrates a NoC topology on a floorplan with a communication policy 1700 aimed at optimizing wire length with best effort performance in accordance with various aspects and embodiments of the present invention. [Figure 17B] FIG. 17 illustrates a NoC topology on a floorplan having a communication policy 1710 for low latency communication in accordance with various aspects and embodiments of the present invention. [Figure 18A]FIG. 18 illustrates an incremental compositing mode 1800 for initial setup of a segment connected from node “S” to node “D” in accordance with various aspects and embodiments of the present invention. [Figure 18B] FIG. 18 illustrates an incremental compositing mode 1810 for physical immutability of segments with minimally changed parameters in accordance with various aspects and embodiments of the present invention. [Figure 18C] FIG. 18 illustrates an incremental compositing mode 1820 for logical immutability of segments with topology optimizing and configuration preserving parameters in accordance with various aspects and embodiments of the present invention. [Figure 18D] FIG. 18 illustrates an incremental synthesis mode 1830 for mutability of network elements with parameters to optimize topology and adapt configuration in accordance with various aspects and embodiments of the present invention. [Figure 19] FIG. 1 illustrates a process of NoC synthesis based on a mesh custom sub-network description according to various aspects and embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] Detailed Description In the following, various examples of the present technology are described, illustrating various aspects and embodiments of the present invention. In general, the examples can use the described aspects in any combination. All statements herein that recite principles, aspects, and embodiments, as well as specific examples thereof, are intended to encompass both their structural and functional equivalents. Moreover, such equivalents are intended to include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

[0033] It should be noted that, as used herein, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Throughout this specification, reference to "one aspect," "aspect," "particular aspect," "various aspects," or similar language means that the particular aspect, feature, structure, or characteristic described in connection with any embodiment is included in at least one embodiment of the invention.

[0034] Throughout this specification, the appearance of the phrases "according to one or more embodiments," "in one embodiment," "in at least one embodiment," "in an embodiment," "in a particular embodiment," and similar language may, but do not necessarily, all refer to the same or similar embodiments. Furthermore, the aspects and embodiments of the invention described herein are merely exemplary and should not be construed as limiting the scope or spirit of the invention as understood by those of ordinary skill in the art. The disclosed invention may be effectively made or used in any embodiment, including any novel aspects described herein. All statements herein reciting principles, aspects, and embodiments of the invention are intended to encompass both structural and functional equivalents thereof. Such equivalents are intended to include both currently known equivalents and equivalents developed in the future.

[0035] As used herein, "master" and "initiator" refer to similar intellectual property (IP) modules or units, and these terms are used interchangeably within the scope and embodiments of the present invention. As used herein, "slave" and "target" refer to similar IP modules or units, and these terms are used interchangeably within the scope and embodiments of the present invention. As used herein, a transaction may be a request transaction or a response transaction. Examples of request transactions include write requests and read requests.

[0036] As used herein, a node is defined as a distribution point and / or a communication endpoint that can create, receive, and / or transmit information over a communication path or channel. A node may refer to any one of a switch, a splitter, a merger, a buffer, and an adapter. As used herein, splitters and mergers are switches, but not all switches are splitters or mergers. As used herein, in accordance with various aspects and embodiments of the invention, the term "splitter" refers to a switch having a single ingress port and multiple egress ports. As used herein, in accordance with various aspects and embodiments of the invention, the term "merger" refers to a switch having a single egress port and multiple ingress ports.

[0037] 1A, a network-on-chip (NoC) 100 is shown according to various aspects and embodiments of the present invention. The NoC 100 is an example of a network. According to various aspects and embodiments of the present invention, the network includes a set of nodes and a set of edges, each of which has a model and can be used at a synthesis center to perform and implement transformations on the network and converge to the best solution that meets the specified requirements. The NoC 100 includes nodes and endpoints and uses assembled basic network functions such as network interface units (NIUs) 102, 104, 106, 108, 110, 112, 130, 132, and 134, nodes / switches 114, 116, 118, 120, and 122, adapters such as adapter 126, and buffers such as buffer 124. The NoC basic network functions use an internal transport protocol specific to the NoC 100 to communicate with each other, typically based on the transmission of packets. The NIU translates protocols used by attached system-on-chip (SoC) units (not shown) to the transport protocols used within the NoC 100. The switches route traffic flows between sources and destinations. Buffers 124 are used to store packets to insert pipeline elements to span long distances or to handle rate adaptation between high speed transmitters and low speed receivers or vice versa. Adapters 126 handle various translations between data widths, clocks, and power domains.

[0038] 1B, NoC 150 is shown having various elements such as NIUs, switches, and occlusion areas in a floorplan. NoC 150 includes various connectivity elements through various switches. According to one aspect of the invention, a set of constraints is used as input to a tool, which will be described in more detail below. According to some aspects of the invention, the tool executes a set of sub-steps to produce a description (synthesis) of the resulting NoC, such as NoC 150, with its configured elements and the location of each element on the floorplan. The generated description is used to actually implement the NoC hardware, using the physical information produced to provide guidance to the back-end implementation flow.

[0039] 2A, in accordance with some aspects of the present invention, a set of constraints (210, 212, 214, 216, and scenarios) are provided to a synthesis tool 220. In accordance with some embodiments and aspects of the present invention, the capabilities and capabilities of the tool 220 may include third-party ASIC implementation tools such as logic synthesis, place and route back-end tools. A designer or user constructs a set of constraints that are provided to the tool 220. The constraints are captured in a machine-readable format, such as a computer file that uses a defined format to capture information that is understood and processed by the tool. In accordance with one aspect of the present invention, the format is XML. In accordance with another aspect of the present invention, the format is JSON. The scope of the present invention is not limited by the particular format used.

[0040] 2B, the tool reads a file containing a description of the constraints and executes a synthesis process. According to some aspects of the invention, the synthesis process is subdivided into multiple steps. A sequencer 250 is responsible for executing each step of the process. According to some aspects of the invention, a set of steps are executed by the sequencer 250 of the tool 220 in light of the constraints indicated by the user / designer. The scope of the invention is not limited by the number and type of steps that the sequencer 250 can call and execute.

[0041] Referring again to FIG. 2A in conjunction with FIG. 2B, according to various aspects of the present invention, a network designer provides and defines a set of constraints, such as constraints 210, 212, 214, and 216. The sequencer 250 receives various inputs including: an input 251 including a global unified roadmap with connectivity between initiators and targets, including roadmap creation and information between each master and slave; an input 252 including traffic classification and main switch creation; an input 254 including main switch decomposition into mergers and splitters; an input 258 including information regarding physical distribution of splitters and mergers in the roadmap; an input 259 including information regarding edge clustering; and an input 260 including information regarding performance-aware node clustering. According to one aspect of the present invention, the sequencer 250 also receives an input 262 including information regarding optimization and network restructuring. According to one aspect of the present invention, the sequencer 250 receives an input 264 including information regarding routing and legalization. According to various aspects and embodiments of the present invention, the sequencer 250 uses all the inputs 251-264 to generate the network. According to various aspects and embodiments of the invention, sequencer 250 uses a combination of inputs 251-264 to generate a network.

[0042] According to various aspects of the invention, the input 251 includes input for a global integration roadmap. The global integration roadmap includes an integration model that captures a global physical view of the connectivity of the free space of the floorplan as well as the connectivity between initiators and targets. The global integration roadmap is modeled by a graph of physical nodes and standard segments that are used to position the nodes (splitters, mergers, switches, adapters) of the network being built. The global integration roadmap is used to anchor the computation. According to various aspects of the invention, the global integration roadmap is persistent, meaning that it is data that the system exports and re-consumes in incremental synthesis and subsequent runs.

[0043] According to some aspects of the invention, the input 259 includes information regarding edge clustering. Edge clustering aims to minimize resources and improve performance objectives through appropriate algorithms and techniques. According to some aspects of the invention, the edge clustering is applied in conjunction and cooperation with the node clustering of the input 260. Edge clustering and node clustering can be used in combination by mixing, by applying in parallel, or by applying in sequence. The advantage and goal is to expand the scope of synthesis and span a larger solution space for the network.

[0044] According to various aspects of the invention, the input 262 includes information regarding the restructuring. The restructuring includes various transformations and capabilities. According to some aspects of the invention, the transformation is logical in that there is a change in the structure of the network. According to some aspects of the invention, the transformation is physical because there is a physical change in the network, such as moving a node to a new location. Other examples of restructuring include subdividing a node into smaller nodes, changing parents between nodes, duplication of network subparts to avoid deadlocks and address congestion, and physically rerouting links to avoid congested areas or to meet timing constraints.

[0045] 3, a floorplan 300 of a chip on which a NoC is implemented is shown, having locations of various initiator and target interfaces, in accordance with various aspects of the present invention. Physical constraints 210 provide physical information for the design, including the size of the chip on which the NoC is implemented, various occlusion areas on the floorplan, which are rectangles representing areas of the chip on which NoC logic cannot be present or placed, free space, which is the area of ​​the chip on which NoC logic can be present and is defined by areas not covered by occlusion, and locations of interfaces between the SoC units and the NoC, which are locations of initiator and target interfaces, such as the NIU.

[0046] According to various aspects of the invention, other constraints may be provided, including the extension of clock domains, as well as power domains 212. Domains 212 include areas of the chip where logic belonging to a particular domain may be placed.

[0047] According to various aspects of the present invention, functionality of a logic library used to implement a NoC is provided, including the size of a reference logic gate and the time it takes a signal to cover a distance of 1 mm.

[0048] Referring again to FIG. 2A, in accordance with various aspects of the present invention, an SoC includes multiple clock domains and multiple power domains. A clock domain is defined by all logic fed by a given clock input. The clock input is characterized by its most critical parameter, the frequency of the clock. A power domain is defined by all logic powered from the same power supply. In accordance with various aspects of the present invention, the power supplies are gated, thus power domains can be turned on or off or isolated from other power domains. Thus, the designer provides a set of clock and power domain constraints 212 as part of the initial design.

[0049] According to various aspects of the invention, initiators and targets are communicatively connected to the NoC. Initiators are units that send requests, typically read and write commands. Targets are units that act on or respond to requests, typically read and write commands. Each initiator is attached or connected to the NoC through an NIU. An NIU attached to an initiator is called an Initiator Network Interface Unit (INIU). Furthermore, each target is attached to the NoC through an NIU. An NIU attached to a target is called a Target Network Interface Unit (TNIU). The main function of the NoC is to transport each request from an initiator to the desired destination target, and if the request asks for or requires a response, the NoC transports each target's response to the corresponding requesting initiator. Initiators and targets have many different parameters that characterize them. According to various aspects of the present invention, for each initiator and target, the clock domain and power domain to which they belong are defined. The width of the data bus they use to transmit and receive write and read payloads is several bits. According to various aspects of the present invention, the width of the data bus for the connection (communication path to and from the target) used to transmit the write request and receive the write response is also defined. Furthermore, the clock and power domain definitions are references to the aforementioned clock and power domains present in the SoC, as described herein.

[0050] With continued reference to Figures 2A and 2B, and also with reference to Figure 4, a connectivity table 400 is shown. According to various aspects of the present invention, the table 400 allows traffic to be defined by classification. The tool allows the use of a traffic class label for each connection between an initiator and a target. As shown in the table 400, there are three traffic classes: L1, L2, and L3. The traffic class labels are any label selected by the user or designer. Any number of labels can be defined, and the scope of the present invention is not limited by the number of labels. Each label represents an independent network resource need. Each label is given a separate sub-network by the present invention, which can be physically distinct or use a virtual network if supported by the underlying NoC technology.

[0051] According to various aspects of the invention, an initiator does not need to be able to send requests to every target or slave connected to the NoC. The exact definition of targets that can receive requests from an initiator is outlined or described in a connectivity table, such as table 400. The connectivity and traffic class labeling information can be represented as a matrix. Each master has a row and each slave has a column. If a master must be able to send traffic to a slave, a traffic class label must be present at the intersection between the master row and the slave column. If no label is present at the intersection, the tool does not require connectivity between that master and that slave. For example, master 1 (M1) is in communication with slave 1 (S1) using a defined label 1 (L1), but M1 does not communicate with S2, and therefore there is no label at the intersection of M1 and S2. According to various aspects of the invention, the actual format used to represent connectivity can vary, so long as each pair of master-slave combinations has a precise definition of its traffic class, or no classification label in the absence of a connection.

[0052] Referring now to FIG. 5, a table 500 is shown according to various aspects of the present invention, including various scenarios of read (RD) and write (WR) transactions (as shown in FIG. 2A). The table 500 includes information that defines various throughput rates provided to the tool. The scenarios define the expected performance in terms of throughput of data between the master and the slave. Each scenario describes the expected required read bandwidth and the expected required write bandwidth between each initiator and each target. The throughput is defined in Bytes per second (B / s). A typical SoC has multiple operating modes. As an example, an SoC for a smartphone may have a gaming operating mode, an audio call operating mode, an idle operating mode, etc. These define scenarios that depend on different throughput rates. Thus, the set of scenarios represents the different operating modes that the SoC supports, and correspondingly, the expected NoC minimum performance in terms of throughput between the master and the slave.

[0053] A scenario can be represented as two matrices, one defining the read throughput and one defining the write throughput. According to various aspects of the invention, the read throughput requirement is used to size the response network that handles data returning from the slave to the master. The write throughput requirement is used to size the request network that is data moving from the master to the slave, according to various aspects of the invention. An example of throughput requirements for various scenarios, according to various aspects of the invention, is shown in table 500. The actual format used to represent the scenarios can vary, so long as each (master, slave) pair has a precise definition of the minimum throughput required for reads and writes. In table 500, a read transaction from M1 to S1 has a minimum performance throughput of 100MB / s. In table 500, a write transaction from M1 to S1 has a minimum throughput of 50MB / s.

[0054] According to some aspects of the invention, a tool scenario is not defined, where the tool optimizes the NoC synthesis process for physical cost, such as lowest gate cost and / or lowest wire cost.

[0055] 6 in conjunction with FIG 2B, an initial network 600 is created in accordance with various aspects of the present invention. Network 600 implements a connectivity matrix having the following defined parameters or components:

[0056] One Network Interface Unit per master, One Network Interface Unit per slave, One switch is created for each defined traffic class, called the main switch for the class. After each initiator / master NIU, there is one switch that splits the traffic to the different main switches that this master needs to reach, One switch in front of each target / slave NIU that merges traffic from the different main switches sending traffic to that target The data width of each switch and the clock domain it belongs to are calculated using the data width of each attached interface and their clock domains as input to the tool. According to various aspects of the invention, each step of transforming a network that is part of a NoC also performs a calculation of the data width and clock domain of the newly created network element.

[0057] 7 and 2B, the network 600 of FIG. 6 is shown and a tool process transforms the network 600 according to various aspects of the invention. The sequencer 250 has an input 254 representing a main switch decomposition into mergers and splitters. The tool decomposes each main switch of the network 600 into an equivalent implementation with splitters and mergers. According to various aspects of the invention, some switches have a single ingress port and multiple egress ports. According to various aspects of the invention, some switches have multiple ingress ports and a single egress port. Each main switch ingress port is connected to a splitter and each main switch egress port is connected to a merger. To the main switches, splitters and mergers are connected together according to the connectivity table.

[0058] 8, a floorplan 800 according to various aspects of the present invention is shown. The sequencer 250 has an input 256 representing the creation of a roadmap between each master and slave. The floorplan 800 includes physical paths 802 calculated between a master interface (M0) on the floorplan and each of its connected slaves, such as slave S0, slave S1, slave S2, and slave S3. The path 802 is called the splitter roadmap of master M0, and although not shown, all masters have splitter roadmaps. The tool uses any suitable algorithm to find paths between a source point and multiple destination points, including algorithms that minimize the length of the paths.

[0059] 9, the floor plan 800 is shown with calculated physical paths 902 between the slave interfaces of slave S0 and each of its connected masters on the floor plan. The paths 902 are the merger roadmap of slave S0. As is evident, every slave has a merger roadmap. The tool uses any suitable algorithm to find paths between multiple source and destination points, including algorithms that minimize the length of the paths. In accordance with various aspects of the present invention, the tool transforms the network to maintain its functionality and add location information to the network elements.

[0060] 10, a floorplan 800 is shown with a path 1002 in accordance with various aspects of the present invention. The sequencer 250 has an input 258 that provides the physical distribution of splitters and mergers on the roadmap. Using this tool, each switch is decomposed into mergers and splitters. Using the tool, each splitter in a main switch is further decomposed into a cascade of splitters, and each splitter in the cascade is placed at a branch point in the splitter roadmap of its attached master. A branch point in the roadmap is defined by the fact that a path is split into two or more branches.

[0061] 11, a floor plan 800 is shown with a path 1102 according to various aspects of the invention. Using a tool, each switch of each merger in the main switch is further decomposed into a cascade of mergers, with each merger of the cascade being placed at a branch point of the attached slave's merger roadmap. A branch point of the roadmap is defined by the fact that the path is split into two or more branches. The process of decomposing a splitter within a cascade of splitters maintains the original splitter functionality since the number of inputs to the cascade is still one and the number of outputs of the cascade is identical to the number of outputs of the original splitter. The process of decomposing a merger within a cascade of mergers maintains the original merger functionality since the number of outputs of the cascade is still one and the number of inputs to the cascade is identical to the number of inputs to the original merger. According to various aspects of the invention, the effect of the process is to obtain a set of basic switches, represented by mergers and splitters, physically located near where the actual connections between the switches are required.

[0062] According to various aspects of the invention, the tool transforms the network to reduce the number of wires used between achievable switches while maintaining the performance defined in the scenario, which is a set of required minimum throughputs between masters and slaves. According to various aspects of the invention, switches are clustered for performance-aware switching, and mergers and splitters distributed over the roadmap are treated similarly to normal switches.

[0063] According to one aspect of the invention, the tool uses an iterative process to merge switches under conditions where performance is still met until no further switch merging can occur. The tool uses a process that is described as follows.

[0064] 1) While further switch fusion is not possible, do the following: a) Select a candidate switch to merge with one of its neighbors. The selection process ensures that all switches in the network are eventually candidates.

[0065] b) Once a candidate is selected, search for neighbors to fuse. The neighbor criterion is based on the evaluation of a cost function. The cost function shall return the switch that is "best suited" to fuse with the candidate. The definition of "best suited" is implementation dependent, but the cost function shall be such that the potential fusion of two switches maximizes the gain in terms of at least one metric, including wire length, logic area, power, and performance.

[0066] c) If a merge occurs, test whether the performance scenarios still all meet the minimum throughput requirements. If not, these two switches cannot be merged. The process performed by the tool explores another neighbor until no more neighbors can be found, in which case all switches are left as they are, or until one neighbor is found that can be merged with the candidate without violating the minimum throughput requirements of all scenarios, in which case the network is modified by merging the candidate switch with its neighbor.

[0067] According to various aspects of the invention, a process can prevent a switch from growing beyond a certain size (maximum ingress ports, maximum egress ports). If the combined switch exceeds a set threshold, a merge is prevented.

[0068] Now referring to FIG. 12, a candidate switch SW3 is shown next to switch SW4 for a merger according to various aspects of the present invention. A sequencer 250 has an input 260 that provides performance aware switching clustering. The tool executes a process to merge two switches. When the switches are merged, the wires that were coming out of different switches are simplified to one wire from each connected switch to the combined switch. According to various aspects of the present invention, switches SW3 and SW4 are merged. The connections between SW1, SW4 and SW3 are combined and replaced with a single connection between SW1 and SW3_4. Thus, long connections between distant switches are eliminated and reduced to a minimum, while connections between close switches are eliminated and made inside the switches themselves.

[0069] 2B, inputs 262 to sequencer 250 include various optimizations that may be performed to further reduce the number of wires used by the network, the area of ​​the network elements, and the power consumed by the network elements. Examples of such optimizations include detecting links that may be removed because they are not being used or because their traffic may be rerouted, reducing the width of links if they are wider than required in the scenario, and performing wire length optimization by finding the optimal placement of all switch elements that minimizes the total wire length of the network, which is the sum of the products of the distance spanned by each connection between network elements and the width of that connection.

[0070] 2B, inputs 264 to sequencer 250 include creating a legal NoC by modifying the location of network elements such that they fit into the allocated free space, do not overlap, and are within the limitations of the corresponding clock and power domains. According to various aspects of the invention, the area occupied on the die by each network element is calculated using information provided regarding the capabilities of the technology, such as the area of ​​a reference logic gate. Each element is then tested for the correctness of its placement (there is enough free space for the element and other elements do not overlap). If the test fails, the element is moved until a suitable location is found that passes the test.

[0071] format 13, a floorplan 1300 illustrates a deadlock-free NoC that can be represented in terms of multiple segments and turns. A segment represents a directed channel between two components, e.g., “A” 1311 and “B” 1301, “B” 1301 and “C” 1302, “C” 1302 and “D” 1303, and / or “D” 1303 and “A” 1311. A first segment 1304 holds the physical path in the floor plan between "A" 1311 and "B" 1301, a second segment 1305 holds the physical path in the floor plan between "B" 1301 and "C" 1302, a third segment 1306 holds the physical path in the floor plan between "C" 1302 and "D" 1303, and a fourth segment 1307 holds the physical path in the floor plan between "D" 1303 and "A" 1311, which is represented by physical coordinates (x i ,y i ). It is within the scope of the present invention for a segment to have one or more associated cost metrics that can be utilized during synthesis and / or generation to track the cost of a particular routine.

[0072] A turn, which is a pair of segments, may be utilized to avoid deadlocks in the network. Considering the permissible turns 1308, 1309, and 1310, the network remains deadlock-free as long as there are no cycles between the segments. According to other aspects or embodiments of the invention, cycles may exist between nodes. Turns have dependencies between segments, which is the basic mechanism that ensures that the network is deadlock-free. It is within the scope of the invention that cycles exist between nodes in order to reuse wires without causing deadlocks, so that only the channels necessary to prevent node cycles are allocated. As a result, this eliminates unnecessary channels and reduces the associated wire costs associated therewith.

[0073] Referring again to FIG. 13, the presence of a first turn 1308 from a first segment 1304 to a second segment 1305 indicates that a packet may be routed from the first segment 1304 to the second segment 1305. The presence of a second turn 1309 from the second segment 1305 to a third segment 1306 indicates that a packet may be routed from the second segment 1305 to the third segment 1306. The presence of a third turn 1310 from the third segment 1306 to a fourth segment 1307 indicates that a packet may be routed from the third segment 1306 to the fourth segment 1307. With respect to segment division, a segment "S1"-"S2" may be divided into a plurality of segments at any point (x i ,y i ), which can result in two new segments. Since there is no turn (D,A) that approaches (A,B), this network is deadlock-free.

[0074] 14A-14D, one embodiment of segment splitting on a NoC 1400 is shown. A segment 1403 (FIG. 14A) is defined by node "A" 1401 through node "B" 1402. The segment 1403 may be split 1404 (FIG. 14A) at any point (xi, yi) of its physical route into a new first segment 1409A (FIG. 14B-14D) and a new second segment 1409B (FIG. 14B-14D). FIGS. 14B-14D best show the result of this split 1404 (FIG. 14A) where a newly created node "S" 1408 (FIG. 14B-14D) is formed. A first turn 1405, a second turn 1406 (FIG. 14B-14D), and a third turn 1407 are shown.

[0075] FIG. 14B shows a segment split of a NoC topology with split segment "A" 1401-"B" 1402 updated to use two new subsegments "A" 1401-"S" 1408 and "S" 1408 "B" 1402. The newly created node "S" 1408 is a new switch in the NoC. The set of turns that contain the split segment is updated to use the two new subsegments. A new turn 1406 is added while maintaining turn 1407.

[0076] Because the split segment resulted in a subsegment with a variable route, the split segment is no longer considered "as is". This recursive representation is essential for incrementality, as it ensures that a segment that is part of an existing route and may need to be split can still be recovered as a set of subsegments when reconstructing the existing route. Splitting a segment allows it to be connected to a new segment, which results in a new set of turns.

[0077] FIG. 14C shows a new segment 1411 represented by a channel between node “N” 1410 and node “S” 1408 that is merged into the split segment resulting in a new turn 1412 .

[0078] 14D shows that the new segment 1413, represented by the channel between node "N" 1410 and node "S" 1408, is branched into a split segment resulting in a new turn 1414. The added node "N" 1410 may include, but is not limited to, an IP block and / or an initiator.

[0079] process According to one aspect and embodiment of the present invention, the system executes a generation and synthesis process, where all existing network routes are translated into segments and turns. In one embodiment, the entire NoC is described as a set of at least one segment, defined by the physical paths existing between two nodes (S, D), for example. According to various aspects and embodiments of the present invention, if the network is not deadlock-free, the system provides a "failed" notification and returns it to the user, since according to one or more aspects of the present invention, the network or NoC must first be deadlock-free. The system also extracts a set of connections that do not have defined routes and / or connections that need to be synthesized. It sorts the extracted set of connections given a heuristic. According to various aspects and embodiments of the present invention, for each connection from source "S" to destination "D", a single connection synthesis process includes splitting, creating, and route calculation using a configuration searcher, a configuration filtering module, a configuration selection module. It configures each of the newly created components, switches, and links such that the bandwidth requirements are met by assigning clock domains and data width settings.

[0080] FIG. 15 is a flow chart illustrating a method 1500 for a NoC generator using a topology synthesis process. The input 1503A to be synthesized may be a new connection 1501, and / or the input 1503B may be an existing segment 1502. The new connection 1501 includes creating new components, such as switches and / or links, to define a network route from “S” to “D”. The existing segment 1502 may be re-represented as a pair of segments having at least one segment and / or at least one turn. The existing network has a set of turns that cannot be changed. When a new segment is added, a turn associated with the newly added segment is also added to complete the route from “S” to “D”. The added turn does not create a cycle and / or a deadlock with the existing turns.

[0081] The configuration searcher 1504 receives an input 1503A which is a new connection 1501 and an input 1503B which is an existing segment 1502. Since there are multiple ways to connect from segment "S" to "D", the configuration searcher 1504 influences the best configuration based on the communication policy 1506 assigned to each segment. The configuration searcher 1504 searches various ways to connect "S" to "D" using a search for legal configurations 1505. The legal configurations 1505 are a list of described parameters. The configuration searcher 1504 is configured to traverse the segment to search and / or consider and analyze at least one configuration of location possibilities to split the segment from a list of meaningful configurations stored in the memory. The configuration searcher 1504 may have a configuration with a new incoming segment to connect "S" to some segment of the NoC. If "S" is already connected, it already has an incoming segment. The configuration seeker 1504 may have a configuration with a new outgoing segment to connect to.

[0082] The cost of a given path is updated at each step according to the communication policy 1506. In one example, depending on whether the communication policy 1506 prioritizes wire length and / or latency, traveling in an existing segment away from the destination may be more or less costly than creating a new segment that reaches the destination directly. It is within the scope of the present invention that established shortest path algorithms explore concrete segments and identify potential future segments using cost updates as a way to effectively enforce some communication policies.

[0083] The main configuration search process 1504 is * and / or may be designed as a specialized version of a common shortest path algorithm, including but not limited to Dijkstra's. A given step in the shortest path algorithm considers different points that can be reached from a current point. The current point is at least one point along the physical path of an existing segment. The path from the current point to the next point in the current segment is considered.

[0084] In one embodiment, the path may proceed one step along the path of the current segment. In one embodiment, when the end of the path of a segment is reached, the path may proceed to the first point of the path of any of the next segments, such as a segment that is directly connected to the current segment and around which the current segment can "turn."

[0085] In one embodiment, if the destination is not connected, such as if there is no outgoing segment, the path may jump directly to the destination point, which corresponds to creating a new outgoing segment. The new and / or future outgoing segments are then added to the configuration.

[0086] In yet other embodiments, a path may jump to any point in any segment as long as no circular dependencies are created, the two segments have compatible communication policies, and the communication policies allow merging, which corresponds to creating a new internal segment that is added to the configuration.

[0087] Referring again to FIG. 15, the configuration filtering module 1507 has a predefined list that includes data including, but not limited to, which configurations are legal, which configurations result in deadlocks, and which configurations are suboptimal. The configuration filtering module 1507 filters the configurations given multiple criteria, including, but not limited to, communication policy 1506 based criteria and / or any custom criteria, and keeps only a subset. In an example of custom criteria, a user, such as a programmer, may base a parameter on low latency defined by a shorter length between routes from "S" to "D". The user may define a maximum length of the path. The configuration filtering module 1507 of the communication policy 1506 removes routes if the length of the path exceeds a user-defined threshold. In another example, the parameter may be based on the use of a minimum number of extra wires. In another example, the parameter may be based on a cost function that prioritizes routes from "S" to "D" that have the lowest cost. The configuration filtering module 1507 is customizable to user-defined parameters. Users may set their own filters and discard certain types of configurations.

[0088] The first criterion is a communication policy 1506 based criterion. The user may control the manner in which new segments are created. A communication policy 1506 is a set of parameters that may be associated with any given connection in the network. The system may have multiple communication policies defined, and each connection may be associated with one communication policy 1506. A communication policy 1506 has parameters and flags. In one example of a flag, low latency is when the connection should be implemented in a manner that minimizes the total path length from source to destination. In another example of a flag, enable serialization is when links included in the path from source to destination can use serialization to save wires. Some configurations of a given connection may not be legal with respect to the communication policy 1506 that governs the connection. Eligible configurations 1508 are filtered versions of legal configurations. In one example, if a connection "S" to "D" is configured to have a low latency communication policy, restrictions on the total length of the route and the number of hops or components traversed must be applied, and candidate configurations that do not fall within these restrictions are discarded.

[0089] Referring again to FIG. 15, after filtering, the configuration filtering module 1507 outputs eligible configurations 1508. It is desirable to select one of the eligible configurations which is performed by the configuration selection module 1509. Selecting the best configuration is accomplished using the configuration selection module 1509, which retains only one final configuration to be implemented as the final composition of connections "S" to "D". The metric used to select the best configuration is configurable and may take into account several parameters based on the community policy 1506. In one embodiment, the communication policy parameter is the total additional wire length. The length of the additionally created segments creates the wires required to traverse the route. There is a cost associated with the wires. A parameter that aims to minimize the total wire length to reduce the cost of the topology would be more desirable. In one embodiment, the communication policy parameter is the total route length. The total length of the route is a combination of the sum of the existing segments and the newly added segments. This parameter focuses on minimizing latency. In another embodiment, the communication policy parameter is based on the bandwidth distribution. This parameter optimizes performance by focusing on the traffic distribution on the segments and the associated congestion levels.

[0090] Once the best configuration 1510 is selected, the system implements 1511 the best configuration 1510 by splitting the involved segments, creating 1512 new segments and turns, and applying it to the network. It is within the scope of the invention that the best configuration is the final configuration. When a segment is split, it is split with all existing segments that need to be connected to the new segment at the point dictated by the selected configuration. With regard to optimization, if the split point is within a certain distance from one of the endpoints of the segment and the endpoint is a switch, the endpoint should be reused for the connection instead of creating a new switch. This allows reducing the number of switches created. Creates 1512 the necessary new segments dictated by the selected configuration and activates the corresponding turns. The newly created 1512 segments and turns are input to a routing tool 1513 that combines them with the existing 1502 segments and turns to generate the final route 1514. The route is calculated from "S" to "D" taking into account the newly created segments. The route is stored in memory. The routing tool 1513 is for routing connections on a geographic floor plan as segments are defined in terms of geographic paths along the floor plan.

[0091] FIG. 16A shows a NoC topology on a floorplan having node "S" 1601 to node "D" 1602. When there is an existing network and a change is requested, such as a request to add a new connection from node "S" 1601 to node "D" 1602, incremental synthesis must be performed. IP blocks are an example of a constraint on the floorplan that a route must navigate. The existing nodes are connected to each other. It is desirable to create a route for a new connection in the existing network without having to make changes to the existing structure.

[0092] FIG. 16B illustrates a NoC topology on a floorplan with the incremental synthesis result of the routing configuration from “S” 1601 to “D” 1602 with node “S” 1601 and new incoming segment 1603 with node 1606, new internal segment 1604 with node, and outgoing segment 1605. The search for legal configurations 1505 is illustrated in the configuration shown in FIG. 16B, where an incoming segment 1603 is added if the node is not already connected to the NoC. In one embodiment, the new incoming segment 1603 can connect “S” 1601 to a segment of the NoC. If “S” 1601 is already connected to a segment of the NoC, it already has an incoming segment.

[0093] In the diagram of FIG. 16B, outgoing segment 1605 existed because "D" was already connected to other nodes. Thus, if "D" is already connected, it already has an outgoing segment. A new outgoing segment may be a configuration option to connect some segments of the NoC to "D."

[0094] Referring again to FIG. 16B, it is within the scope of the present invention that there may be any number of interior segments 1604. At least one and / or more new interior segments may connect existing segments such that an ingress segment reaches an egress segment. A connection between two existing segments is considered only if it does not create a cyclic dependency between the segments, ensuring that only deadlock-free configurations are considered. Composition may include computing a network route without creating new switches and / or segments. This is the case when both "S" and "D" are connected to the network and the ingress segment can already reach the egress segment given only existing turns. An important aspect of the present invention is that composition may define future segments, whereby no concrete segments are created in the topology during the exploration phase.

[0095] In one embodiment, the system may pre-set some common communication policies to make the selection easier for the user. Instead of requiring the user to create a communication policy, it is more desirable for the user to select from a list of presets. Connections associated with different communication policies have a composite route that is physically separated. During composition, the configuration filtering module 1507 (FIG. 15) and the configuration selection module 1509 (FIG. 15) output the best configuration 1510 for implementing 1511 the route depending on the communication policy 1506 (FIG. 15).

[0096] FIG. 17A shows a NoC topology on a floorplan with a communication policy 1700 that aims to optimize wire length with best-effort performance. FIGS. 17A and 17B show how the same connection can result in different implementations based on the selected communication policy. In the diagram of FIG. 17A, the focus is on connecting node "S" to node "D", and the parameter of wire length is the main criterion for optimization. The configuration selection module selects the implementation that creates the least amount of extra wire. Having a short incoming segment 1703 and one turn 1704 activated is shown to meet the parameter requirements.

[0097] Figure 17B shows a NoC topology on a floorplan with a communication policy 1710 for low latency communication. In this example, there is a preference for a direct connection 1713 between node "S" 1711 and node "D" 1712, rather than traversing several switches. One turn 1714 that is activated is near "D". This configuration incurs more extra wires and is more expensive, but it is the user-selected path from "S" to "D" that has the shortest length.

[0098] The basic method for incrementally synthesizing new connections while reusing existing segments is best illustrated in Figures 1-17B. This embodiment relies on splitting existing segments and branching new segments. At the end of the process, only the newly created components, such as clocks and / or data widths, are configured, while the existing components remain unchanged. Referring again to Figure 15, existing segments and turns 1502 are modified by user control at incremental levels. The user utilizes communication policies 1506 to control the creation and selection of new segments in the network, as well as modifying existing topologies or segments. In one example, reusing existing segments in new routes may not be desirable due to performance considerations or previous optimizations that the user may have performed and that rely on the segments remaining unchanged. If a segment is split, hops may be added to traverse multiple routes, which may not be the desired outcome. As a result, the system defines several incremental levels or modes based on the physical changeability of the segments, the physical changeability of the switches, and the logical changeability of the network elements. It is more desirable to capture the user's intent when synthesizing a set of new connections in the presence of an existing NoC topology.

[0099] In an alternative embodiment, the incremental compositing mode allows the user to customize how the existing topology is modified.

[0100] Regarding the physical modifiability of a segment, a segment is modifiable by default. A segment may be split to branch off a new segment. A user may make a segment unmodifiable, for example if they do not want to add a switch to an existing route.

[0101] With reference to the physical mutability of a switch, a new segment may be connected to an existing endpoint of an immutable segment if the endpoint is a switch. If it is not desirable to change the physical size of a switch, the switch may be immutable, so that new segments cannot be connected to an immutable switch.

[0102] Referring now to logical mutability of network elements, as a default, existing network elements, including but not limited to data width and / or assigned clocks, are not reconfigured by the incremental synthesis process. Only newly created switches and adapters are configured. This may result in inefficient configurations such as insufficient bandwidth and / or too many clock domain crossings. Any component may be marked as logically mutable to allow existing components to be reconfigured given the resulting new topology. In an example of how pre-configured incremental synthesis modes can be defined within a system based on the aforementioned concepts, three pre-configured modes are described.

[0103] 18A illustrates an incremental synthesis mode 1800 for the initial setup of a segment connected from node “S” 1801 to node “D” 1802. A high bandwidth segment 1803 and a low bandwidth segment 1804 traverse the existing NoC topology route. During the initial setup, user parameters determine how the existing topology is modified to connect “S” 1801 to “D” 1802.

[0104] 18B shows an incremental synthesis mode 1810 for physical immutability of segments with minimal change parameters. The segment is split 1811, a new segment is branched 1812, and a U-turn is created in the deadlock-free network to connect "S" 1801 to "D" 1802 with minimal changes. The high bandwidth segment 1803 is unchanged to prevent splitting, and the traversal of the low bandwidth segment 1804 is routed around the existing NoC topology route.

[0105] It is more desirable to preserve the maximum amount of existing topology. All segments are made physically immutable with the exception of inbound and outbound segments, as inbound and outbound segments are required to implement new connections. All switches are physically immutable and all network elements are logically immutable. In one example, if one segment from "S" 1801 to "D" 1802 is marked immutable, it prevents segment splits and facilitates routes around existing segments. As a result, the existing segment remains unchanged.

[0106] FIG. 18C illustrates an incremental synthesis mode 1820 for logical immutability of segments with parameters that optimize the topology and preserve the configuration. The low bandwidth 1804 segment is split 1821, a new segment 1822 is branched, and a new turn is created to connect "S" 1801 to "D" 1802. The high bandwidth is not fully utilized because it is connected to a lower bandwidth and the switches cannot be changed. It would be more desirable for some switches to be changed to adapt. This preset splits existing segments and allows the switches to have new connections for a more optimized topology. As a result, better cost by reusing existing elements can be achieved. For example, existing network elements may be made logically immutable to keep the clock frequencies, clocks assigned to the switches, and / or other attributes unchanged.

[0107] FIG. 18D shows an incremental synthesis mode 1830 for changeability of network elements with parameters to optimize the topology and adapt the configuration. A high bandwidth 1803 segment was split 1831, a new segment 1832 was branched, and a new turn was created to connect "S" 1801 to "D" 1802. The switch was changed so that it was connected to a higher bandwidth, so the high bandwidth is fully utilized. A higher flexibility to the synthesis process is achieved if all segments can be split, switches can be connected to new segments, and / or if the result is improved by reconfiguring components, e.g. changing clocks to improve performance.

[0108] Figure 19 shows the process of NoC synthesis based on the mesh custom sub-network description. First, mesh segments are generated and optimally physically placed on the requested space. Second, new mesh segments, which are considered as existing segments by the incremental synthesis process, are used expediently when appropriate to generate the final route. The result is a topology that mixes the automatically generated regular mesh topology with the new optimally synthesized segments. In a fully connected system, the NoC 1900 has each node 1901 connected to every other node. A region 1902 is specified for a 3x3 mesh using an XY routing algorithm. As a result of the synthesis process 1903, the NoC 1905 uses the requested mesh segments and the newly synthesized segments. The automatically synthesized local tree 1904 is shown. A mesh is generated and optimally placed within the specified region 1906.

[0109] According to another aspect of the invention, there is provided an extension of clock and power domains on the floorplan, where each element is tested to ensure that it is located within the boundaries of the specified clock and power domains. If the test fails, the element is moved until a suitable location is found where the test passes. Once a suitable placement is found for each element, routing is performed for each connection between the elements. The routing process finds suitable paths for the sets of wires that make the connections between the elements. After routing is performed, distance-spanning pipeline elements are inserted into the links as necessary using information provided about the capabilities of the present technology based on the time it takes a signal to cover a distance of 1 mm.

[0110] According to some aspects and embodiments of the invention, the tool generates one or more computer files that describe the generated NoC, which include: A list of network elements and their configuration: data width, clock domain.

[0111] The location of each generated network element on the floor plan. A set of routes through network elements that implement a connection.

[0112] According to an aspect of the invention, a route is an ordered list of network elements, one for each pair of (initiator, target) and one for each pair of (target, initiator), that describes how traffic between the pairs flows and through which elements.

[0113] According to various aspects of the invention, a tool is used to generate metrics for the generated NoC, such as a histogram of wire length distribution, number of switches, and a histogram of switches by size.

[0114] According to another aspect of the invention, the tool automatically inserts various adapters and buffers into the network. The tool inserts adapters based on the accommodation required between two elements having different data widths, different clock and power domains. The tool inserts buffers based on the scenario and the detected rate mismatch.

[0115] According to some aspects and embodiments, the tool can be used to ensure that multiple iterations of synthesis are performed for incremental optimization of the NoC, including situations where one constraint provided to the tool is information about a previous run.

[0116] After the software performs the synthesis process, the results are generated in a machine-readable form, such as a computer file, using a well-defined format to capture the information. An example of such a format is XML, and another example of such a format is JSON. The scope of the invention is not limited by any particular format.

[0117] Some aspects of the invention use an incremental approach to network synthesis. This incremental approach is useful in many situations. For example, in some embodiments, the incremental process begins with a specification and a blank floorplan. These and other embodiments, some of which are discussed above.

[0118] According to some aspects and embodiments, a connection may have a communication policy that specifies, for example, the sensitivity of the connection to latency.

[0119] Certain methods according to various aspects of the present invention can be performed by instructions stored on a non-transitory computer-readable medium. The non-transitory computer-readable medium stores code including instructions that, when executed by one or more processors, cause a system or computer to perform steps of the methods described herein. Non-transitory computer-readable media include rotating magnetic disks, rotating optical disks, flash random access memory (RAM) chips, and other mechanically moving or solid-state storage media. Any type of computer-readable medium is suitable for storing code including instructions according to various examples.

[0120] It should be noted that although specific examples have been described herein, different combinations of different components from different examples may be possible. Salient features are presented to better explain the examples, but it will be apparent that certain features can be added, modified, and / or omitted without changing the functional aspects of these examples as described.

[0121] Various examples are methods that use any or a combination of machine behaviors. The method examples are completed wherever most of the constituent steps are performed. For example, according to various aspects and embodiments of the present invention, an IP element or unit includes a processor (e.g., CPU or GPU), random access memory (RAM, e.g., off-chip dynamic RAM or DRAM), network interfaces for wired or wireless connections such as Ethernet, WIFI, 3G, 4G Long Term Evolution (LTE), 5G, and other wireless interface standard radios. The IP may also include various I / O interface devices for various peripheral devices such as touch screen sensors, geolocation receivers, microphones, speakers, Bluetooth peripherals, and USB devices (such as keyboards and mice, among others), as needed. By executing instructions stored in the RAM device, the processor performs the steps of the methods described herein.

[0122] Some examples are one or more non-transitory computer-readable media configured to store such instructions for the methods described herein. Any machine that holds a non-transitory computer-readable medium containing any of the necessary code can perform an example. Some examples may be implemented as a physical device such as a semiconductor chip, a hardware description language representation of the logical or functional behavior of such a device, and one or more non-transitory computer-readable media configured to store such a hardware description language representation. All statements herein reciting principles, aspects, and embodiments encompass both structural and functional equivalents thereof. Elements coupled herein have an operative relationship that can be realized by direct connection or indirectly with one or more other intervening elements.

[0123] Those skilled in the art will recognize many modifications and variations. Modifications and variations include any relevant combination of the disclosed features. All statements herein reciting principles, aspects, and embodiments encompass both structural and functional equivalents thereof. Elements described herein as "coupled" or "communicatively coupled" have an effective relationship that can be achieved by a direct connection or an indirect connection using one or more other intervening elements. Embodiments described herein as "communicating" or "in communication" with other devices, modules, or elements include any form of communication or link and include an effective relationship. For example, the communication link can be established using a wired connection, a wireless protocol, a near-field protocol, or RFID.

[0124] To the extent that the terms "including," "includes," "having," "has," "with," or variations thereof are used in any of the detailed description and claims, such terms are intended to be inclusive in the same manner as the term "comprising."

[0125] The scope of the present invention, therefore, is not intended to be limited to the exemplary embodiments shown and described herein. Rather, the scope and spirit of the present invention is embodied in the appended claims.

Claims

1. A method for generating a deadlock-free network-on-chip (NoC), Generating a new NoC configuration by synthesizing at least one new connection with an existing deadlock-free NoC configuration, This involves generating a first new deadlock-free route from source to destination by using existing routes and adding new connections, For each existing route in the aforementioned deadlock-free NoC configuration, the existing route is translated into segments and turns. Identifying one or more of the new connections to be synthesized based on the synthesis order, For each of the new connections, identify a plurality of possible routes from the source to the destination for the one or more new connections, according to the synthesis order, wherein the plurality of possible routes are eligible routes to avoid deadlocks. In order to identify the first new deadlock-free route, at least one of the plurality of possible routes is filtered based on the criteria. Including generating Methods that include...

2. The method according to claim 1, wherein the first new deadlock-free route includes at least one of an existing physical segment and a new physical segment.

3. A method for synthesizing network-on-chip (NoC) topologies, The aforementioned NoC topology is received as input, The reuse of an existing segment within the NoC topology in a new route, wherein the existing segment is formed by a path between a first node and a second node. In order to form a divided segment, the existing segment is recursively divided at any point along the path, The new path is synthesized by adding a new segment and a new turn to the divided segment, wherein the new segment and the new turn avoid circular dependencies in order to ensure a deadlock-free segment. A deadlock-free NoC topology is generated by routing packets from the existing segment to the new segment using the new route. Methods that include...

4. The method according to claim 3, further comprising translating the NoC topology into existing segments and existing turns.

5. A non-temporary computer-readable medium for storing code, wherein the code, when executed by one or more processors, is transmitted to the one or more processors. The network-on-chip (NoC) input topology is received, Determine the source-destination pairs in the input topology to be selected for synthesis and at least one existing connection between the source-destination pairs, The source-destination pair is then transferred to multiple segments. The at least one existing connection is transferred to multiple existing segments, By analyzing the multiple segments to identify whether or not there is a deadlock, it is determined whether or not the NoC is deadlock-free. In response to the NoC determining that it is deadlock-free, a pair of segments that do not have a defined route are extracted from the plurality of segments and sorted using a heuristic. The plurality of segments and the plurality of existing segments are input to the configuration search unit. Based on the multiple segments that satisfy the communication policy and the multiple existing segments, a configuration filtering module that communicates with the configuration search unit is used to output a qualifying configuration. A configuration selection module communicating with the configuration filtering module is used to select a final configuration to be implemented to connect the source-destination pair from the eligible configurations, the final configuration comprising at least one segment selected from the plurality of segments, At least one existing segment selected from the plurality of existing segments, which needs to be connected to the aforementioned at least one segment, is divided in terms of the final configuration. Activate the corresponding turn that connects the at least one existing segment to the at least one segment, A non-temporary computer-readable medium that causes a route for the source-destination pair to be calculated using the corresponding turns connecting the at least one existing segment to the at least one segment.

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