Memory system

Abstract

To prevent the performance of a memory system from degrading caused by GC processing.SOLUTION: A memory system according to one embodiment includes: a nonvolatile memory including a plurality of blocks, each of which includes a plurality of physical memory areas; and a memory controller for dividing a logical address space into a plurality of banks and associating a block with each of the plurality of banks. The memory controller is configured to: selectively scan a portion related to a first bank among the plurality of banks in a table in which a physical address corresponding to a physical memory area in which valid data is stored is mapped on the logical address space; detect a first physical address corresponding to a first physical memory area in a first block associated with the first bank as a result of scanning; read first valid data stored in the first block based on the first physical address; and write the first valid data in a second block associated with the first bank.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The embodiments relate to a memory system. [Background technology]

[0002] There is known a memory system including a NAND flash memory as a nonvolatile memory and a memory controller that controls the nonvolatile memory. The memory controller executes a garbage collection (GC) process to secure a memory area in the nonvolatile memory where data can be written. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2014 / 0068152 [Patent Document 2] U.S. Pat. No. 1,121,6368 [Patent Document 3] U.S. Patent No. 8,762,627 Summary of the Invention [Problem to be solved by the invention]

[0004] Suppresses performance degradation of the memory system caused by GC processing. [Means for solving the problem]

[0005] A memory system according to an embodiment includes a non-volatile memory including a plurality of blocks, each including a plurality of physical memory areas, and a memory controller that divides a logical address space into a plurality of banks and associates a block with each of the plurality of banks. The memory controller is configured to selectively scan a portion of a table that maps physical addresses corresponding to physical memory areas in which valid data is stored onto the logical address space, the portion relating to a first bank among the plurality of banks, detect a first physical address corresponding to a first physical memory area in a first block associated with the first bank as a result of the scan, read first valid data stored in the first block based on the first physical address, and write the first valid data to a second block associated with the first bank. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an information processing system according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of the configuration of a logical address space managed in the memory system according to the first embodiment. [Diagram 3] FIG. 2 is a diagram showing an example of a configuration of a logical address used in the memory system according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing an example of the relationship between banks and blocks according to the first embodiment. [Diagram 5] FIG. 2 is a block diagram showing an example of the overall configuration of a memory controller according to the first embodiment. [Figure 6] FIG. 2 is a block diagram showing an example of the hardware configuration of a cache according to the first embodiment. [Figure 7] FIG. 2 is a block diagram showing an example of a hardware configuration of a write buffer according to the first embodiment. [Figure 8] FIG. 4 is a diagram showing an example of a data structure of an L2P table according to the first embodiment. [Figure 9] FIG. 2 is a block diagram showing an example of a functional configuration of a memory controller according to the first embodiment. [Figure 10]11 is a flowchart showing an example of a GC process in the memory system according to the first embodiment. [Figure 11] FIG. 11 is a diagram showing an example of the configuration of a logical address used in the memory system according to the second embodiment. [Figure 12] FIG. 11 is a block diagram showing an example of a functional configuration of a memory system according to a second embodiment. [Figure 13] 13 is a flowchart showing an example of a GC process in the memory system according to the second embodiment. [Figure 14] 13 is a flowchart showing an example of a GC process in a memory system according to a modified example of the second embodiment. [Figure 15] 13 is a flowchart showing a first example of a determination process in a memory system according to a modified example of the second embodiment. [Figure 16] 13 is a flowchart showing a second example of a determination process in a memory system according to a modified example of the second embodiment. [Figure 17] 13 is a flowchart showing a third example of a determination process in the memory system according to the modified example of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are given common reference symbols. When multiple components having a common reference symbol are to be distinguished from one another, a subscript is added to the common reference symbol. When no particular distinction is required between multiple components, only the common reference symbol is added to the multiple components, and no subscript is added.

[0008] 1. First embodiment 1.1 Configuration 1.1.1 Information Processing System The configuration of the information processing system according to the first embodiment will be described.

[0009] FIG. 1 is a block diagram showing an example of the configuration of an information processing system according to the first embodiment. As shown in FIG. 1, the information processing system 1 includes a host 2 and a memory system 3. The host 2 and the memory system 3 are connected via a host bus HB. The host 2 and the memory system 3 are configured to communicate a minimum of 64 bytes (B) of data. Hereinafter, the minimum unit in data communication between the host 2 and the memory system 3 is also referred to as "access granularity." Communication between the host 2 and the memory system 3 is performed, for example, using CXL TM (Computer Express Link TM )

[0010] The host 2 is, for example, a server in a data center. The host 2 manages a logical address space with logical addresses corresponding to an access granularity. The logical address space is a memory address space used by the host 2 to access the memory system 3. When the access granularity is 64B (=2 6 B), the capacity of the logical address space (i.e., the capacity of the memory system 3 visible to the host 2) is 256 GB (= 2 38 In the case of B), the logical address space is expressed by a logical address of 32 (=38-6) bits or more. In the following description, the bit width of the logical address is assumed to be N bits (N is an integer of 2 or more).

[0011] The memory system 3 may be, for example, a SD TM The memory system 3 is a storage device such as a memory card, a Universal Flash Storage (UFS), or a Solid State Drive (SSD). The memory system 3 divides the logical address space into a plurality of small logical address spaces and manages them. Hereinafter, the small logical address spaces are also called "banks".

[0012] 2 is a diagram showing an example of a configuration of a logical address space managed by the memory system according to the first embodiment. As shown in FIG. 2, the memory system 3 divides the logical address space into two n Banks BANK(BANK0, BANK1, …, BANK(2n The memory system 3 then defines a bank address that can uniquely identify each bank. Here, n is a natural number. Number of banks: 2 n is, for example, 1024 or more.

[0013] 3 is a diagram showing an example of a configuration of a logical address used in the memory system according to the first embodiment. As shown in FIG. 3, the memory system 3 has an N-bit logical address LA <n-1:0>, the n-bit bank address LAa <n-1:0>and (Nn)-bit split logical address <n-n-1:0>and divided into.

[0014] 1.1.2 Memory System Next, the internal configuration of the memory system 3 will be described with reference to Fig. 1 again. The memory system 3 includes a non-volatile memory 10 and a memory controller 20. The non-volatile memory 10 and the memory controller 20 are connected via a memory bus MB. The communication between the non-volatile memory 10 and the memory controller 20 complies with, for example, a single data rate (SDR) interface, a toggle double data rate (DDR) interface, or an open NAND flash interface (ONFI).

[0015] The nonvolatile memory 10 is, for example, a NAND flash memory. The nonvolatile memory 10 has a physical memory area associated with a physical address space. The physical address space is an address space indicating a plurality of storage locations on the physical memory area in the memory system 3. A physical address is an address used by the memory controller 30 to access the physical address space. Specifically, the nonvolatile memory 10 includes a plurality of blocks BLK. Each of the plurality of blocks includes a plurality of memory cells (not shown). The block BLK is, for example, a data erase unit. Hereinafter, a block BLK in which no valid data is stored is referred to as a "free block BLK" and, as necessary, is distinguished from a block BLK in which valid data is stored.

[0016] The memory controller 20 is configured with an integrated circuit such as a System-on-a-Chip (SoC). The memory controller 20 controls the nonvolatile memory 10 based on a request from the host 2. Specifically, when the memory controller 20 receives a write request from the host 2, it writes data to be written (write data) to the nonvolatile memory 10. Also, when the memory controller 20 receives a read request from the host 2, it reads data to be read (read data) from the nonvolatile memory 10 and transmits it to the host 2.

[0017] The memory controller 20 may execute internal processing without depending on a request from the host 2. An example of the internal processing is GC (Garbage Collection) processing. The GC processing is processing to release one or more blocks BLK in which the valid data was stored fragmentarily as a free block BLK by writing back the valid data stored fragmentarily in one or more blocks BLK to one free block BLK.

[0018] 1.1.3 Relationship between banks and blocks FIG. 4 is a diagram showing an example of the relationship between banks and blocks according to the first embodiment. n Banks BANK(BANK0~BANK(2 n 1)) and a plurality of blocks BLK in the non-volatile memory 10 are shown.

[0019] The memory controller 20, for example, divides a plurality of blocks BLK in the nonvolatile memory 10 into n +1) groups GP0 to GP(2 n -1) and GP_FB. n Groups GP0 to GP(2 n 1-1) is made up of one or more blocks BLK in which valid data is stored. And the group GP_FB is made up of all the free blocks BLK in the non-volatile memory 10.

[0020] The memory controller 20 includes: n Groups GP0 to GP(2 n -1) respectively, 2 n Banks BANK0~BANK(2 n In other words, the memory controller 20 exclusively limits the blocks BLK to which data is written among the banks BANK so that the logical addresses LA corresponding to the write data written to the blocks BLK in a certain group GP have the same bank address LAa.

[0021] This allows the memory controller 20 to identify one or more blocks BLK belonging to a group GPx associated with a bank BANKx based on a bank address LAa indicating the bank BANKx. Specifically, the memory controller 20 stores a GP map table that associates each group GP with a set of physical addresses (block addresses) indicating the blocks BLK belonging to each group GP. This allows the memory controller 20 to identify a group GP based on the bank address LAa and to identify a block BLK belonging to the identified group GP based on the GP map table.

[0022] Therefore, the memory controller 20 can specify the physical memory area in the non-volatile memory 10 where valid data is stored with the access granularity by combining a part of the physical address PA with the bank address LAa without using the full-size physical address PA. That is, the memory controller 20 can specify the physical memory area in the non-volatile memory 10 where valid data is stored with the access granularity based on the combination of the entry position of the GP map table and the data position in the block BLK indicated by the entry position with the access granularity. Hereinafter, the part of the physical address PA that can specify the physical memory area in which valid data is stored with the access granularity by combining it with the bank address LAa is referred to as the "divided physical address PAa".

[0023] In addition, the GC process will n When a block BLKx belonging to any one of groups GP0 to GP(2-1) is released and becomes a free block BLKx, the memory controller 20 cancels the association between the free block BLKx and the bank address LAa. As a result, the free block BLKx is assigned to group GP_FB. Then, the memory controller 20 newly reassociates an arbitrary free block BLKy belonging to group GP_FB with the bank address LAa in place of the block BLKx. As a result, the free block BLKy is assigned to any one of groups GP0 to GP(2-1). n -1).

[0024] 1.1.4 Memory Controller Configuration Next, the configuration of the memory controller 20 will be described.

[0025] 1.1.4.1 Hardware Configuration (Overall composition) 5 is a block diagram showing an example of the overall configuration of the memory controller according to the first embodiment. The memory controller 20 includes a host interface circuit (host I / F) 21, a control circuit 22, a cache 23, a memory interface circuit (memory I / F) 24, a write buffer 25, and a system buffer 26. The functions of the host interface circuit 21, the control circuit 22, the cache 23, the memory interface circuit 24, the write buffer 25, and the system buffer 26 described below can be realized by dedicated hardware, a processor that executes a program, or a combination of these.

[0026] The host interface circuit 21 is hardware that controls communication between the memory controller 20 and the host 2. The host interface circuit 21 is connected to the host 2 via a host bus HB.

[0027] The control circuit 22 is a circuit that controls the entire memory controller 20. The control circuit 22 includes, for example, a processor such as a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory).

[0028] The cache 23 is, for example, a static random access memory (SRAM) or a dynamic random access memory (DRAM). Frequently accessed data is stored in the cache 23. Write data from the host 2 is first stored in the cache 23 via the host interface circuit 21. The write data stored in the cache 23 is sent to a write buffer 25.

[0029] The memory interface circuit 24 is hardware that controls communication between the memory controller 20 and the nonvolatile memory 10. The memory interface circuit 24 is connected to the nonvolatile memory 10 via a memory bus MB.

[0030] The write buffer 25 is, for example, a DRAM. The write buffer 25 buffers write data between the cache 23 and the memory interface circuit 24.

[0031] The system buffer 26 is, for example, a DRAM. The system buffer 26 stores system data. The system data is data for managing the non-volatile memory 10 and the write buffer 25. The system buffer 26 stores an L2P table 26a and a GP map table 26b as an example of the system data. The L2P table 26a indicates the correspondence from the logical address LA to the physical address PA. The data structure of the L2P table 26a will be described in detail later. (cache) Fig. 6 is a block diagram showing an example of a hardware configuration of a cache according to the first embodiment. As shown in Fig. 6, the cache 23 includes a plurality of cache lines CL. Each cache line CL includes a plurality of cache units CU, each having a storage capacity equivalent to an access granularity. In the example of Fig. 6, a case is shown in which the cache line CL includes eight cache units CU0 to CU7. Consecutive logical addresses are associated with the cache units CU0 to CU7 in the cache line CL. Note that data stored in the cache line CL may be stored intermittently in the cache units CU0 to CU7.

[0032] Data stored in the cache 23 is evicted in units of cache lines CL. That is, as in the example of Fig. 6, when a cache line CL is composed of eight cache units CU0 to CU7, the unit size of data evicted from the cache 23 is 64B x 8 = 512B. Note that not all data evicted need to be valid data. That is, the size of valid data evicted from a cache line CL by one eviction process can range from 64B to 512B. (write buffer) 7 is a block diagram showing an example of a hardware configuration of the write buffer according to the first embodiment. As shown in FIG. 7, the write buffer 25 has two n Write buffer units WBU0 to WBU(2 n -1).

[0033] Write buffer units WBU0 to WBU(2 n Each of the write buffer units WBU0 to WBU(2-1) has a storage capacity (for example, 4 KB) corresponding to the data (write unit) written in one write process. n -1) are banks BANK0 to BANK(2 n The write buffer units WBU0 to WBU(2 n The data buffered in the groups GP0 to GP(2-1) are respectively transferred to the memory interface circuit 24. n The data is written to memory cells in the block BLK belonging to the block BLK-1). (L2P table) FIG. 8 is a diagram showing an example of the data structure of the L2P table according to the first embodiment. As shown in FIG. 8, the L2P table 26a is configured with a plurality of storage areas (entries). The number of entries configuring the L2P table 26a is determined by the access granularity and the capacity of the memory system 3 visible to the host 2. For example, when the access granularity is 64B (=2 6 B), the capacity of memory system 3 seen by host 2 is 256GB (=2 38 In the case of B), the L2P table 26a is 4G (=2 32 ) entries. Each of the multiple entries is uniquely identified by the corresponding logical address LA. That is, each of the multiple entries is accessed using the corresponding logical address LA as a pointer ptr. The number of entries associated with the same bank address LAa among the multiple entries is 2 n Specifically, if the total number of entries is 4G, the number of entries that can be associated with one bank is 2 (32-n) It becomes an individual.

[0034] In each of the multiple entries, a divided physical address PAa corresponding to a physical memory area in which valid data is stored can be stored. When the divided physical address PAa is stored, valid data corresponding to the logical address LA pointing to the entry is stored in the non-volatile memory 10. That is, the L2P table 26a has a data structure in which the divided physical address PAa corresponding to the physical memory area in which valid data is stored is mapped onto the logical address space.

[0035] As described above, the memory controller 20 cannot specify, with access granularity, the physical memory area in the nonvolatile memory 10 in which valid data is stored, using only the divided physical address PAa. However, the memory controller 20 can specify, with access granularity, the physical memory area in the nonvolatile memory 10 in which valid data is stored, using a combination of the entry position of the GP map table 26b included in the divided physical address PAa and the data position in the block BLK indicated by the entry position.

[0036] Each of the multiple entries may store a physical address PA_WBU indicating a physical memory area in the write buffer unit WBU. When the physical address PA_WBU is stored, valid data corresponding to the logical address LA indicating the entry is stored in the write buffer 25.

[0037] Each of the multiple entries may store a physical address PA_CU indicating a physical memory area in the cache unit CU. When the physical address PA_CU is stored, valid data corresponding to the logical address LA pointing to the entry is stored in the cache 23.

[0038] A physical address PA may not be stored in each of the multiple entries. When a physical address PA is not stored, valid data corresponding to the logical address LA pointing to the entry is not stored in the physical memory area in the memory system 3. In the example of Fig. 8, "NULL" is written in the entry in which a physical address PA is not stored.

[0039] 1.1.4.2 Functional Configuration Fig. 9 is a block diagram showing an example of the functional configuration of the memory controller according to the first embodiment. Fig. 9 shows the functional configuration of the memory controller 20 mainly related to the write process and the GC process. The control circuit 22 functions as, for example, a write controller 22a, a NAND controller 22b, and a GC controller 22c with respect to the write process and the GC process.

[0040] First, the functional configuration relating to the write process will be described.

[0041] When the write data WD is received from the cache 23, the write controller 22a determines a physical memory area of ​​the non-volatile memory 10 to which the write data WD is to be written. The write controller 22a generates a divided physical address PAa from a physical address PA corresponding to the determined physical memory area based on a bank address LAa in the logical address LA corresponding to the write data WD, and stores the divided physical address PAa in the L2P table 26a. The write controller 22a also buffers the write data WD in a write buffer unit WBU associated with the corresponding bank BANK.

[0042] When the write data WD is received from the write buffer 25, the NAND controller 22b writes the write data WD to a physical memory area in the nonvolatile memory .

[0043] The L2P table 26a is updated each time depending on, for example, where the write data WD is stored in which of the cache 23, the write buffer 25, and the non-volatile memory 10. The GP map table 26b stores a group GP and a pair of block addresses indicating blocks BLK belonging to the group GP in association with each other.

[0044] The main functional configuration of the memory controller 20 regarding the write process is as described above.

[0045] Next, the functional configuration related to GC processing will be described.

[0046] The GC controller 22c manages the number of valid data for a plurality of blocks BLK in the non-volatile memory 10. When a block BLK occurs in which the number of valid data is equal to or less than a threshold, the GC controller 22c starts executing GC processing for the block BLK. Specifically, the GC controller 22c identifies a bank BANK corresponding to a group GP to which the block BLK to be GC processed belongs. The GC controller 22c selectively scans a plurality of entries specified by a bank address LAa corresponding to the identified bank BANK in the L2P table 26a using a scan signal Srq. As a result of the scan, the GC controller 22c acquires a divided physical address PAa of valid data stored in the block BLK to be GC processed. The GC controller 22c issues a read request Rrq to a physical memory area identified by the acquired divided physical address PAa and bank address LAa.

[0047] When the NAND controller 22b receives the read request Rrq, it executes a read process and reads out, as read data RD, valid data stored in the block BLK to be GC processed from the nonvolatile memory 10. The read data RD is transmitted from the NAND controller 22b to the write controller 22a via the GC controller 22c.

[0048] Upon receiving the read data RD, the write controller 22a executes a write-back process to write the read data RD back to the block BLK that belongs to the same group GP and is being updated as write data WD. Details of the write-back process are the same as those of the write process described above, and therefore will not be described here.

[0049] Prior to the write-back process, the memory controller 20 allocates a free block BLK from the group GP_FB to the group GP to which the block BLK to be GC processed belongs so that blocks BLK to which data can be written are not depleted. After allocating the block BLK to be GC processed to the group GP_FB as a free block BLK, the memory controller 20 allocates a new free block BLK from the group GP_FB to the group GP to be GC processed.

[0050] The main functional configuration of the memory controller 20 regarding the GC processing is as described above.

[0051] 1.2 Operation Next, the operation of the memory system according to the first embodiment will be described.

[0052] 1.2.1 GC processing Fig. 10 is a flowchart showing an example of GC processing in the memory system according to the first embodiment. In the GC processing shown in Fig. 10, it is assumed that a writable free block BLK is assigned from the group GP_FB to the group GP to which the GC processing target block BLK belongs.

[0053] When a block BLK in which the number of valid data items falls below a threshold value occurs (start), the GC controller 22c regards the block BLK as a GC processing target block BLK, and identifies a bank BANK corresponding to a group GP to which the GC processing target block BLK belongs (S11).

[0054] The GC controller 22c selects a logical address LA, which is the start position of the scan, from the bank BANK identified in the process of S11 (S12). As the start position of the scan, for example, the lowest or highest address of the logical address LA including the bank address LAa corresponding to the identified bank BANK is selected.

[0055] The GC controller 22c determines whether valid data has been detected in the GC processing block BLK based on the logical address LA selected in the processing of S12 (S13). Specifically, the GC controller 22c refers to the L2P table 26a using the logical address LA selected in the processing of S12. The GC controller 22c then determines whether valid data has been detected in the GC processing block BLK by determining whether a divided physical address PAa corresponding to the GC processing block BLK is stored in the referenced entry.

[0056] If valid data is detected in the GC processing target block BLK (S13; yes), the GC controller 22c acquires the divided physical address PAa corresponding to the detected valid data from the L2P table 26a (S14).

[0057] If valid data is not detected in the GC processing target block BLK (S13; no), or after the processing of S14, the GC controller 22c determines whether or not scanning of the bank BANK identified in the processing of S11 has been completed (S15).

[0058] If the scan of the bank BANK specified in the process of S11 has not been completed (S15; no), the GC controller 22c increments the selected logical address (S16).

[0059] After the process of S16, the GC controller 22c determines whether or not valid data is detected in the GC processing target block BLK based on the logical address selected in the process of S16 (S13). Then, the subsequent processes of S14 to S16 are executed. As a result, the processes of S13 to S16 are repeated until the scan of the bank BANK specified in the process of S11 is completed.

[0060] When the scan of the bank BANK identified in the processing of S11 is completed (S15; yes), the NAND controller 22b reads the valid data detected in the processing of S13 from the GC processing target block BLK based on the divided physical address PAa obtained in the processing of S14 (S17).

[0061] After the process of S17, the NAND controller 22b writes back all the valid data read in the process of S17 to one write-back target block BLK in the group GP to which the GC processing target block BLK belongs (S18).

[0062] After the process of S18, the memory controller 20 releases the GC process target block BLK as a free block BLK (S19). Then, the GC process target block BLK is assigned to the group GP_FB. In addition, the memory controller 20 assigns a new writable free block BLK to the group GP to which the GC process target block BLK belongs.

[0063] When the process of S19 ends, the GC process ends (END).

[0064] 1.3 Effects of the First Embodiment According to the first embodiment, the memory controller 20 divides the logical address space into a plurality of banks BANK. The memory controller 20 exclusively manages the blocks BLK corresponding to each of the plurality of banks BANK. In the GC process, the GC controller 22c selectively scans a portion of the L2P table 26a related to one bank BANK corresponding to the GC process target block BLK. As a result of the scan, the GC controller 22c detects a divided physical address PAa corresponding to a physical memory area in which valid data is stored in the GC process target block BLK. The NAND controller 22b reads out the valid data stored in the GC process target block BLK based on the detected divided physical address PAa. The write controller 22a and the NAND controller 22b write the read out valid data back to a free block BLK belonging to the same group GP as the GC process target block BLK. This makes it possible to turn a block BLK in which valid data has been stored fragmentarily due to random writing with low access granularity into a free block BLK. This makes it possible to suppress a decrease in the physical memory area in which data can be written.

[0065] Furthermore, the memory controller 20 can execute the GC process while limiting the range of scanning to a portion of the L2P table 26a related to one bank BANK. Therefore, the range of scanning is reduced to half compared to the case where the entire L2P table 26a is scanned. n Therefore, the load of accessing the L2P table 26a can be reduced.

[0066] The L2P table 26a has a data structure in which a physical address corresponding to a physical memory area in which valid data is stored is mapped onto a logical address space. That is, the memory system 3 can execute the GC process without using a data structure (P2L table) in which a logical address corresponding to valid data is mapped onto a physical address space. Therefore, according to the first embodiment, the memory system 3 does not need to store the P2L table in, for example, the non-volatile memory 10. Therefore, WAF (Write Amplification), which is an index indicating the efficiency of writing to the non-volatile memory 10, can be improved more than when the P2L table is stored in the non-volatile memory 10.

[0067] 2. Second embodiment Next, a memory system according to a second embodiment will be described. The second embodiment differs from the first embodiment in that defragmentation processing is performed in conjunction with GC processing. In the following description, configurations and operations different from the first embodiment will be mainly described. Descriptions of configurations and operations equivalent to those of the first embodiment will be omitted as appropriate.

[0068] 2.1 Logical Address 11 is a diagram showing an example of a configuration of a logical address used in a memory system according to the second embodiment. FIG. 11 corresponds to FIG. 3 in the first embodiment. As shown in FIG. 11, in the second embodiment, the memory system 3 has an N-bit logical address LA <n-1:0>, the n-bit bank address LAa <n-1:0>and k-bit alignment address LAc <k-1:0>and (Nnk-1)-bit split logical address <n-n-k-1:0>and divided into.

[0069] The alignment address LAc indicates the order of the consecutive 64B data when an access (sequential access) to the consecutive 64B data occurs. By explicitly dividing the alignment address LAc from the bank address LAa and the divided logical address LAb, the memory system 3 can associate the consecutive 64B data with one bank BANK. Therefore, the memory system 3 can store the consecutive 64B data in one group GP.

[0070] In the following, when there is valid data contiguous to a certain valid data (target valid data) of an access granularity, the valid data contiguous to the target valid data is referred to as "alignment data" of the target data. The alignment data of the target valid data is stored in a group GP associated with the same bank BANK as the target valid data. However, the alignment data of the target valid data may be stored in a block BLK different from the block BLK in which the target valid data is stored.

[0071] 2.2 Memory Controller Functional Configuration Fig. 12 is a block diagram showing an example of a functional configuration of a memory controller according to the second embodiment. Fig. 12 corresponds to Fig. 9 in the first embodiment. The control circuit 22 functions as, for example, a write controller 22a, a NAND controller 22b, and a GC controller 22d with respect to the write process and the GC process.

[0072] The functional configuration relating to the write process is the same as in the first embodiment, so a description thereof will be omitted.

[0073] The functional configuration related to GC processing will be explained.

[0074] The GC controller 22d manages the number of valid data for a plurality of blocks BLK in the non-volatile memory 10. When a block BLK occurs in which the number of valid data is equal to or less than a threshold, the GC controller 22d starts executing GC processing for the block BLK. Specifically, the GC controller 22d identifies a bank BANK corresponding to a group GP to which the block BLK to be GC processed belongs. The GC controller 22d selectively scans a plurality of entries specified by a bank address LAa corresponding to the identified bank BANK in the L2P table 26a using a scan signal Srq. As a result of the scan, the GC controller 22d acquires a divided physical address PAa of the target valid data stored in the block BLK to be GC processed. The GC controller 22d further acquires a divided physical address PAa of the alignment data of the target valid data stored in the block BLK to be GC processed. The GC controller 22d issues a read request Rrq to a physical memory area identified by the acquired divided physical address PAa and bank address LAa.

[0075] When the NAND controller 22b receives the read request Rrq, it executes a read process and reads out, as read data RD, the target valid data and alignment data stored in the block BLK that is the target of GC processing from the nonvolatile memory 10. The read data RD is transmitted from the NAND controller 22b to the write controller 22a via the GC controller 22d.

[0076] Upon receiving the read data RD, the write controller 22a executes a write-back process to write the read data RD back as write data WD to the block BLK that belongs to the same group GP and is being updated. During the write-back process, the target valid data and alignment data stored in the GC processing target block BLK are rearranged in alignment order based on the alignment address LAc. Details of the write-back process are the same as those of the write process described above, and therefore will not be described here.

[0077] Prior to the write-back process, the memory controller 20 allocates a free block BLK from the group GP_FB to the group GP to which the block BLK to be GC processed belongs so that blocks BLK to which data can be written are not depleted. After allocating the block BLK to be GC processed to the group GP_FB as a free block BLK, the memory controller 20 allocates a new free block BLK from the group GP_FB to the group GP to be GC processed.

[0078] The main functional configuration of the memory controller 20 regarding the GC processing is as described above.

[0079] 2.3 GC Processing Fig. 13 is a flowchart showing an example of GC processing in the memory system according to the second embodiment. Fig. 13 corresponds to Fig. 10 in the first embodiment.

[0080] When a block BLK in which the number of valid data items falls below a threshold value occurs (start), the GC controller 22d regards the block BLK as a GC processing target block BLK, and identifies a bank BANK corresponding to a group GP to which the GC processing target block BLK belongs (S21).

[0081] The GC controller 22d selects a logical address LA, which is the start position of the scan, from the bank BANK identified in the process of S21 (S22). As the start position of the scan, for example, the lowest or highest address of the logical address LA including the bank address LAa corresponding to the identified bank BANK is selected.

[0082] The GC controller 22d determines whether or not target valid data of the GC processing block BLK has been detected based on the logical address LA selected in the process of S22 (S23). Specifically, the GC controller 22d refers to the L2P table 26a using the logical address LA selected in the process of S22. Then, the GC controller 22d determines whether or not target valid data of the GC processing block BLK has been detected by determining whether or not a divided physical address PAa corresponding to the GC processing block BLK is stored in the referenced entry.

[0083] When target valid data in the GC processing target block BLK is detected (S23; yes), the GC controller 22d acquires the divided physical address PAa corresponding to the detected target valid data from the L2P table 26a (S24).

[0084] If the target valid data of the GC processing block BLK is not detected (S23; no), the GC controller 22d determines whether or not alignment data of the target valid data of the GC processing block BLK is detected based on the logical address LA selected in the processing of S22 (S25). Specifically, the GC controller 22d refers to the L2P table 26a using the logical address LA including the alignment address LAc that is consecutive to the alignment address LAc in the logical address LA selected in the processing of S22. Then, the GC controller 22d determines whether or not alignment data is stored in the referenced entry, thereby determining whether or not alignment data of the target valid data of the GC processing block BLK is detected.

[0085] If alignment data of the target valid data of the GC processing target block BLK is detected (S25; yes), the GC controller 22d acquires the divided physical address PAa corresponding to the detected alignment data from the L2P table 26a (S26).

[0086] If alignment data is not detected for the target valid data of the GC processing target block BLK (S25; no), after processing of S24 or processing of S26, the GC controller 22d determines whether scanning of the bank BANK identified in processing of S21 has been completed (S27).

[0087] If the scan of the bank BANK specified in the process of S21 has not been completed (S27; no), the GC controller 22d increments the selected logical address (S28).

[0088] After the process of S28, the GC controller 22d determines whether or not the target valid data of the GC processing target block BLK is detected based on the logical address selected in the process of S28 (S23). Then, the subsequent processes of S24 to S28 are executed. As a result, the processes of S23 to S28 are repeated until the scan of the bank BANK specified in the process of S21 is completed.

[0089] When the scan of the bank BANK identified in the processing of S21 is completed (S27; yes), the NAND controller 22b reads a dataset including the target valid data detected in the processing of S23 and the alignment data detected in the processing of S25 from the group GP corresponding to the bank BANK identified in the processing of S21 based on the processing of S24 and the divided physical address PAa obtained in the processing of S26 (S29).

[0090] After the process of S29, the NAND controller 22b writes back the data set read in the process of S29 into the write-back target block BLK in the group GP to which the GC processing target block BLK belongs so that the data set is arranged in one write unit (S30). As a result, the target valid data in the GC processing target block BLK, which was stored fragmentarily in the group GP, and the alignment data of the target valid data are consolidated into one block BLK. That is, defragmentation processing is further executed in conjunction with the GC processing.

[0091] After the process of S30, the memory controller 20 releases the GC process target block BLK as a free block BLK (S31). Then, the GC process target block BLK is assigned to the group GP_FB. In addition, the memory controller 20 assigns a new writable free block BLK to the group GP to which the GC process target block BLK belongs.

[0092] When the process of S31 ends, the GC process ends (ends).

[0093] 2.4 Effects of the Second Embodiment According to the second embodiment, the memory controller 20 divides the logical address LA into a bank address LAa, a divided logical address LAb, and an alignment address LAc. This allows the memory controller 20 to associate multiple consecutive 64B data with the same bank BANK. This allows the GC controller 22d to detect alignment data of the target valid data in the GC processing target block BLK by selectively scanning one bank BANK in the L2P table 26a, which is executed during GC processing. Therefore, the GC controller 22d can execute defragmentation processing in conjunction with GC processing. Therefore, similar to the first embodiment, fragmented data can be consolidated into one free block BLK while suppressing the access load to the L2P table 26a.

[0094] 3. Modifications Various modifications can be applied to the above-described embodiment.

[0095] In the above-mentioned second embodiment, the case where the defragmentation process is unconditionally executed when the alignment data exists has been described, but the present invention is not limited to this. For example, it may be determined whether or not to execute the defragmentation process. In the following, the configuration and operation different from the second embodiment will be mainly described. The description of the configuration and operation equivalent to the second embodiment will be omitted as appropriate.

[0096] 3.1 GC processing Fig. 14 is a flowchart showing an example of GC processing in a memory system according to a modified example, which corresponds to Fig. 13 in the second embodiment.

[0097] When a block BLK in which the number of valid data items falls below a threshold value occurs (start), the GC controller 22d regards the block BLK as a GC processing target block BLK, and identifies a bank BANK corresponding to a group GP to which the GC processing target block BLK belongs (S41).

[0098] The GC controller 22d executes a scan process on the bank BANK identified in the process of S41 (S42). The process of S42 is equivalent to the processes of S22 to S28 in Fig. 13. As a result, the GC controller 22d acquires a divided physical address PAa at which valid data in the GC processing target block BLK is stored, and a divided physical address PAa at which alignment data of the valid data is stored.

[0099] After the process of S42, the GC controller 22d executes a judgment process (S43). The GC controller 22d uses the judgment process to judge whether or not to execute defragmentation. The details of the judgment process will be described later.

[0100] If it is determined that defragmentation processing is to be performed (S44; yes), the NAND controller 22b reads a dataset including valid data in the GC processing target block BLK and alignment data of the valid data from the group GP corresponding to the bank BANK identified in the processing of S41, based on the divided physical address PAa obtained in the processing of S43 (S45).

[0101] After the process of S45, the NAND controller 22b writes back the data set read in the process of S45 into the write-back target block BLK in the group GP to which the GC processing target block BLK belongs so that the data set is arranged in one write unit (S46). As a result, the valid data in the GC processing target block BLK that was stored fragmentarily in the group GP and the alignment data of the valid data are consolidated into one block BLK. That is, defragmentation processing is further executed in conjunction with the GC processing.

[0102] If it is determined that the defragmentation process is not to be performed (S44; no), the NAND controller 22b reads out the valid data in the GC processing target block BLK from the group GP corresponding to the bank BANK identified in the processing of S41, based on the divided physical address PAa obtained in the processing of S43 (S47).

[0103] After the process of S47, the NAND controller 22b writes back all valid data read in the process of S47 to the write-back target block BLK in the group GP to which the GC processing target block BLK belongs (S48). In other words, defragmentation processing is not executed in conjunction with the GC processing.

[0104] After the process of S46 or the process of S48, the memory controller 20 releases the GC processing target block BLK as a free block BLK (S49). Then, the GC processing target block BLK is assigned to the group GP_FB. In addition, the memory controller 20 assigns a new writable free block BLK to the group GP to which the GC processing target block BLK belongs.

[0105] When the process of S49 ends, the GC process ends (ends).

[0106] 3.2 Judgment process Next, the details of the determination process will be described. As the determination process, for example, the following three examples are given.

[0107] 3.2.1 First Example 15 is a flowchart showing a first example of a determination process in a memory system according to a modified example. In the first example, whether or not to perform defragmentation is determined based on the ratio of sequential accesses (sequential access rate) in accesses from the host 2.

[0108] When the determination process is started (START), the GC controller 22d determines whether or not the sequential access rate is equal to or greater than a threshold value (S51).

[0109] If the sequential access rate is equal to or greater than the threshold (S51; yes), the GC controller 22d determines to execute defragmentation processing (S52).

[0110] If the sequential access rate is less than the threshold value (S51; no), the GC controller 22d determines not to execute defragmentation processing (S53).

[0111] After the process of S52 or the process of S53, the determination process ends (END).

[0112] 3.2.2 Second Example 16 is a flowchart showing a second example of the determination process in the memory system according to the modified example. In the second example, whether or not defragmentation can be performed is determined based on the number of alignment data stored in the non-volatile memory 10.

[0113] When the determination process is started (START), the GC controller 22d determines whether or not all alignment data has been detected (S61).

[0114] If there is undetected alignment data (S61; no), the GC controller 22d judges whether the number of alignment data stored in the non-volatile memory 10 is equal to or greater than a threshold (S62). For example, a value of 80% of the total number of alignment data that can be stored in the non-volatile memory 10 is applied as the threshold in the process of S62. Note that, if alignment data is stored in the cache 23 and the write buffer 25, the number of alignment data is excluded from the total number of alignment data that can be stored in the non-volatile memory 10 before the threshold is applied.

[0115] If all alignment data has been detected (S61; yes), or if the number of alignment data stored in the non-volatile memory 10 is equal to or greater than a threshold (S62; yes), the GC controller 22d determines to execute defragmentation processing (S63).

[0116] If the number of alignment data stored in the non-volatile memory 10 is less than the threshold value (S62; no), the GC controller 22d determines not to execute defragmentation processing (S64).

[0117] After the process of S63 or the process of S64, the determination process ends (END).

[0118] 3.2.3 Third Example 17 is a flowchart showing a third example of a determination process in a memory system according to a modified example. In the third example, whether or not to perform defragmentation is determined based on the relationship between the number of valid data in a GC processing target block BLK and the number of alignment data outside the GC processing target block BLK.

[0119] When the determination process is started (START), the GC controller 22d determines whether or not the number of valid data in the detected GC processing target block BLK is greater than the number of alignment data outside the GC processing target block BLK (S71).

[0120] If the number of valid data in the GC processing block BLK is equal to or less than the number of alignment data outside the GC processing block BLK (S71; no), the GC controller 22d calculates how many blocks BLK the detected alignment data is distributed and stored in. Then, the GC controller 22d determines whether the calculated number of blocks BLK is equal to or greater than a threshold value (S72).

[0121] If the number of valid data within the GC processing target block BLK is greater than the number of alignment data outside the GC processing target block BLK (S71; yes), or if the number of blocks BLK in which alignment data is stored is greater than or equal to a threshold value (S72; yes), the GC controller 22d determines to perform defragmentation processing (S73).

[0122] If the number of blocks BLK in which alignment data is stored is less than the threshold value (S72; no), the GC controller 22d determines not to execute defragmentation processing (S74).

[0123] After the process of S73 or the process of S74, the determination process ends (END).

[0124] 3.3 Effects of Modifications According to the modified example, the GC controller 22d determines whether or not to execute the defragmentation process during the GC process. This makes it possible to avoid excessive execution of the defragmentation process. This makes it possible to suppress the deterioration of the WAF and to suppress the pressure on the communication band with the non-volatile memory 10.

[0125] Specifically, for example, when the sequential access ratio is high, data fragmentation is unlikely to occur, and the demand for defragmentation is relatively low. According to the first modified example, the GC controller 22d determines whether or not defragmentation is possible based on the sequential access ratio. This allows for intensive defragmentation to be performed when the random access ratio, which is likely to cause data fragmentation, is high.

[0126] Also, for example, not all alignment data is necessarily stored in the memory system 3. When the number of alignment data stored in the memory system 3 is small, the demand for defragmentation is relatively low. According to the second modified example, the GC controller 22d determines whether or not to perform defragmentation based on the number of alignment data stored in the non-volatile memory 10. This allows for concentrated defragmentation when a certain amount of alignment data is available.

[0127] Also, for example, it may be more efficient to execute defragmentation when a certain block BLK becomes a GC processing target block BLK than to execute defragmentation when another block BLK becomes a GC processing target block BLK. According to the third modified example, the GC controller 22d determines whether or not to execute defragmentation based on the magnitude relationship between the number of target valid data and the number of alignment data. This makes it possible to appropriately select a GC process that is efficient when executing defragmentation together.

[0128] In addition, even if there is more alignment data than the target valid data, if the alignment data is distributed across many blocks BLK, it may be better to perform defragmentation. According to the third modified example, the GC controller 22d determines to perform defragmentation when the number of alignment data is greater than the number of target valid data and the number of blocks BLK in which the alignment data is stored exceeds a threshold value. This makes it possible to detect a state in which the alignment data is extremely fragmented and appropriately aggregate the valid data.

[0129] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0130] 1. Information processing system 2. Host 3. Memory system 10...Non-volatile memory 20…Memory controller 21...Host interface circuit 22...Control circuit 22a…Light controller 22b…NAND controller 22c, 22d...GC controller 23…Cache 24...Memory interface circuit 25…Write buffer 26...System buffer 26a…L2P table 26b…GP Map Table

Claims

1. a non-volatile memory including a plurality of blocks, each including a plurality of physical memory regions; a memory controller that divides a logical address space into a plurality of banks and associates a block with each of the plurality of banks; Equipped with The memory controller identifying a first bank among the plurality of banks; selectively scanning a portion of a table that maps physical addresses corresponding to physical memory areas in which valid data is stored onto the logical address space, the portion relating to the first bank; As a result of the scan, a first physical address corresponding to a first physical memory area in a first block associated with the first bank is detected; reading first valid data stored in the first block based on the first physical address; writing the first valid data to a second block associated with the first bank; As a result of the scan, a second physical address corresponding to a second physical memory area in one or more third blocks different from the first block and associated with the first bank is detected; reading second valid data stored in the third block based on the second physical address; writing the second valid data together with the first valid data into the second block; It was configured as follows: Memory system.

2. the memory controller is configured to cancel the association between the first block and the first bank after the first valid data is written to the second block; 10. The memory system of claim 1.

3. The memory controller Dividing the logical address space into a plurality of alignment orders independent of the plurality of banks; The first valid data and the second valid data are written to the second block in a state where they are rearranged in accordance with the alignment order. It was configured as follows:

10. The memory system of claim 1.

4. the memory controller is configured to determine whether to read the second valid data and write the second valid data together with the first valid data to the second block; 4. The memory system of claim 3.

5. the memory controller is configured to read the second valid data and write the second valid data together with the first valid data to the second block when a ratio of sequential accesses among accesses from the host is equal to or greater than a threshold value; 5. The memory system of claim 4.

6. When the memory controller detects a number of the second physical addresses equal to or greater than a threshold value, reading the second valid data; writing the second valid data together with the first valid data into the second block; It was configured as follows:

5. The memory system of claim 4.

7. When the second physical addresses corresponding to all alignment orders are detected, the memory controller reading the second valid data; writing the second valid data together with the first valid data into the second block; It was configured as follows:

7. The memory system of claim 6.

8. If the number of the detected first physical addresses is greater than the number of the detected second physical addresses, the memory controller: reading the second valid data; writing the second valid data together with the first valid data into the second block; It was configured as follows:

5. The memory system of claim 4.

9. When the number of the detected first physical addresses is equal to or less than the number of the detected second physical addresses and the number of the third blocks is equal to or greater than a threshold, the memory controller: reading the second valid data; writing the second valid data together with the first valid data into the second block; It was configured as follows:

5. The memory system of claim 4.

10. A non-volatile memory including a plurality of blocks, each including a plurality of physical memory regions; a memory controller that divides a logical address space into a plurality of banks and associates a block with each of the plurality of banks; a buffer including a plurality of buffer units each including a plurality of physical memory areas and respectively associated with the plurality of banks; Equipped with The memory controller identifying a first bank among the plurality of banks; selectively scanning a portion of a table that maps physical addresses corresponding to physical memory areas in which valid data is stored onto the logical address space, the portion relating to the first bank; As a result of the scan, a first physical address corresponding to a first physical memory area in a first block associated with the first bank is detected; reading first valid data stored in the first block based on the first physical address; writing the first valid data to a second block associated with the first bank; It is configured as follows: the number of said buffer units is equal to the number of said banks; the memory controller is configured to cause each of the plurality of buffer units to store valid data to be stored in a block associated with a corresponding bank; Memory system.

11. the memory controller further detects, as a result of the scan, a third physical address corresponding to a third physical memory area in a first buffer unit associated with the first bank; reading third valid data stored in the first buffer unit based on the third physical address; writing the third valid data together with the first valid data into the second block; It was configured as follows:

11. The memory system of claim 10.

12. a cache including a plurality of cache lines, each including a plurality of physical memory regions; the memory controller is configured to store valid data associated with consecutive logical addresses in each of the plurality of cache lines; 10. The memory system of claim 1.

13. the memory controller further detects, as a result of the scan, a fourth physical address corresponding to a fourth physical memory area in a first cache line associated with the first bank; reading fourth valid data stored in the first cache line based on the fourth physical address; writing the fourth valid data together with the first valid data into the second block; It was configured as follows:

13. The memory system of claim 12.

14. The memory controller, Detecting the first block associated with the first bank as a block to be garbage collected; Detecting the third block associated with the first bank as a block that will not be garbage collected. It was configured as follows:

10. The memory system of claim 1.

15. The memory controller, If the number of valid data in the first block is equal to or less than a threshold, the first block is detected as a block to be garbage collected; If the number of valid data in the third block exceeds the threshold, the third block is detected as a block that will not be garbage collected. It was configured as follows:

10. The memory system of claim 1.

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