Semiconductor Devices

Abstract

To reduce the manufacturing cost of a semiconductor device.SOLUTION: A semiconductor device according to the present disclosure includes a first semiconductor chip including a first power transistor and a temperature sensing diode, and a second semiconductor chip including a second power transistor but not including a temperature sensing diode.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, a semiconductor device manufacturing technique, and a chipset providing technique, and more particularly to a semiconductor device including a plurality of semiconductor chips each having a power transistor, a technique that is effective when applied to the semiconductor device manufacturing technique, and the chipset providing technique. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2015-2229 (Patent Document 1) describes a technique related to a semiconductor device including a semiconductor chip including a power transistor and a temperature sensing diode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-2229 A Summary of the Invention [Problem to be solved by the invention]

[0004] The present inventor is engaged in the manufacture and design of semiconductor devices including a plurality of semiconductor chips including power transistors and temperature sensing diodes. In recent years, there has been a demand for reducing the cost of the above-mentioned semiconductor devices, and in order to meet this demand, the present inventor has been continuing to study ways to reduce the cost of semiconductor devices. In other words, when manufacturing a semiconductor device including a plurality of semiconductor chips including power transistors and temperature sensing diodes, it is desirable to devise ways to reduce the cost of semiconductor devices in order to meet market needs. [Means for solving the problem]

[0005] A semiconductor device in one embodiment includes a first semiconductor chip including a first power transistor and a temperature sensing diode, and a second semiconductor chip including a second power transistor but not including a temperature sensing diode.

[0006] A manufacturing method of a semiconductor device in one embodiment includes a step of mounting a first semiconductor chip including a first power transistor and a temperature sensing diode on a first chip mounting portion, and mounting a second semiconductor chip including a second power transistor but not a temperature sensing diode on a second chip mounting portion.

[0007] In one embodiment, a method for providing a chipset includes providing a first semiconductor chip including a first power transistor and a temperature sensing diode, and a second semiconductor chip including a second power transistor but no temperature sensing diode.

[0008] Here, in the first semiconductor chip, the first pad is exposed in a first opening of the protective film, and the second pad is exposed in a second opening of the protective film, while in the second semiconductor chip, the first pad and the second pad are each covered with a protective film so as not to be exposed from the protective film. Effect of the Invention

[0009] According to one embodiment, the manufacturing cost of a semiconductor device can be reduced. [Brief description of the drawings]

[0010] [Figure 1] 1A is a circuit symbol that typically shows a first power transistor and a temperature sensing diode, and FIG. 1B is a circuit symbol that typically shows a second power transistor, a third power transistor, and a fourth power transistor, respectively. [Diagram 2] FIG. 1 is a diagram showing a configuration in which the basic concept is applied to an improved half-bridge circuit. [Diagram 3]3 is a schematic diagram showing a mounting configuration of a semiconductor device that embodies the improved half-bridge circuit shown in FIG. 2, which is a half-bridge circuit to which the basic concept is applied. FIG. [Figure 4] 1 is a diagram illustrating a schematic diagram of a flow of heat generated by operating power transistors provided in each of a plurality of semiconductor chips. [Diagram 5] FIG. 13 is a diagram showing a mounting configuration of a semiconductor device according to a first modified example. [Figure 6] FIG. 11 is a diagram showing a mounting configuration of a semiconductor device according to a second modified example. [Figure 7] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 8] 8 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 7. [Figure 9] 9 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 8. [Figure 10] 10 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 9. [Figure 11] 11 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 10. [Figure 12] 12 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 11. [Figure 13] FIG. 2A is a diagram showing a planar layout of a first semiconductor chip which is an embedded chip, and FIG. 2B is a diagram showing a planar layout of a second semiconductor chip which is a non-embedded chip. [Figure 14] 13(a) is a cross-sectional view taken along line AA in FIG. 13(a), and (b) is a cross-sectional view taken along line BB in FIG. 13(b). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In all the drawings for explaining the embodiments, the same members are generally designated by the same reference numerals, and the repeated explanations thereof will be omitted. In addition, hatching may be applied even to plan views in order to make the drawings easier to understand.

[0012] The technical idea of ​​this embodiment is a technical idea related to a semiconductor device including a power transistor. In this embodiment, the power transistor is assumed to be a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but the technical idea of ​​this embodiment is not limited to this and can also be applied to a mode in which the power transistor is configured from an IGBT (Insulated Gate Bipolar Transistor).

[0013] <General half-bridge circuit configuration> For example, a half-bridge circuit is used as a motor drive circuit for driving a motor. A typical half-bridge circuit has a DC power supply, a high-side transistor, and a low-side transistor. Specifically, a high-side transistor and a low-side transistor are connected in series to a DC power supply, and a motor is connected in parallel to the low-side transistor. In a typical half-bridge circuit configured in this way, when the high-side transistor is turned on and the low-side transistor is turned off, a current flows from the power supply potential (positive potential) of the DC power supply through the high-side transistor and the motor to the reference potential (0V) of the DC power supply. This allows the motor to rotate.

[0014] On the other hand, if the high-side transistor is turned off and the low-side transistor is turned on from this state, the high-side transistor turns off and no current is supplied to the motor. At this time, a back electromotive force is generated in the motor due to the parasitic inductance contained in the motor, but because the low-side transistor is on, a regenerative current based on the back electromotive force flows in the loop formed by the low-side transistor and the motor connected in parallel to each other. This generates a regenerative brake in the motor, and the motor stops quickly without spinning freely. Note that if the high-side transistor is turned on and the low-side transistor is turned off from a state in which current is flowing through the motor, and both the high-side transistor and the low-side transistor are turned off, the motor will spin freely and stop.

[0015] In this manner, a typical half-bridge circuit is configured.

[0016] Here, for example, the low-side transistor is composed of a first power transistor formed on a first semiconductor chip, and the high-side transistor is composed of a second power transistor formed on a second semiconductor chip separate from the first semiconductor chip.

[0017] At this time, when the power transistor is operated, the semiconductor chip generates heat. As a result, the semiconductor chip becomes hot, and there is a risk that the power transistor will be destroyed. For this reason, a temperature sensing diode for detecting the temperature of the semiconductor chip is formed in the semiconductor chip together with the power transistor. This allows the temperature of the semiconductor chip to be detected by the temperature sensing diode. Therefore, based on the temperature detected by the temperature sensing diode, the operation of the power transistor can be stopped before the temperature of the semiconductor chip rises to a temperature at which the power transistor is destroyed. In other words, by incorporating a temperature sensing diode in the semiconductor chip in which the power transistor is formed, the semiconductor device constituted by the semiconductor chip having the power transistor can be protected.

[0018] Therefore, for example, in a semiconductor device that is a component of a general half-bridge circuit, a temperature sensing diode is formed together with a first power transistor in a first semiconductor chip, and a temperature sensing diode is formed together with a second power transistor in a second semiconductor chip. However, if the temperature sensing diode is built into both the first semiconductor chip and the second semiconductor chip included in the semiconductor device, the manufacturing cost of the semiconductor device increases.

[0019] In view of this, in the present embodiment, a measure is taken to reduce the manufacturing cost of the semiconductor device. The technical concept of this embodiment in which the measure is taken will be described below.

[0020] <Basic Concept of the Embodiment> The basic idea of ​​this embodiment is that the semiconductor device has a first semiconductor chip including a first power transistor and a temperature sensing diode, and a second semiconductor chip including a second power transistor but not including a temperature sensing diode. In other words, the basic idea is that in a semiconductor device having a first semiconductor chip and a second semiconductor chip, a temperature sensing diode is provided only in either the first semiconductor chip or the second semiconductor chip, rather than providing a temperature sensing diode in both the first semiconductor chip and the second semiconductor chip. In other words, the basic idea is that in a semiconductor device including a plurality of semiconductor chips each having a power transistor, a temperature sensing diode is built in only one semiconductor chip. According to this basic idea, it is not necessary to provide a temperature sensing diode in all of the plurality of semiconductor chips each having a power transistor constituting the semiconductor device, so that the manufacturing cost of the semiconductor device can be reduced.

[0021] For example, if a semiconductor device having a first semiconductor chip including a first power transistor and a temperature sensing diode and a second semiconductor chip including a second power transistor but not including a temperature sensing diode is a component of a half-bridge circuit, the first power transistor is one of the high-side transistor and the low-side transistor that constitute the half-bridge circuit, and the second power transistor is the other of the high-side transistor and the low-side transistor that constitute the half-bridge circuit. In other words, the first semiconductor chip incorporating the temperature sensing diode may be either a low-side transistor or a high-side transistor.

[0022] According to this basic concept, since a temperature sensing diode is provided in only one of the multiple semiconductor chips, the manufacturing costs of the semiconductor device, which is a component of the half-bridge circuit, can be reduced compared to a configuration in which temperature sensing diodes are built into all of the multiple semiconductor chips.

[0023] <Improvement of half-bridge circuit> In a typical half-bridge circuit, the low-side transistor and the high-side transistor are each configured on a single semiconductor chip.

[0024] In this regard, for example, a configuration in which the low-side transistor is made up of multiple semiconductor chips and the multiple semiconductor chips (i.e., multiple power transistors formed on the multiple semiconductor chips) are connected in parallel with each other can disperse heat generated by operating the low-side transistor, rather than making the low-side transistor up from a single semiconductor chip. Similarly, by making the high-side transistor up from multiple semiconductor chips, heat generated by operating the high-side transistor can be disperse. As a result, damage to each power transistor can be suppressed, and the reliability of the semiconductor device can be improved.

[0025] <Application of the basic concept to an improved half-bridge circuit> The basic concept can also be applied to the improved half-bridge circuit. That is, on the premise that each of the low-side transistor and the high-side transistor is configured by parallel connection of multiple semiconductor chips (i.e., multiple power transistors formed on multiple semiconductor chips), a temperature sensing diode is provided only on one of the multiple semiconductor chips, instead of providing a temperature sensing diode on all of the multiple semiconductor chips.

[0026] This eliminates the need to provide a temperature sensing diode in each of the semiconductor chips that constitute the semiconductor device, thereby reducing the manufacturing costs of the semiconductor device.

[0027] For example, consider an example of an improved half-bridge circuit in which the low-side transistor is composed of a first power transistor Q1 and a third power transistor Q3 connected in parallel, and the high-side transistor is composed of a second power transistor Q2 and a fourth power transistor Q4 connected in parallel, and apply the basic concept to this example.

[0028] Here, the semiconductor chip on which the first power transistor Q1 is formed is referred to as the first semiconductor chip, the semiconductor chip on which the second power transistor Q2 is formed is referred to as the second semiconductor chip, the semiconductor chip on which the third power transistor Q3 is formed is referred to as the third semiconductor chip, and the semiconductor chip on which the fourth power transistor Q4 is formed is referred to as the fourth semiconductor chip.

[0029] In this case, when the basic concept is applied, a temperature sensing diode is built into only one of the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip, while the other three semiconductor chips do not have a temperature sensing diode. For example, suppose that the first semiconductor chip is provided with a temperature sensing diode, while the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip do not have a temperature sensing diode.

[0030] Fig. 1(a) is a circuit symbol that shows a schematic diagram of a first power transistor Q1. In Fig. 1(a), in addition to the circuit symbol showing the first power transistor, the circuit symbol of a temperature sensing diode that is provided on the first semiconductor chip together with the first power transistor is also shown.

[0031] Here, for example, the first power transistor Q1 is composed of a power MOSFET. In this case, the first power transistor Q1 has a gate, a source, and a drain, and also includes a body diode that is parasitically present due to the device structure. In addition, a temperature sensing diode is formed on the first semiconductor chip on which the first power transistor Q1 is formed, and the temperature sensing diode has an anode and a cathode.

[0032] On the other hand, Fig. 1(b) is a circuit symbol that shows each of the second power transistor Q2, the third power transistor Q3, and the fourth power transistor Q4 in a schematic manner. As shown in Fig. 1(b), these power transistors are not equipped with temperature sensing diodes, so the circuit symbol of the temperature sensing diode is not shown.

[0033] For example, each of the second power transistor Q2, the third power transistor Q3, and the fourth power transistor Q4 is composed of a power MOSFET. In this case, each power transistor has a gate, a source, and a drain, and also includes a body diode that is parasitically present due to the device structure.

[0034] Using the circuit symbols shown in FIG. 1(a) and FIG. 1(b) described above, a configuration in which the basic concept is applied to an improved half-bridge circuit is illustrated in FIG. 2.

[0035] FIG. 2 is a diagram showing a configuration in which the basic concept is applied to an improved half-bridge circuit.

[0036] 2, in the improved half-bridge circuit, the low-side transistor is composed of a first power transistor Q1 and a third power transistor Q3 connected in parallel, while the high-side transistor is composed of a second power transistor Q2 and a fourth power transistor Q4 connected in parallel. Since the low-side transistor and the high-side transistor are connected in series, the first power transistor Q1 and the second power transistor Q2 are connected in series, and the third power transistor Q3 and the fourth power transistor Q4 are also connected in series.

[0037] In this way, by applying the basic concept to the improved half-bridge circuit, it is possible to reduce the on-resistance by improving the half-bridge and to reduce the manufacturing cost of the semiconductor device by the basic concept. That is, according to the semiconductor device having the configuration shown in Fig. 2, it is possible to improve the performance of the semiconductor device and reduce the manufacturing cost of the semiconductor device.

[0038] In the basic concept, a temperature sensing diode is provided in only one semiconductor chip among a plurality of semiconductor chips. In this case, the position where the semiconductor chip provided with the temperature sensing diode is mounted is important. This is because if the semiconductor chip provided with the temperature sensing diode is not placed in an appropriate position, the overheated state of the semiconductor device cannot be properly grasped. For example, if the semiconductor chip provided with the temperature sensing diode can be placed in the hot spot where the temperature is the highest, the overheated state of the semiconductor device can be properly grasped. In other words, if the semiconductor chip provided with the temperature sensing diode is not placed in the hot spot, a semiconductor chip not provided with a temperature sensing diode will be placed in the hot spot, and as a result, even if this semiconductor chip has reached an overheated state, it is difficult to properly detect the above-mentioned overheated state with the temperature sensing diode of the semiconductor chip with the built-in temperature sensing diode placed in a place other than the hot spot. Therefore, in embodying the basic concept, it is desirable to appropriately design the position where the semiconductor chip provided with the temperature sensing diode is mounted. In the following, an embodiment that embodies the basic concept in consideration of this will be described with reference to the drawings.

[0039] <Embodiment> <<Semiconductor device mounting configuration>> FIG. 3 is a schematic diagram showing a mounting configuration of a semiconductor device 100 that embodies the improved half-bridge circuit shown in FIG. 2 and to which the basic concept is applied.

[0040] 3, the semiconductor device 100 has a chip mounting portion DP1 and a chip mounting portion DP2. The chip mounting portion DP1 and the chip mounting portion DP2 are arranged to be aligned in the X direction (second direction). That is, the chip mounting portion DP2 is arranged next to the chip mounting portion DP1 so as to be spaced apart from the chip mounting portion DP1 in a plan view. Each of the chip mounting portion DP1 and the chip mounting portion DP2 extends in the Y direction (first direction) intersecting the X direction.

[0041] Next, a low-side transistor consisting of a parallel connection of a first power transistor Q1 and a third power transistor Q3 shown in Fig. 2 is mounted on the chip mounting part DP1. Specifically, a first semiconductor chip CHP1 on which the first power transistor Q1 and a temperature detection diode are formed, and a third semiconductor chip CHP3 on which the third power transistor Q3 is formed but no temperature detection diode is formed are mounted on the chip mounting part DP1. In particular, as shown in Fig. 3, the first semiconductor chip CHP1 and the third semiconductor chip CHP3 are arranged side by side in a plan view with a space therebetween in the Y direction. For example, each of the first semiconductor chip CHP1 and the third semiconductor chip CHP3 is mounted on the chip mounting part DP1 via a conductive adhesive material typified by solder or silver paste.

[0042] A high-side transistor consisting of a parallel connection of the second power transistor Q2 and the fourth power transistor Q4 shown in Fig. 2 is mounted on the chip mounting part DP2. Specifically, a second semiconductor chip CHP2 having the second power transistor Q2 but no temperature sensing diode formed thereon and a fourth semiconductor chip CHP4 having the fourth power transistor Q4 but no temperature sensing diode formed thereon are mounted on the chip mounting part DP2. In particular, as shown in Fig. 3, the second semiconductor chip CHP2 and the fourth semiconductor chip CHP4 are arranged side by side in a plan view with a space therebetween in the Y direction. For example, each of the second semiconductor chip CHP2 and the fourth semiconductor chip CHP4 is mounted on the chip mounting part DP2 via a conductive adhesive material.

[0043] 3, the second semiconductor chip CHP2 is electrically connected to the chip mounting part DP1 via a clip CLP1 which is a plate-shaped member. For example, the clip CLP1 is connected to the first portion P1 of the chip mounting part DP1 via a conductive adhesive material.

[0044] Similarly, the fourth semiconductor chip CHP4 is electrically connected to the chip mounting part DP1 via a clip CLP2 which is a plate-shaped member. For example, the clip CLP2 is connected to the second portion P2 of the chip mounting part DP1 via a conductive adhesive material.

[0045] Here, the first semiconductor chip CHP1 is disposed between a first portion P1 of the chip mounting portion DP1 to which the clip CLP1 is connected and a second portion P2 of the chip mounting portion DP1 to which the clip CLP2 is connected in a plan view. On the other hand, the third semiconductor chip CHP3 is disposed such that the second portion P2 of the chip mounting portion DP1 is located between the first semiconductor chip CHP1 and the third semiconductor chip CHP3 in a plan view.

[0046] 3, the semiconductor device 100 further includes a conductor pattern portion CP disposed between the chip mounting portion DP1 and the chip mounting portion DP2 in a plan view. The conductor pattern portion CP includes a first extending portion extending in the Y direction and a second extending portion extending in the X direction, and has, for example, an inverted L-shaped planar shape.

[0047] 3, the first semiconductor chip CHP1 is electrically connected to the conductor pattern portion CP via a clip CLP3 which is a plate-shaped member. For example, the clip CLP3 is connected to the third portion P3 of the conductor pattern portion CP via a conductive adhesive material.

[0048] Similarly, the third semiconductor chip CHP3 is electrically connected to the conductor pattern portion CP via a clip CLP4 which is a plate-shaped member. For example, the clip CLP4 is connected to the fourth portion P4 of the conductor pattern portion CP via a conductive adhesive material.

[0049] Here, the clip CLP1 straddles the second semiconductor chip CHP2 and the chip mounting part DP1 so as not to come into physical contact with the conductor pattern part CP. Also, the clip CLP2 straddles the fourth semiconductor chip CHP4 and the chip mounting part DP1 so as not to come into physical contact with the conductor pattern part CP.

[0050] 3, the clip CLP3 is disposed between the clips CLP1 and CLP2 in plan view. Moreover, the clip CLP2 is disposed between the clips CLP3 and CLP4 in plan view.

[0051] 3, the semiconductor device 100 further includes wide leads WLD1 and WLD2 formed integrally with the chip mounting portion DP1, wide leads WLD3 and WLD4 formed integrally with the chip mounting portion DP2, and a plurality of leads LD arranged to be spaced apart from the chip mounting portions DP1 and DP2. At this time, the wide lead WLD1 is arranged adjacent to the first semiconductor chip CHP1 in the X direction, while the wide lead WLD2 is arranged adjacent to the third semiconductor chip CHP3 in the X direction. Also, the wide lead WLD3 is arranged adjacent to the second semiconductor chip CHP2 in the X direction, while the wide lead WLD4 is arranged adjacent to the fourth semiconductor chip CHP4 in the X direction.

[0052] Here, as shown in FIG. 3, the width (width in the Y direction) of each of the wide leads WLD1, WLD2, WLD3 and WLD4 is greater than the width (width in the Y direction) of each of the multiple leads.

[0053] In the manner described above, the semiconductor device 100 in the embodied embodiment is mounted and configured.

[0054] <<Features of the Realization>> Next, features of the embodiment will be described.

[0055] The first feature of the embodiment is that, based on the basic idea of ​​providing a temperature sensing diode only in one of the semiconductor chips provided with a power transistor, the semiconductor chip provided with both the power transistor and the temperature sensing diode is disposed in a location of the semiconductor device that generates a large amount of heat. In other words, the feature is that the semiconductor chip provided with the temperature sensing diode is disposed in the location that is most likely to become hot among the locations where the multiple semiconductor chips are mounted.

[0056] As a result, according to the feature, even if only one of the semiconductor chips is provided with a temperature sensing diode, the semiconductor chip provided with the temperature sensing diode is disposed at the hot spot where the temperature is the highest, so that the overheating state of the semiconductor device can be properly grasped. As a result, it is possible to prevent the semiconductor chip from becoming too hot and destroying the power transistor. In other words, based on the temperature detected by the temperature sensing diode, the operation of the power transistor can be stopped before the temperature of the semiconductor chip rises to a temperature at which the power transistor is destroyed. Thus, according to the feature, it is possible to improve the reliability of the semiconductor device while reducing the manufacturing cost of the semiconductor device by adopting the basic concept.

[0057] Thus, the characteristic point is that a semiconductor chip with a built-in temperature sensing diode is disposed at the hot spot where the temperature becomes the highest. Here, specifically, among the locations where a plurality of semiconductor chips are mounted, the location that is most likely to become hot is the area in FIG. 3 where the first semiconductor chip CHP1 is mounted. That is, as shown in FIG. 3, in plan view, it is the area where the first semiconductor chip CHP1 is disposed between the first portion P1 of the chip mounting part DP1 to which the clip CLP1 is connected and the second portion P2 of the chip mounting part DP1 to which the clip CLP2 is connected. In the following, it will be explained that the above-mentioned area is the hot spot that is most likely to become hot in the semiconductor device 100 having the mounting configuration shown in FIG. 3.

[0058] Fig. 4 is a diagram showing, for example, a schematic diagram of the flow of heat generated by operating the power transistors provided in each of the multiple semiconductor chips. In Fig. 4, the arrows indicate the flow of heat, and the thicker the arrow, the larger the heat flow. Looking at Fig. 4 in consideration of this, it can be seen that the tips of the arrows are concentrated from various directions in the area where the first semiconductor chip CHP1 is mounted.

[0059] For example, it can be seen that the arrow indicating the heat generated in the second semiconductor chip CHP2 flowing in through the clip CLP1, the arrow indicating the heat generated in the fourth semiconductor chip CHP4 flowing in through the clip CLP2, and the arrow indicating the heat generated in the third semiconductor chip CHP3 traveling through the chip mounting part DP1 are concentrated in the area where the first semiconductor chip CHP1 is mounted. Considering that the first semiconductor chip CHP1 itself also generates heat, this means that heat is likely to gather in the area where the semiconductor chip CHP1 is mounted, and therefore the first semiconductor chip CHP1 is likely to become hot.

[0060] Therefore, in the embodiment, a temperature sensing diode is mounted on the first semiconductor chip CHP1 mounted in the region between the first portion P1 and the second portion P2. That is, as shown in FIG. 4, the region between the first portion P1 and the second portion P2 is a hot spot where the temperature is the highest, and the first semiconductor chip CHP1 provided with a temperature sensing diode is disposed in this hot spot. As a result, in the embodiment, the hot spot of the semiconductor device 100 can be monitored by the temperature sensing diode. In other words, in the embodiment, the overheated state of the semiconductor device 100 can be appropriately grasped. As a result, in the semiconductor device 100 in the embodiment, it is possible to prevent the power transistor provided in the first semiconductor chip CHP1 disposed in the hot spot from being destroyed.

[0061] Next, a second feature of the embodiment is that, for example, as shown in Figures 3 and 4, a wide lead is provided next to each of the multiple semiconductor chips in the X direction. In other words, the second feature is that there is a wide lead corresponding to each of the multiple semiconductor chips, and each of the multiple semiconductor chips and the wide lead are arranged on a straight line in the X direction. For example, in Figures 3 and 4, a wide lead WLD1 is arranged next to the first semiconductor chip CHP1, while a wide lead WLD2 is arranged next to the third semiconductor chip CHP3. Similarly, in Figures 3 and 4, a wide lead WLD3 is arranged next to the second semiconductor chip CHP2, while a wide lead WLD4 is arranged next to the fourth semiconductor chip CHP4.

[0062] Here, the width of the wide lead in the Y direction is larger than the width of the lead LD in the Y direction. As a result, according to the second feature, as shown in Fig. 4, heat generated in each of the multiple semiconductor chips can be efficiently dissipated from the wide lead with a larger width in the Y direction that is arranged adjacently. As a result, according to the embodiment, the reliability of the semiconductor device 100 can be improved.

[0063] <<Variation 1>> FIG. 5 is a diagram showing a mounting configuration of a semiconductor device 100A in the first modification.

[0064] As shown in Fig. 5, in the semiconductor device 100A, the distance between the first semiconductor chip CHP1 and the third semiconductor chip CHP3 mounted on the chip mounting portion DP1 is greater than the distance between the first semiconductor chip CHP1 and the third semiconductor chip CHP3 in the embodiment shown in Fig. 3. In particular, as shown in Fig. 5, in this modification 1, a first portion connecting the clip CLP1 and the chip mounting portion DP1 and a second portion connecting the clip CLP2 and the chip mounting portion DP1 are present between the first semiconductor chip CHP1 and the third semiconductor chip CHP3 in a plan view. At this time, the first semiconductor chip CHP1 is provided with a temperature sensing diode together with a power transistor, while the second semiconductor chip CHP2, the third semiconductor chip CHP3, and the fourth semiconductor chip CHP4 are provided with power transistors but are not provided with a temperature sensing diode.

[0065] In this way, the basic idea of ​​this embodiment can be embodied not only as in the embodiment shown in FIG. 3, but also as in the present modified example 1 shown in FIG.

[0066] <<Variation 2>> In the improved half-bridge circuit, the low-side transistor is configured by a parallel connection of power transistors provided on each of a plurality of semiconductor chips, and the high-side transistor is configured by a parallel connection of power transistors provided on each of a plurality of semiconductor chips. In this case, in the above-mentioned embodiment, an example is described in which two semiconductor chips are used as the plurality of semiconductor chips. Specifically, as shown in FIG. 3, the low-side transistor is configured by a parallel connection of power transistors provided on each of the first semiconductor chip CHP1 and the third semiconductor chip CHP3, and the high-side transistor is configured by a parallel connection of power transistors provided on each of the second semiconductor chip CHP2 and the fourth semiconductor chip CHP4.

[0067] In this regard, in this modified example, an example in which three semiconductor chips are used as the multiple semiconductor chips will be described. For example, the low-side transistor is configured by a parallel connection of power transistors provided on the first semiconductor chip CHP1, the third semiconductor chip CHP3, and the fifth semiconductor chip CHP5, respectively, and the high-side transistor is configured by a parallel connection of power transistors provided on the second semiconductor chip CHP2, the fourth semiconductor chip CHP4, and the sixth semiconductor chip CHP6, respectively.

[0068] FIG. 6 is a diagram showing a mounting configuration of a semiconductor device 100B in the second modification.

[0069] 6, three semiconductor chips, a first semiconductor chip CHP1, a third semiconductor chip CHP3, and a fifth semiconductor chip CHP5, are mounted on the chip mounting part DP1. On the other hand, three semiconductor chips, a second semiconductor chip CHP2, a fourth semiconductor chip CHP4, and a sixth semiconductor chip CHP6, are mounted on the chip mounting part DP2.

[0070] As shown in FIG. 6, in a plan view, the first semiconductor chip CHP1 is provided between a first portion P1 connecting the clip CLP1 and the chip mounting portion DP1 and a second portion P2 connecting the clip CLP2 and the chip mounting portion DP1.

[0071] Similarly, in plan view, the fifth semiconductor chip CHP5 is provided between the fifth portion P5 connecting the clip CLP5 and the chip mounting portion DP1 and the first portion P1 connecting the clip CLP1 and the chip mounting portion DP1.

[0072] 6, in plan view, the clip CLP6 is provided between the clip CLP5 and the clip CLP1, and connects the fifth semiconductor chip CHP5 and the sixth portion P6 of the conductor pattern portion CP. Similarly, in plan view, the clip CLP3 is provided between the clip CLP1 and the clip CLP2, and connects the first semiconductor chip CHP1 and the third portion P3 of the conductor pattern portion CP.

[0073] 6, the first semiconductor chip CHP1 is provided between the first portion P1 and the second portion P2, and the fifth semiconductor chip CHP5 is provided between the fifth portion P5 and the first portion P1. Therefore, not only the first semiconductor chip CHP1 but also the fifth semiconductor chip CHP5 are disposed in hot spots where the temperature increases.

[0074] For this reason, from the viewpoint of providing a temperature sensing diode in a semiconductor chip arranged at a hot spot, for example, not only a power transistor and a temperature sensing diode may be provided in the first semiconductor chip CHP1, but also a power transistor and a temperature sensing diode may be provided in the fifth semiconductor chip CHP5. As a result, in the semiconductor device 100B having a plurality of hot spots, each of the plurality of hot spots can be monitored by a temperature sensing diode, thereby improving the reliability of the semiconductor device 100B.

[0075] 6, the first semiconductor chip CHP1 is not only provided between the first portion P1 and the second portion P2, but is also disposed between the fifth semiconductor chip CHP5 and the third semiconductor chip CHP3. Therefore, the first semiconductor chip CHP1 is affected by both the heat generated by the third semiconductor chip CHP3 and the heat generated by the fifth semiconductor chip CHP5. As a result, the temperature of the first semiconductor chip CHP1 is likely to increase.

[0076] Therefore, for example, the distance L2 between the first semiconductor chip CHP1 and the third semiconductor chip CHP3 may be made longer than the distance L1 between the first semiconductor chip CHP1 and the fifth semiconductor chip CHP5. In this case, the effect of heat from the third semiconductor chip CHP3 can be reduced, and the temperature rise of the first semiconductor chip CHP1 can be mitigated. Therefore, the reliability of the semiconductor device 100B can be improved.

[0077] <<Method of manufacturing a semiconductor device according to an embodiment>> Next, a method for manufacturing a semiconductor device according to an embodiment will be described.

[0078] First, as shown in Fig. 7, a lead frame LF having chip mounting parts DP1, DP2, and conductor pattern parts CP is prepared. Then, a conductive adhesive 10 made of, for example, solder or silver paste is applied to a part of the chip mounting part DP1 and a part of the chip mounting part DP2. Also, a first semiconductor chip CHP1 including a power transistor and a temperature sensing diode, a second semiconductor chip CHP2 including a power transistor but not including a temperature sensing diode, a third semiconductor chip CHP3, and a fourth semiconductor chip CHP4 are prepared. That is, a chip set including the first semiconductor chip CHP1, the second semiconductor chip CHP2, the third semiconductor chip CHP3, and the fourth semiconductor chip CHP4 is prepared.

[0079] Next, as shown in FIG. 8, by using a die bonding device, a first semiconductor chip CHP1 and a third semiconductor chip CHP3 are mounted on the chip mounting portion DP1 via a conductive adhesive 10, and a second semiconductor chip CHP2 and a fourth semiconductor chip CHP4 are mounted on the chip mounting portion DP2 via a conductive adhesive 10.

[0080] Then, as shown in FIG. 9, conductive adhesive 20 is applied onto a partial area of ​​the chip mounting portion DP1, a partial area of ​​the conductor pattern portion CP, the first semiconductor chip CHP1, the second semiconductor chip CHP2, the third semiconductor chip CHP3 and the fourth semiconductor chip CHP4.

[0081] 10, multiple clips are mounted. Specifically, the second semiconductor chip CHP2 and the first portion P1 of the chip mounting portion DP1 are connected by a clip CLP1, and the fourth semiconductor chip CHP4 and the second portion P2 of the chip mounting portion DP1 are connected by a clip CLP2. Furthermore, the first semiconductor chip CHP1 and the third portion P3 of the conductor pattern portion CP are connected by a clip CLP3, and the third semiconductor chip CHP3 and the fourth portion P4 of the conductor pattern portion CP are connected by a clip CLP4.

[0082] 11, by using a wire bonding device, the first semiconductor chip CHP1 and the leads LD are connected by bonding wires W, and the third semiconductor chip CHP3 and the leads LD are connected by bonding wires W. Similarly, the second semiconductor chip CHP2 and the leads LD are connected by bonding wires W, and the fourth semiconductor chip CHP4 and the leads LD are connected by bonding wires W.

[0083] Thereafter, as shown in Fig. 12, the sealing body MR is formed by resin sealing (molding). Next, burrs are removed, and a plating layer is formed as necessary on the outer lead portion of the lead LD exposed from the sealing body MR. Next, after a mark is formed on the surface of the sealing body MR, the lead LD is cut at a predetermined position outside the sealing body MR, thereby separating the sealing body MR from the frame of the lead frame LF. Then, the outer lead portion of the lead LD protruding from the sealing body MR is bent.

[0084] In this manner, the semiconductor device according to the embodied embodiment can be manufactured.

[0085] <<The need for ingenuity>> In the above-mentioned method for manufacturing a semiconductor device, a semiconductor chip including a power transistor and a temperature sensing diode (hereinafter, sometimes referred to as an embedded chip) and a semiconductor chip including a power transistor but not including a temperature sensing diode (hereinafter, sometimes referred to as a non-embedded chip) are used. These embedded chips and non-embedded chips are provided as a chip set by a device manufacturer to an assembly manufacturer, for example, and the assembly manufacturer uses the provided chip set to manufacture a semiconductor device. At this time, the chip set includes an embedded chip and a non-embedded chip, but if the embedded chip and the non-embedded chip cannot be distinguished from each other in appearance, a normal semiconductor device cannot be manufactured. Therefore, in order to realize the basic idea, it is necessary to make the embedded chip and the non-embedded chip distinguishable from each other in appearance. That is, a device for distinguishing the embedded chip and the non-embedded chip from each other in appearance is desired.

[0086] The following describes these improvements.

[0087] <<Measures for distinguishing appearance>> FIG. 13(a) is a diagram showing a planar layout of a first semiconductor chip CHP1 which is an embedded chip, and FIG. 13(b) is a diagram showing a planar layout of a second semiconductor chip CHP2 (third semiconductor chip CHP3, fourth semiconductor chip CHP4) which is a non-embedded chip.

[0088] 13(a), the first semiconductor chip CHP1 has a plurality of pads exposed from the polyimide resin film PI. Specifically, the first semiconductor chip CHP1 has a source pad SP, a Kelvin pad KLP, a gate pad GP, an anode pad AP, and a cathode pad KP on the surface thereof so as to be exposed from the polyimide resin film PI.

[0089] 13(b), the second semiconductor chip CHP2 has a plurality of pads exposed from the polyimide resin film PI and a plurality of pads covered with the polyimide resin film PI. Specifically, the second semiconductor chip CHP2 has a source pad SP, a Kelvin pad KLP, and a gate pad GP on its surface so as to be exposed from the polyimide resin film PI, while the second semiconductor chip CHP2 has an anode pad AP and a cathode pad KP on its surface so as to be covered with the polyimide resin film PI.

[0090] In this way, in the first semiconductor chip CHP1, which is an embedded chip, the anode pad AP and the cathode pad KP are exposed from the polyimide resin film PI. In contrast, in the second semiconductor chip CHP2, which is a non-embedded chip, the anode pad AP and the cathode pad KP are covered with the polyimide resin film PI. In this respect, the first semiconductor chip CHP1 and the second semiconductor chip CHP2 have different appearances, which allows the first semiconductor chip CHP1 and the second semiconductor chip CHP2 to be distinguished from each other in appearance. That is, in a chip set having an embedded chip and a non-embedded chip, the embedded chip and the non-embedded chip can be distinguished from each other depending on whether the anode pad AP and the cathode pad KP are exposed. As a result, according to this embodiment, it is possible to suppress erroneous recognition of an embedded chip and a non-embedded chip at an assembly manufacturer to which the chip set is provided.

[0091] As described above, the first semiconductor chip CHP1, which is an embedded chip, includes a temperature sensing diode and therefore uses the anode pad AP and the cathode pad KP. For this reason, in the first semiconductor chip CHP1, the anode pad AP and the cathode pad KP are exposed from the polyimide resin film PI.

[0092] In contrast, the second semiconductor chip CHP2, which is a non-embedded chip, does not include a temperature sensing diode, and therefore the anode pad AP and cathode pad KP are not used. For this reason, in the second semiconductor chip CHP2, the anode pad AP and cathode pad KP are covered with the polyimide resin film PI.

[0093] In the first place, since the anode pad AP and the cathode pad KP are not used in the second semiconductor chip CHP2, which is a non-built-in chip, it is also considered that there is no need to form the anode pad AP and the cathode pad KP. In this regard, for the reasons described below, even in the second semiconductor chip CHP2, which is a non-built-in chip that does not have a temperature sensing diode, the unnecessary anode pad AP and cathode pad KP are provided.

[0094] In other words, if the anode pad AP and cathode pad KP are not provided in the non-embedded chip, the non-embedded chip will have a different device structure from the embedded chip that has the anode pad AP and cathode pad KP. For example, in this case, the presence or absence of the anode pad AP and cathode pad KP will cause differences in the electric field distribution and parasitic capacitance between the embedded chip and the non-embedded chip, resulting in different device characteristics between the embedded chip and the non-embedded chip. In other words, since it is desirable for the device characteristics to be equivalent in the embedded chip and the non-embedded chip, it is desirable to avoid differences in device characteristics caused by the presence or absence of the anode pad AP and cathode pad KP as much as possible.

[0095] Therefore, in the embodied embodiment, even though the anode pad AP and cathode pad KP are unnecessary in a chip that does not have a built-in chip, the anode pad AP and cathode pad KP are provided in the chip that does not have a built-in chip from the viewpoint of suppressing deviation in device characteristics. In other words, the technical significance of providing the unnecessary anode pad AP and cathode pad KP in a chip that does not have a built-in chip is to suppress deviation in device characteristics between the built-in chip and the non-built-in chip that is caused by the presence or absence of the anode pad AP and cathode pad KP.

[0096] Therefore, in the embodiment, not only the built-in chip but also the non-built-in chip is provided with an anode pad AP and a cathode pad KP, while in the non-built-in chip, the anode pad AP and the cathode pad KP are covered with a polyimide resin film PI so that the built-in chip and the non-built-in chip can be distinguished from each other in appearance. As a result, in the embodiment, the built-in chip and the non-built-in chip can be distinguished from each other in appearance while suppressing the difference in device characteristics between the built-in chip and the non-built-in chip. Therefore, in the embodiment, it is possible to provide a chip set including a built-in chip and a non-built-in chip that can be distinguished from each other in appearance. In other words, in the embodiment, it is possible to realize a method for providing a chip set that can suppress erroneous recognition of the built-in chip and the non-built-in chip.

[0097] <<Device structure>> First, the device structure of the built-in chip will be described with reference to the drawings.

[0098] FIG. 14(a) is a cross-sectional view taken along line AA in FIG. 13(a).

[0099] 14(a), the first semiconductor chip CHP1, which is an embedded chip, has, for example, a semiconductor substrate SUB made of a silicon substrate, an insulating film IF1 formed on the semiconductor substrate SUB, and an insulating film IF2 formed on the insulating film IF1. The first semiconductor chip CHP1 has an anode pad AP formed on the insulating film IF2, a cathode pad KP formed on the insulating film IF2, and a polyimide resin film PI, which is a protective film formed on the insulating film IF2. Here, the first semiconductor chip CHP1 further includes the following components. That is, the first semiconductor chip CHP1 has a p-type impurity region and an n-type impurity region, a polysilicon film PF, which is a semiconductor layer formed on the insulating film IF1 and is a component of a temperature detection diode, a via VA1 formed in the insulating film IF2 and electrically connecting the anode pad AP and the polysilicon film PF to each other, and a via VA2 formed in the insulating film IF2 and electrically connecting the cathode pad KP and the polysilicon film PF to each other.

[0100] At this time, the via VA1 is connected to the polysilicon film PF in the p-type impurity region, while the via VA2 is connected to the polysilicon film PF in the n-type impurity region. In other words, the polysilicon film PF has a p-type polysilicon film PPF corresponding to the p-type impurity region and an n-type polysilicon film NPF corresponding to the n-type impurity region, and the via VA1 is connected to the p-type polysilicon film PPF, while the via VA2 is connected to the n-type polysilicon film NPF.

[0101] As shown in FIG. 14(a), in the first semiconductor chip CHP1, the anode pad AP is exposed in an opening OP1 of the polyimide resin film PI, and the cathode pad KP is exposed in an opening OP2 of the polyimide resin film PI.

[0102] In this manner, the device structure of the first semiconductor chip CHP1 is realized.

[0103] Next, the device structure of a non-embedded chip will be described with reference to the drawings.

[0104] FIG. 14(b) is a cross-sectional view taken along line BB in FIG. 13(b).

[0105] 14(b), the second semiconductor chip CHP2 which is a non-embedded chip has, for example, a semiconductor substrate SUB made of a silicon substrate, an insulating film IF1 formed on the semiconductor substrate SUB, and an insulating film IF2 formed on the insulating film IF1. The second semiconductor chip CHP2 has an anode pad AP formed on the insulating film IF2, a cathode pad KP formed on the insulating film IF2, and a polyimide resin film PI which is a protective film formed on the insulating film IF2.

[0106] At this time, as shown in FIG. 14(b), in the second semiconductor chip CHP2, the anode pads AP and the cathode pads KP are each covered with the polyimide resin film PI so as not to be exposed from the polyimide resin film PI.

[0107] In this manner, the device structure of the second semiconductor chip CHP2 is realized.

[0108] 14(a), the first semiconductor chip CHP1 includes a temperature sensing diode, and therefore has a polysilicon film PF corresponding to the temperature sensing diode, and this polysilicon film PF is composed of a p-type polysilicon film PPF and an n-type polysilicon film NPF. In the first semiconductor chip CHP1, the anode pad AP is connected to the p-type polysilicon film PPF through a via VA1, while the cathode pad KP is connected to the n-type polysilicon film NPF through a via VA2.

[0109] 14(b), the second semiconductor chip CHP2 does not include a temperature sensing diode, and therefore the polysilicon film PF corresponding to the temperature sensing diode, the via VA1 connected to the anode pad AP, and the via VA2 connected to the cathode pad KP are not formed in the second semiconductor chip CHP2. That is, in the second semiconductor chip CHP2, each of the anode pad AP and the cathode pad KP functions as a "dummy pad."

[0110] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention.

[0111] In the above embodiment, a power MOSFET is used as an example of a power transistor, but the technical ideas of the above embodiment are not limited to this and can be widely applied to cases where an IGBT is used. In this case, the following terms are replaced.

[0112] "Source" → "Emitter" "Source pad" → "Emitter pad" "Drain" → "Collector" [Explanation of symbols]

[0113] 10 Conductive adhesive 20 Conductive adhesive 100 Semiconductor device 100A Semiconductor Device 100B Semiconductor device AP Anode Pad CHP1 First semiconductor chip CHP2 Second semiconductor chip CHP3 3rd Semiconductor Chip CHP4 4th semiconductor chip CHP5 5th semiconductor chip CHP6 6th semiconductor chip CLP1 Clip CLP2 Clip CLP3 Clip CLP4 Clip CLP5 Clip CLP6 Clip CP Conductor pattern section DP1 chip mounting area DP2 chip mounting area GP Gate Pad IF1 insulating film IF2 insulating film KLP Kelvin Pad KP Kelvin Pad LD Lead LF Lead Frame MR sealed body NPF n-type polysilicon film OP1 opening OP2 opening PF Polysilicon film PI Polyimide resin film PPF p-type polysilicon film P1 Part 1 P2 2nd part P3 3rd part P4 Part 4 P5 Part 5 P6 Part 6 Q1 First power transistor Q2 Second power transistor Q3 3rd power transistor Q4 Fourth power transistor SP Source Pad SUB Semiconductor Substrate VA1 Via VA2 Via W Bonding Wire WLD1 Wide lead WLD2 Wide lead WLD3 Wide lead WLD4 Wide lead WLD5 Wide Lead WLD6 Wide lead

Claims

1. A first chip mounting portion; a second chip mounting portion disposed adjacent to and spaced apart from the first chip mounting portion in a plan view; a first semiconductor chip mounted on the first chip mounting portion and including a first power transistor and a temperature sensing diode; a second semiconductor chip mounted on the second chip mounting portion and including a second power transistor but not including a temperature sensing diode; a third semiconductor chip mounted on the first chip mounting portion and including a third power transistor but not including a temperature sensing diode; a fourth semiconductor chip mounted on the second chip mounting portion and including a fourth power transistor but not including a temperature sensing diode; a conductor pattern portion disposed between the first chip mounting portion and the second chip mounting portion; Equipped with the second semiconductor chip is electrically connected to the first chip mounting portion via a first plate-like member, the fourth semiconductor chip is electrically connected to the first chip mounting portion via a second plate-like member, the first semiconductor chip is electrically connected to the conductor pattern portion via a third plate-like member; A semiconductor device, wherein, in a planar view, the longitudinal axis of the first plate-shaped member, the longitudinal axis of the second plate-shaped member, and the longitudinal axis of the third plate-shaped member are parallel to each other, and the longitudinal axis of the third plate-shaped member is disposed between the longitudinal axis of the first plate-shaped member and the longitudinal axis of the second plate-shaped member.

2. 2. The semiconductor device according to claim 1, the semiconductor device is a component of a half-bridge circuit, the first power transistor is one of a high-side transistor and a low-side transistor that configure the half-bridge circuit, the second power transistor is the other of the high-side transistor and the low-side transistor that form the half-bridge circuit.

3. 3. The semiconductor device according to claim 2, each of the first power transistor and the third power transistor constitutes the low-side transistor of the half-bridge circuit; each of the second power transistor and the fourth power transistor constitutes the high-side transistor of the half-bridge circuit; the first power transistor is connected in series with the second power transistor; the third power transistor is connected in series with the fourth power transistor; the first power transistor is connected in parallel with the third power transistor; the second power transistor is connected in parallel with the fourth power transistor.

4. 4. The semiconductor device according to claim 3, A semiconductor device wherein, in a planar view, the first semiconductor chip is arranged between a first portion of the first chip mounting portion to which the first plate-shaped member is connected and a second portion of the first chip mounting portion to which the second plate-shaped member is connected.

5. 5. The semiconductor device according to claim 4, the third semiconductor chip is electrically connected to the conductor pattern portion via a fourth plate-like member, the first plate-like member straddles the second semiconductor chip and the first chip mounting portion so as not to come into physical contact with the conductor pattern portion; the second plate-like member straddles the fourth semiconductor chip and the first chip mounting portion so as not to come into physical contact with the conductor pattern portion, The second plate-shaped member is disposed between the third plate-shaped member and the fourth plate-shaped member in a plan view.

6. 6. The semiconductor device according to claim 5, The semiconductor device further comprises: a first wide lead formed integrally with the first chip mounting portion; a second wide lead formed integrally with the first chip mounting portion; a third wide lead formed integrally with the second chip mounting portion; a fourth wide lead formed integrally with the second chip mounting portion; a plurality of leads arranged so as to be spaced apart from the first chip mounting portion and the second chip mounting portion; and each of the first chip mounting portion and the second chip mounting portion extends in a first direction in a plan view; the second chip mounting portion is disposed adjacent to the first chip mounting portion in a second direction intersecting the first direction; the first wide lead is disposed adjacent to the first semiconductor chip in the second direction; the second wide lead is disposed adjacent to the third semiconductor chip in the second direction; the third wide lead is disposed adjacent to the second semiconductor chip in the second direction; the fourth wide lead is disposed adjacent to the fourth semiconductor chip in the second direction; a width of each of the first wide lead, the second wide lead, the third wide lead, and the fourth wide lead is greater than a width of each of the plurality of leads;

7. 2. The semiconductor device according to claim 1, Each of the first semiconductor chip and the second semiconductor chip includes: a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a second insulating film formed on the first insulating film; a first pad formed on the second insulating film; a second pad formed on the second insulating film; a protective film formed on the second insulating film; and The first semiconductor chip further includes: a semiconductor layer having a first impurity region of a first conductivity type and a second impurity region of a second conductivity type, the semiconductor layer being formed on the first insulating film and being a component of the temperature sensing diode; a first via formed in the second insulating film, electrically connecting the first pad and the semiconductor layer to each other; a second via formed in the second insulating film, electrically connecting the second pad and the semiconductor layer to each other; and the first via is connected to the semiconductor layer in the first impurity region; the second via is connected to the semiconductor layer in the second impurity region; In the first semiconductor chip, the first pad is exposed in a first opening of the protective film, and the second pad is exposed in a second opening of the protective film; In the second semiconductor chip, the first pads and the second pads are each covered with the protective film so as not to be exposed from the protective film.

8. 8. The semiconductor device according to claim 7, the semiconductor layer is a polysilicon film, the first conductivity type is p-type, The second conductivity type is n-type.

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