Integrated component including capacitor and discrete varistor

Abstract

To provide an integrated component and a method of forming the same that result in improved, and miniaturized and increased functionality and / or operational characteristics.SOLUTION: In a multiterminal multilayer device 600 being an integrated component, a varistor 660 has external varistor terminations 662, 664, and a lead configuration arrangement is used to place a device 600 and a varistor 660 parallel to each other. More specifically, leads 648, 650, and 652 are respectively attached to external (capacitor device) terminations 604, 608, and 606 of the device 600, while the leads 648 and 652 are respectively connected to the external side (varistor) terminations 662 and 664 of the varistor 660.SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is incorporated by reference in its entirety and has a filing date of 2019. This application claims the benefit of U.S. Provisional Patent Application No. 62 / 838,410, filed April 25, 2007. [Background technology]

[0002]

[0002] For some time now, the design of various electronic components has been driven by a trend toward miniaturization as well as increased functionality. This trend has been driven by a general industry trend towards ever smaller electronic components with improved operating characteristics. While some applications can equally benefit from multiple components, the amount of space that such electronic components can occupy, for example on a circuit board, is severely limited.

[0003]

[0003] Multilayer ceramic devices such as multilayer ceramic capacitors and varistors are stacked. It may consist of multiple dielectric electrode layers arranged in a folded configuration. During fabrication, the layers may be pressed together to form a monolithic stack structure.

[0004]

[0004] Accordingly, improved miniaturization and increased functionality and / or operating characteristics are desired. It would be advantageous if a device and corresponding method could be provided which results in: Summary of the Invention [Means for solving the problem]

[0005] According to one embodiment of the present invention, an integrated device having a capacitor and a varistor function is provided. The integrated component may include a multilayer capacitor including a first active terminal, a second active terminal, at least one ground terminal, and a pair of capacitors connected in series between the first active terminal and the second active terminal. The integrated component may include a discrete varistor with a first external varistor terminal connected to the first active terminal of the multilayer capacitor and a second external varistor terminal connected to the second active terminal.

[0006] According to another embodiment of the present invention, an integrated structure having a capacitor and a varistor function is provided. A method for forming a component may include providing a multilayer capacitor body including electrodes forming a pair of capacitors; forming a first active terminal, a second active terminal, and at least one ground terminal external to the multilayer capacitor body such that the pair of capacitors is connected in series between the first active terminal and the second active terminal; and stacking a discrete varistor with the multilayer capacitor body such that a first varistor terminal of the discrete varistor is connected to the first active terminal and a second varistor terminal is connected to the second active terminal.

[0007]

[0007] Other features and aspects of the present invention are discussed in greater detail below.

[0008] A complete and effective disclosure of the subject matter of this disclosure, including the best mode thereof, directed to one of ordinary skill in the art. The disclosure is described herein with reference to the accompanying drawings in which: [Brief description of the drawings]

[0008] [Figure 1A]

[0009] 1 is an external perspective view of an exemplary embodiment of a multi-terminal, multi-layer device according to the subject matter of the present disclosure, for use in SMD configurations and the like. FIG. [Figure 1B]

[0010] FIG. 1B shows a first electrode layer of the device of FIG. 1A. [Figure 1C]

[0011] FIG. 1B shows a second electrode layer of the device of FIG. 1A. [Figure 1D]

[0012] FIG. 1B illustrates a stack of alternating first and second electrode layers of the device of FIG. 1A. [Figure 1E]

[0013] FIG. 1B shows the device of FIG. 1A further including leads connected to respective external terminals of the device. [Figure 1F]

[0014] FIG. 1B is a schematic diagram of the device of FIG. 1A. [Figure 2A]

[0015] FIG. 1B shows an alternative first electrode layer of the device of FIG. 1A, in which the second electrode layer comprises a T-shaped electrode. [Figure 2B] FIG. 1B shows an alternative second electrode layer of the device of FIG. 1A, in which the second electrode layer comprises a T-shaped electrode. [Figure 2C]

[0016] FIG. 2C illustrates a stack of alternating first and second electrode layers as illustrated in FIGS. 2A and 2B. [Figure 3A]

[0017] FIG. 2 illustrates an integrated component including a multilayer capacitor and a discrete varistor in a stacked configuration in accordance with the subject matter of the present disclosure. [Figure 3B]

[0018] FIG. 3B is a schematic diagram of the device of FIG. 3A. [Figure 3C]

[0019] FIG. 2 is an exterior perspective view of another embodiment of an integrated component in accordance with the subject matter of the present disclosure. [Figure 4] 1 is a flow chart of a method for forming an integrated component having capacitor and varistor functionality according to an aspect of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0020] Repeat use of reference characters throughout the present specification and the accompanying drawings is intended to represent the same or similar features, elements or steps thereof.

[0021] Reference will now be made in detail to various embodiments of the invention, one or more examples of which are set forth below. Each example is provided as an explanation of the invention, not a limitation of the invention. Indeed, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope or spirit of the invention. For example, features illustrated or described as part of one embodiment can be used in another embodiment to yield yet a further embodiment. It is therefore intended that the present invention cover such modifications and variations as come within the scope of the appended claims and their equivalents.

[0010]

[0022] Generally speaking, the present invention relates to an integrated device including a multilayer capacitor and a discrete varistor. Without intending to be limited by theory, a capacitor is an electrical component that stores electrical energy in an electric field. Without intending to be limited by theory, a varistor is an electrical component that has an electrical resistance that can change with an applied voltage, thereby making it a voltage-dependent resistor.

[0011]

[0023] Combining a capacitor and varistor can provide filtering and EMI and / or EMI / ESD circuit protection in a single package, which can be particularly useful where space is limited. The present invention can be particularly useful in automotive applications, such as motor start-stop applications.

[0012]

[0024] The integrated component multilayer capacitor may have a split feedthrough type construction, with a first active terminal, a second active terminal, and a The semiconductor device may include a first active terminal and a pair of capacitors connected in series between the first active terminal and the second active terminal. The capacitors may be formed by internal electrodes separated by a dielectric layer.

[0013]

[0025] The discrete varistor may include a first external varistor terminal connected to the first active terminal of the multilayer capacitor and a second external varistor terminal connected to the second active terminal. The layers may be stacked together to form a single monolithic integrated component. In some embodiments, the leads may be connected to external terminals and / or the integrated component may be overmolded. Thus, the overmolded layer may encapsulate the discrete varistors and the multilayer capacitors.

[0014]

[0026] The multilayer capacitor may include at least one ground terminal located external to the ceramic body. The first plurality of electrode layers may be disposed within the body and connected to the first active terminal. The second plurality of electrode layers may be disposed within the body and connected to the second active terminal. The third plurality of electrode layers may be connected to the ground terminal and may be capacitively coupled with each of the first and second plurality of electrode layers to form a split feed-through type structure. The first capacitor may be formed in a first overlap region between the first and third plurality of electrode layers. The second capacitor may be formed in a second overlap region between the second and third plurality of electrode layers.

[0015]

[0027] In one embodiment, the first capacitor may have a first capacitance and the second capacitor may have a second capacitance. In some embodiments, the first and second overlap areas may be approximately equal, such that the second capacitance may be approximately equal to the first capacitance. However, in other embodiments, the first and second overlap areas may be different, such that the first capacitance may be greater or less than the second capacitance.

[0016]

[0028] For example, at least one of the first capacitances of the second capacitances can be in the range of about 10 nF to about 3 μF, in some embodiments in the range of about 200 nF to about 2 μF, and in some embodiments in the range of about 400 nF to about 1.5 μF. The second capacitance can be in the range of about 5% to about 500%, in some embodiments in the range of about 10% to about 300%, in some embodiments in the range of about 25% to about 200%, and in some embodiments in the range of about 50% to about 150% of the first capacitance.

[0017]

[0029] In some embodiments, the third plurality of electrode layers can be generally cross-shaped and can be connected to a pair of opposing ground terminals. For example, the third plurality of electrode layers can each include a pair of opposing edges. One of the opposing edges can be connected to a first ground terminal and the other of the opposing edges can be connected to a second ground terminal.

[0018]

[0030] The monolithic body may not include an additional capacitor formed within the monolithic body. For example, the first, second, and third pluralities of electrodes may be comprised of electrode stacks that extend through a majority of the thickness of the monolithic body. For example, the ratio of the thickness of the electrode stacks to the thickness of the monolithic body may range from about 0.5 to about 0.97, in some embodiments, from about 0.6 to about 0.95, and in some embodiments, from about 0.7 to about 0.9.

[0019]

[0031] In some embodiments, the components may include one or more leads connected to external terminals. For example, the first and second leads may be coupled to the first and second active terminals, respectively. The third lead and / or the fourth lead may be coupled to a ground terminal. The components are overmolded such that the leads protrude from the overmolded package to connect the components.

[0020]

[0032] In other embodiments, at least one of the first active terminal, the second active terminal, or the at least one ground terminal may be, for example, a surface mounted device (SMD : As a surface mount device) or as a grid array type implementation (e.g., In addition, a surface mount area may be exposed along the bottom surface of the integrated component for surface mounting the component using a land grid array (LGA), a ball grid array (BGA), etc.

[0021]

[0033] Aspects of the present disclosure can simplify the assembly and / or packaging of leaded or SMD components by replacing multiple discrete capacitors with a single integrated capacitive device. For example, an SMD configuration avoids multiple discrete components on a PCB, saving space on the PCB and potentially lowering inductance and / or equivalent series resistance (ESR). Additionally, the number of solder joints may be reduced, improving reliability.

[0022]

[0034] In general, the dielectric layers of a multilayer capacitor can be made of any material commonly used in the art. For example, the dielectric layers can be made of a ceramic material that contains titanate as a major component. Titanate is barium titanate (BaTiO 3 ) The ceramic materials may also include oxides of rare earth metals and / or compounds of acceptor type elements such as Mn, V, Cl, Mo, Fe, Ni, Cu, Co, etc. Titanates may also include MgO, CaO, Mn 3 O 4 , Y 2 O 3 , V 2 O 5 , ZnO, ZrO 2 , Nb 2 O 5 , Cr 2 O 3 , Fe 2 O 3 , P 2 O 5, SrO, Na 2 OK 2 O, Li 2 O, SiO 2 , WO 3 The ceramic material may also include other additives, organic solvents, plasticizers, binders, dispersants, etc. in addition to the ceramic powder.

[0023]

[0035] In general, the internal electrodes of the multi-layer monolithic device can be made of any material commonly applied in the art. For example, the internal electrodes can be formed by sintering a conductive paste whose main component is a noble metal material. The material may include, but is not limited to, palladium, palladium-silver alloy, nickel, and copper. For example, in one embodiment, the electrode may be made of nickel or a nickel alloy. The alloy may include one or more of Mn, Cr, Co, Al, W, etc., and the Ni content in the alloy is preferably 95% by weight or more. The Ni or Ni alloy may include various trace elements of 0.1% by weight or less, such as P, C, Nb, Fe, Cl, B, Li, Na, K, F, S, etc.

[0024]

[0036] The ceramic body of the multilayer capacitor can be formed using any method commonly known in the art, for example, by forming a laminate of alternating ceramic sheets and patterned internal electrodes, removing the binder from the laminate, sintering the debindered laminate at a high temperature in the range of 1200° C. to 1300° C. in a non-oxidizing atmosphere, and reoxidizing the sintered laminate in an oxidizing atmosphere.

[0025]

[0037] In general, the varistor may be configured to divert electrical surges to ground. For example, the varistor may have a clamping voltage in the range of about 3 volts to about 150 volts, in some embodiments about 5 volts to about 100 volts, in some embodiments about 10 volts to about 50 volts, and in some embodiments about 15 volts to about 30 volts.

[0026]

[0038] The varistor may include a ceramic body with an external electrode, the ceramic body being fabricated by sintering a laminate of alternating ceramic layers and internal electrodes, each pair of adjacent internal electrodes facing each other with a ceramic layer between them, each of which may be electrically coupled to a different external electrode.

[0027]

[0039] In general, the dielectric layer may include any suitable dielectric material, such as, for example, barium titanate, zinc oxide, or any other suitable dielectric material. For example, various additives may be included in the dielectric material to create or enhance the voltage-dependent resistance of the dielectric material. For example, in some embodiments, the additive may include an oxide of cobalt, bismuth, manganese, or combinations thereof. In some embodiments, the additive may include an oxide of gallium, aluminum, antimony, chromium, boron, titanium, lead, barium, nickel, vanadium, tin, or combinations thereof. The dielectric material may be doped with an additive in a range of about 0.5 mole percent to about 3 mole percent, and in some embodiments, in a range of about 1 mole percent to about 2 mole percent. The average grain size of the dielectric material may contribute to the nonlinear properties of the dielectric material. In some embodiments, the average grain size may be in a range of about 10 microns to 100 microns, and in some embodiments, in a range of about 20 microns to 80 microns. The varistor may also include two terminals, and each electrode may be connected with a respective terminal. The electrodes may provide resistance along their length and / or at the connections between the electrodes and the terminals.

[0028]

[0040] In general, the internal electrodes can be made of any material commonly used in the art. For example, the internal electrodes can be formed by sintering a conductive paste whose main component is a precious metal material. These materials can include, but are not limited to, palladium, palladium-silver alloy, silver, nickel, and copper. For example, in one embodiment, the electrodes can be made of nickel or a nickel alloy. The alloy can include one or more of Mn, Cr, Co, Al, W, etc., and the Ni content in the alloy is preferably 95% by weight or more. The Ni or Ni alloy can include various trace elements, such as P, C, Nb, Fe, Cl, B, Li, Na, K, F, S, etc., at 0.1% by weight or less.

[0029]

[0041] The integrated components may have a variety of sizes. For example, the integrated components may have case sizes ranging from EIA 0504 or smaller to EIA 2920 or larger. Example case sizes include 0805, 1206, 1806, 2020, etc.

[0030]

[0042] As noted above, in some embodiments, the integral component may be overmolded using a variety of suitable. Examples include silicone rubber, thermoplastic elastomers, or other similar polymers.

[0031]

[0043] Exemplary embodiments will now be described with reference to the drawings. FIG. 1A illustrates an exterior perspective view of an exemplary embodiment of a multi-terminal multi-layer device 100 generally in accordance with the subject matter of this disclosure. As illustrated, device 100 may include a body 102, such as a hexahedron. Device 100 may include a first end terminal 104, a second end terminal 106, a first side terminal 108, and a second side terminal 110. All such external terminals are present on a generally designated bottom side 112 of device 100, such as for use in a surface mounted device (SMD) configuration.

[0032]

[0044] The device 100 may include two capacitors formed in series between two of the first and second terminals 104, 106. As will be understood by those skilled in the art in connection with all of the embodiments described herein, the cooperating layers in the subject multi-layer structures comprise electrode layers, which then form an integrated capacitive structure.

[0033]

[0045] FIG 1B shows a first electrode layer 120 of the device 100 of FIG 1A. The electrode configuration 120 may include a cross-shaped electrode 122 having a pair of opposing edges 124, 126 connected to the first and second side terminals 108, 110 (FIG 1A), respectively. FIG 1C shows a second electrode layer 128 including a first electrode 130 connected to the first end terminal 104 and a second electrode 132 connected to the second end terminal 106. FIG 1D shows an alternating Illustrated is an electrode stack 133 of first and second electrode layers 120, 128. It should be understood that the electrode stack 133 may include any suitable number of electrode layers 120, 128.

[0034]

[0046] As shown again with reference to FIG. 1B, the cross-shaped electrode 122 may overlap the first electrode 130 along a first overlap region 134 to form a first capacitor, and may overlap the second electrode 132 along a second overlap region 136 to form a second capacitor.

[0035]

[0047] In some embodiments, the monolithic body 102 (FIG. 1A) may not include additional capacitors (in addition to the first and second capacitors) within the monolithic body 102 (FIG. 1A). For example, the electrode stack 133 described above with reference to FIG. 1D may extend through most of the thickness 138 of the monolithic body 102 (FIG. 1A) in a Z direction 140 perpendicular to the electrodes 122, 130, 132. For example, the ratio of the thickness 142 of the electrode stack 133 in the Z direction 140 to the thickness 138 of the monolithic body 102 may range from about 0.4 to about 0.97.

[0036]

[0048] FIG. 1E shows a perspective view of another embodiment of the device 100 according to the present application, with the lead configuration added to FIG. 1A. More specifically, the leads 148, 150, and 152 are attached to the external terminals 104, 108, and 106, respectively. The leads 148 and 152 may constitute a first and second lead attached to the first pair of terminals 104 and 106, respectively, while the lead 150 may constitute a third lead attached to at least one of the second pair of terminals 108 and 110. Those skilled in the art will also understand that the terminals 108 and 110 may both be connected to the layer 122, such that the lead 150 may be connected to either such terminal 108 or 110 with the same electrical circuitry results. The resulting configuration of the application FIG. 1C is an overmolded three-lead component.

[0037]

[0049] FIGURE 1F shows a schematic diagram of device 100 of application FIGURE 1A in its connection / mounting configuration as illustrated by application FIGURE 1C. More specifically, leads 148, 150, and 152 are shown in contact with series and parallel capacitors, respectively. The capacitance values ​​shown are intended to be merely exemplary and not limiting.

[0038]

[0050] As illustrated, the device 100 provides a single device solution for accommodating series and parallel capacitors. A first capacitor 154 may be formed between the cross-shaped electrode 122 and the first electrode 130 at the first overlap region 134. A second capacitor 156 may be formed between the cross-shaped electrode 122 and the second electrode 132 at the second overlap region 136. The first overlap region 134 may be approximately equal to the second overlap region 136 such that the first and second capacitors exhibit approximately a capacitance. However, in other embodiments, the first overlap region 134 may be larger or smaller than the second overlap region 136, such that the first capacitance may be larger or smaller than the second capacitance. One or both of the first capacitance and the second capacitance may range from about 10 nF to about 3 μF.

[0039]

[0051] 2A and 2B show another embodiment electrode configuration according to aspects of the present disclosure. A first electrode layer 220 may include a cross-shaped electrode 222 having a pair of opposing edges 224, 226 that may be connected to the first and second side terminals 108, 110 (FIG. 1A), respectively. FIG. 1C shows a second electrode layer 228 including a first electrode 230 connected to the first end terminal 104 and a second electrode 232 connected to the second end terminal 106. The first electrode 230 and / or the second electrode 232 may be T-shaped electrodes such that the electrodes 230, 232 extend to side edges 235, 237 of the electrode layer 227 and connect with respective end terminals 104, 106 (FIG. 1A) along at least one side surface 239 of the monolithic body 102.

[0040]

[0052] 2C shows an electrode stack 233 of alternating first and second electrode layers 220, 228. The electrode stack 233 may have a thickness 242 in the Z direction 140.

[0041]

[0053] The ratio of the thickness 242 of the electrode stack 233 in the Z direction 140 to the thickness 138 of the monolithic body 102 (FIG. 1A) can range from about 0.4 to about 0.97.

[0054] As shown, again with reference to FIG. 2A, the cross-shaped electrode 122 may overlap the first electrode 230 along a first overlap region 234 and may overlap the second electrode 232 along a second overlap region 236.

[0042]

[0055] Figure 3A illustrates an exterior perspective view of an exemplary embodiment of a multi-terminal multi-layer device 600 generally in accordance with the subject matter of the present disclosure for use in a stacked configuration with a varistor device 660 with respective additional leads 648, 650, and 652. As discussed further herein, Figure 3B illustrates a schematic diagram of the exemplary embodiment 600 of application Figure 3A.

[0043]

[0056] The varistor 660 may have external varistor terminals 662, 664. A lead configuration arrangement may be used to position the device 600 and varistor 660 parallel to one another. More specifically, the leads 648, 650, and 652 may be attached to the external (capacitor device) terminals 604, 608, and 606, respectively, of the device 600, while the leads 648 and 652 may be connected to the outer (varistor) terminals 662 and 652, respectively, of the varistor 660, as shown. The resulting application of the configuration of FIG. 3A may be overmolded.

[0044]

[0057] FIG. 3B generally illustrates a schematic diagram of the exemplary embodiment 600 of application FIG. 3A in its connection / mounting configuration as illustrated by application FIG. 3A. More specifically, leads 648, 650, and 652 are shown in contact with the series and parallel capacitors, respectively. The capacitance values ​​shown are intended to be merely exemplary and not limiting. A varistor 660 is also in contact with leads 648 and 652 as illustrated, and in parallel relationship with device 600. The varistor characteristics shown are intended to be merely exemplary and not limiting.

[0045]

[0058] FIG. 3C shows a perspective view of an integrated component with capacitor and varistor functions according to an embodiment of the present disclosure. In general, FIG. 3C shows the device of FIG. 3A from another perspective. For example, the embodiment of FIG. 3C provides a device 600, such as a multi-layer ceramic device, at the bottom and a varistor 660 at the top. Such a configuration may allow the device 600 and the varistor 660 to be used as a surface mount device after being combined together, such as by soldering. Additionally, the embodiment shown in FIG. 3C is provided without the leads shown in FIG. 3A. However, it should be understood that leads may also be used in such a configuration.

[0046]

[0059] As illustrated, device 600 provides a single device solution to accommodate series and parallel capacitors. Device 600 shows two representative capacitors 654 and 656, such as may be formed by a multi-layer split feedthrough configuration in isolated regions of device 600.

[0047]

[0060] Although various sizes may be implemented for any of the exemplary embodiments disclosed herein, device 600 and varistor 660 may be considered to represent a standard MLC case size, e.g., 1206 case size. Of course, various sizes may be implemented in various embodiments as necessary or desired for a particular application. All such variations, as well as variations in the exemplary capacitance values, are intended to fall within the spirit and scope of the subject matter of the present disclosure.

[0048]

[0061] As illustrated by the disclosure herein, in some embodiments used in SMD configurations, the subject matter of the present disclosure provides for the replacement of multiple discrete components on a printed circuit board (PCB), thereby saving space and, in some cases, lowering inductance. All such exemplary embodiments of the present disclosure, in some uses thereof, may be packaged into an overmolded three-leaded component. The subject matter of the present disclosure provides for a significant reduction in device size, resulting in a reduced number of solder joints and correspondingly improved reliability.

[0049]

[0062] FIG. 4 is a flow chart of a method 400 for forming an integrated component having capacitor and varistor functionality according to an embodiment of the present disclosure. Generally, the method 400 is described herein with reference to the integrated components 100, 200 described above with reference to FIGS. 1A-3C. However, it should be understood that the disclosed method 400 may be implemented with any suitable integrated components. In addition, FIG. 4 shows steps performed in a particular order for purposes of illustration and discussion, and the methods discussed herein are not limited to a particular order or arrangement. Those skilled in the art using the disclosure provided herein will understand that various steps of the methods disclosed herein may be omitted, rearranged, combined, and / or adapted in various ways without departing from the scope of the present disclosure.

[0050]

[0063] The method 400 may include, at (402), providing a multilayer capacitor body including electrodes forming a pair of capacitors in a split feedthrough type configuration, for example, as described above with reference to FIGS. 1A-3C.

[0051]

[0064] The method may include, at (404), forming first and second active terminals external to the multilayer capacitor body such that a pair of capacitors are connected in series between the first and second active terminals, e.g., as described above with reference to FIGS. 1A-3C.

[0052]

[0065] The method may include, at (406), stacking a discrete varistor with the multilayer capacitor body such that a first varistor terminal of the discrete varistor is connected to the first active terminal and a second varistor terminal is connected to the second active terminal.

[0053]

[0066] It should be understood that the individual steps in achieving the disclosed configurations are intended to be representative only and do not indicate the necessary use of other aspects beyond the general nature of the disclosure otherwise set forth For example, one skilled in the art will recognize that selected steps may be implemented to produce a particular design selected for a given application of the subject matter of the present disclosure. example

[0067] According to one exemplary embodiment of the present disclosure, the integrated component has first and second capacitors each exhibiting approximately 475 nF. The integrated component includes a discrete varistor having a clamping voltage of approximately 22 volts.

[0054]

[0068] According to one exemplary embodiment of the present disclosure, the integrated component has first and second capacitors each exhibiting approximately 685 nF. The integrated component includes a discrete varistor having a clamping voltage of approximately 22 volts.

[0055]

[0069] According to another exemplary embodiment of the present disclosure, the integrated component has first and second capacitors each exhibiting approximately 1 μF. The integrated component includes a discrete varistor having a clamping voltage of approximately 22 volts. Test Method

[0070] The following sections provide exemplary methods for testing varistors to determine various properties of multilayer ceramic capacitors, discrete capacitors, and / or integrated components.

[0056]

[0071] The clamping voltage of the varistor may be measured, for example, using a Keithley 2400 series source measurement unit (SMU), such as a Keithley 2410-C SMU. The varistor may be exposed to an 8 / 20 microsecond current wave, for example according to ANSI standard C62.1. The current wave may have a peak current value of 1 mA. The peak current value may be selected such that the peak current "clamps" the voltage against the varistor. The current may increase to the peak current value and then decay. The "rise" period may be from the start of the current pulse until the current reaches 90% of the peak current value. The "rise" time may be 8 microseconds. The "decay time" may be from the start of the current pulse to 50% of the peak current value. The "decay time" may be 20 microseconds. The clamping voltage measured as the maximum voltage across the varistor during the current wave.

[0057]

[0072] The capacitance of the multilayer capacitor may be measured using a Keithley 2400 series source measurement unit (SMU), such as, for example, a Keithley 2410-C SMU. For example, a first capacitance of a first capacitor may be measured between ground and a first external terminal of the multilayer capacitor. A second capacitance of a second capacitor may be measured between ground and a second external terminal of the multilayer capacitor.

[0058]

[0073] Although such subject matter of the present disclosure has been described in detail with respect to specific embodiments thereof, it will be understood that those skilled in the art, upon arriving at the foregoing understanding, can readily produce modifications, variations, and equivalents to such embodiments. Accordingly, the scope of the present disclosure is by way of example, not limitation, and the disclosure of the subject matter does not exclude the inclusion of such modifications, variations, and / or additions to the subject matter of the present disclosure, as would be readily apparent to one skilled in the art.

Claims

1. a multilayer capacitor comprising a first active terminal, a second active terminal, at least one ground terminal, and a pair of capacitors connected in series between the first active terminal and the second active terminal; a discrete varistor having a first external varistor terminal connected to the first active terminal of the multilayer capacitor and a second external varistor terminal connected to the second active terminal; the first active terminal, the second active terminal, and the at least one ground terminal are exposed along a bottom surface of the multilayer capacitor, the discrete varistor being connected to the first and second active terminals at a top surface of the multilayer capacitor, the top surface facing the bottom surface; the bottom surface of the multilayer capacitor is configured to mount the first active terminal and the second active terminal to a mounting surface, and the at least one ground terminal is exposed to the mounting surface; the pair of capacitors of the multilayer capacitor comprises a plurality of alternating electrode layers arranged in an electrode stack having an electrode stack thickness; the multilayer capacitor has a capacitor thickness from the top surface to the bottom surface; The ratio of the electrode stack thickness to the capacitor thickness ranges from about 0.6 to about 0.

95.

2. 2. An integrated component according to claim 1, comprising: The multilayer capacitor comprises a body having a plurality of dielectric layers, a first plurality of electrode layers, and a second plurality of electrode layers; the first plurality of electrode layers comprises a plurality of first electrodes connected to the first active terminal and a plurality of second electrodes connected to the second active terminal, each of the first plurality of electrode layers comprising a first electrode of the plurality of first electrodes and a second electrode of the plurality of second electrodes; the second plurality of electrode layers comprising a plurality of third electrodes connected to the at least one ground terminal and capacitively coupled with each of the plurality of first electrodes and the plurality of second electrodes to form first capacitors between the plurality of first electrodes and the plurality of third electrodes and to form second capacitors between the plurality of second electrodes and the plurality of third electrodes.

3. each first electrode of the plurality of first electrodes and each second electrode of the plurality of second electrodes is a T-electrode, with each first electrode and each second electrode extending to a side edge of a respective electrode layer of the first plurality of electrode layers; 3. The integrated component of claim 2, wherein each first electrode connects with the first active terminal along at least one side of the body and each second electrode connects with the second active terminal along at least one side of the body.

4. The integrated component of claim 3 , wherein each third electrode of the plurality of third electrodes is generally cross-shaped.

5. 2. The integrated component of claim 1, wherein the ratio of the electrode stack thickness to the capacitor thickness ranges from 0.95 to 0.

97.

6. The integrated component of claim 1 , wherein the at least one ground terminal comprises a first ground terminal and a second ground terminal.

7. 7. The integrated component of claim 6, wherein each of the first and second ground terminals is exposed along the bottom surface of the multilayer capacitor, and each of the plurality of third electrodes includes a pair of opposing edges, one of the opposing edges connected to the first ground terminal and the other of the opposing edges connected to the second ground terminal.

8. 2. The integrated component of claim 1, wherein the pair of capacitors is a first capacitor having a first capacitance and a second capacitor having a second capacitance, each of the first capacitance and the second capacitance being in a range of 475 nF to 1 μF.

9. 10. An assembly comprising the integrated component of claim 1 mounted as a surface mount device on said mounting surface.

10. 1. A method of forming an assembly having an integrated component, the method comprising: providing a multi-layer capacitor body including electrodes forming a pair of capacitors; forming a first active terminal, a second active terminal, and at least one ground terminal external to the multilayer capacitor body such that the pair of capacitors are connected in series between the first active terminal and the second active terminal, the first active terminal, the second active terminal, and the at least one ground terminal being exposed along a bottom surface of the multilayer capacitor; stacking discrete varistors such that a first varistor terminal of a discrete varistor is connected to the first active terminal on a top surface of the multilayer capacitor and a second varistor terminal of a discrete varistor is connected to the second active terminal on the top surface of the multilayer capacitor, the top surface of the multilayer capacitor being opposite the bottom surface of the multilayer capacitor; mounting the bottom side of the multilayer capacitor to a mounting surface with the first active terminal, the second active terminal, and the at least one ground terminal exposed on the mounting surface; the multilayer capacitor body having a plurality of dielectric layers, a first plurality of electrode layers, and a second plurality of electrode layers, the first plurality of electrode layers being stacked alternately with the second plurality of electrode layers; the first plurality of electrode layers comprises a plurality of first electrodes connected to the first active terminal and a plurality of second electrodes connected to the second active terminal, each of the first plurality of electrode layers comprising a first electrode of the plurality of first electrodes and a second electrode of the plurality of second electrodes; each first electrode of the plurality of first electrodes and each second electrode of the plurality of second electrodes are T-electrodes, each first electrode and each second electrode extending to a side edge of a respective electrode layer of the first plurality of electrode layers, each first electrode connecting with the first active terminal along at least one side of the body, and each second electrode connecting with the second active terminal along at least one side of the body; the second plurality of electrode layers includes a plurality of third electrodes connected to the at least one ground terminal and capacitively coupled with each of the plurality of first electrodes and the plurality of second electrodes to form first capacitors between the plurality of first electrodes and the plurality of third electrodes, and to form second capacitors between the plurality of second electrodes and the plurality of third electrodes; wherein each third electrode of the plurality of third electrodes is generally cross-shaped.

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