Multilayer ceramic capacitor having ultra-wideband performance

Abstract

To provide a multilayer ceramic capacitor having ultra-broadband performance.SOLUTION: A multilayer ceramic capacitor 100 includes a monolithic body including a plurality of dielectric layers. A first external terminal 118 is disposed along a first end 119 of the capacitor, and a second external terminal 120 is disposed along a second end 121 thereof. The external terminals have respective bottom portions that extend along a bottom surface 20 of the capacitor. The respective bottom portions of the external terminals are spaced by a bottom external terminal spacing distance 142. Shield electrodes 22, 24 in a bottom shield electrode region 16 are arranged within the monolithic body between a plurality of active electrodes 106, 108 and the bottom surface of the capacitor. The bottom shield electrode is separated from the bottom surface of the capacitor by a distance 63 from the lowest shield to the bottom portion that ranges from about 3 microns to about 10 microns. The ratio of a length 21 of the capacitor to the bottom external terminal spacing distance may be less than about 4.SELECTED DRAWING: Figure 1E

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 62 / 797,542, filed on January 28, 2019, which is hereby incorporated by reference in its entirety.

Background Art

[0002]

[0001] The diversity of modern technological applications has led to a need for effective electronic components and integrated circuits used in those applications. Capacitors are fundamental components used for filtering, coupling, bypassing, and other aspects in such modern applications, which can include wireless communication, alarm systems, radar systems, circuit switching, integrated circuit networks, and many other applications. The dramatic increase in the speed of integrated circuits and the dramatic increase in implementation density require progress, especially in coupling capacitor technology. When high - capacitance coupling capacitors are exposed to high frequencies in many current applications, performance characteristics become increasingly important. Since capacitors are fundamental to such a wide range of diverse applications, their accuracy and efficiency are essential. Therefore, many specific aspects of capacitor design are aimed at improving their performance characteristics.

Summary of the Invention

Means for Solving the Problems

[0003] According to one embodiment of the present invention, a broadband multilayer ceramic capacitor can have a first end and a second end spaced from the first end in the longitudinal direction. The longitudinal direction can be perpendicular to the lateral direction, and the lateral direction and the longitudinal direction can each be perpendicular to the Z direction. The capacitor can include a top surface and a bottom surface opposite the top surface in the Z direction. The broadband multilayer ceramic capacitor can include a monolithic body including a plurality of dielectric layers stacked in the Z direction. A plurality of active electrodes can be disposed within the monolithic body. A first external terminal can be disposed along the first end. The first external terminal can include a bottom portion extending along the bottom surface of the capacitor. A second external terminal can be disposed along the second end. The second external terminal can include a bottom portion extending along the bottom surface of the capacitor. The bottom portion of the first external terminal and the bottom portion of the second external terminal can be spaced apart in the longitudinal direction by a bottom external terminal spacing distance. The capacitor can include a bottom shielding electrode disposed within the monolithic body between the plurality of active electrodes and the bottom surface of the capacitor. The bottom shielding electrode can be spaced from the bottom surface of the capacitor by a distance (bottom-shield-to-bottom distance) from the lowermost shielding portion to the bottom. The distance from the lowermost shielding portion to the bottom can be in the range of about 3 microns to about 100 microns. The capacitor can have a length of the capacitor between the first end and the second end of the capacitor in the longitudinal direction. The ratio of the length of the capacitor to the bottom external terminal spacing distance can be less than about 4.

[0004]

[0003] According to another embodiment of the present invention, a method of forming a broadband multilayer ceramic capacitor is disclosed. The capacitor may have a first end and a second end spaced from the first end in a longitudinal direction perpendicular to a lateral direction. The lateral and longitudinal directions may each be perpendicular to the Z direction. The capacitor may have a top surface and a bottom surface opposite the top surface in the Z direction. The method includes forming a plurality of active electrode layers with a plurality of active electrodes, forming a bottom shielding electrode in a shielding electrode layer, stacking a plurality of active electrode layers, a shielding electrode layer, and a plurality of dielectric layers to form a monolithic body, and forming a first external termination at a first end of the monolithic body, where the first ex ternal terminal includes a bottom portion extending along the bottom surface of the capacitor, and forming a second external termination at a second end of the monolithic body. The second external terminal may include a bottom portion extending along the bottom surface of the capacitor. The bottom portions of the first external terminal and the second external terminal may be spaced apart in the longitudinal direction by a bottom external terminal spacing distance. The capacitor may include a bottom shielding electrode disposed within the monolithic body between the plurality of active electrodes and the bottom surface of the capacitor. The bottom shielding electrode may be spaced from the bottom surface of the capacitor by a distance from the lowermost shielding portion to the bottom. The distance from the lowermost shielding portion to the bottom may range from about 3 microns to about 100 microns. The capacitor may have a length of the capacitor between a first end and a second end of the capacitor in the longitudinal direction. The ratio of the length of the capacitor to the bottom external terminal spacing distance may be less than about 4.

[0005]

[0004] A complete and enabling disclosure of the present invention, including the best mode thereof for those skilled in the art, will be more particularly described in the remainder of this specification, including reference to the accompanying drawings.

Brief Description of the Drawings

[0006]

Figure 1A

[0005] FIG. 1 is a top view of an embodiment of an active electrode layer according to an aspect of the present disclosure.

Figure 1B

[0006] A perspective view of an alternating electrode layer configured as shown in FIG. 1A according to an aspect of the present disclosure.

Figure 1C

[0007] A top view of an embodiment of the working electrode layer of FIG. 1A in which a plurality of capacitive regions are formed according to an aspect of the present disclosure.

Figure 1D

[0008] A top view of an embodiment of the shielding electrode layer in which a plurality of capacitive regions are formed according to an aspect of the present disclosure.

Figure 1E

[0009] A side cross-sectional view of an embodiment of a capacitor including a plurality of regions in which the working electrode layer is configured as shown in FIGS. 1A to 1C and the shielding electrode layer is configured as shown in FIG. 1C according to an aspect of the present disclosure.

Figure 2A

[0010] A top view of another embodiment of the working electrode layer according to an aspect of the present disclosure.

Figure 2B

[0011] A top view of an embodiment of the working electrode layer of FIG. 2A in which a plurality of capacitive regions are formed according to an aspect of the present disclosure.

Figure 2C

[0012] A perspective view of an alternating electrode layer configured as shown in FIG. 2A according to an aspect of the present disclosure.

Figure 3A

[0013] A side cross-sectional view of another embodiment of a capacitor including a plurality of regions in which the working electrode layer is configured as shown in FIGS. 2A to 2C and the shielding electrode layer is configured as shown in FIG. 1D according to an aspect of the present disclosure.

Figure 3B

[0014] A view showing another embodiment of a capacitor according to an aspect of the present disclosure.

Figure 4

[0015] A schematic diagram of a circuit of an embodiment of the capacitor shown in FIGS. 1A to 1E having a plurality of capacitive regions.

Figure 5

[0016] A schematic diagram of a circuit of an embodiment of the capacitor shown in FIGS. 2A to 2C having a plurality of capacitive regions.

Figure 6

[0017] A side cross-sectional view of an embodiment of the capacitor of the present invention.

Figure 7A

[0018] A top view of the anchor electrode, shielding electrode, and working electrode of the capacitor of FIG. 6 according to an embodiment of the present invention.

Figure 7B

Figure 7C

Figure 7D

Figure 8A

[0019] A top view of a further embodiment of the working electrode layer according to a particular embodiment of the present invention.

Figure 8B

Figure 8C

Figure 8D

Figure 9

[0020] A diagram showing the capacitor of FIG. 1E in a second orientation.

Figure 10

[0021] A graph showing the insertion loss response curve measured for one of eight manufactured multilayer ceramic capacitors.

DETAILED DESCRIPTION OF THE INVENTION

[0007]

[0022] It should be understood by those skilled in the art that this discussion is merely illustrative of exemplary embodiments and is not intended to limit the broader aspects of the present invention.

[0023] Generally speaking, the present invention is directed to a multilayer ceramic capacitor. The capacitor includes alternating dielectric layers and electrode layers within a single monolithic body. The capacitor includes a first external terminal disposed along a first end of the capacitor and a second external terminal disposed along a second end of the capacitor. The first external terminal includes a bottom portion extending along the bottom surface of the capacitor, and the second external terminal includes a bottom portion extending along the bottom surface of the capacitor. The bottom portion of the first external terminal and the bottom portion of the second external terminal are longitudinally spaced apart by a bottom external terminal spacing distance. The ratio of the length of the capacitor between the first end and the second end to the bottom external terminal spacing distance is less than about 3, less than about 2.75 in some embodiments, less than about 2.5 in some embodiments, less than about 2.25 in some embodiments, less than about 2 in some embodiments, less than about 1.75 in some embodiments, less than about 1.5 in some embodiments, and may also be less than about 1.25 in some embodiments.

[0008]

[0024] The capacitor can include a bottom shielding electrode. The bottom shielding electrode can be disposed between the plurality of active electrodes and the bottom surface of the capacitor. The distance from the lowermost shielding portion to the bottom can be defined as the distance between the shielding electrode and the bottom surface of the capacitor. When a plurality of shielding electrode layers are included, the distance from the lowermost shielding portion to the bottom can be defined as the distance between the lowermost layer of the shielding electrode layers and the bottom surface. The distance from the lowermost shielding portion to the bottom can range from about 3 microns to about 100 microns, from about 4 microns to about 75 microns in some embodiments, from about 5 microns to about 60 microns in some embodiments, and from about 8 microns to about 30 microns in some embodiments.

[0009]

[0025] The inventors have discovered that such a configuration can provide a multilayer ceramic capacitor having low insertion loss over a wide range of frequencies. Generally, insertion loss is the loss of power through the capacitor and can be measured using any method well known in the art.

[0010]

[0026] The shielding electrode can be arranged in a monolithic body in various configurations that can exhibit different insertion loss characteristics. For example, in one embodiment, the shielding electrode can be arranged between the working electrode region and the bottom surface of the capacitor. The dielectric region without the shielding electrode can be arranged, for example, between the working electrode region and the upper surface of the capacitor as described below with reference to FIG. 1E. In such an embodiment, the capacitor can exhibit an insertion loss that exceeds about -0.5 dB at about 1 GHz to about 40 GHz, exceeds about -0.4 dB in some embodiments, exceeds about -0.35 dB in some embodiments, and exceeds about -0.3 dB in some embodiments. In some embodiments, the capacitor can exhibit an insertion loss that exceeds about -0.4 dB at about 10 GHz, exceeds about -0.35 dB at about 10 GHz in some embodiments, exceeds about -0.3 dB in some embodiments, and exceeds about -0.25 dB at about 1 0 GHz. The capacitor can exhibit an insertion loss that exceeds about -0.4 dB at about 20 GHz, exceeds about -0.35 dB at about 20 GHz in some embodiments, and exceeds about -0.3 dB at about 20 GHz in some embodiments. The capacitor can exhibit an insertion loss that exceeds about -0.4 dB at about 30 GHz, exceeds about -0.35 dB at about 30 GHz in some embodiments, exceeds about -0.3 dB at about 30 GHz in some embodiments, and exceeds about -0.25 dB at about 30 GHz in some embodiments. The capacitor can exhibit an insertion loss that exceeds about -0.4 dB at about 40 GHz, exceeds about -0.35 dB at about 40 GHz in some embodiments, exceeds about -0.3 dB at about 40 GHz in some embodiments, and exceeds about -0.25 dB at about 40 GHz in some embodiments.

[0011]

[0027] In some embodiments, the broadband multilayer ceramic capacitor can exhibit an insertion loss in the range of from about -0.05 dB to about -0.4 dB at from about 5 GHz to about 20 GHz, in some embodiments from about -0.05 dB to about -0.3 dB at from about 10 GHz to about 20 GHz, in some embodiments from about -0.05 dB to about -0.3 dB at from about 20 GHz to about 30 GHz, and in some embodiments from about -0.05 dB to about -0.3 dB at from about 30 GHz to about 40 GHz.

[0012]

[0028] In another embodiment, one or more bottom shielding electrodes can be disposed between the active electrode region and the bottom surface of the capacitor. One or more top shielding electrodes can be disposed between the active electrode region and the top surface of the capacitor, as described below with reference to, for example, FIG. 3B. In such embodiments, the insertion loss can be, for example, about -0.25 dB or more, such as about -0.28 dB or more, about -0.23 dB or more, about -0.3 dB or more when measured over a frequency range of 4 GHz to 10 GHz.

[0013]

[0029] In such embodiments, the insertion loss can be, for example, about -0.35 dB or more, such as about -0.38 dB or more, about -0.34 dB or more, about -0.4 dB or more when measured over a frequency range of 13 GHz to 20 GHz.

[0014]

[0030] In such embodiments, the insertion loss can be, for example, about -0.32 dB or more, such as about -0.4 dB or more, about -0.38 dB or more, about -0.35 dB or more, about -0.45 dB or more when measured over a frequency range of 23 GHz to 30 GHz.

[0015]

[0031] In such embodiments, the insertion loss can be, for example, about -0.43 dB or more, such as about -0.5 dB or more, about -0.48 dB or more, about -0.45 dB or more, about -0.55 dB or more when measured over a frequency range of 33 GHz to 40 GHz.

[0016]

[0032] In some embodiments, the ratio of the thickness of the capacitor to the distance from the lowermost shielding portion to the bottom is greater than about 3, in some embodiments greater than about 5, in some embodiments greater than about 10, in some embodiments greater than about 15, in some embodiments greater than about 20, and in some embodiments may be greater than about 40. The ratio of the thickness of the capacitor to the distance from the lowermost shielding portion to the bottom can range from about 10 to about 100, in some embodiments from about 20 to about 80, and in some embodiments from about 30 to about 50.

[0017]

[0033] The upper external terminal spacing distance can also be formed between the first external terminal and the second external terminal. More specifically, the first external terminal can include an upper portion extending along the upper surface of the capacitor. The second external terminal can include an upper portion extending along the upper surface of the capacitor. The upper portions of the first external terminal and the second external terminal can be separated from each other in the longitudinal direction by the upper external terminal spacing distance. The upper external terminal spacing distance can be approximately equal to the bottom external terminal spacing distance. In some embodiments, the ratio of the length of the capacitor between the first end and the second end to the upper external terminal spacing distance is less than about 4, in some embodiments less than about 3.5, in some embodiments less than about 3.25, in some embodiments less than about 3, in some embodiments less than about 2.75, in some embodiments less than about 2.5, in some embodiments less than about 2.25, in some embodiments less than about 2, in some embodiments less than about 1.75, in some embodiments less than about 1.5, in some embodiments less than about 1.25, and in some embodiments may be less than about 1.1.

[0018]

[0034] The monolithic body of the capacitor can include a dielectric material that is exposed between the bottom portions of the first external terminal and the second external terminal along the bottom surface of the capacitor.

[0019]

[0035] In some embodiments, the capacitor can include an upper shielding electrode disposed between the plurality of active electrodes and the upper surface of the capacitor. The upper shielding electrode can be spaced from the upper surface of the capacitor by a top-shield-to-top distance. The ratio of the top-shield-to-top distance to the bottom-shield-to-bottom distance can be between about 0.8 and about 1.2, about 0.9 and about 1.1 in some embodiments, about 0.95 and about 1.05 in some embodiments, and about 0.98 and about 1.02 in some embodiments.

[0020]

[0036] The ratio of the thickness of the capacitor to the bottom-shield-to-bottom distance can be greater than about 2, greater than about 3 in some embodiments, greater than about 5 in some embodiments, greater than about 10 in some embodiments, greater than about 15 in some embodiments, greater than about 20 in some embodiments, and even greater than about 40 in some embodiments.

[0021]

[0037] An additional bottom shielding electrode can be aligned substantially with the bottom shielding electrode in the Z direction. The bottom shielding electrode can be connected to the first external terminal, and the additional bottom shielding electrode can be connected to the second external terminal.

[0022]

[0038] The shielding electrodes can have various shapes. For example, in some embodiments, the bottom shielding electrode can define a stepped profile between two longitudinal edges. The bottom shielding electrode can have a first longitudinal edge and a second longitudinal edge that are each laterally aligned and face away from the first external terminal. The second longitudinal edge can be offset longitudinally from the first longitudinal edge by a shielding electrode offset distance. However, in some embodiments, one or more of the shielding electrodes can be rectangular and have no stepped profile. Further, one or more of the shielding electrodes (e.g., the bottom shielding electrode and / or the upper shielding electrode) can be laterally symmetric with respect to a longitudinal centerline extending longitudinally.

[0023]

[0039] An additional bottom shielding electrode connected to the second external terminal and substantially aligned with the bottom shielding electrode in the Z direction can similarly have a stepped shape. More specifically, the first longitudinal edge can be aligned laterally and face away from the second external terminal, and the second longitudinal edge can be aligned laterally and face away from the second external terminal. The second longitudinal edge can be offset longitudinally from the first longitudinal edge by approximately the shielding electrode offset distance.

[0024]

[0040] The first shielding gap distance can be formed longitudinally between the first longitudinal edge of the bottom shielding electrode and the first longitudinal edge of the additional bottom shielding electrode. The capacitor can have a length of the capacitor between the first end and the second end of the capacitor in the longitudinal direction. The ratio of the length of the capacitor to the first shielding gap distance is greater than about 2, greater than about 3 in some embodiments, greater than about 4 in some embodiments, greater than about 5 in some embodiments, greater than about 10 in some embodiments, greater than about 15 in some embodiments, greater than about 20 in some embodiments, and may be greater than about 50 in some embodiments.

[0025]

[0041] The second shielding gap distance can be formed longitudinally between the second longitudinal edge of the bottom shielding electrode and the second longitudinal edge of the additional bottom shielding electrode. The ratio of the length of the capacitor to the second shielding gap distance is greater than about 2, greater than about 3 in some embodiments, greater than about 4 in some embodiments, greater than about 5 in some embodiments, greater than about 10 in some embodiments, greater than about 15 in some embodiments, greater than about 20 in some embodiments, and may be greater than about 50 in some embodiments.

[0026]

[0042] The first shielding gap distance and / or the second shielding gap distance can range from about 10 microns to about 200 microns, in some embodiments from about 20 microns to about 150 microns, and in some embodiments from about 30 microns to about 80 microns.

[0027]

[0043] The shielding electrode offset distance can range from about 75 microns to about 300 microns, in some embodiments from about 100 microns to about 250 microns, and in some embodiments from about 125 microns to about 175 microns.

[0028]

[0044] The broadband multilayer ceramic capacitor can have a capacitor thickness in the Z direction between the top surface and the bottom surface. The ratio of the capacitor thickness to the Z-direction thickness of the upper shielding electrode region can range from about 2.1 to about 20, in some embodiments from about 2.2 to about 10, in some embodiments from about 2.5 to about 7, in some embodiments from about 2.7 to about 6, and in some embodiments from about 3 to about 5. The ratio of the capacitor thickness to the Z-direction thickness of the bottom shielding electrode region can range from about 2.1 to about 20, in some embodiments from about 2.2 to about 10, in some embodiments from about 2.5 to about 7, in some embodiments from about 2.7 to about 6, and in some embodiments from about 3 to about 5.

[0029]

[0045] The ratio of the capacitor thickness to the thickness of the active electrode region can range from about 1.1 to about 20, in some embodiments from about 1.5 to about 15, in some embodiments from about 1.7 to about 12, in some embodiments from about 2 to about 10, and in some embodiments from about 3 to about 7.

[0030]

[0046] The capacitor can include a plurality of electrode regions stacked upright in the Z direction. The plurality of electrode regions can include a dielectric region, an active electrode region, and a shielding electrode region. The active electrode region can include a plurality of active electrode layers. The shielding electrode region can include at least one shielding electrode. The active electrode region can be disposed between the dielectric region and the shielding electrode region in the Z direction.

[0031]

[0047] The dielectric region can extend from the active electrode region to the upper surface of the broadband multilayer ceramic capacitor. The dielectric region may not have an active electrode and / or a shielding electrode. For example, the dielectric region extends from one end of the capacitor by more than 25% of the length of the capacitor, in some embodiments by more than 20% of the length of the capacitor, in some embodiments by more than 15% of the length of the capacitor, in some embodiments by more than 10% of the length of the capacitor, in some embodiments by more than 5% of the length of the capacitor, and in some embodiments by more than 2% of the length of the capacitor, and may not have an electrode layer. For example, In some embodiments, the dielectric region can include one or more floating electrodes and / or dummy electrode tabs. However, in other embodiments, the dielectric region may not have all electrode layers. In some embodiments, the broadband multilayer ceramic capacitor may not have a shielding electrode in the Z direction on top of the plurality of active electrode layers. In some embodiments, the broadband multilayer ceramic capacitor may not have a shielding electrode in the Z direction on top of the lowermost electrode layer among the plurality of active electrode layers.

[0032]

[0048] The broadband multilayer ceramic capacitor can have the thickness of the capacitor in the Z direction between the upper surface and the bottom surface. The dielectric region can have the thickness of the dielectric region in the Z direction. The ratio of the thickness of the capacitor to the thickness of the dielectric region can be in the range of about 1.1 to about 20, in some embodiments about 1.5 to about 10, and in some embodiments about 1.7 to about 5.

[0033]

[0049] Aspects of the present disclosure are directed to broadband multilayer capacitors that exhibit insertion loss characteristics that are susceptible to orientation. For example, the capacitor may exhibit a first insertion loss value at a test frequency higher than about 2 GHz in a first orientation, and in a second orientation, at approximately the test frequency, at least about 0.3 dB, in some embodiments at least about 0.4 dB, and in some embodiments at least about 0.5 dB different from the first insertion loss, a second insertion loss value. The capacitor can be rotated by 90 degrees or more about the longitudinal direction with respect to the first orientation in the second orientation. For example, in some embodiments, the capacitor can be rotated by approximately 180 degrees about the longitudinal direction with respect to the first orientation in the second orientation. In other embodiments, the capacitor can be rotated by approximately 90 degrees about the longitudinal direction with respect to the first orientation in the second orientation.

[0034]

[0050] The test frequency can range from about 10 GHz to about 20 GHz, in some embodiments from about 10 GHz to about 30 GHz, and in some embodiments from about 10 GHz to about 40 GHz.

[0035] I. Exemplary Embodiments

[0051] Referring to FIGS. 1A - 1E, one embodiment of a multilayer ceramic capacitor 100 is disclosed. FIG. 1E is a simplified side view of the multilayer capacitor 100 mounted on a mounting surface 101 such as a printed circuit board or a substrate. The multilayer capacitor 100 can include a plurality of electrode regions 10 stacked in the Z - direction 136. The plurality of electrode regions 10 can include a dielectric region 12, a working electrode region 14, and a shielding electrode region 16. The working electrode region 14 can be disposed between the dielectric region 12 and the shielding electrode region 16 in the Z - direction 136. The dielectric region 12 can extend from the working electrode region 14 to the top surface 18 of the broadband multilayer ceramic capacitor 100. The capacitor 100 can include a bottom surface 20 opposite the top surface 18 in the Z - direction 136.

[0036]

[0052] The electrode region 10 can include a plurality of dielectric layers. Some of the dielectric layers can include electrode layers formed therein. Generally, the thicknesses of the dielectric layer and the electrode layer are not limited and can be any thickness required according to the performance characteristics of the capacitor. For example, the thickness of the electrode layer is not limited thereto, and can be, for example, from about 500 nm or more such as about 1 μm or more, about 2 μm or more, about 3 μm or more, about 4 μm or more, to about 10 μm or less such as about 5 μm or less, about 4 μm or less, about 3 μm or less, about 2 μm or less. For example, the electrode layer can have a thickness from about 1 μm to about 2 μm. Further, in one embodiment, the thickness of the dielectric layer can be defined according to the above thickness of the electrode layer. Also, it should be understood that such a thickness of the dielectric layer, if present, is also applicable to the layer between any active electrode layer and / or shielding electrode layer as defined herein.

[0037]

[0053] Generally, the present invention provides a multilayer capacitor having a unique electrode arrangement and configuration that provides various benefits and advantages. In this regard, it should be understood that the materials used to construct the capacitor may not be limited and may be any material widely used in the art, and may be formed using any method widely used in the art.

[0038]

[0054] Generally, the dielectric layer is typically formed from a material having a relatively high dielectric constant (K) from about 10 to about 40,000, in some embodiments from about 50 to about 30,000, and in some embodiments from about 100 to about 20,000.

[0039]

[0055] In this regard, the dielectric material may be ceramic. The ceramic can be provided in various forms such as a wafer (e.g., pre-fired), or a dielectric material co-fired within the device itself.

[0040]

[0056] Specific examples of types of high dielectric materials include, for example, NPO (COG) (up to about 100), X7R (from about 3,000 to about 7,000), X7S, Z5U and / or Y5V materials. The above materials are described by the definitions recognized in their industrial fields, and some of such definitions are the standard classifications established by the Electronic Industries Association (EIA) of the United States. It should also be recognized that the above materials should be recognized as such by those skilled in the art. For example, such materials can include ceramics. Such materials can include perovskites such as barium titanate and related solid solutions (such as barium strontium titanate, barium calcium titanate, barium zirconium titanate, barium strontium zirconium titanate, barium calcium zirconium titanate, etc.), lead titanate and related solid solutions (such as lead zirconium titanate, lead lanthanum zirconium titanate), sodium bismuth titanate, etc. In a specific embodiment, for example, barium strontium titanate (「BSTO」) of the formula Ba x Sr 1-x TiO 3 may be used, where x ranges from 0 to 1 in the above formula, and in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other suitable perovskites are, for example, Ba x Ca 1-x TiO 3 where x ranges from about 0.2 to about 0.8, and in some embodiments from about 0.4 to about 0.6, Pb x Zr 1-x TiO 3 (「PZT」) where x ranges from about 0.05 to about 0.4, lead lanthanum zirconium titanate (「PLZT」), lead titanate (PbTiO 3 ), barium calcium zirconium titanate (BaCaZrTiO 3 ), sodium nitrate (NaNO 3 ), KNbO 3 ), LiNbO 3 ), LiTaO 3 ), PbNb 2 O 6 ), PbTa2 O 6 、KSr(NbO 3 )、およびNaBa 2 (NbO 3 ) 5 KHb 2 PO 4 can be included. Even more complex perovskites can include A[B1 1 / 3 B2 2 / 3 O 3 materials, where in the above formula A is Ba x Sr 1-x (x can be a value from 0 to 1), B1 is Mg y Zn 1-y (y can be a value from 0 to 1), B2 is Ta z Nb 1-z (z can be a value from 0 to 1). In a specific embodiment, the dielectric layer can include titanic acid.

[0041]

[0057] The electrode layer can be formed from any of a variety of different metals known in the art. The electrode layer may be made of a metal such as a conductive metal. The materials can include noble metals (such as silver, gold, palladium, platinum, etc.), base metals (such as copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, as well as sputtered layers of chromium, nickel, and gold respectively, may also be suitable. Also, the electrode may also be made of a low-resistance material such as silver, copper, gold, aluminum, palladium, etc. In a specific embodiment, the electrode layer can include nickel or an alloy thereof.

[0042]

[0058] Referring back to FIG. 1E, in some embodiments, the dielectric region 12 may not have an electrode layer extending more than 25% of the length 21 of the capacitor 100 from the first end 119 or the second end 120 of the capacitor 100. For example, in such embodiments, the dielectric region 12 may include one or more floating electrodes and / or dummy electrode tabs. However, in other embodiments, the dielectric region 12 may not have any electrode layers. In some embodiments, the broadband multilayer ceramic capacitor 100 may not have the shielding electrodes 22, 24 on the plurality of active electrode layers 102, 104 in the Z direction 136. In some embodiments, the broadband multilayer ceramic capacitor 100 may not have the shielding electrodes 22, 24 on the lowermost electrode layer 19 of the plurality of active electrode layers 102, 104 in the Z direction 136.

[0043]

[0059] The plurality of active electrode layers 102, 104 may be disposed within the active electrode region 14. Each active electrode layer 102, 104 may include one or more active electrodes, as described below with reference to FIGS. 1A - 1C, for example. For example, in some embodiments, each active electrode layer 102, 104 may include a first electrode 106 and a second electrode 108.

[0044]

[0060] The shielding electrode region 16 may include one or more shielding electrodes, as described below with reference to FIG. 1D, for example. For example, the shielding electrode region 16 may include a first shielding electrode 22 disposed within the monolithic body of the capacitor 100. The first shielding electrode 22 may be parallel to the longitudinal direction 132. The first shielding electrode 22 may be connected to the first external terminal 118. The shielding electrode region 16 may include a second shielding electrode 24 that may be connected to the second external terminal 120. The second shielding electrode 24 may be substantially aligned with the first shielding electrode 22 in the Z direction 136.

[0045]

[0061] The first external terminal 118 can be connected to the first electrode 106 of the first electrode layer 102 and the second (opposing) electrode 108 of the second electrode layer 104. The second external terminal 120 can be connected to the first electrode 106 of the second electrode layer 104 and the second (opposing) electrode 108 of the first electrode layer 102.

[0046]

[0062] The first external terminal 118 can have a bottom portion 138 that extends along the bottom surface 20 of the capacitor 100. The second external terminal 120 can have a bottom portion 140 that extends along the bottom surface 20 of the capacitor 100. The bottom portion 138 of the first external terminal 118 and the bottom portion 140 of the second external terminal 120 can be spaced apart in the longitudinal direction 132 by a bottom external terminal spacing distance 142. The ratio of the length 21 of the capacitor to the bottom external terminal spacing distance 142 can be less than about 4.

[0047]

[0063] The first external terminal 118 can include an upper portion 144 that extends along the upper surface 18 of the capacitor 100. The second external terminal 120 can include an upper portion 146 that extends along the upper surface 18 of the capacitor 100. The upper portion 144 of the first external terminal 118 can be spaced apart in the longitudinal direction 132 by an upper external terminal spacing distance 148 that is approximately equal to the bottom external terminal spacing distance 142.

[0048]

[0064] The dielectric material of the monolithic body of the capacitor 100 can be exposed along the bottom surface 20 of the capacitor 100 between the bottom portion 138 of the first external terminal 118 and the bottom portion 140 of the second external terminal 120. Similarly, the dielectric material of the monolithic body of the capacitor 100 can be exposed between the upper portion 144 of the first external terminal 118 and the upper portion 146 of the second external terminal 120.

[0049]

[0065] Generally, with respect to the embodiments discussed herein, the external terminals are in the art It can be formed from any of a variety of different metals known in the art. The external terminals can be formed from any of a variety of different metals known in the art. The external terminals may be made of a metal such as a conductive metal. The materials can include precious metals (such as silver, gold, palladium, platinum, etc.), base metals (such as copper, tin, nickel, chromium, titanium, tungsten, etc.), as well as various combinations thereof. In a particular embodiment, the external terminals can include copper or an alloy thereof.

[0050]

[0066] The external terminals can be formed using any method widely known in the art. The external terminals can be formed using techniques such as sputtering, coating, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, propellant spraying / airbrushing, etc.

[0051]

[0067] In one embodiment, the external terminals can be formed such that the external terminals are relatively thick. For example, such terminals can be formed by adding a thick film strip of metal to the exposed portion of the electrode layer (e.g., by immersing the capacitor in a liquid external terminal material). Such a metal is present on the glass substrate and can include silver or copper. By way of example, such a strip can be printed and fired on the capacitor. Subsequently, an additional plating layer of metal (such as nickel, tin, solder, etc.) can be formed on the terminal strip so that the capacitor can be soldered to the substrate. Such application of the thick film strip can be carried out using any method widely known in the art (e.g., by a termination machine and a printing wheel for transferring a metal-containing paste onto the exposed electrode layer).

[0052]

[0068] The thickly plated external terminals can have an average thickness of about 150 μm or less, such as about 125 μm or less, about 100 μm or less, about 80 μm or less. The thickly plated external terminals can have an average thickness of about 25 μm or more, such as about 35 μm or more, about 50 μm or more, about 75 μm or more. For example, the thickly plated external terminals can have an average thickness ranging from about 25 μm to about 150 μm, such as from about 35 μm to about 125 μm, from about 50 μm to about 100 μm.

[0053]

[0069] In another embodiment, the external terminals can be formed such that the external terminals are thin film metal plating. Such thin film plating can be formed by depositing a conductive material such as a conductive metal on the exposed portion of the electrode layer. For example, the leading edge of the electrode layer can be exposed to enable the formation of plated terminations.

[0054]

[0070] The thinly plated external terminals can have an average thickness of about 50 μm or less, such as about 40 μm or less, about 30 μm or less, about 25 μm or less. The thinly plated external terminals can have an average thickness of about 5 μm or more, such as about 10 μm or more, about 15 μm or more. For example, the external terminals can have an average thickness ranging from about 5 μm to about 50 μm, such as from about 10 μm to about 40 μm, from about 15 μm to about 30 μm, from about 15 μm to about 25 μm.

[0055]

[0071] Generally, the external terminals can include plated terminals. For example, the external terminals can include electroplated terminals, electroless plated terminals, or a combination thereof. For example, the electroplated terminals can be formed by electroplating. The electroless plated terminals can be formed by electroless plating.

[0056]

[0072] When multiple layers constitute an external terminal, the external terminal can include an electroplated terminal and an electroless plated terminal. For example, electroless plating can be used first to deposit an initial layer of material. Next, the plating technique can be switched to an electrochemical plating system that can enable faster construction of the material.

[0057]

[0073] When forming a plated terminal using any plating method, the leading edge of the lead tab of the electrode layer exposed from the capacitor body is exposed to the plating solution. By exposing, in one embodiment, the capacitor can be immersed in the plating solution.

[0058]

[0074] The plating solution contains a conductive material such as a conductive metal used to form the plated terminal. Such a conductive material may be any of the above materials or any material widely known in the art. For example, the plating solution may be a nickel sulfamate bath solution or other nickel solution so that the plated layer and the external terminal contain nickel. Alternatively, the plating solution may be a copper acid bath or other suitable copper solution so that the plated layer and the external terminal contain copper.

[0059]

[0075] Furthermore, it should be understood that the plating solution can also contain other additives widely known in the art. For example, the additives can include other organic additives and media that can assist the plating process. Additionally, the additives can be used to use the plating solution at a desired pH. In one embodiment, a resistance-reducing additive can be used in the solution to assist in the complete plating coating and the bonding of the plating material to the capacitor and the exposed leading edge of the lead tab.

[0060]

[0076] The capacitor can be exposed, immersed, or dipped in the plating solution for a predetermined amount of time. Such exposure time is not necessarily limited and can be an amount of time sufficient to deposit enough plating material to form the plating terminals. In this regard, the time must be sufficient to allow the formation of a continuous connection between the exposed adjacent leading edges of the lead tabs of each electrode layer of a set of alternating dielectric and electrode layers, with a given polarity.

[0061]

[0077] Generally, the difference between electrolytic plating and electroless plating is that electrolytic plating uses an electrical bias, such as by using an external power source. The electrolytic plating solution is typically exposed to a high current density range, for example, 10 - 15 amp / ft 2 (rated 9.4 volts). The connection can be formed using a negative connection to the capacitor that requires the formation of the plating terminals and a positive connection to a solid material (e.g., Cu in a Cu plating solution) in the same plating solution. That is, the capacitor is biased to the opposite polarity of the plating solution. Using such a method, the conductive material of the plating solution is attracted to the metal of the exposed leading edge of the lead tab of the electrode layer.

[0062]

[0078] Various pretreatment steps can be used before immersing or exposing the capacitor in the plating solution. Such steps can be carried out for various purposes, including catalyzing, accelerating, and / or improving the adhesion of the plating material to the leading edge of the lead tab.

[0063]

[0079] Furthermore, an initial cleaning step may be used before plating or any other pretreatment step. Such a step may be used to remove any accumulation of oxides formed on the exposed lead tabs of the electrode layer. This cleaning step may be particularly useful for assisting in the removal of any accumulation of nickel oxide when the internal electrodes or other conductive elements are formed of nickel. Component cleaning may be achieved by complete immersion in a precleaning bath, such as one containing an acid cleaner. In one embodiment, the exposure may be for a predetermined time, such as about 10 minutes. Also, cleaning may alternatively be achieved by chemical polishing or a passivating step.

[0064]

[0080] Furthermore, to facilitate the deposition of the conductive material, an exposed metal leading edge of the lead tab of the electrode layer may be activated. Activation may be achieved by immersion in a palladium salt, a photo-patterned palladium organometallic precursor (via a mask or laser), a screen-printed or inkjet-deposited palladium compound, or an electrophoretic palladium deposit. It should be recognized that palladium-based activation is here disclosed merely as an example of an activation solution that often works well as the activation of exposed tab portions formed of nickel or its alloys. However, it should be understood that other activation solutions may equally be utilized.

[0065]

[0081] Alternatively, instead of or in addition to the activation step, an activation dopant can be introduced into the conductive material when forming the electrode layer of the capacitor. For example, if the electrode layer contains nickel and the activation dopant contains palladium, a palladium dopant can be introduced into the nickel ink or composition for forming the electrode layer. By doing so, the palladium activation step can be eliminated. It should further be recognized that some of the above activation methods, such as organometallic precursors, are also suitable for the co-deposition of glass formers to enhance the adhesion to the generally ceramic body of the capacitor. When the activation step is carried out as described above, traces of the activator material can often remain on the exposed conductive portions before and after the terminal plating.

[0066]

[0082] Furthermore, a post-treatment step after plating can also be used. Such steps can be carried out for various purposes, including enhancing and / or improving the adhesion of the material. For example, after carrying out the plating step, a heating (or annealing) step can be used. Such heating can be carried out by baking, laser ablation, UV exposure, microwave exposure, arc welding, and so on.

[0067]

[0083] As shown herein, the external terminal can include at least one plating layer. In one embodiment, the external terminal can comprise only one plating layer. However, it should be understood that the external terminal can comprise a plurality of plating layers. For example, the external terminal can comprise a first plating layer and a second plating layer. Furthermore, the external terminal can also comprise a third plating layer. The material of these plating layers can be any material widely known in the art mentioned above.

[0068]

[0084] For example, one plating layer, such as a first plating layer, can include copper or its alloy. Another plating layer, such as a second plating layer, can include nickel or its alloy. Another plating layer, such as a third plating layer, can include a combination such as tin, lead, gold, or an alloy. As an alternative, the initial plating layer can include nickel, followed by a plating layer of tin or gold. In another embodiment, an initial copper plating layer can be formed, and then a nickel layer can be formed.

[0069]

[0085] In one embodiment, the initial or first plating layer can be a conductive metal (such as copper). This region can then be coated with a second layer containing a resistive polymer material for sealing. This region can then be polished to selectively remove the resistive polymer material and then replated with a third layer containing a conductive metal material (such as copper).

[0070]

[0086] The second layer above the initial plating layer can correspond to a solder barrier layer, such as a nickel - solder barrier layer. In some embodiments, the layer can be formed by electroplating an additional layer of metal (such as nickel) on top of an initial electroless or electrolytic plating layer (such as plated copper). Other exemplary materials for the layer, such as the solder barrier layer, include nickel - phosphorus, gold, and silver. The third layer above the solder barrier layer can, in some embodiments, correspond to a conductive layer such as plated Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable plated solder.

[0071]

[0087] Furthermore, an electroplating step can form a layer of subsequent metal plating to provide a resistive alloy coating or a higher - resistance metal alloy coating, such as electroless Ni - P alloy, on top of such metal plating. However, it should be understood that it is also possible to include any metal coating, as would be understood by those skilled in the art from the complete disclosure herein.

[0072]

[0088] All of the above steps may occur as bulk processes, such as barrel plating, fluidized bed plating, and / or flow-through plating termination processes, all of which are recognized as being well known in the art. According to such bulk processes, multiple components can be processed at once, providing an effective and rapid termination process. This is particularly advantageous with respect to conventional termination methods, such as the printing of thick film terminations, which require the processing of individual components.

[0073]

[0089] As described herein, the formation of the external terminals is generally guided by the position of the exposed leading edge of the lead tabs of the electrode layer. Such a phenomenon can be called "self-determination" because the formation of the external plating terminals is determined by the configuration of the exposed conductive metal of the electrode layer at the selected peripheral positions on the capacitor. In some embodiments, the capacitor can include "dummy tabs" that provide exposed conductive metal along a portion of the monolithic body of the capacitor that does not include other electrodes (e.g., the working electrode or the shielding electrode).

[0074]

[0090] It should also be recognized that additional techniques for forming the terminals of the capacitor may also be within the scope of the present technology. Exemplary alternatives include, but are not limited to, the formation of terminations by plating, magnetism, masking, electrophoresis / electrostatics, sputtering, vacuum deposition, printing, or other techniques for forming both thick film conductive layers and thin film conductive layers.

[0075]

[0091] Figure 1A shows a top view of an embodiment of the working electrode configuration for one or more electrodes within the working electrode region 14 according to an aspect of the present disclosure. More specifically, the working electrode region 14 can include a first electrode layer 102 and a second electrode layer 104 arranged alternately, as described below with reference to FIG. 1B. Referring to FIG. 1A, each electrode layer 102, 104 can include a first electrode 106 and a second electrode 108. The first electrode 106 can have a base portion 114 that extends in the transverse direction 134 along the longitudinal edge of the first electrode 106. The first electrode 106 can have a pair of electrode arms 110 that extend in the longitudinal direction 132 from the base portion 114. The second electrode 108 can have a base portion 114 that extends in the transverse direction 134 along the longitudinal edge of the second electrode layer 108. The second electrode 10 can have a pair of electrode arms 110 that extend in the longitudinal direction 132 from the base portion 114.

[0076]

[0092] The electrode arms 110 of the first electrode 106 can be generally aligned longitudinally with the respective electrode arms 110 of the second electrode 108. An arm gap 226 can be defined between the aligned electrode arms 110 of the first and second electrodes 106, 108 in the longitudinal direction 132.

[0077]

[0093] A central edge gap distance 23 can be defined between the central portion 122 of the first electrode and the second electrode arm 110 in the transverse direction 134. A central end gap distance 24 can be defined between the central portion 122 of the first electrode 106 and the base portion 114 of the second electrode 108 in the longitudinal direction 132. In some embodiments, the central edge gap distance 23 may be approximately equal to the central end gap distance 24.

[0078]

[0094] The central portion 112 of the first electrode 106 has a first width 27 at a first position, and a second It can have a second width 29 that is greater than the first width 27 at the position. The first position of the first width 27 can be offset in the longitudinal direction 132 from the second position of the second width. Such a configuration can enable adjustment of the overlapping region between the central portions 112 of adjacent electrodes in the Z direction 136 without changing the central edge gap distance 23.

[0079]

[0095] Referring to FIG. 1B, a plurality of first electrode layers 102 and a plurality of second electrode layers 104 can be arranged in an alternating left-right opposite configuration. As shown, the central portions 112 of each electrode layer are at least partially overlapping. FIG. 1B shows a total of four electrode layers. However, it should be understood that any number of electrode layers can be used to obtain a desired capacitance for a desired application.

[0080]

[0096] Referring to FIG. 1C, some capacitive regions can be formed between the first electrode 106 and the second electrode 108. For example, in some embodiments, a central capacitive region 122 can be formed between the central portion 112 of the first electrode 106 and the base portion 114 and / or the arm 128 of the second electrode 108. In some embodiments, an arm gap capacitive region 124 can be formed within an arm gap 240 between the electrode arms 110 of the first electrode 106 and the second electrode 108.

[0081]

[0097] FIG. 1D shows a shielding electrode layer 26 that may be included within a shielding electrode region 16 (shown in FIG. 1E) within the monolithic body of capacitor 100. As shown above, the first shielding electrode 22 may be parallel to the longitudinal direction 132 (e.g., parallel to the upper and lower surfaces 18, 20 shown in FIG. 1E). The first shielding electrode 22 may be aligned in the transverse direction 134 and may have a first longitudinal edge 28 that faces away from the first external terminal 118 (shown in FIG. 1E) and the first end 119. The first shielding electrode 22 may be aligned in the transverse direction 134 and may have a second longitudinal edge 30 that faces away from the first external terminal (shown in FIG. 1E) and the first end 119. The second longitudinal edge 30 may be offset from the first longitudinal edge 28 in the longitudinal direction 132 by a shielding electrode offset distance 32.

[0082]

[0098] The second shielding electrode 24 may be connected to the second external terminal 120 (shown in FIG. 1E) and the second end 121. The second shielding electrode 24 may be substantially aligned with the first shielding electrode 22 in the Z direction 136 (shown in FIG. 1E). The second shielding electrode 24 may have a configuration similar to that of the first shielding electrode 22. For example, the second shielding electrode 24 may be aligned in the transverse direction 134 and may have a first longitudinal edge 28 that faces away from the second external terminal 120 (shown in FIG. 1E) and the second end 121. The second shielding electrode 24 may be aligned in the transverse direction 134 and may have a second longitudinal edge 30 that faces away from the second external terminal 120 (shown in FIG. 1E) and the second end 121. The second longitudinal edge 30 of the second shielding electrode 24 may be offset from the first longitudinal edge 28 of the second shielding electrode 24 in the longitudinal direction 132 by a shielding electrode offset distance 32.

[0083]

[0099] The first shielding capacitive region 34 can be formed between the first longitudinal edges 28 of the first and second shielding electrodes 119, 121. The second shielding capacitive region 36 can be formed between the second longitudinal edges 30 of the first and second shielding electrodes 119, 121. In some embodiments, the width 38 of the first longitudinal edge 28 in the transverse direction 134 may be shorter than the width 40 of the first shielding electrode 22 in the transverse direction 134.

[0084]

[0100] The first shielding gap distance 42 can be formed between the first longitudinal edge 28 of the first shielding electrode 2 2 and the first longitudinal edge 28 of the second shielding electrode 24 in the longitudinal direction 132. The second shielding gap distance 44 can be formed between the second transverse edge 30 of the first shielding electrode 22 and the second transverse edge 30 of the second shielding electrode 22 in the longitudinal direction 132.

[0085]

[0101] In some embodiments, the third shielding gap distance 46 can be formed between the third longitudinal edge 48 of the first shielding electrode 2 2 and the third longitudinal edge 48 of the second shielding electrode 24. The third shielding capacitive region 51 can be formed between the third longitudinal edges 48 of the first and second shielding electrodes 119, 121. In some embodiments, the third shielding gap distance 46 may be approximately equal to the second shielding gap distance 44, such that the third shielding capacitive region 51 may be substantially similar in size and shape to the second shielding capacitive region 36. For example, in some embodiments, the first shielding electrode 22 and / or the second shielding electrode 24 may be symmetric with respect to the longitudinal center line 50 extending in the longitudinal direction 132.

[0086]

[0102] However, in other embodiments, the third capacitive region 51 has a different size and / or shape than the second capacitive region 36, and the third shielding gap distance 46 may be longer or shorter than the second shielding gap distance 44 so as to generate a different capacitance than the second capacitive region.

[0087]

[0103] In some embodiments, one or more of the shielding electrodes 22, 24 may be rectangular in shape. In other words, it should be understood that the shielding electrode offset distance 32 may be zero or near zero, such that the first longitudinal edge 28 and the second longitudinal edge 30 are aligned or near aligned.

[0088]

[0104] 2A and 2B show alternative embodiments of the first and second electrode layers 102, 104. 1 illustrates an embodiment of the electrode layers 102, 104. More specifically, each electrode layer 102, 104 may include a first electrode 106 and a second electrode 108. The first electrode 106 may have a base portion 114. A pair of electrode arms 110 and at least one central portion 112 may extend from the base portion 114. The second electrode 108 may have a base portion 114 extending along a longitudinal edge of the second electrode layer 108. The second electrode 106 may have a pair of electrode arms 110 extending from the base portion 114. The electrode regions 12, 14, 16 may be substantially non-overlapping.

[0089]

[0105] Referring to FIG. 1E, in some embodiments, a broadband multilayer ceramic capacitor The sensor 100 can have a capacitor thickness 56 in the Z direction 136 between the top surface 18 and the bottom surface 20 .

[0090]

[0106] The dielectric region 12 may have a dielectric region thickness 58 in the Z direction 136. In some embodiments, the ratio of the capacitor thickness 56 to the dielectric region thickness 58 may be less than about 10.

[0091]

[0107] The working electrode area 14 has a thickness in the Z direction 136 of the working electrode area thickness 59. It can be obtained. The working electrode region 14 may not have the shielding electrodes 22 and 24, and / or may include only overlapping electrodes. The thickness 59 of the working electrode region can be defined between the lowermost working electrode layer 19 and the uppermost electrode layer 65. The ratio of the thickness 56 of the capacitor to the thickness 59 of the working electrode region can be in the range of about 1.1 to about 20.

[0092]

[0108] The shielding electrode region 16 can have a thickness 61 of the shielding electrode region in the Z direction 136. It can be done. The thickness 61 of the shielding electrode region can be defined between the bottom surface 20 of the capacitor 100 and the lowermost electrode layer 19 among the plurality of working electrodes. The ratio of the thickness 56 of the capacitor to the thickness 61 of the shielding electrode region can be in the range of about 1.1 to about 20.

[0093]

[0109] In some embodiments, the distance 63 from the shielding portion to the bottom surface can be defined as the distance between the shielding electrodes 22, 24 and the bottom surface 20 of the capacitor 100. When a plurality of shielding electrode layers are included, the distance 63 from the shielding portion to the bottom surface can be defined as the distance between the lowermost layer of the shielding electrode layers and the bottom surface 20. The ratio of the thickness 56 of the capacitor to the distance 63 from the shielding portion to the bottom surface can be greater than about 2.

[0094]

[0110] In some embodiments, the shielding electrodes 22 and 24 can be separated from the working electrodes 106 and 108 by a distance 67 from the first shielding portion to the working portion. The ratio of the distance 67 from the first shielding portion to the working portion to the distance 63 from the shielding portion to the bottom surface can be in the range of about 1 to about 20.

[0095]

[0111] Furthermore, FIG. 2A shows an electrode arm 1 having a main portion 128 and a stepped portion 130 ​is shown at 10. More specifically, the electrode arm 110 of the first electrode 106 can include a first longitudinal edge 60 that extends in the lateral direction 134 and can define an edge of the stepped portion 130. The second longitudinal edge 62 can extend in the lateral direction 134 and can define an edge of the main portion 128 of the arm 110. The first longitudinal edge 60 can be offset from the second longitudinal edge 62 in the longitudinal direction 132 by an offset distance 64 of the arm. One or both of the electrode arms 110 of the first electrode 106 and / or the second electrode 108 can include respective main and stepped portions 128, 130. For example, both arms 110 of both electrodes 106, 108 can include respective main portions 128 and stepped portions 130, as shown, for example, in FIG. 2A. The main arm gap 240 can be formed between the stepped portions 130 of the aligned arms 110. The stepped arm gap 242 can be formed between the main portions 128 of the aligned arms 110.

[0096]

[0112] Referring to FIG. 2B, several capacitive regions can be formed between the first electrode 106 and the second electrode 108 of the electrode configuration of FIG. 2A. For example, in some embodiments, a central capacitive region 122 can be formed between the central portion 112 of the first electrode 106 and the base portion 114 and / or the arm 110 of the second electrode 108. In some embodiments, a main arm gap capacitive region 125 can be formed within the main arm gap 240, and a stepped gap capacitive region 126 can be formed within the stepped arm gap 242.

[0097]

[0097]

[0113] Referring to FIG. 3A, in some embodiments, the dielectric region 12 is at the first end It can include a first dummy tab electrode 52 connected to an end and / or a second dummy tab electrode 54 connected to a second terminal 120. More specifically, the dummy tab electrodes 52, 54 can be used, for example, to form (e.g., deposit) the terminals 118, 120 using a fine copper terminal process. The dummy tab electrodes 52, 54 can extend from the first end 119 or the second end 121 by less than 25% of the length 21 of the capacitor.

[0098]

[0114] The electrode configuration described herein is the central portion 11 between adjacent electrode layers 102, 104 A primary capacitive element (i.e., parallel plate capacitance) between the two, and additional secondary capacitive elements can be expected as described above with reference to FIGS. 1C, 1D, and 2B. These configurations are schematically shown in FIGS. 4A and 4B.

[0099]

[0115] In some embodiments, the capacitor 100 can include one or more floating electrodes 111. The floating electrode 111 can be disposed within the dielectric region 12. However, in other embodiments, the floating electrode 111 can be disposed within the active electrode region 14 and / or the shielding electrode region 16. Generally, such a floating electrode 111 is not directly connected to the external terminals 118, 120.

[0100]

[0116] However, in some embodiments, the floating electrode can be part of a floating electrode layer that includes at least one electrode electrically connected to an external terminal. However, such a floating electrode layer includes at least one floating electrode that does not directly contact such an electrode or the external terminal. However, in some embodiments, the floating electrode can be part of a floating electrode layer that includes at least one electrode electrically connected to an external terminal. However, such a floating electrode layer includes at least one floating electrode that does not directly contact such an electrode or the external terminal.

[0101]

[0117] The floating electrode is arranged according to any method known in the art Moreover, it can be configured. For example, the floating electrode can be provided so as to overlap at least a part thereof, such as the central portion of the first working electrode and / or the second working electrode of the working electrode layer. In this regard, the floating electrode layer can be alternately laminated and arranged with the first electrode layer and the second internal electrode layer. In this regard, such layers can be separated by a dielectric layer.

[0102]

[0118] Furthermore, such a floating electrode can have any shape widely known in the art. For example, in one embodiment, the floating electrode layer can include at least one floating electrode having a dagger-like configuration. For example, such a configuration may be similar to the configuration and shape of the first electrode described herein. However, it should be understood that such a first electrode may or may not include an electrode arm having a stepped portion.

[0103]

[0119] Furthermore, in one embodiment, the floating electrode layer can include at least one floating electrode whose end portion is adjacent to at least one external terminal but does not contact such an external terminal. In this regard, such a gap can be called a longitudinal floating electrode gap. Such a longitudinal floating electrode gap can be more than about 3%, such as about 5% or more, of the longitudinal length of the capacitor, and can be up to about 50%, such as about 40% or less, about 30% or less, about 20% or less, about 10% or less. from more than 0%.

[0104]

[0120] FIG. 3B shows another embodiment of the capacitor 160 according to an aspect of the present disclosure. The capacitor 160 can include a plurality of dielectric regions 162. The plurality of dielectric regions 162 can include a working electrode region 14, a bottom shielding electrode region 164, and an upper shielding electrode region 166. The working electrode region 14 can be disposed between the bottom shielding electrode region 164 and the upper shielding electrode region 166.

[0105]

[0121] In some embodiments, the capacitor 160 or a portion thereof may be 1. For example, the shielding electrodes 22, 24 of the bottom shielding electrode region 164 may be symmetrical about the longitudinal centerline 167 relative to the shielding electrodes 22, 24 of the top electrode region 166. In other words, the shield-to-bottom distance 63 may be approximately equal to the shield-to-top distance 168, which may be defined between the shielding electrodes 22, 24 of the top shielding electrode region 166 and the top surface 18 of the capacitor 160. For example, in some embodiments, the ratio of the shield-to-bottom distance 63 to the shield-to-top distance 168 may range from about 0.8 to about 1.2, in some embodiments from about 0.9 to about 1.1, in some embodiments from about 0.95 to about 1.05, and in some embodiments from about 0.98 to about 1.02.

[0106]

[0122] The shielding electrodes 22, 24 in the upper shielding electrode region 166 are shielded from the working electrodes 106, 108. from the first shielding portion by a second shielding portion to working portion distance 169. The ratio of the second shielding portion to working portion distance 169 to the shielding portion to top surface distance 168 can range from about 1 to about 20. Additionally, the ratio of the first shielding portion to working portion distance 67 to the second shielding portion to working portion distance 169 can range from about 0.8 to about 1.2.

[0107]

[0123] The capacitor 160 is in a first orientation (as shown) such that the capacitor 160 has a long A third orientation (which may appear substantially similar to that shown) rotated 180 degrees about the longitudinal direction 132 may exhibit equivalent insertion loss characteristics. However, a second orientation of the capacitor 160 may be defined relative to the first orientation by rotating 90 degrees about the longitudinal direction 132 such that the shield electrodes 22, 24 are perpendicular to the mounting surface 101.

[0108]

[0124] In the first orientation, the capacitor 160 is The value of the insertion loss of 1 can be indicated. The capacitor 160 may exhibit a value of the second insertion loss at approximately the test frequency in a second orientation with respect to the mounting surface, and may be at least about 0.3 dB different from the value of the first insertion loss.

[0109]

[0125] FIG. 4 schematically shows three capacitive elements of the electrode configuration of FIG. 1C, namely, between adjacent electrode layers the primary capacitive element 112′, the central capacitive element 122′, and the arm gap capacitive element 124′. The capacitive elements 112′, 122′, and 124′ respectively correspond to the central region 112, the central capacitive region 122, and the arm gap capacitive region 124 of FIG. 1C. Further, in FIG. 4, the external terminals are shown as 118 and 128.

[0110]

[0126] FIG. 5 schematically shows four capacitive elements of the electrode configuration of FIG. 2B, and the capacitive elements 112′, 122′, and 125′, and 126′ respectively correspond to the central region 112, the capacitive region 122, the main arm gap capacitive region 125, and the staircase gap capacitive region 126 of FIG. 2B. It should be understood that the dimensions of the various gaps can be selectively designed to achieve the respective desired capacitance values of the capacitive elements shown in FIGS. 4 and 5. More specifically, various parameters such as the configuration of the capacitor, the number of electrode layers, the surface area of the overlapping central portion of the electrode pair, the distance separating the electrodes, the dielectric constant of the dielectric material, etc. can be selected to achieve the desired capacitance value. Nevertheless, the capacitors disclosed herein can include an array of capacitors combined in series and in parallel to provide effective broadband performance.

[0111]

[0127] In an exemplary embodiment of an ultra-wideband capacitor, the primary capacitor 112′ is connected Adapted to operate in a generally lower frequency range, such as from about a few kilohertz (kHz) to about 200 megahertz (MHz), it can accommodate a relatively large capacitance. On the other hand, the secondary capacitors 122’, 124’, 125’ and / or 126’ are typically configured to operate in a relatively higher frequency range, such as from about 200 megahertz (MHz) to several gigahertz (GHz), and can accommodate capacitors with relatively smaller values.

[0112]

[0128] Referring to FIG. 6, in some embodiments, the multilayer capacitor 300 may include a first external terminal 118 disposed along an end portion 119 of the first, and a second external terminal 120 disposed along a second end portion 121 that is opposite to the first end portion 119 in the longitudinal direction 132. The multilayer capacitor 300 may include a plurality of dielectric layers and a plurality of electrode layers, and the electrode layers face the dielectric layers disposed between each adjacent pair of electrode layers and are alternately arranged with a spacing therebetween.

[0113]

[0113]

[0129] Furthermore, as shown above, the multilayer capacitor can include a shielding electrode. For example, as shown in FIG. 6, the multilayer capacitor 300 can include a first shielding region 210 and a second shielding region 212, and each of the shielding regions 210, 212 can include one or more shielding electrode layers 214. The shielding regions 210, 212 can be separated from the active electrode region 216 by a dielectric region (e.g., one that does not include any electrode layers).

[0114]

[0114]

[0130] The shielding electrode layer 214 can have a first shielding electrode configuration in which each shielding electrode 220 is substantially rectangular. In other embodiments, the shielding electrode layer 214 can have a second shielding electrode configuration in which the shielding electrode 122 has steps 224, as described above with reference to the electrodes in FIG. 1D.

[0115]

[0115]

[0131] In some embodiments, the active electrode 218 region is between the first and second shielding regions It can be arranged between 210 and 212. The working electrode region 216 can include a plurality of alternating working electrode layers 218, as described with reference to FIGS. 2A to 2D, for example. Further, a pair of ceramic covers 227 can be arranged along the upper surface and / or the bottom surface of the capacitor 300. The ceramic cover 227 can include a dielectric material that is the same as or similar to the dielectric material of the plurality of dielectric layers.

[0116]

[0132] Referring to FIG. 6, in some embodiments, the multilayer capacitor 300 can also include anchor electrode regions 302, 304, 316, and / or 318. For example, the multilayer capacitor 300 can include a first anchor electrode region 304 above the working electrode region 216. Further, the shielding electrode region 210 including the shielding electrode layer 214 can be arranged above, such as above the first anchor electrode region 304. Further, the second anchor electrode region 302 can be arranged above, such as above the shielding electrode region 210. Similarly, the multilayer capacitor 300 can include a third anchor electrode region 316 below, such as immediately below the working electrode region 216. Further, the shielding electrode region 210 including the shielding electrode layer 214 can be arranged below, such as immediately below the third anchor electrode region 316. Further, the fourth anchor electrode region 318 can be arranged below, such as immediately below the shielding electrode region 210. In this regard, the working electrode region 216 can be arranged, for example, between the first anchor electrode region 304 and the third anchor electrode region 316. The working electrode region 216 can be configured as described above with reference to FIGS. 1A to 1C and FIGS. 2A to 2C, or as described below with reference to FIGS. 8A to 8D.

[0117]

[0133] Referring to FIG. 7A, the anchor electrode regions 302, 304, 316, and / or Alternatively, 318 can include a plurality of anchor electrode layers 310, each having a pair of anchor electrodes 312. The anchor electrode 312 can include a pair of electrode arms 314. Each electrode arm 314 of the anchor electrode 312 can include a main portion 328 and a stepped portion 330 in a similar form as described above with reference to the electrodes in FIGS. 1A and 2, for example.

[0118]

[0134] Referring to FIGS. 7B to 7D, the anchor electrode 312 can have various configurations. For example, referring to FIG. 7B, in some embodiments, the electrode arm 314 of the anchor electrode 312 may not include steps. For example, such an electrode can be provided in a C-shaped configuration without steps. Referring to FIG. 7C, in some embodiments, the electrode arm 314 of the anchor electrode 312 can include a stepped portion 320 offset inwardly from the outer lateral edge 322 of the anchor electrode 312. Referring to FIG. 7D, in other embodiments, the stepped portion 320 can be offset from the inner lateral edge 324 of the arm 314 of the anchor electrode 312. Still other configurations are possible. For example, in some embodiments, the stepped portion 320 can be offset from both the outer lateral edge 322 and the inner lateral edge 324.

[0119]

[0135] Referring to FIGS. 8A to 8C, in some embodiments, the working electrodes 106, 108 can have various other configurations. For example, referring to FIG. 8A, in some embodiments, each of the first electrode 106 and the second electrode 108 can include a single arm 110 instead of a pair of arms 110, 202 as described above with respect to FIG. 1A. In this regard, such an electrode can include one electrode including a central portion extending from the base and one electrode arm also extending from the base portion. On the other hand, the counter electrode can include a base portion and only one electrode arm extending from the base portion of such a second electrode.

[0120]

[0136] Referring to FIG. 8B, in some embodiments, the first electrode 106 and the second electrode Each of the electrodes 108 can include a central portion 112. For example, each electrode 106, 108 can include a central portion 112 extending from a respective base portion in addition to at least one electrode arm 110, 202, such as two electrode arms 110, 202 extending from a respective base portion.

[0121]

[0137] Referring to FIG. 8C, in some embodiments, the electrode assemblies of the electrodes 106, 108 may be 8D , in some embodiments, the electrode arm 110 of the electrode 106, 108 can have a stepped portion 130 that is offset outwardly from the inner lateral edge 324 of the electrode arm's main portion, in a direction away from the lateral centerline 236 of at least one of the electrodes 106, 108 of the electrode layer. Finally, with reference to FIG. 8D , in some embodiments, the electrode arm 110 of the electrode 106, 108 can have a stepped portion 130 that is offset from both the outer lateral edge 322 and the inner lateral edge 324 of the electrode arm 110, 202.

[0122] II. Insertion Loss

[0138] Aspects of the present disclosure provide broadband laminate capacitors that exhibit orientation sensitive insertion loss characteristics. The broadband multilayer capacitor is intended for use in a multilayer ceramic capacitor having a first orientation and a test frequency that varies by more than about 0.3 dB from the insertion loss at the test frequency in the second orientation. In the first orientation, the longitudinal direction 132 of the multilayer ceramic capacitor 100 may be parallel to the mounting surface 101 (e.g., as shown in FIG. 1E). In the first orientation, the electrodes (e.g., working electrodes 106, 108 and shielding electrodes 22, 24) may be approximately parallel to the mounting surface 101. Additionally, the shielding electrode region 1 (including the shielding electrodes 22, 24) may be disposed between the working electrode region 14 (including the working electrodes 106, 108) and the mounting surface 101 in the first orientation, e.g., as shown in FIG. 1E.

[0123]

[0139] Referring to FIG. 9, in the second orientation, the multilayer ceramic capacitor 100 can be rotated 180 degrees about the longitudinal direction 136 with respect to the first orientation (shown in FIG. 1E). Therefore, in the second orientation, the dielectric region 16 can be disposed between the active electrode region 14 and the mounting surface 101 with respect to the Z direction 136.

[0124]

[0140] The capacitor can exhibit a first insertion loss value at a test frequency exceeding about 2 GHz in the first orientation and a second insertion loss value at the test frequency in the second orientation. In some embodiments, the test frequency can be in the range of about 10 GHz to about 30 GHz or higher. The value of the second insertion loss can differ from the value of the first insertion loss by at least about 0.3 dB.

[0125]

[0125] III. Test Method

[0141] A test assembly can be used to test performance characteristics such as the insertion loss and reflection loss of a capacitor according to aspects of the present disclosure. For example, the capacitor can be mounted on a test substrate. The input line and the output line can each be connected to the test substrate. The test substrate can include a microstrip line or a test trace that electrically connects the input line and the output line to respective external terminations of the capacitor. The test traces can be spaced apart by about 0.432 mm (0.017 inches) or about 0.610 mm (0.024 inches).

[0126]

[0126]

[0142] The input signal is from a source signal generator (e.g., 1806 Keithley 2400 Series SourceMeter Unit (SMU), e.g., Keithley 2410-C It can be supplied to the input line using an SMU, and the resulting output signal of the capacitor can be measured on the output line (e.g., using a source signal generator). This test method can be repeated for a plurality of capacitors having the same design and nominal dimensions. The results of the insertion loss can be measured in a first orientation and a second orientation. To determine the nominal insertion loss sensitivity value of the capacitor group, the difference in the results of such insertion loss can be calculated and averaged.

[0127]

[0143] This procedure can be repeated for the various configurations of the capacitors described herein. It can be repeated.

[0128] Examples

[0144] Eight multilayer ceramic capacitors having the configuration described above together with FIGS. 1A to 1E were manufactured, and the insertion loss response characteristics in the first orientation and the second orientation were tested. The multilayer ceramic capacitors had the following dimensions corresponding to the dimensions annotated in FIGS. 1A to 1E.

[0129]

Table 1

[0130]

[0145] Therefore, the ratio of the length 21 of the capacitor to the bottom external terminal spacing distance 142 was about 2 .6.

[0146] The insertion loss response characteristics were measured for eight multilayer ceramic capacitors of the same design and nominal dimensions (within manufacturing tolerances). The values of the insertion loss were sampled at 30 GHz and 40 GHz in the first orientation and the second orientation for each of the eight multilayer ceramic capacitors. The difference in the values of the insertion loss at 30 GHz and 40 GHz in the first orientation and the second orientation was calculated for each capacitor. The resulting delta values of the insertion loss at 30 GHz and 40 GHz were averaged to determine the following average insertion loss delta values between the first orientation and the second orientation, respectively, at 30 GHz and 40 GHz.​​

[0131]

Table 2

[0132]

[0147] As shown in the above table, the average insertion losses of the manufactured multilayer ceramic capacitors exceeded 0.3 dB at both 30 GHz and 40 GHz, and the standard deviations were 0.041 and 0.05 at 30 GHz and 40 GHz, respectively. As shown in the above table, the standard deviations of the delta values of the average insertion losses at 30 GHz and 40 GHz for the eight groups of multilayer ceramic capacitors were also calculated.

[0133]

[0148] FIG. 10 shows the insertion loss response curve of one of the multilayer ceramic capacitors that showed insertion loss values very close to the above average values. The difference between the insertion loss in the first orientation and the insertion loss in the second orientation from the insertion loss response curve of FIG. 10 was as follows.

[0134]

[0134]

Table 3

[0135]

[0149] Furthermore, the capacitor was able to exhibit excellent insertion loss characteristics in the first orientation. Referring to FIG. 10, the insertion loss 302 in the first orientation exceeded about -0.8 dB at about 10 GHz, about 20 GHz, about 30 GHz, about 40 GHz, about 50 GHz, and about 60 GHz. The insertion loss 302 in the first orientation exceeded about -0.5 dB at about 10 GHz, about 20 GHz, about 30 GHz, and about 40 GHz.

[0136]

[0150] These and other modifications and variations of the present invention depart from the spirit and scope of the present invention It can be practiced by those skilled in the art without undue burden. Further, it should be understood that aspects of various embodiments can be exchanged with each other, both in whole or in part. Furthermore, those skilled in the art will recognize that the above description is merely exemplary and is not intended to limit the invention further described in the appended claims.

Claims

1. A broadband multilayer ceramic capacitor having a first end portion and a second end portion spaced apart in a longitudinal direction perpendicular to the lateral direction from the first end portion, wherein the lateral direction and the longitudinal direction are each perpendicular to the Z direction, and the capacitor includes a top surface and a bottom surface on the opposite side of the top surface in the Z direction, and the broadband multilayer ceramic capacitor includes a monolithic body including a plurality of dielectric layers stacked in the Z direction, a plurality of active electrodes disposed within the monolithic body, a first external terminal disposed along the first end portion, the first external terminal including a bottom portion extending along the bottom surface of the capacitor, a second external terminal disposed along the second end portion, the second external terminal including a bottom portion extending along the bottom surface of the capacitor, and the bottom portions of the first external terminal and the second external terminal being spaced apart by a bottom external terminal spacing distance in the longitudinal direction, a bottom shielding electrode disposed within the monolithic body between the plurality of active electrodes and the bottom surface of the capacitor, the bottom shielding electrode being spaced apart from the bottom surface of the capacitor by a distance from the lowermost shielding portion to the bottom, and the capacitor has a capacitor thickness in the Z direction between the top surface and the bottom surface, and a ratio of the capacitor thickness to the distance from the lowermost shielding portion to the bottom is in the range of 34 to 100, and the capacitor has a capacitor length in the longitudinal direction between the first end portion and the second end portion of the capacitor, and a ratio of the capacitor length to the bottom external terminal spacing distance is less than 4, the bottom shielding electrode is connected to the first external terminal, the bottom shielding electrode is aligned in the lateral direction and has a first longitudinal edge facing the side opposite to the first external terminal, the bottom shielding electrode is aligned in the lateral direction and has a second longitudinal edge facing the side opposite to the first external terminal, and the second longitudinal edge is offset from the first longitudinal edge by a shielding electrode offset distance in the longitudinal direction, a broadband multilayer ceramic capacitor.

2. the first external terminal includes an upper portion extending along the top surface of the capacitor, The second external terminal includes an upper portion extending along the upper surface of the capacitor, and the upper portion of the first external terminal and the upper portion of the second external terminal are separated from each other in the longitudinal direction by an upper external terminal spacing distance that is substantially equal to the bottom external terminal spacing distance. The broadband multilayer ceramic capacitor according to claim 1. **Claim 3** The monolithic body includes a dielectric material, and the dielectric material is exposed between the bottom portion of the first external terminal and the bottom portion of the second external terminal along the bottom surface of the capacitor. The broadband multilayer ceramic capacitor according to claim 1. **Claim 4** The bottom shielding electrode is disposed between the plurality of active electrodes and the bottom surface of the capacitor. The broadband multilayer ceramic capacitor according to claim 1. **Claim 5** The broadband multilayer ceramic capacitor according to claim 4, further comprising an upper shielding electrode disposed between the plurality of active electrodes and the upper surface of the capacitor. **Claim 6** The upper shielding electrode is separated from the upper surface of the capacitor by a distance from the uppermost shielding portion to the upper part, and the ratio of the distance from the uppermost shielding portion to the upper part to the distance from the lowermost shielding portion to the bottom part is between 0.8 and 1.

2. The broadband multilayer ceramic capacitor according to claim 5. **Claim 7** The broadband multilayer ceramic capacitor according to claim 1, further comprising an additional bottom shielding electrode substantially aligned with the bottom shielding electrode in the Z direction, the bottom shielding electrode being connected to the first external terminal, and the additional bottom shielding electrode being connected to the second external terminal. **Claim 8** The broadband multilayer ceramic capacitor according to claim 1, further comprising an additional bottom shielding electrode connected to the second external terminal and substantially aligned with the bottom shielding electrode in the Z direction, the additional bottom shielding electrode being aligned in the lateral direction and having a first longitudinal edge facing the side opposite to the second external terminal, the additional bottom shielding electrode being aligned in the lateral direction and having a second longitudinal edge facing the side opposite to the second external terminal, and the second longitudinal edge being offset from the first longitudinal edge in the longitudinal direction by approximately the shielding electrode offset distance. The broadband multilayer ceramic capacitor according to claim 1. **Claim 9** The broadband multilayer ceramic capacitor according to claim 8, wherein a first shielding gap distance is formed between a first longitudinal edge of the bottom shielding electrode and a first longitudinal edge of the additional bottom shielding electrode in the longitudinal direction.

10. Further comprising an additional bottom shielding electrode connected to the second external terminal and substantially aligned with the bottom shielding electrode in the Z direction, wherein a shielding gap distance is formed between the bottom shielding electrode and the additional bottom shielding electrode in the longitudinal direction. The broadband multilayer ceramic capacitor according to claim 1, wherein the capacitor has a length of the capacitor in the longitudinal direction between a first end and a second end of the capacitor, and a ratio of the length of the capacitor to the shielding gap distance is greater than 5.

11. The broadband multilayer ceramic capacitor according to claim 9, wherein a second shielding gap distance is formed between a second longitudinal edge of the bottom shielding electrode and a second longitudinal edge of the additional bottom shielding electrode in the longitudinal direction.

12. The broadband multilayer ceramic capacitor according to claim 1, wherein the capacitor has a length of the capacitor in the longitudinal direction between a first end and a second end of the capacitor, and a ratio of the length of the capacitor to the shielding electrode offset distance is greater than 2.

13. The broadband multilayer ceramic capacitor according to claim 1, wherein there is no shielding electrode on the plurality of active electrode layers in the Z direction.

14. The broadband multilayer ceramic capacitor according to claim 1, further comprising a dielectric region between the plurality of active electrodes and the upper surface of the capacitor, and there is no electrode layer in the dielectric region.

15. The broadband multilayer ceramic capacitor according to claim 1, wherein the active electrode comprises a first electrode including a base portion electrically connected to the first external terminal, a first electrode arm extending from the base portion in the longitudinal direction, and a central portion extending from the base portion in the longitudinal direction.

16. The broadband multilayer ceramic capacitor according to claim 1, wherein the broadband multilayer ceramic capacitor exhibits an insertion loss exceeding -0.4 dB at 5 GHz to 20 GHz.

17. The broadband multilayer ceramic capacitor according to claim 1, wherein the broadband multilayer ceramic capacitor exhibits an insertion loss exceeding -0.4 dB at 20 GHz to 40 GHz.

18. A method of forming a broadband multilayer ceramic capacitor having a first end portion and a second end portion spaced apart in a longitudinal direction perpendicular to the lateral direction from the first end portion, wherein the lateral direction and the longitudinal direction are each perpendicular to the Z direction, the capacitor has an upper surface and a bottom surface on the opposite side of the upper surface in the Z direction, the capacitor has a thickness in the Z direction between the upper surface and the bottom surface, and the method includes: forming a plurality of active electrode layers with a plurality of active electrodes; forming a bottom shielding electrode on a shielding electrode layer; stacking the plurality of active electrode layers, the shielding electrode layer, and a plurality of dielectric layers to form a monolithic body, wherein the bottom shielding electrode is spaced apart from the bottom surface of the capacitor by a distance from the lowermost shielding portion to the bottom, and a ratio of the thickness of the capacitor to the distance from the lowermost shielding portion to the bottom is in a range of 34 to 100; forming a first external terminal at a first end portion of the monolithic body, the first external terminal including a bottom portion extending along the bottom surface of the capacitor; forming a second external terminal at a second end portion of the monolithic body, the second external terminal including a bottom portion extending along the bottom surface of the capacitor, the bottom portion of the first external terminal and the bottom portion of the second external terminal being spaced apart by a bottom external terminal spacing distance in the longitudinal direction, the capacitor having a length in the longitudinal direction between the first end portion and the second end portion of the capacitor, and a ratio of the length of the capacitor to the bottom external terminal spacing distance being less than 4; the bottom shielding electrode is connected to the first external terminal; the bottom shielding electrode is aligned in the lateral direction and has a first longitudinal edge facing the side opposite to the first external terminal; the bottom shielding electrode is aligned in the lateral direction and has a second longitudinal edge facing the side opposite to the first external terminal, and the second longitudinal edge is offset from the first longitudinal edge by a shielding electrode offset distance in the longitudinal direction.

19. The broadband multilayer ceramic capacitor according to claim 1, wherein a distance from the lowermost shielding portion to the bottom is less than 10 microns.

20. A broadband multilayer ceramic capacitor having a first end and a second end spaced apart in a longitudinal direction perpendicular to the lateral direction from the first end, wherein the lateral direction and the longitudinal direction are each perpendicular to the Z direction, and the capacitor includes an upper surface and a bottom surface on the opposite side of the upper surface in the Z direction, and the broadband multilayer ceramic capacitor includes a monolithic body including a plurality of dielectric layers stacked in the Z direction, a plurality of active electrodes disposed within the monolithic body, a first external terminal disposed along the first end, and a second external terminal disposed along the second end, and a pair of bottom shielding electrodes disposed within the monolithic body between the plurality of active electrodes and the bottom surface of the capacitor, the pair of bottom shielding electrodes including a first bottom shielding electrode and a second bottom shielding electrode aligned with each other along the Z direction, comprising the first bottom shielding electrode being connected to the first external terminal, the second bottom shielding electrode being connected to the second external terminal, the first bottom shielding electrode having a first longitudinal edge aligned in the lateral direction and facing the side opposite to the first external terminal, and a second longitudinal edge aligned in the lateral direction and facing the side opposite to the first external terminal, and the second longitudinal edge being offset from the first longitudinal edge in the longitudinal direction by a first shielding electrode offset distance, the second bottom shielding electrode having a first longitudinal edge aligned in the lateral direction and facing the side opposite to the second external terminal, and a second longitudinal edge aligned in the lateral direction and facing the side opposite to the second external terminal, and the second longitudinal edge being offset from the first longitudinal edge in the longitudinal direction by a second shielding electrode offset distance, a first shielding gap distance being formed between the first longitudinal edge of the first bottom shielding electrode and the first longitudinal edge of the second bottom shielding electrode in the longitudinal direction, a second shielding gap distance being formed between the second longitudinal edge of the first bottom shielding electrode and the second longitudinal edge of the second bottom shielding electrode in the longitudinal direction, The capacitor has a length of the capacitor in the longitudinal direction between the first end portion and the second end portion of the capacitor, The ratio of the length of the capacitor to the first shielding gap distance is greater than 5, A broadband multilayer ceramic capacitor in which the ratio of the length of the capacitor to the second shielding gap distance is greater than 2.

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