Capacitive Feedthrough for Hybrid Enclosed Modules for Space Applications

Abstract

The present invention relates to a hermetically sealable capacitive feedthrough (1) for a hybrid module for space applications, the capacitive feedthrough (1) comprising a multilayer ceramic structure having two opposing outer surfaces including a top surface (10) and a bottom surface (20), and metallized outer closure side walls (31, 32, 33, 34) extending vertically between the opposing outer surfaces (10, 20) around the multilayer ceramic structure. The multilayer ceramic structure has, on its upper surface (10), a metallized upper central region (11) designed to receive an input electrical signal to be filtered, a dielectric upper region (12) extending around the metallized upper central region (11), and a metallized upper peripheral region (13) extending around the dielectric upper region (12) until it joins the metallized outer closure sidewalls (31, 32, 33, 34) to act as an electrical ground together with the metallized outer closure sidewalls (31, 32, 33, 34), the dielectric upper region (12) being designed to ensure electrical isolation between the input electrical signal and the electrical ground. and a bottom surface (20) including a metallized bottom central region (21) designed to provide a filtered output electrical signal, a dielectric bottom region (22) extending around the metallized bottom central region (21), and a metallized bottom peripheral region (23) extending around the dielectric bottom region (22) until it joins with the metallized outer closure sidewalls (31, 32, 33, 34) to act as an electrical ground together with the metallized outer closure sidewalls (31, 32, 33, 34), the dielectric bottom region (22) being designed to ensure electrical isolation between the filtered output electrical signal and the electrical ground.The multilayer ceramic structure further includes ceramic layers (41, 42, 43, 44, 45, 46, 47, 48), a first metallization layer (51, 53, 55, 57), and one or more second metallization layers (52, 54, 56) stacked on one another, such that each first metallization layer (51, 53, 55, 57) is interposed between two respective ceramic layers (41, 42, 43, 44, 45, 46, 47, 48) disposed directly above and below the first metallization layer (51, 53, 55, 57), and each / its second metallization layer (52, 54, 56) is interposed between two respective ceramic layers (41, 42, 43, 44, 45, 46, 47, 48) disposed directly above and below the second metallization layer (52, 54, 56). The first and second metallization layers (51, 52, 53, 54, 55, 56, 57) are interposed between the respective ceramic layers (42, 43, 44, 45, 46, 47), and the first and second metallization layers (51, 52, 53, 54, 55, 56, 57) are vertically alternated, whereby each / its second metallization layer (52, 54, 56) has a respective upper first metallization layer (53, 55, 57) disposed above the second metallization layer (52, 54, 56) and a respective lower first metallization layer (51, 53, 55) disposed below the second metallization layer (52, 54, 56), and two ceramic layers (41, 48) are disposed directly below the top surface (10) and directly above the bottom surface (11), respectively. The first metallization layers (51, 53, 55, 57) are bonded to the metallized outer closure sidewalls (31, 32, 33, 34), whereby the first metallization layers (51, 53, 55, 57), the metallized outer closure sidewalls (31, 32, 33, 34), and the metallized top and bottom peripheral regions (13, 23) form an electrical ground structure. Each / its second metallization layers (52, 54, 56) are separated from the metallized outer closure sidewalls (31, 32, 33, 34) by a respective first dielectric gap designed to ensure electrical isolation between the second metallization layers (52, 54, 56) and the electrical ground structure.Each / its second metallization layer (52, 54, 56) is connected to the upper second metallization layer (52, 54, 56) or metallization upper central region (11) through the upper ceramic layer (43, 44, 45, 46, 47, 48) and the respective upper first metallization layer (53, 55, 57) to the second metallization layer (52, 54, 56) and the upper second metallization layer (52, 54, 56) / metallization upper central region (11) and each of the first conductive vias (62, 63, 64) is separated from a respective overlying first metallization layer (53, 55, 57) by a respective second dielectric gap extending around the respective first conductive via (62, 63, 64), thereby forming a respective first capacitor; Each / its second metallization layer (52, 54, 56) is connected to the underlying second metallization layer (52, 54, 56) or metallized bottom central region (21) through the underlying ceramic layer (41, 42, 43, 44, 45, 46) and the respective underlying first metallization layer (51, 53, 55) to the second metallization layer (52, 54, 56) and the underlying second metallization layer (52, 54, 56) / metallized bottom central region (21) The metallization top and bottom central regions (11, 21) and the second metallization layers (52, 54, 56), together with the respective conductive vias (61, 62, 63) and the respective capacitors, form a capacitive feedthrough structure configured to receive an input electrical signal at the metallization top central region (11) and provide a filtered output electrical signal at the metallization bottom central region (21), whereby filtering of the input electrical signal is performed by the capacitors. The metallization top and bottom central regions (11, 21) are planar regions without openings.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims priority to Italian Patent Application No. 102020000017554, filed July 20, 2020, the entire disclosure of which is incorporated herein by reference.

[0002] The present invention relates generally to hermetically sealed hybrid modules used for space applications (e.g., aboard spacecraft, satellites, space platforms, etc.), and more particularly to capacitive feedthroughs that are hermetically sealable to the hermetically sealed hybrid modules, ensuring electromagnetic interference (EMI) filtering and resulting electromagnetic compatibility (EMC) radiated emissions performance suitable for the hermetically sealed hybrid modules. [Background technology]

[0003] As is known, hybrid modules are now widely used for space applications in general and for electronic equipment on board spacecraft in particular.

[0004] In particular, in the space sector, the terms "hermetically sealed hybrid module", "hybrid (sealed) module", "hybrid microcircuit / circuit", or simply "(sealed) hybrid" refer to a combination of elements (e.g., one or more wiring boards, one or more active or passive elements, etc.) typically located inside a hermetically sealed package / enclosure / casing and designed to perform one or more predetermined electronic functions, where: · Wiring substrates (e.g., thick film substrates, thin film substrates, co-fired ceramic substrates, direct bond copper (DBC) substrates, etc.) may or may not have integrated passive components (e.g., resistors, inductors, capacitors). Passive elements can be monolithic or individual chip or packaged components. The predetermined electronic functionality may include digital or analog functionality, low frequency or radio frequency (e.g., microwave) functionality, low power or high power functionality, and may be combined depending on the specific application.

[0005] The main advantages of this technology are: · the cost of procuring components; and Electrical parasitic effects of package components, which are important when modules operate at high frequencies The use of natural mold parts allows for a reduction in

[0006] The electromagnetic compatibility (EMC) radiated emissions performance of a radio frequency (RF) hybrid enclosed module (e.g., a microwave hybrid enclosed module) is primarily determined by the effectiveness of the module's electromagnetic shielding. In this regard, a weak point in the hybrid module's electromagnetic shielding is represented by direct current (DC) feedthroughs (i.e., elements designed and used to provide a DC bias inside the hybrid module), which typically do not provide adequate electromagnetic interference (EMI) filtering. Unfortunately, there is currently no practically effective solution to this problem.

[0007] In fact, current feedthrough solutions used for hybrid modules are typically based on the use of capacitive feedthroughs that are placed (e.g., by gluing or screwing) on ​​a surface / wall as close as possible to the outer wall of the hybrid module and connected to the inside of the hybrid module via non-capacitive feedthroughs. However, this solution is only partial and substantially ineffective because EMI can exist in the area (typically a void) between the outer wall of the hybrid module and the surface / wall on which the capacitive feedthrough is placed, thereby risking this interference entering the hybrid module through the non-capacitive feedthrough. In fact, the non-capacitive feedthroughs do not provide actual EMI shielding, thereby acting as a "crack" through which EMI can enter the hybrid module.

[0008] There are two main reasons, namely: the high temperatures involved in the assembly process of the hybrid module (e.g., brazing temperatures of approximately 300°C) necessary to ensure a hermetic seal of the hybrid module; Typical sizes / structures of known capacitive feedthroughs However, current capacitive feedthroughs prevent placement directly on the hybrid module housing,

[0009] In fact, these high temperatures affect the reliability of current capacitive feedthroughs, which have internal glass components that exhibit cracks that are unacceptable from a quality point of view after only a few heat treatment cycles.

[0010] It is noteworthy that capacitive feedthroughs are nowadays used in technology sectors other than the space sector.

[0011] For example, U.S. Patent Application Publication No. 2005 / 190527(A1) describes several feedthrough capacitor structures for active implantable medical devices, which are based on a multilayer structure having one or more hollow passages with a surface metallization and terminations with metallized openings on the opposing faces of the multilayer structure.

[0012] Specifically, U.S. Patent Application Publication No. 2005 / 190527(A1) discloses a feedthrough terminal assembly for an active implantable medical device, the feedthrough terminal assembly comprising: a feedthrough capacitor having an aperture therethrough; first and second sets of electrode plates alternating with dielectric layers, the second set of electrode plates being conductively coupled to a housing of the active implantable medical device; terminal pins extending at least partially through the apertures; conductive inserts disposed in the apertures to conductively couple the terminal pins to the first set of electrode plates and to mechanically couple the terminal pins to the feedthrough capacitor; and a surface metal coating within the apertures to conductively couple the first set of electrode plates, the conductive inserts being disposed between the terminal pins and the inner aperture surface metal coating and in physical contact with the terminal pins and the inner aperture surface metal coating.

[0013] The solution according to US Patent Application Publication No. 2005 / 190527(A1) is specifically designed for use in cardiac pacemakers and defibrillators and is applicable to both hermetically sealed and non-hermetically sealed housings and septa.

[0014] Furthermore, U.S. Patent Application Publication No. 2005 / 190527(A1) states that the solution disclosed therein is theoretically applicable to space electronics modules. However, the structure of the feed-through capacitor described in U.S. Patent Application Publication No. 2005 / 190527(A1) does not actually provide EMI filtering performance suitable for space applications, and requires many elements such as terminal pins, conductive inserts, and conductive ferrules (necessary for signal propagation through the feed-through capacitor), which complicates the manufacturing process of such feed-through capacitors.

[0015] Another example of a hermetic feedthrough for an implantable medical device is disclosed in U.S. Patent No. 7,164,572 (B1), which relates to a multi-pass, unipolar, co-fired hermetic electrical feedthrough and method of fabrication therefor. However, it should be noted that the electrical feedthrough assembly according to U.S. Patent No. 7,164,572 (B1) is not capacitive and is certainly unsuitable for space applications. [Prior art documents] [Patent documents]

[0016] [Patent Document 1] US Patent Application Publication No. 2005 / 190527 [Patent Document 2] U.S. Patent No. 7,164,572 Summary of the Invention [Problem to be solved by the invention]

[0017] In view of the foregoing, the applicant has felt the need to carry out in-depth research to develop an innovative capacitive feedthrough for space applications, and in particular for use with hybrid enclosed modules, and has therefore conceived the present invention.

[0018] It is therefore an object of the present invention to provide a capacitive feedthrough for use with a hybrid sealed module, which in particular ensures EMI filtering and a resulting EMC radiated emissions performance suitable for the hybrid sealed module, and which can be hermetically sealed to the hybrid module for space applications. [Means for solving the problem]

[0019] This and other objects are achieved by the present invention in that it relates to a hermetically sealable capacitive feedthrough for a hybrid module for space applications, as defined in the appended claims.

[0020] Specifically, the capacitive feedthrough according to the present invention comprises a multi-layer ceramic structure, the multi-layer ceramic structure comprising: two opposing exterior surfaces, including a top surface and a bottom surface; a metallized outer closure sidewall extending vertically between said opposing outer surfaces around the multilayer ceramic structure; and It has.

[0021] Specifically, the multilayer ceramic structure comprises: On the top, a metallized upper central area designed to receive the input electrical signal to be filtered; a dielectric upper region extending around the metallized upper central region; a metallized upper peripheral region extending around the dielectric upper region until it joins with the metallized outer closure sidewall to act as an electrical ground together with the metallized outer closure sidewall, the dielectric upper region being designed to ensure electrical isolation between the input electrical signal and the electrical ground; and Including, On the bottom, - a metallized bottom central area designed to provide a filtered output electrical signal, said metallized top and bottom central areas being planar areas without openings; a dielectric bottom region extending around a metallized bottom central region; a metallized bottom perimeter region extending around the dielectric bottom region until it joins with the metallized outer closure sidewall to act as an electrical ground together with the metallized outer closure sidewall, the dielectric bottom region being designed to ensure electrical isolation between the filtered output electrical signal and electrical ground; and Includes:

[0022] The multilayer ceramic structure also includes a ceramic layer, a first metallization layer, and one or more second metallization layers stacked together, thereby: each first metallization layer is interposed between two respective ceramic layers disposed directly above and below said first metallization layer; each / its second metallization layer is interposed between two respective ceramic layers located directly above and below said second metallization layer; The first and second metallization layers are vertically alternated, whereby each / its second metallization layer - a respective upper first metallization layer disposed above said second metallization layer; - a respective lower first metallization layer disposed below said second metallization layer; and Two ceramic layers are placed directly below the top surface and directly above the bottom surface.

[0023] A first metallization layer is coupled to the metallized outer closure sidewall, whereby the first metallization layer, the metallized outer closure sidewall, and the metallized top and bottom peripheral regions form an electrical ground structure.

[0024] Each / its second metallization layer is separated from the metallization outer closure sidewall by a respective first dielectric gap designed to ensure electrical insulation between said second metallization layer and said electrical ground structure.

[0025] Each / its second metallization layer connected to an upper second metallization layer or metallization upper central region through the upper ceramic layer and each upper first metallization layer using respective first conductive vias extending vertically between said second metallization layer and said upper second metallization layer / metallization upper central region, each said first conductive via being separated from its respective upper first metallization layer by a respective second dielectric gap extending around said respective first conductive via, thereby forming a respective first capacitor; Each / its second metallization layer connected to a lower second metallization layer or metallization bottom central region through the lower ceramic layer and the respective lower first metallization layer using respective second conductive vias extending vertically between said second metallization layer and said lower second metallization layer / metallization bottom central region, each said second conductive via being separated from a respective said lower first metallization layer by a respective third dielectric gap extending around said respective second conductive via, thereby forming a respective second capacitor.

[0026] The metallization top and bottom central regions and the second metallization layer, together with the respective conductive vias and respective capacitors, form a capacitive feedthrough structure configured to receive an input electrical signal at the metallization top central region and to provide a filtered output electrical signal at the metallization bottom central region, whereby filtering of the input electrical signal is performed by the capacitors.

[0027] For a better understanding of the invention, preferred embodiments, intended purely as non-limiting examples, will now be described with reference to the accompanying drawings (not all of which are to scale): [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 2 is a schematic diagram of an example of a capacitive feedthrough in accordance with a preferred, non-limiting embodiment of the present invention; [Figure 2]FIG. 2 is a schematic diagram of an example of a capacitive feedthrough in accordance with a preferred, non-limiting embodiment of the present invention; [Figure 3] FIG. 2 is a schematic diagram of an example of a capacitive feedthrough in accordance with a preferred, non-limiting embodiment of the present invention; [Figure 4] FIG. 2 is a schematic diagram of an example of a capacitive feedthrough in accordance with a preferred, non-limiting embodiment of the present invention; [Figure 5] FIG. 5 is a schematic circuit diagram of the capacitive feedthrough of FIGS. [Figure 6] 5A-5C are schematic diagrams illustrating examples of hermetic sealing of the capacitive feedthrough of FIGS. 1-4 into a hybrid module. DETAILED DESCRIPTION OF THE INVENTION

[0029] The following description is presented to enable one skilled in the art to make and use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art without departing from the scope of the invention as claimed. Thereby, the present invention is not intended to be limited to the embodiments shown and described, but is intended to be accorded the widest scope of protection consistent with the features defined in the appended claims.

[0030] The present invention arises from the applicant's idea of ​​using a multilayer ceramic substrate (preferably a multilayer high temperature co-fired ceramic (HTCC) or low temperature co-fired ceramic (LTCC) substrate, advantageously a multilayer HTCC / LTCC planar substrate) to provide EMI filtering and to create a capacitive feedthrough that can be hermetically sealed (conveniently using a eutectic alloy) to the outer wall of the hybrid module (specifically the outer wall of the housing / casing of the hybrid module), thereby resulting in an entire hermetic assembly to which filtered DC bias access is provided.

[0031] More briefly, therefore, the present invention relates to the use of multilayer ceramic substrates to fabricate hermetic, EMI-filtering, capacitive feedthrough devices that are hermetically sealable to hybrid hermetic modules.

[0032] 1-4 schematically illustrate an example of a capacitive feedthrough (generally designated by the reference numeral 1) according to a preferred, non-limiting embodiment of the present invention. Specifically, FIG. 1 is a schematic perspective view of the capacitive feedthrough 1, FIG. 2 is a schematic top view of the capacitive feedthrough 1, FIG. 3 is a schematic bottom view of the capacitive feedthrough 1, and FIG. 4 is a schematic vertical cross-sectional view of the capacitive feedthrough 1.

[0033] As shown in Figures 1 to 4, the capacitive feedthrough 1 is conveniently shaped as a cube or rectangular parallelepiped (which may more broadly have the shape of a parallelepiped, hexahedron, prism, or polyhedron), two opposing outer surfaces including a top surface 10 and a bottom surface 20; four metallized outer closure side walls 31, 32, 33, 34 (conveniently made of a metal-coated ceramic material, preferably a gold-metallized ceramic material), - extending vertically between the top surface 10 and the bottom surface 20; - Extends around a multi-layer ceramic structure, - Designed to act as an electrical ground Four metallized outer closure side walls 31, 32, 33, 34 have It comprises a multilayer ceramic structure (preferably a multilayer HTCC or LTCC structure, conveniently a multilayer HTCC / LTCC planar substrate).

[0034] Specifically, the multilayer ceramic structure: On the top surface 10, a metallized upper central area 11 (conveniently made of a metal-coated ceramic material, preferably gold-metallized), which is a planar area without openings and is conveniently square or rectangular, designed to receive an input electrical signal to be filtered (conveniently a DC bias signal such as a voltage applied from the outside to the inside of the hermetic hybrid, not shown in FIGS. 1 to 4); a dielectric upper region 12 (conveniently made of a ceramic material without a metal coating) extending around the metallized upper central region 11 and conveniently shaped as a square or rectangular frame; a metallized upper peripheral region 13 (conveniently made of a metal-coated ceramic material, preferably made of a ceramic material metallized with gold) extending around the dielectric upper region 12 until it joins with the metallized outer closure side walls 31, 32, 33, 34, and conveniently shaped as a square or rectangular frame, so as to act as an electrical ground together with the metallized outer closure side walls 31, 32, 33, 34 (the dielectric upper region 12 is designed to ensure electrical isolation between the input electrical signal and the electrical ground); Including, On the bottom 20, - a metallized bottom central area 21 (conveniently made of a metal-coated ceramic material, preferably gold-metallized) which is a planar area without apertures, conveniently square or rectangular, designed to provide a filtered output electrical signal; a dielectric bottom area 22 (conveniently made of ceramic material without a metal coating) extending around the metallized bottom central area 21 and conveniently shaped as a square or rectangular frame; a metallized bottom peripheral region 23 (conveniently made of a metal-coated ceramic material, preferably made of a ceramic material metallized with gold) extending around the dielectric bottom region 22 until it joins with the metallized outer closure side walls 31, 32, 33, 34, and conveniently shaped as a square or rectangular frame, so as to act as an electrical ground together with the metallized outer closure side walls 31, 32, 33, 34 (the dielectric bottom region 22 is designed to ensure electrical isolation between the filtered output electrical signal and the electrical ground); Includes:

[0035] As shown in FIGS. 2-4, the metallized top central region 11 is larger than the metallized bottom central region 21, while the metallized bottom peripheral region 23 is larger than the metallized top peripheral region 13.

[0036] Furthermore, as shown in Figure 4, the multilayer ceramic structure a first ceramic layer 41 disposed (i.e., spanning) the metallized bottom central region 21, the dielectric bottom region 22, and the metallized bottom peripheral region 23; a first metallization layer 51 is disposed on (i.e., extends over) the first ceramic layer 41; a second ceramic layer 42 is disposed (i.e., extends) over the first metallization layer 51; a second metallization layer 52 is disposed on (i.e., extends over) the second ceramic layer 42; a third ceramic layer 43 is disposed (i.e., extends) over the second metallization layer 52; a third metallization layer 53 is disposed on (i.e., extends over) the third ceramic layer 43; a fourth ceramic layer 44 is disposed on (i.e., extends over) the third metallization layer 53; a fourth metallization layer 54 disposed on (i.e., extending over) the fourth ceramic layer 44; a fifth ceramic layer 45 is disposed on (i.e., extends over) the fourth metallization layer 54; a fifth metallization layer 55 is disposed on (i.e., extends over) the fifth ceramic layer 45; a sixth ceramic layer 46 disposed on (i.e., extending over) the fifth metallization layer 55; a sixth metallization layer 56 disposed on (i.e., extending over) the sixth ceramic layer 46; a seventh ceramic layer 47 is disposed (i.e., extends) over the sixth metallization layer 56; a seventh metallization layer 57 is disposed on (i.e., extends over) the seventh ceramic layer 47; an eighth ceramic layer 48 is disposed on (i.e., extends over) the seventh metallization layer 57 between said seventh metallization layer 57 and the metallized upper central region 11, the dielectric upper region 12, and the metallized upper peripheral region 13; The ceramic substrate comprises eight (internal) ceramic layers and seven (internal) metallized layers (conveniently made of a metal-coated ceramic material, preferably made of a gold-metallized ceramic material) stacked on top of one another in such a way that

[0037] The first, third, fifth and seventh metallization layers 51, 53, 55, 57 are bonded / connected to the metallized outer closure sidewalls 31, 32, 33, 34, whereby the first, third, fifth and seventh metallization layers 51, 53, 55, 57, the metallized outer closure sidewalls 31, 32, 33, 34, the metallized top peripheral region 13 and the metallized bottom peripheral region 23 form an electrical ground structure.

[0038] Instead, the second, fourth and sixth metallization layers 52, 54, 56 are separated from the metallized outer closure sidewalls 31, 32, 33, 34 by respective first dielectric gaps (conveniently made of a non-metal coated ceramic material) extending around the second / fourth / sixth metallization layers 52 / 54 / 56 between the second / fourth / sixth metallization layers 52 / 54 / 56 and the metallized outer closure sidewalls 31, 32, 33, 34.

[0039] Furthermore, the second metallization layer 52 is electrically connected to the metallization bottom central region 21 using a first conductive via 61 (e.g., made of gold), which first conductive via 61 extending vertically through the second ceramic layer 42, the first metallization layer 51, and the first ceramic layer 41 between said second metallization layer 52 and said metallized bottom central region 21; separated from the first metallization layer 51 by a second dielectric gap (conveniently made of a non-metal coated ceramic material) that extends between and around the first conductive via 61 and the first metallization layer 51, thereby forming a first capacitor.

[0040] The fourth metallization layer 54 is electrically connected to the second metallization layer 52 using a second conductive via 62 (e.g., made of gold), which a fourth ceramic layer 44, a third metallization layer 53, and a third ceramic layer 43 extending vertically between the fourth metallization layer 54 and the second metallization layer 52; separated from the third metallization layer 53 by a third dielectric gap (conveniently made of a non-metal coated ceramic material) that extends between and around the second conductive via 62 and the third metallization layer 53, thereby forming a second capacitor.

[0041] The sixth metallization layer 56 is electrically connected to the fourth metallization layer 54 using a third conductive via 63 (e.g., made of gold), which a sixth ceramic layer 46, a fifth metallization layer 55, and extending vertically through the fifth ceramic layer 45 between said sixth metallization layer 56 and said fourth metallization layer 54; separated from the fifth metallization layer 55 by a fourth dielectric gap (conveniently made of a non-metal coated ceramic material) that extends between and around the third conductive via 63 and the fifth metallization layer 55, thereby forming a third capacitor.

[0042] Additionally, the sixth metallization layer 56 is also electrically connected to the metallization upper central region 11 using a fourth conductive via 64 (e.g., made of gold), which extending vertically between the sixth metallization layer 56 and the metallized upper central region 11 through the seventh ceramic layer 47, the seventh metallization layer 57, and the eighth ceramic layer 48; separated from the seventh metallization layer 57 by a fifth dielectric gap (conveniently made of a non-metal coated ceramic material) that extends between and around the fourth conductive via 64 and the seventh metallization layer 57, thereby forming a fourth capacitor.

[0043] As such, the metallization top and bottom central regions 11, 21, the second, fourth and sixth metallization layers 52, 54, 56, the first, second, third and fourth conductive vias 61, 62, 63, 64, and the corresponding first, second, third and fourth capacitors form a capacitive feedthrough structure configured to receive an input electrical signal (conveniently a DC bias signal such as a voltage brought from the outside to the inside of the hermetic hybrid) at the metallization top central region 11 and output a corresponding filtered electrical signal at the metallization bottom central region 21, the input electrical signal being filtered by said first, second, third and fourth capacitors.

[0044] Figure 5 shows An input terminal / port P, which is a schematic representation of the metallized upper central region 11 in and, Output terminal / port P, which is a schematic representation of the metallized bottom central region 21 out and, A series of three resistors R1, R2, R3 interconnected with four shunt capacitors C1, C2, C3, C4, which schematically represent the capacitive feedthrough structure described earlier; 1 shows a schematic circuit diagram of a capacitive feedthrough 1 including:

[0045] Therefore, as explained earlier, the input terminal / port P in The input electrical signal received at is filtered by shunt capacitors C1, C2, C3, C4, whereby a corresponding filtered electrical signal is output to output terminal / port P out It is provided at.

[0046] In this manner, EMI affecting the DC bias provided to the hybrid module is filtered by the capacitive feedthrough 1, thereby providing the capacitive feedthrough 1 with the ability to provide an EMI-free DC bias signal to the hybrid module.

[0047] Advantageously, the capacitive feedthrough 1 can be hermetically sealed to the wall of the housing / casing of the hybrid module by using a eutectic alloy with a predetermined melting temperature (eg 300 / 320° C.).

[0048] In this regard, Figure 6 shows a schematic example of a hermetic sealing of a capacitive feedthrough 1 into a hybrid module. Specifically, Figure 6 shows a vertical cross-section of a capacitive feedthrough 1 embedded in a cavity formed in an outer (metal) wall (indicated by reference numeral 70) of a (metal) enclosure / casing of a hybrid module (not shown in Figure 6).

[0049] The capacitive feedthrough 1 is hermetically sealed to the outer wall 70 of the hybrid module using a eutectic alloy 80 (e.g., a gold-tin (AuSn) alloy), which Between: an outer wall 70 of the hybrid module (in particular the part forming the cavity in which the capacitive feedthrough 1 is arranged / inserted); the metallized outer closure side walls 31, 32, 33, 34 of the capacitive feedthrough 1 and partially the bottom surface 20 of the capacitive feedthrough 1 (specifically only a portion of the metallized bottom peripheral area 23); It is interposed between The hybrid module and the capacitive feedthrough 1 are heated to a predetermined temperature (e.g., 320°C) so as to melt the eutectic alloy 80 and thereby form a hermetic seal between the capacitive feedthrough 1 and the outer wall 70 of the hybrid module.

[0050] More specifically, the capacitive feedthrough 1 is positioned / inserted into a cavity formed by the outer wall 70 of the hybrid module such that the bottom surface 20 faces towards the inside of the hybrid module, while the top surface 10 faces towards the outside of the hybrid module.

[0051] Conveniently, a wire (not shown in FIG. 6) may be soldered (e.g., using an indium-lead (InPb) solder alloy) to the metallized upper central region 11 to provide an input electrical signal to be filtered before being supplied to the hybrid module. For this purpose, American Wire Gauge (AWG) wire may be conveniently used, the diameter of which may be determined based on the current of the input electrical signal.

[0052] Also, a fine wire (not shown in FIG. 6) may be conveniently brazed (e.g., by thermal compression) to the metallized bottom central region 21 to receive the filtered electrical signal provided by the capacitive feedthrough 1 (the diameter of the fine wire being smaller than the diameter of the wire brazed to the top surface 10).

[0053] The encapsulation of the capacitive feedthrough 1 may advantageously be based on other alloys different from (and having a different melting temperature than) the AuSn alloy, such as a gold-germanium (AuGe) alloy.

[0054] As explained above, the capacitive feedthrough 1 represents only a non-limiting example according to a preferred (again non-limiting) embodiment of the present invention.

[0055] In this regard, a capacitive feedthrough according to a more general embodiment of the invention comprises a multilayer ceramic structure, the multilayer ceramic structure comprising: two opposing exterior surfaces including a solid top surface and a solid bottom surface; a metallized outer closure sidewall extending vertically between said opposing outer surfaces around the multilayer ceramic structure; and It is noteworthy that

[0056] Specifically, the multilayer ceramic structure comprises: On the top, a metallized upper central area, which is a planar area without apertures, designed to receive the input electrical signal to be filtered; a dielectric upper region extending around the metallized upper central region; a metallized upper peripheral region extending around the dielectric upper region until it joins with the metallized outer closure sidewall to act as an electrical ground together with the metallized outer closure sidewall, the dielectric upper region being designed to ensure electrical isolation between the input electrical signal and the electrical ground; and Including, On the bottom, a metallized bottom central area that is a planar area without apertures, designed to provide a filtered output electrical signal; a dielectric bottom region extending around a metallized bottom central region; a metallized bottom perimeter region extending around the dielectric bottom region until it joins with the metallized outer closure sidewall to act as an electrical ground together with the metallized outer closure sidewall, the dielectric bottom region being designed to ensure electrical isolation between the filtered output electrical signal and electrical ground; and Includes:

[0057] Also, a multilayer ceramic structure may include four or more ceramic layers stacked together, two or more first metallization layers, and one or more second metallization layers. each first metallization layer is interposed between two respective ceramic layers disposed immediately above and below said first metallization layer; each / its second metallization layer is interposed between two respective ceramic layers located directly above and below said second metallization layer; Each / its second metallization layer - a respective upper first metallization layer disposed above said second metallization layer; - a respective lower first metallization layer disposed below said second metallization layer; the first and second metallization layers alternate vertically, and Two ceramic layers are positioned directly below the top surface and directly above the bottom surface, respectively. Further includes:

[0058] A first metallization layer is coupled to the metallized outer closure sidewall, whereby the first metallization layer, the metallized outer closure sidewall, and the metallized top and bottom peripheral regions form an electrical ground structure.

[0059] Each / its second metallization layer is separated from the metallization outer closure sidewall by a respective first dielectric gap designed to ensure electrical insulation between said second metallization layer and said electrical ground structure.

[0060] Each / its second metallization layer connected to an upper second metallization layer or metallization upper central region through the upper ceramic layer and each upper first metallization layer using respective first conductive vias extending vertically between the second metallization layer and the upper second metallization layer / the metallization upper central region, each first conductive via being separated from a respective upper first metallization layer by a respective second dielectric gap extending around the respective first conductive via, thereby forming a respective first capacitor; and connected to a lower second metallization layer or metallization bottom central region through the lower ceramic layer and the respective lower first metallization layer using respective second conductive vias extending vertically between said second metallization layer and said lower second metallization layer / metallization bottom central region, each said second conductive via being separated from a respective said lower first metallization layer by a respective third dielectric gap extending around said respective second conductive via, thereby forming a respective second capacitor.

[0061] The metallization top central region, the metallization bottom central region, and the second metallization layer, together with the respective conductive vias and the respective capacitors, form a capacitive feedthrough structure configured to receive an input electrical signal at the metallization top central region and to provide a filtered output electrical signal at the metallization bottom central region, whereby filtering of the input electrical signal is performed by the capacitors.

[0062] It is noteworthy that the capacitive feedthrough according to the invention can be used advantageously not only for DC signals but also for low frequency signals such as modulated signals. For example, the capacitive feedthrough can be conveniently designed to perform a predetermined low pass filtering (e.g. up to 100 MHz), thereby enabling its use for both DC signals and low frequency signals (e.g. modulated signals).

[0063] In view of the foregoing, the technical advantages and innovative features of the present invention will be readily apparent to those skilled in the art.

[0064] Specifically, the present invention provides: a hybrid hermetic module and an EMI filtering capacitive feedthrough device based on a multilayer ceramic substrate that is hermetically sealed (conveniently using a eutectic alloy) to the hybrid hermetic module, It provides filtered DC bias access It is important to emphasize that it is possible to fabricate the entire sealing assembly.

[0065] To that end, the present invention teaches the use of multilayer ceramic substrates (preferably multilayer HTCC / LTCC substrates, advantageously multilayer HTCC / LTCC planar substrates) that can be conveniently brazed to the external (metallic) walls of the hybrid module without reliability issues, thereby ensuring the level of hermetic sealing required for space applications.

[0066] The internal layers of the multilayer ceramic substrate are advantageously utilized to create capacitive feedthrough structures (with metal planes parallel to each other). In particular, the shape and size of each internal metal plane can be conveniently designed in a three-dimensional (3D) electromagnetic simulator to adjust / optimize the filtering performed by the capacitive feedthrough (e.g., to enable its use not only for DC signals, but also for low-frequency signals such as modulated signals, as described above).

[0067] It is noteworthy that the use of a capacitive feedthrough structure based on a multilayer ceramic substrate as an EMI filter hermetically sealed in the housing of a hybrid module to solve the EMC / EMI shielding problem of the hybrid module is innovative, and the present invention allows for miniaturization of the device size thanks to its reduced dimensions compared to conventional non-hermetic capacitive feedthroughs. For example, the present invention advantageously allows for the use of a multilayer HTCC substrate in the form of a parallelepiped with dimensions of 2.75x2.75x2.5 mm, while the limiting dimensions of conventional glass capacitive feedthroughs are on the order of 4x4x20 mm.

[0068] Furthermore, contrary to the feedthrough capacitor structure described in US Patent Application Publication No. 2005 / 190527(A1), the capacitive feedthrough structure according to the present invention provides excellent EMI filtering performance, in particular, provides EMI filtering performance suitable for space applications, and does not require the additional elements of the feedthrough capacitor structure disclosed in US Patent Application Publication No. 2005 / 190527(A1) (such as a hollow passage with a surface metal coating, and a metallized opening, a terminal pin, a conductive insert, and a conductive ferrule), thereby making the manufacturing process of the capacitive feedthrough structure according to the present invention much simpler.

[0069] Finally, it will be apparent that numerous modifications and variations can be made to the present invention, all of which are within the scope of the invention as defined in the appended claims. [Explanation of symbols]

[0070] 1 Capacitive Feedthrough 10 Top side 11 Metallization upper central area 12 Dielectric upper region 13 Metallized upper peripheral area 20 bottom 21 Metallized bottom central area 22 Dielectric bottom region 23 Metallized bottom perimeter area 41 First ceramic layer 42 Second ceramic layer 43 Third ceramic layer 44 Fourth ceramic layer 45 Fifth ceramic layer 46 Sixth ceramic layer 47 Seventh Ceramic Layer 48 Eighth Ceramic Layer 51 First Metallization Layer 52 Second Metallization Layer 53 Third Metallization Layer 54 Fourth Metallization Layer 55 Fifth Metallization Layer 56 Sixth Metallization Layer 57 Seventh Metallization Layer 61 First conductive via 62 Second conductive via 63 Third Conductive Via 64 Fourth Conductive Via 70 Outer wall of enclosure / casing 80 Eutectic Alloy C1, C2, C3, C4 shunt capacitors P in Input terminal / port P out Output terminal / port R1, R2, R3 registers

Claims

1. A hermetically sealable capacitive feedthrough (1) for a hybrid module for space applications, comprising a multilayer ceramic structure, said multilayer ceramic structure comprising: two opposing outer surfaces including a top surface (10) and a bottom surface (20); a metallized outer closure sidewall (31, 32, 33, 34) extending vertically around the multilayer ceramic structure between the opposing outer surfaces (10, 20); and The multilayer ceramic structure comprises: On the upper surface (10), a metallized upper central area (11) designed to receive the input electrical signal to be filtered; a dielectric upper region (12) extending around said metallized upper central region (11); a metallized upper peripheral region (13) extending around the dielectric upper region (12) until it joins with the metallized outer closure sidewalls (31, 32, 33, 34) so ​​as to act as an electrical ground together with the metallized outer closure sidewalls (31, 32, 33, 34), the dielectric upper region (12) being designed to ensure electrical isolation between the input electrical signal and the electrical ground; Including, On the bottom surface (20), a metallized bottom central region (21) designed to provide a filtered output electrical signal; a dielectric bottom region (22) extending around said metallized bottom central region (21); a metallized bottom periphery region (23) extending around the dielectric bottom region (22) until joining the metallized outer closure sidewalls (31, 32, 33, 34) to act as an electrical ground together with the metallized outer closure sidewalls (31, 32, 33, 34), the dielectric bottom region (22) being designed to ensure electrical isolation between the filtered output electrical signal and the electrical ground; Including, The multilayer ceramic structure further includes ceramic layers (41, 42, 43, 44, 45, 46, 47, 48), a first metallization layer (51, 53, 55, 57), and one or more second metallization layers (52, 54, 56) stacked on top of one another, thereby: each first metallization layer (51, 53, 55, 57) is interposed between two respective ceramic layers (41, 42, 43, 44, 45, 46, 47, 48) disposed directly above and below said first metallization layer (51, 53, 55, 57); each second metallization layer (52, 54, 56) is interposed between two respective ceramic layers (42, 43, 44, 45, 46, 47) disposed directly above and below said second metallization layer (52, 54, 56); The first and second metallization layers (51, 52, 53, 54, 55, 56, 57) are vertically alternated, so that each second metallization layer (52, 54, 56) a respective upper first metallization layer (53, 55, 57) disposed above said second metallization layer (52, 54, 56); a lower first metallization layer (51, 53, 55) disposed below each of the second metallization layers (52, 54, 56); and Two ceramic layers (41, 48) are disposed directly below the top surface (10) and directly above the bottom surface (11), respectively; the first metallization layer (51, 53, 55, 57) is bonded to the metallized outer closure sidewalls (31, 32, 33, 34), whereby the first metallization layer (51, 53, 55, 57), the metallized outer closure sidewalls (31, 32, 33, 34), and the metallized top and bottom peripheral regions (13, 23) form an electrical ground structure; each second metallization layer (52, 54, 56) is separated from said metallization outer closure sidewall (31, 32, 33, 34) by a respective first dielectric gap designed to ensure electrical insulation between said second metallization layer (52, 54, 56) and said electrical ground structure; Each second metallization layer (52, 54, 56) connected to the upper second metallization layer (52, 54, 56) or the metallization upper central region (11) through the upper ceramic layer (43, 44, 45, 46, 47, 48) and the respective upper first metallization layer (53, 55, 57) by respective first conductive vias (62, 63, 64) extending vertically between the second metallization layer (52, 54, 56) and the upper second metallization layer (52, 54, 56) or the metallization upper central region (11), each of the first conductive vias (62, 63, 64) being separated from its respective upper first metallization layer (53, 55, 57) by a respective second dielectric gap extending around the respective first conductive via (62, 63, 64), thereby forming a respective first capacitor; Each of the second metallization layers (52, 54, 56) comprises: connected to a lower second metallization layer (52, 54, 56) or said metallization bottom central region (21) through a lower ceramic layer (41, 42, 43, 44, 45, 46) and each lower first metallization layer (51, 53, 55) using a respective second conductive via (61, 62, 63) extending vertically between said second metallization layer (52, 54, 56) and said lower second metallization layer (52, 54, 56) or said metallization bottom central region (21), each said second conductive via (61, 62, 63) being separated from a respective lower first metallization layer (51, 53, 55) by a respective third dielectric gap extending around each said second conductive via (61, 62, 63), thereby forming a respective second capacitor; the metallization top and bottom central regions (11, 21) and the second metallization layer (52, 54, 56), together with the respective conductive vias (61, 62, 63, 64) and the respective capacitors, form a capacitive feedthrough structure configured to receive the input electrical signal in the metallization top central region (11) and to provide the filtered output electrical signal in the metallization bottom central region (21), whereby filtering of the input electrical signal is performed by the capacitors; A capacitive feedthrough (1), characterized in that said metallized top and bottom central regions (11, 21) are planar regions without openings.

2. 2. The capacitive feedthrough of claim 1, wherein the metallized top central region (11) is larger than the metallized bottom central region (21) and the metallized bottom peripheral region (23) is larger than the metallized top peripheral region (13).

3. 3. The capacitive feedthrough of claim 1, wherein the multilayer ceramic structure includes four or more ceramic layers (41, 42, 43, 44, 45, 46, 47, 48) and two or more first metallization layers (51, 53, 55, 57).

4. 4. A capacitive feedthrough according to claim 1, wherein the multilayer ceramic structure is a high-temperature or low-temperature co-fired ceramic multilayer substrate.

5. 5. The capacitive feedthrough of claim 4, wherein the multilayer ceramic structure is a multilayer high temperature co-fired ceramic planar substrate or a low temperature co-fired ceramic planar substrate.

6. 6. The capacitive feedthrough of claim 1, wherein the metallized outer closure sidewalls (31, 32, 33, 34), the metallized top and bottom central regions (11, 21), the metallized top and bottom peripheral regions (13, 23), and the first and second metallized layers (51, 52, 53, 54, 55, 56, 57) are made of a metal-coated ceramic material.

7. 7. The capacitive feedthrough of claim 6, wherein the metallized outer closure sidewalls (31, 32, 33, 34), the metallized top and bottom central regions (11, 21), the metallized top and bottom peripheral regions (13, 23), and the first and second metallized layers (51, 52, 53, 54, 55, 56, 57) are made of a ceramic material metallized with gold.

8. 8. The capacitive feedthrough of claim 1, wherein the dielectric top and bottom regions (12, 22) are made of a ceramic material without a metal coating, and for each second metallization layer (52, 54, 56), the respective first, second, and third dielectric gaps are made of a ceramic material without a metal coating.

9. A capacitive feedthrough as described in any one of claims 1 to 8, wherein for each second metallization layer (52, 54, 56), each of the conductive vias (61, 62, 63, 64) is made of gold.

10. a hybrid sealed module; A capacitive feedthrough (1) according to any one of claims 1 to 9, hermetically sealed to the hybrid hermetic module using a eutectic alloy (80); 1. A sealed assembly for space applications, comprising:

11. 11. The sealing assembly of claim 10, wherein the capacitive feedthrough (1) is hermetically sealed to the hybrid sealed module such that the bottom surface (20) of the capacitive feedthrough (1) faces toward the inside of the hybrid module and the top surface (10) of the capacitive feedthrough (1) faces toward the outside of the hybrid module.

12. The sealing assembly of claim 10 or 11, wherein the eutectic alloy (80) is a gold-tin alloy or a gold-germanium alloy.

13. A space platform including a seal assembly according to any one of claims 10 to 12.

14. The space platform of claim 13 , wherein the space platform is a satellite, a spacecraft, a space station, or a space vehicle.

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