structure

Abstract

To provide a structure that reduces manufacturing costs by eliminating the need for an adhesive layer to fix a height adjustment portion (spacer) for adjusting the height of a semiconductor chip to a substrate, while fine-tuning the height from the substrate to the semiconductor chip to a specified value.SOLUTION: A structure 100 includes a substrate B, wirings E1 and E2 provided on the substrate B, an insulating layer SR provided on the substrate B so as to cover all or a part of the wirings E1 and E2, a height adjustment portion D provided in a first region A1 on the substrate B via the insulating layer SR and made of at least one of an organic resin and an organic resin composition, and a first semiconductor chip IC1 arranged on the height adjustment portion D so as to be supported by the height adjustment portion D.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a structure including a semiconductor chip. [Background technology]

[0002] Conventionally, a structure (semiconductor device) has been disclosed that includes a substrate, a height-adjusting member (spacer) mounted on the substrate via a first adhesive layer, a first semiconductor chip mounted on the height-adjusting member via a second adhesive layer, a second semiconductor chip mounted on the substrate via the second adhesive layer, a plurality of bonding wires connecting each wiring provided on the substrate to the terminals of each semiconductor chip, and a sealing member that seals these components on the substrate (see, for example, Patent Document 1).

[0003] In such a conventional structure, the height adjustment member is made of an inorganic material, and therefore, in order to fix the height adjustment member to the substrate, the first adhesive layer is required as described above, and the manufacturing cost of the structure is increased because steps for forming and aligning the first adhesive layer are required.

[0004] Furthermore, since the height-adjusting member is an inorganic member, it is difficult to fine-tune its thickness, making it difficult to fine-tune the height from the substrate to the first semiconductor chip; for example, it is necessary to adjust the height by adjusting the thickness of the first adhesive layer that fixes the height-adjusting member to the substrate, thereby necessitating further individual settings.

[0005] As described above, the above-mentioned conventional technology structure reduces manufacturing costs by eliminating the need for an adhesive layer to fix a height adjustment part (spacer) for adjusting the height of the semiconductor chip to the substrate, but has the problem that it is not possible to fine-tune the height from the substrate to a specified value. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-138035 A Summary of the Invention [Problem to be solved by the invention]

[0007] Therefore, in consideration of the problems of the conventional technology, the present invention aims to provide a structure that can finely adjust the height from the substrate to a predetermined value while reducing manufacturing costs by eliminating the need for an adhesive layer to fix a height adjustment part (spacer) for adjusting the height of the semiconductor chip to the substrate. [Means for solving the problem]

[0008] A structure according to an embodiment of the present invention comprises: A substrate; Wiring provided on the substrate; an insulating layer provided on the substrate so as to cover all or a part of the wiring; a height adjusting portion provided in the first region on the substrate via the insulating layer and made of at least one of an organic resin and an organic resin composition; a first semiconductor chip disposed on the height adjustment portion so as to be supported by the height adjustment portion; Equipped with.

[0009] In the structure according to the embodiment of the present invention, a resin layer that seals the first semiconductor chip on the substrate; It may further include:

[0010] In the structure according to the embodiment of the present invention, a second semiconductor chip disposed in a second region on the substrate, the second semiconductor chip being disposed with the insulating layer interposed therebetween, the second semiconductor chip being disposed in a second region different from the first region on the substrate; The semiconductor device may further include a resin layer that seals the first semiconductor chip and the second semiconductor chip on the substrate.

[0011] In the structure according to the embodiment of the present invention, A height from an upper surface of the substrate to an upper surface of the height adjustment portion may be set to be higher than a height from the upper surface of the substrate to an upper surface of the second semiconductor chip.

[0012] In the structure according to the embodiment of the present invention, An end portion of the first semiconductor chip may be located above or beside the second semiconductor chip at the same height.

[0013] In the structure according to the embodiment of the present invention, A first insulating adhesive layer may be provided in the first region to bond an upper surface of the height adjustment portion and a lower surface of the first semiconductor chip.

[0014] In the structure according to the embodiment of the present invention, The height adjustment unit is a first height adjustment portion extending in a first direction in the first region; a second height adjustment portion extending in the first direction in the first region and spaced apart from the first height adjustment portion, The resin layer may be provided between the first height adjustment portion and the second height adjustment portion.

[0015] In the structure according to the embodiment of the present invention, The height adjustment unit is a third height adjustment portion extending in a second direction different from the first direction in the first region; a fourth height adjustment portion extending in the second direction in the first region and spaced apart from the first to third height adjustment portions, The resin layer may be provided between the first to fourth height adjustment portions.

[0016] In the structure according to the embodiment of the present invention, The insulating layer and the height adjusting portion may be made of at least one of the same organic resin and organic resin composition.

[0017] In the structure according to the embodiment of the present invention, The height adjustment portion may include a base portion provided between the insulating layer and the first and second height adjustment portions.

[0018] In the structure according to the embodiment of the present invention, The insulating layer, the first and second height adjustment portions, and the base portion may be made of the same organic resin.

[0019] In the structure according to the embodiment of the present invention, At least one of the organic resin and the organic resin composition may be photosensitive.

[0020] In the structure according to the embodiment of the present invention, a second insulating adhesive layer that adheres between the upper surface of the insulating layer and the lower surface of the second semiconductor chip in the second region; The semiconductor device may further include a second bonding wire that connects a second wiring of the wirings and a terminal provided on the upper surface of the second semiconductor chip.

[0021] In the structure according to the embodiment of the present invention, a bump electrode that connects a second wiring of the wirings and a terminal provided on a lower surface of the second semiconductor chip; The semiconductor device may further include an underfill resin provided between the insulating layer and the second semiconductor chip, bonding the insulating layer to the lower surface of the second semiconductor chip and sealing the terminals and the bump electrodes.

[0022] In the structure according to the embodiment of the present invention, The distance between the lower surface of the first semiconductor chip and the second bonding wires may be set to a preset distance.

[0023] In the structure according to the embodiment of the present invention, The semiconductor device may further include a first bonding wire that connects a first wiring of the wirings and a terminal provided on an upper surface of the first semiconductor chip.

[0024] In the structure according to the embodiment of the present invention, The resin layer may be made of a different material from that of the height adjustment portion.

[0025] In the structure according to the embodiment of the present invention, One or a plurality of third semiconductor chips may be stacked on the first semiconductor chip.

[0026] In the structure according to the embodiment of the present invention, The first semiconductor chip may include a semiconductor memory.

[0027] In the structure according to the embodiment of the present invention, The second semiconductor chip may include a controller that controls an operation of the first semiconductor chip.

[0028] In the structure according to the embodiment of the present invention, The insulating layer may be made of a solder resist.

[0029] In the structure according to the embodiment of the present invention, The height adjustment portion may be insulating.

[0030] In the structure according to the embodiment of the present invention, The distance between the bottom surface of the first semiconductor chip and the top surface of the second semiconductor chip may be set to a preset distance. Effect of the Invention

[0031] According to one embodiment of the present invention, a structure can be provided that can reduce manufacturing costs by eliminating the need for an adhesive layer to fix a height adjustment portion (spacer) for adjusting the height of a semiconductor chip to a substrate, while allowing the height from a substrate to be finely adjusted to a predetermined value. [Brief description of the drawings]

[0032] [Figure 1] FIG. 1 is a cross-sectional view that diagrammatically illustrates an example of a cross section of a structure 100 according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a top view showing an example of a configuration focusing on a region in the vicinity of height adjustment unit D of structure 100 shown in FIG. [Diagram 3] FIG. 3 is a top view showing another example of the configuration focusing on the region in the vicinity of height adjustment unit D of structure 100 shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view that diagrammatically illustrates an example of a cross section of a structure 100A according to a first modified example. [Diagram 5] FIG. 5 is a cross-sectional view that diagrammatically illustrates an example of a cross section of a structure 100B according to the second modified example. [Figure 6] FIG. 6 is a top view showing an example of a configuration focusing on a region near height adjustment unit D of structure 100B shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view that diagrammatically illustrates another example of a cross section of the structure 100B according to the second modified example. [Figure 8] FIG. 8 is a cross-sectional view that diagrammatically illustrates an example of a cross section of a structure 100C according to a third modified example. [Figure 9] FIG. 9 is a top view showing an example of a configuration focusing on a region near height adjustment unit D of structure 100C shown in FIG. [Figure 10]FIG. 10 is a cross-sectional view that diagrammatically illustrates another example of a cross section of a structure 100C according to the third modified example. [Figure 11] FIG. 11 is a cross-sectional view that diagrammatically illustrates an example of a cross section of a structure 100D according to a fourth modified example. [Figure 12] FIG. 12 is a cross-sectional view that diagrammatically illustrates another example of a cross section of a structure 100D according to the fourth modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Hereinafter, embodiments and modifications of the present invention will be described in detail with reference to the drawings. Note that the embodiments described below are merely examples of the present disclosure, and the present disclosure should not be construed as being limited to these embodiments or their modifications. In addition, terms used in this specification that specify shapes, geometric conditions, and the extent thereof, such as "parallel" and "orthogonal," as well as values ​​of length and angle, are not to be bound by strict meanings, but are to be interpreted to include a range within which similar functions can be expected. In addition, in the drawings referred to in this embodiment, the same parts or parts having similar functions are denoted by the same or similar reference numerals, and repeated explanations thereof may be omitted. Furthermore, the dimensional ratios of the drawings may differ from the actual ratios for the convenience of explanation, and some components may be omitted from the drawings.

[0034] Hereinafter, a structure according to an embodiment of the present disclosure will be described with reference to FIGS.

[0035] Here, Fig. 1 is a cross-sectional view that shows a schematic example of a cross section of a structure 100 according to an embodiment of the present invention. And Fig. 2 is a top view that shows an example of a configuration focusing on a region in the vicinity of height adjustment unit D of structure 100 shown in Fig. 1. Note that the cross section taken along line A-A in Fig. 2 corresponds to the cross section of the configuration focusing on the region in the vicinity of height adjustment unit D of structure 100 shown in Fig. 1. Also, Fig. 3 is a top view showing another example of the configuration focusing on the region near the height adjustment unit D of the structure 100 shown in Fig. 1. Note that the cross section taken along the line A-A shown in Fig. 3 corresponds to the cross section of the configuration focusing on the region near the height adjustment unit D of the structure 100 shown in Fig. 1.

[0036] [Structure] The structure 100 of this embodiment includes, for example, as shown in FIG. 1, a substrate B, wirings E1, E2, EX (first wiring E1, second wiring E2, third wiring EX), an insulating layer SR, a height adjustment portion D, a first insulating adhesive layer M1, a first semiconductor chip IC1, a first bonding wire W1, a second insulating adhesive layer M2, a second semiconductor chip IC2, a second bonding wire W2, a third insulating adhesive layer M3a, a third semiconductor chip IC3a, a third bonding wire W3a, and a resin layer F.

[0037] 1, the structure 100 is, for example, a semiconductor memory device. However, the configuration of the structure 100 can also be applied to semiconductor devices other than semiconductor memory devices and other devices.

[0038] [substrate] 1 is, for example, a printed wiring board. This substrate B includes, for example, a base material made of glass epoxy resin.

[0039] A plurality of wirings E1, E2, and EX are provided on the substrate B. The plurality of wirings E1, E2, and EX are fixed to the substrate B. Note that the plurality of wirings E1, E2, and EX are, for example, wirings containing copper, but may be composed of other conductive metals such as aluminum.

[0040] [Insulation layer] The insulating layer SR of the structure 100 shown in FIG. 1 is provided on the substrate B so as to cover all or part of the wirings E1, E2, and EX.

[0041] In particular, this insulating layer SR is made of, for example, at least one of a photosensitive resin and a photosensitive resin composition, but may be made of other organic resins or the like.

[0042] This insulating layer SR is, for example, composed of a solder resist, which is a cured ink that covers the surface of the substrate B on which wiring is provided and becomes an insulating film that protects the pattern circuit. The ink for forming the solder resist is classified into, for example, "alkali development type solder resist ink", "UV curing type solder resist ink", "thermosetting type solder resist ink", etc., depending on the method of forming the coating film. For example, "alkali development type solder resist ink" is a solder resist ink that can form a fine pattern by exposing a printed wiring board on which solder resist ink has been applied over the entire surface by screen printing, spraying, or curtain method through a negative film on which a pattern has been made, and developing the uncured parts with a dilute alkaline developer. Also, "UV curing type solder resist ink" is a type of solder resist ink that is pattern printed by a screen printing method and cured by irradiating UV light (ultraviolet rays). Also, "thermosetting type solder resist ink" is a type of solder resist ink that is pattern printed by a screen printing method and cured by heating.

[0043] Here, as an example, a method of patterning using a photosensitive resin composition will be described below, although it goes without saying that a dry film can be used instead of the photosensitive resin composition.

[0044] First, the photosensitive resin composition is applied to the surface of the substrate. The application method is not particularly limited, and a known application method such as a screen printing method, a bar coater, or a blade coater can be adopted. The thickness of the photosensitive resin can be appropriately adjusted by the amount of application.

[0045] Next, the coating film of the resin composition is exposed through a negative mask having a predetermined pattern. The exposure may be either contact exposure or non-contact exposure. Alternatively, a pattern may be formed in the coating film by a laser direct imaging device without using a mask.

[0046] The coating film is then developed to give the exposed coating a pattern. By using a dilute alkaline aqueous solution as the developer, it is possible to obtain a coating film with excellent resolution after exposure with little damage to the exposed coating film.

[0047] After development, the photosensitive resin composition is fully cured by heat or ultraviolet irradiation, thereby forming a cured resin layer having a desired pattern.

[0048] [Height adjustment section] The height adjusting portion D of the structure 100 shown in FIG.

[0049] The height adjustment section D is made of, for example, at least one of an organic resin and an organic resin composition (hereinafter, also referred to as an organic resin material). In particular, the height adjustment section D is made of, for example, at least one of a photosensitive resin and a photosensitive resin composition. It is preferable that the height adjustment section D has insulating properties.

[0050] The insulating layer SR and the height adjusting portion D may have the same composition, or may have different compositions.

[0051] Here, the height adjustment portion D may include, for example, a base portion DX, a first height adjustment portion D1, and a second height adjustment portion D2, as shown in FIG. 1 and FIG.

[0052] The first height adjustment portion D1 extends in the first direction X in the first region A1, for example, as shown in FIGS.

[0053] Also, the second height adjustment portion D2 extends in the first direction X in the first region A1 and is spaced apart from the first height adjustment portion D1. Note that, although the first height adjustment portion D1 and the second height adjustment portion D2 are arranged parallel to each other in the first region A1 in the example of Fig. 1 and Fig. 2, they do not necessarily have to be arranged parallel to each other as long as they can support the first semiconductor chip IC1.

[0054] In particular, a resin layer F is provided between the first height adjustment portion D1 and the second height adjustment portion D2, as shown in Figures 1 and 2. That is, the resin layer F is filled between the first height adjustment portion D1 and the second height adjustment portion D2.

[0055] Furthermore, in the example of FIG. 2, the first and second height adjustment portions D1, D2 are arranged in two rows, but each height adjustment portion may be arranged in four rows.

[0056] That is, the height adjustment portion D may include, for example, a base portion DX, a first height adjustment portion D1, a second height adjustment portion D2, a third height adjustment portion D3, and a fourth height adjustment portion D4, as shown in FIG. 3.

[0057] The first height adjustment portion D1 extends in the first direction X in the first region A1, for example, as shown in FIGS.

[0058] Also, the second height adjustment portion D2 extends in the first direction X in the first region A1 and is spaced apart from the first height adjustment portion D1. Note that, although the first height adjustment portion D1 and the second height adjustment portion D2 are arranged parallel to each other in the first region A1 in the examples of Fig. 1 and Fig. 3, they do not necessarily have to be arranged parallel to each other as long as they can support the first semiconductor chip IC1.

[0059] Furthermore, the third height adjustment portion D3 extends in a second direction Y different from (for example, perpendicular to) the first direction X in the first region A1, as shown in FIG. 3, and is spaced apart from the first and second height adjustment portions D1 and D2.

[0060] Also, the fourth height adjustment portion D4, for example, as shown in FIG. 3, extends in the second direction Y in the first region A1 and is provided spaced apart from the first to third height adjustment portions D1, D2, and D3.

[0061] Here, a resin layer F is provided between the first to fourth height adjustment portions D1, D2, D3, and D4. That is, above the substrate B, the resin layer F is filled between the first height adjustment portion D1, the second height adjustment portion D2, the third height adjustment portion D3, and the fourth height adjustment portion D4.

[0062] 1 to 3 are merely examples, and may have other configurations and arrangements that have similar functions, or may be omitted as necessary, as described later. That is, the height adjustment unit D may be configured with only the base portion DX.

[0063] The height adjustment portion D is formed by, for example, patterning by inkjet coating of an organic resin material, patterning by pattern printing of an organic resin material, or patterning of a photosensitive organic resin material using photolithography technology (exposure, development), followed by a predetermined curing process. In particular, patterning of a photosensitive organic resin material is preferable in that a fine pattern can be formed when finely forming height adjustment portions such as D1 and D2. Patterning by pattern printing is preferable in that it can be easily performed when forming a shape such as the pedestal portion DX. In addition, adhesion to the base (insulating layer SR) is also obtained.

[0064] The insulating layer SR and the height adjustment portion D may be made of, for example, the same organic resin material. That is, the insulating layer SR, the first and second height adjustment portions D1 and D2, and the base portion DX may be made of the same organic resin material.

[0065] In this case, the organic resin material is, for example, at least one of a photosensitive resin and a photosensitive resin composition.

[0066] In this case, for example, the insulating layer SR, the first and second height adjustment parts D1, D2, and the pedestal part DX can be formed by a method for forming a multi-stage solder resist structure. That is, for example, after forming a film of a photosensitive organic resin material on the insulating layer SR, it is possible to simultaneously form the insulating layer SR, the first and second height adjustment parts D1, D2, and the pedestal part DX by exposing and developing the film in stages so as to leave the parts corresponding to the first and second height adjustment parts D1, D2.

[0067] However, the insulating layer SR and the height adjustment portion D may be made of, for example, different organic resin materials as necessary. That is, the insulating layer SR, the first and second height adjustment portions D1 and D2, and the base portion DX may be made of different organic resin materials.

[0068] [First semiconductor chip] The first semiconductor chip IC1 of the structure 100 shown in FIG.

[0069] The first semiconductor chip IC1 includes, for example, any semiconductor memory, and specifically, the semiconductor memory includes, for example, a NAND flash memory.

[0070] [First insulating adhesive layer] The first insulating adhesive layer M1 is provided on the lower surface of the first semiconductor chip IC1, and adheres between the upper surface of the height adjustment portion D and the lower surface of the first semiconductor chip IC1 in the first region A1. That is, the first insulating adhesive layer M1 fixes the lower surface of the first semiconductor chip IC1 to the upper surface of the height adjustment portion D. The first insulating adhesive layer may be located only on the contact surface with the lower surface of the first semiconductor chip IC1, or may be located on the entire lower surface of the first semiconductor chip IC1.

[0071] The first insulating adhesive layer M1 may be made of a suitable material such as a die attach material, a die attach film, or other similar materials.

[0072] [First bonding wire] The first bonding wire W1 electrically connects the first wiring E1 of the wirings E1, E2, and EX to a terminal G1 provided on the upper surface of the first semiconductor chip IC1.

[0073] The material of the first bonding wires W1 is, for example, gold, but is not limited to this.

[0074] [Second semiconductor chip] The second semiconductor chip IC2 is arranged in a second area A2 different from the first area A1 on the substrate B, with an insulating layer SR interposed therebetween.

[0075] For example, as shown in FIG. 1, the end IC1a of the first semiconductor chip IC1 is located above the second semiconductor chip IC2, but it may be located beside the second semiconductor chip IC2 at the same height.

[0076] Here, the second semiconductor chip IC2 includes, for example, a controller that controls the operation of the first semiconductor chip IC1.

[0077] More specifically, the controller included in the second semiconductor chip IC2 is, for example, a controller integrated circuit that controls a NAND flash memory.

[0078] The controller included in the second semiconductor chip IC2, for example, writes data to the semiconductor memory of the first semiconductor chip IC1, reads data from the semiconductor memory of the first semiconductor chip IC1, erases data from the semiconductor memory of the first semiconductor chip IC1, and so on in accordance with external commands, thereby managing the storage state of the data in the semiconductor memory of the first semiconductor chip IC1.

[0079] [Second insulating adhesive layer] The second insulating adhesive layer M2 is provided on the lower surface of the second semiconductor chip IC2 and adheres between the upper surface of the insulating layer SR and the lower surface of the second semiconductor chip IC2 in the second region A2. That is, the lower surface of the second semiconductor chip IC2 is fixed to the upper surface of the insulating layer SR by the second insulating adhesive layer M2. The second insulating adhesive layer may be located only on the contact surface with the lower surface of the second semiconductor chip IC2 or may be located on the entire lower surface of the second semiconductor chip IC2.

[0080] The second insulating adhesive layer M2 may be made of a suitable material such as a die attach material, a die attach film, or other similar materials.

[0081] [Second bonding wire] The second bonding wire W2 electrically connects the second wiring E2 of the multiple wirings E1, E2, EX to a terminal G2 provided on the upper surface of the second semiconductor chip IC2.

[0082] The material of the second bonding wires W2 is, for example, gold, but is not limited to this.

[0083] [Third semiconductor chip] The third semiconductor chip IC3a of the structure 100 shown in Fig. 1 is arranged on the first semiconductor chip IC1 so as to be shifted in the first direction X from the position where the first semiconductor chip IC1 is inserted, particularly when wiring is performed by wire bonding as shown in Fig. 1. In this manner, one third semiconductor chip IC3a may be mounted on the first semiconductor chip IC1.

[0084] Also, the third semiconductor chip IC3a includes, for example, an arbitrary semiconductor memory like the first semiconductor chip IC1, and specifically, as this semiconductor memory, for example, it includes a NAND flash memory.

[0085] In this case, the controller included in the second semiconductor chip IC2, for example, in accordance with external commands, writes data to the semiconductor memories of the first semiconductor chip IC1 and the third semiconductor chip IC3a, reads data from the semiconductor memories of the first semiconductor chip IC1 and the third semiconductor chip IC3a, and erases data from the semiconductor memories of the first semiconductor chip IC1 and the third semiconductor chip IC3a, thereby managing the storage state of the data in the semiconductor memories of the first semiconductor chip IC1 and the third semiconductor chip IC3a.

[0086] As mentioned above, the example of Figure 1 shows a case where one third semiconductor chip IC3a is mounted on the first semiconductor chip IC1, but as described in a modified example below, the number of third semiconductor chips stacked on the first semiconductor chip IC1 may be, for example, two or more.

[0087] [Third insulating adhesive layer] The third insulating adhesive layer M3a is provided on the lower surface of the third semiconductor chip IC3a and is adapted to bond between the lower surface of the third semiconductor chip IC3a and the upper surface of the first semiconductor chip IC1. That is, the lower surface of the third semiconductor chip IC3a is fixed to the upper surface of the first semiconductor chip IC1 by the third insulating adhesive layer M3a. The third insulating adhesive layer may be located only on the contact surface with the lower surface of the third semiconductor chip IC3a or may be located on the entire lower surface of the second semiconductor chip IC3a.

[0088] The third insulating adhesive layer M3 may be made of a suitable material such as a die attach material, a die attach film, or other similar materials.

[0089] [Third bonding wire] The third bonding wire W3a electrically connects between wiring (not shown) provided on the substrate and a terminal G3a provided on the upper surface of the third semiconductor chip IC3a.

[0090] The material of the third bonding wires W3a is, for example, gold, but is not limited to this.

[0091] [Resin layer] The resin layer F encapsulates, on the substrate B, the wirings E1, E2, EX, the first bonding wire W1, the second bonding wire W2, the third bonding wire W3a, the first semiconductor chip IC1, the second semiconductor chip IC2, and the third semiconductor chip IC3a.

[0092] The resin layer F is made of, for example, a material different from that of the height adjustment portion D. However, the resin layer F may be made of the same material as that of the height adjustment portion D. The resin layer F is, for example, at least one of a thermosetting resin and a thermosetting resin composition.

[0093] Here, for example, as shown in Figure 1, the height from the top surface of the substrate B to the top surface of the height adjustment portion D (in the example of Figure 1, the top surfaces of the first height adjustment portion D1 and the second height adjustment portion D2) (in particular, the height to the bottom surface of the first semiconductor chip IC1 and the bottom surface of the first insulating adhesive layer M1) is equal to or higher than the height from the top surface of the substrate B to the top surface of the second semiconductor chip IC2.

[0094] In particular, the distance (shortest distance) Ha between the bottom surface of the first semiconductor chip IC1 (in the example of Figure 1, the bottom surface of the first insulating adhesive layer M1) and the top surface of the second semiconductor chip IC2 is set to a predetermined distance (this distance Ha is adjusted by adjusting the height of the height adjustment portion D).

[0095] In this way, by finely adjusting the height of the height adjustment portion D in the structure 100, it becomes possible to appropriately control, for example, the distance in the third direction Z between the first semiconductor chip IC1 and the second semiconductor chip IC2 whose arrangement regions overlap. In other words, it becomes possible to control the film thickness of the structure 100 to an optimal film thickness.

[0096] In addition, the distance Hb (shortest distance in the third direction Z) between the underside of the first semiconductor chip IC1 (in the example of Figure 1, the underside of the first insulating adhesive layer M1) and the second bonding wire W2 is set to a preset distance (this distance Hb is adjusted by adjusting the height of the height adjustment portion D).

[0097] In this way, by finely adjusting the height of the height adjustment portion D in the structure 100, for example, in the area where the first semiconductor chip IC1 and the second semiconductor chip IC2 are arranged overlapping, the distance between the second bonding wire W2 and the first semiconductor chip IC1 can be controlled to an optimal film thickness, thereby improving the product yield of the structure 100.

[0098] As described above, the structure 100 of this embodiment comprises a substrate B, wirings E1, E2, and EX provided on the substrate B, an insulating layer SR provided on the substrate B so as to cover all or part of the wirings E1, E2, and EX, a height adjustment portion D provided in a first region A1 on the substrate B via the insulating layer SR and composed of at least one of an organic resin and an organic resin composition, and a first semiconductor chip IC1 arranged on the height adjustment portion D so as to be supported by the height adjustment portion D.

[0099] In this way, by applying the height adjustment portion D composed of at least one of an organic resin and an organic resin composition as a spacer for adjusting the height from the substrate B to the first semiconductor chip IC1, an adhesive layer for fixing the height adjustment portion D to the substrate B is not required, thereby reducing the manufacturing cost of the structure 100.

[0100] Furthermore, since the height adjustment portion D, which is made of at least one of an organic resin and an organic resin composition, can easily have its thickness finely adjusted, it becomes easy to finely adjust the height from the substrate B to the first semiconductor chip IC1.

[0101] In other words, according to the structure 100 of this embodiment, it is possible to provide a structure that can finely adjust the height from the substrate to the semiconductor chip to a predetermined value while reducing manufacturing costs by eliminating the need for an adhesive layer for fixing a height adjustment portion (spacer) for adjusting the height of the semiconductor chip to the substrate.

[0102] Various modifications can be made to the above-described embodiment. Each modification will be described below with reference to the drawings as necessary. In the following description and the drawings used in the following description, the same reference numerals as those used for the corresponding parts in the above-described embodiment will be used for parts that can be configured in the same manner as in the above-described embodiment, and duplicated descriptions will be omitted. In addition, if it is clear that the effects obtained in the above-described embodiment can also be obtained in the modification, the description may be omitted.

[0103] (First Modification) In the above-described embodiment, an example of the configuration of the structure 100 has been described. In particular, in the example of Fig. 1, a configuration in which one third semiconductor chip is mounted on the first semiconductor chip has been described. However, for example, two or more (multiple) third semiconductor chips may be stacked on the first semiconductor chip.

[0104] In this first modified example, an example of a configuration in which two third semiconductor chips are stacked on the first semiconductor chip IC1 will be described. The other configurations of the structure according to this modified example are similar to those of the structure 100 of the above-described embodiment.

[0105] Here, FIG. 4 is a cross-sectional view that diagrammatically illustrates an example of a cross section of a structure 100A according to a first modified example.

[0106] For example, as shown in FIG. 4, in a structure 100A according to a first modified example, two third semiconductor chips IC3a and IC3b are stacked on a first semiconductor chip IC1.

[0107] The third semiconductor chips IC3a and IC3b include any semiconductor memory, for example, like the first semiconductor chip IC1, and specifically, the semiconductor memory includes, for example, a NAND flash memory. However, each of the third semiconductor chips IC3a and IC3b may be a semiconductor device other than a semiconductor memory.

[0108] 4, the third insulating adhesive layer M3a is provided on the lower surface of the third semiconductor chip IC3a and bonds the lower surface of the third semiconductor chip IC3a and the upper surface of the first semiconductor chip IC1. That is, the lower surface of the third semiconductor chip IC3a is fixed to the upper surface of the first semiconductor chip IC1 by the third insulating adhesive layer M3a.

[0109] 4, the third insulating adhesive layer M3b is provided on the lower surface of the third semiconductor chip IC3b and bonds the lower surface of the third semiconductor chip IC3b and the upper surface of the third semiconductor chip IC3a. That is, the third insulating adhesive layer M3b fixes the lower surface of the third semiconductor chip IC3b to the upper surface of the third semiconductor chip IC3a.

[0110] As shown in FIG. 4, the third bonding wires W3a and W3b electrically connect between wiring (not shown) provided on the substrate and terminals G3a and G3b provided on the upper surfaces of the third semiconductor chips IC3a and IC3b, respectively.

[0111] The number of third semiconductor chips IC3a, IC3b stacked on the first semiconductor chip IC1 may be, for example, three or more.

[0112] As described above, the other configurations of the structure 100A according to the first modified example are similar to those of the embodiment described above.

[0113] Therefore, in the structure 100A relating to this first modified example, by applying a height adjustment portion D composed of at least one of an organic resin and an organic resin composition as a spacer for adjusting the height from the substrate B to the first semiconductor chip IC1, an adhesive layer for fixing the height adjustment portion D to the substrate B is not required, and the manufacturing cost of the structure 100 is reduced.

[0114] Furthermore, in the structure 100A relating to this first modified example, the height adjustment portion D, which is made of at least one of an organic resin and an organic resin composition, can easily have its film thickness finely adjusted, making it easy to finely adjust the height from the substrate B to the first semiconductor chip IC1.

[0115] In other words, according to the first modified example structure 100A, the manufacturing cost can be reduced by eliminating the need for an adhesive layer for fixing a height adjustment part (spacer) for adjusting the height of the semiconductor chip to the substrate, while the height from the substrate to the first semiconductor chip IC1 can be fine-tuned to a predetermined value.

[0116] (Second Modification) In the above-described embodiment and the first modified example, examples of the configuration of the structure 100, 100A have been described. In particular, in the example of FIG. 1 and FIG. 4, a configuration has been described in which the height adjustment part D includes the first and second height adjustment parts D1, D2 in addition to the pedestal part DX. For example, by providing the first and second height adjustment parts D1, D2 (the third and fourth height adjustment parts D3, D4) made of at least one of an organic resin and an organic resin composition on the height adjustment part DX, it is possible to reduce the amount of organic resin material used that constitutes the height adjustment part D while finely adjusting the height. However, in the case where a further thinning of the structure is assumed in the height adjustment part D, in order to reduce the film thickness of the height adjustment part D made of at least one of an organic resin and an organic resin composition, the first and second height adjustment parts D1, D2 may be omitted and the height adjustment part D may be made of only the pedestal part DX (i.e., the height may be adjusted only by the pedestal part DX).

[0117] In this second modified example, an example of a configuration in which two third semiconductor chips are stacked on the first semiconductor chip IC1 will be described. The other configurations of the structure according to this modified example are similar to those of the structure 100 of the above-described embodiment.

[0118] Here, Fig. 5 is a cross-sectional view that shows a schematic example of a cross section of structure 100B according to the second modified example. Also, Fig. 6 is a top view that shows an example of a configuration focusing on a region near height adjustment unit D of structure 100B shown in Fig. 5. Also, Fig. 7 is a cross-sectional view that shows a schematic example of another cross section of structure 100B according to the second modified example.

[0119] For example, as shown in FIGS. 5 and 6, the height adjustment portion D of a structure 100B does not include the first and second height adjustment portions D1, D2 as shown in FIG. 1, and includes only a base portion DX.

[0120] 5, the lower surface of the first semiconductor chip IC1 is bonded and fixed by the first insulating adhesive layer M1 to the upper surface of the pedestal portion DX of the height adjustment portion D. That is, the first semiconductor chip IC1 is directly supported by the pedestal portion DX of the height adjustment portion D.

[0121] In the second variant, too, as shown in FIG. 5, there may be only one third semiconductor chip IC3a mounted on the first semiconductor chip IC1, or, as shown in FIG. 7, two or more (multiple) third semiconductor chips IC3a, IC3b may be stacked on the first semiconductor chip IC1.

[0122] As described above, the other configurations of the structure 100B according to the second modified example are similar to those of the embodiment described above.

[0123] Therefore, in the structure 100B relating to this second modified example, by applying a height adjustment portion D composed of at least one of an organic resin and an organic resin composition as a spacer for adjusting the height from the substrate B to the first semiconductor chip IC1, an adhesive layer for fixing the height adjustment portion D to the substrate B is not required, and the manufacturing cost of the structure 100 is reduced.

[0124] Furthermore, in the structure 100B relating to this second modified example, the height adjustment portion D, which is made of at least one of an organic resin and an organic resin composition, can easily have its film thickness finely adjusted, making it easy to finely adjust the height from the substrate B to the first semiconductor chip IC1.

[0125] In other words, according to the second modified example structure 100B, the manufacturing cost can be reduced by eliminating the need for an adhesive layer for fixing a height adjustment part (spacer) for adjusting the height of the semiconductor chip to the substrate, while the height from the substrate to the first semiconductor chip IC1 can be fine-tuned to a predetermined value.

[0126] (Third Modification) In the above-described embodiment, particularly in the examples of Figures 1 to 3, the height adjustment unit D includes a plurality of height adjustment parts. However, the height adjustment unit D may include a single height adjustment part.

[0127] Therefore, in this third modified example, an example of a configuration in which the height adjustment unit D includes one height adjustment portion D1 will be described. The other configurations of the structure according to this modified example are similar to the configurations of the structure 100 of the embodiment described above.

[0128] Here, Fig. 8 is a cross-sectional view that shows a schematic example of a cross section of structure 100C according to the third modified example. Also, Fig. 9 is a top view that shows an example of a configuration focusing on a region near height adjustment unit D of structure 100C shown in Fig. 8. Also, Fig. 10 is a cross-sectional view that shows a schematic example of another cross section of structure 100C according to the third modified example.

[0129] For example, as shown in FIGS. 8 and 9, the height adjustment portion D of the structure 100C may include a base portion DX and a first height adjustment portion D1.

[0130] 9, the lower surface of the first semiconductor chip IC1 is bonded and fixed by a first insulating adhesive layer M1 to the upper surface of a first height adjustment part D1 provided on a pedestal part DX of the height adjustment part D. That is, the first semiconductor chip IC1 is supported by the pedestal part DX of the height adjustment part D and the first height adjustment part D1.

[0131] In the third modified example as well, as shown in FIG. 8, there may be one third semiconductor chip IC3a mounted on the first semiconductor chip IC1, or, as shown in FIG. 10, two or more (multiple) third semiconductor chips IC3a, IC3b may be stacked on the first semiconductor chip IC1.

[0132] As described above, the other configurations of the structure 100C according to the third modified example are similar to those of the embodiment described above.

[0133] Therefore, in the structure 100C relating to this third modified example, by applying a height adjustment portion D composed of at least one of an organic resin and an organic resin composition as a spacer for adjusting the height from the substrate B to the first semiconductor chip IC1, an adhesive layer for fixing the height adjustment portion D to the substrate B is not required, and the manufacturing cost of the structure 100 is reduced.

[0134] Furthermore, in the structure 100C relating to this third modified example, the height adjustment portion D, which is made of at least one of an organic resin and an organic resin composition, can easily have its film thickness finely adjusted, making it easy to finely adjust the height from the substrate B to the first semiconductor chip IC1.

[0135] In other words, according to the third modified example structure 100C, the manufacturing cost can be reduced by eliminating the need for an adhesive layer for fixing a height adjustment part (spacer) for adjusting the height of the semiconductor chip to the substrate, while the height from the substrate to the first semiconductor chip IC1 can be fine-tuned to a predetermined value.

[0136] (Fourth Modification) In the above-described embodiment and each modified example, particularly in the examples of Figures 1, 4, 5, 7, and 8, the configuration has been described in which each terminal of the second semiconductor chip IC2 is connected by wire bonding. However, in the structure, each terminal of the second semiconductor chip IC2 may be connected by flip chip bonding.

[0137] In this fourth modified example, an example of a configuration (flip-chip type) in which each terminal of the second semiconductor chip IC2 is connected by flip-chip bonding will be described. The other configurations of the structure according to this modified example are similar to those of the structure 100 of the embodiment described above, and can be similarly applied to the configurations of the structures of the modified examples.

[0138] Here, Fig. 11 is a cross-sectional view that typically shows one example of a cross section of structure 100D according to the fourth modified example, and Fig. 12 is a cross-sectional view that typically shows another example of a cross section of structure 100D according to the fourth modified example.

[0139] For example, as shown in FIG. 11, a structure 100D includes bump electrodes BN and underfill resin UF as a flip-chip bonding configuration instead of wire bonding.

[0140] [Bump electrode] The bump electrode BN electrically connects the second wiring E2 of the wirings E1, E2, and EX to a terminal K2 provided on the lower surface of the second semiconductor chip IC2.

[0141] [Underfill resin] The underfill resin UF is provided between the insulating layer SR and the lower surface of the second semiconductor chip IC2, and includes underfill resin UF that bonds the insulating layer SR to the lower surface of the second semiconductor chip IC2 and seals the terminals K2 and the bump electrodes BN.

[0142] In the fourth variant as well, as shown in FIG. 11, there may be one third semiconductor chip IC3a mounted on the first semiconductor chip IC1, or as shown in FIG. 12, two or more (multiple) third semiconductor chips IC3a, IC3b may be stacked on the first semiconductor chip IC1.

[0143] As described above, the other configurations of the structure 100D according to the fourth modified example are similar to those of the previously described embodiment.

[0144] Therefore, even in this fourth modified example, by applying a height adjustment portion D composed of at least one of an organic resin and an organic resin composition as a spacer for adjusting the height from the substrate B to the first semiconductor chip IC1, an adhesive layer for fixing the height adjustment portion D to the substrate B is not required, and the manufacturing cost of the structure 100 is reduced.

[0145] Furthermore, in this fourth modified example, the height adjustment portion D, which is made of at least one of an organic resin and an organic resin composition, can easily have its film thickness finely adjusted, making it easy to finely adjust the height from the substrate B to the first semiconductor chip IC1.

[0146] In other words, according to the fourth modified example structure 100D, the manufacturing cost can be reduced by eliminating the need for an adhesive layer for fixing a height adjustment part (spacer) for adjusting the height of the semiconductor chip to the substrate, while the height from the substrate to the first semiconductor chip IC1 can be fine-tuned to a predetermined value.

[0147] Although the embodiments and modifications of the present invention have been described, these embodiments and modifications are presented as examples and are not intended to limit the scope of the invention. These embodiments and modifications can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0148] 100, 100A, 100B, 100C, 100D Structure B Substrate BN bump electrode E1 First wiring E2 2nd wiring EX 3rd Wiring SR Insulation Layer D Height adjustment section D1 First height adjustment part D2 Second height adjustment part D3 3rd height adjustment part D4 4th height adjustment part DX pedestal part M1 First insulating adhesive layer IC1 First semiconductor chip IC1a end W1 First bonding wire M2 2nd insulation adhesive layer IC2 Second semiconductor chip W2 Second bonding wire M3a, M3b 3rd insulating adhesive layer IC3a, IC3b 3rd semiconductor chip W3a, W3b 3rd bonding wire F Resin layer X 1st direction Y Second direction Z 3rd direction G1, G2, G3a, G3b, K2 terminals A1 1st area A2 2nd area Ha: the distance (shortest distance) between the bottom surface of the first semiconductor chip IC1 and the top surface of the second semiconductor chip IC2 Hb: the distance (shortest distance) between the bottom surface of the first semiconductor chip IC1 and the second bonding wire W2 UF Underfill Resin

Claims

1. A substrate; Wiring provided on the substrate; an insulating layer provided on the substrate so as to cover all or part of the wiring; a height adjusting portion provided in the first region on the substrate via the insulating layer and made of at least one of an organic resin and an organic resin composition; a first semiconductor chip disposed on the height adjustment portion so as to be supported by the height adjustment portion; Equipped with the height adjustment unit includes a first height adjustment portion extending in a first direction in the first region, and a second height adjustment portion extending in the first direction in the first region and spaced apart from the first height adjustment portion; A structure, wherein the height adjustment portion includes a base portion provided between the insulating layer and the first and second height adjustment portions.

2. The structure according to claim 1 , further comprising a resin layer that encapsulates the first semiconductor chip on the substrate.

3. a second semiconductor chip disposed in a second region on the substrate, the second semiconductor chip being disposed via the insulating layer, the second semiconductor chip being disposed in a second region different from the first region on the substrate; The structure according to claim 1 , further comprising: a resin layer that seals the first semiconductor chip and the second semiconductor chip on the substrate.

4. The structure according to claim 1 , further comprising a first insulating adhesive layer that bonds the upper surface of the height adjusting portion and the lower surface of the first semiconductor chip in the first region.

5. The structure according to claim 1 , wherein the insulating layer and the height adjusting portion are made of at least one of the same organic resin and organic resin composition.

6. The structure according to claim 1 , wherein at least one of the organic resin and the organic resin composition is photosensitive.

7. a second insulating adhesive layer that adheres the upper surface of the insulating layer and the lower surface of the second semiconductor chip in the second region; 4. The structure according to claim 3, further comprising: a second bonding wire connecting a second wiring of the wirings and a terminal provided on the top surface of the second semiconductor chip.

8. a bump electrode connecting a second wiring of the wirings and a terminal provided on the underside of the second semiconductor chip; 4. The structure according to claim 3, further comprising: an underfill resin provided between the insulating layer and the second semiconductor chip, which bonds the insulating layer to the underside of the second semiconductor chip and seals the terminals and the bump electrodes.

9. 8. The structure according to claim 7, wherein the distance between the bottom surface of the first semiconductor chip and the second bonding wire is set to a predetermined distance.

10. 9. The structure according to claim 7, further comprising a first bonding wire connecting a first wiring of the wirings and a terminal provided on the top surface of the first semiconductor chip.

11. The structure according to claim 2 , wherein the resin layer is made of a material different from that of the height adjusting portion.

12. The structure of claim 1 , wherein one or more third semiconductor chips are stacked on the first semiconductor chip.

13. The structure of claim 1 , wherein the first semiconductor chip includes a semiconductor memory.

14. The structure of claim 3 , wherein the second semiconductor chip includes a controller that controls the operation of the first semiconductor chip.

15. The structure of claim 1 , wherein the insulating layer is made of solder resist.

16. The structure according to claim 1 , wherein the height adjusting portion has insulating properties.

17. 4. The structure according to claim 3, wherein a distance between the bottom surface of the first semiconductor chip and the top surface of the second semiconductor chip is set to a predetermined distance.

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