Multilayer ceramic electronic component and manufacturing method thereof

Abstract

To secure an insulation property between internal electrodes regardless of the number of grain boundaries of grains forming a dielectric layer which is disposed between the internal electrodes.SOLUTION: A multilayer ceramic electronic component comprises: a ceramic element assembly in which dielectric layers and internal electrodes are alternately laminated in a first axis direction and which includes a pair of principal surfaces opposed to each other in the first axis direction, a pair of side faces opposed to each other in a second axis direction orthogonal to the first axis direction and a pair of end faces opposed to each other in a third axis direction orthogonal to the first axis direction and the second axis direction; and external electrodes which are provided in ends of the ceramic element assembly in the third axis direction so as to be conducted with the internal electrodes led out on a different end face of the ceramic element assembly in the third axis direction. A grain forming the dielectric layer includes a segregation part containing a rare earth element and / or a transition metal element different from a main component of the dielectric layer inside a grain boundary.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a multilayer ceramic electronic component and a method for manufacturing the same. [Background technology]

[0002] Recently, there has been known a multilayer ceramic electronic component having a capacitance forming portion in which internal electrodes and dielectric layers are alternately laminated, and in which a side margin portion is formed on the side surface of the capacitance forming portion. In a multilayer ceramic electronic component, insulation between the internal electrodes must be ensured, and proposals have been made to suppress the occurrence of short circuits between the internal electrodes (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-143392 A Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, it is believed that the insulation between internal electrodes is ensured by the grain boundaries of the particles forming the dielectric layer. Multilayer ceramic electronic components are becoming increasingly multi-layered. As the number of layers increases, the thickness of the dielectric layer between the internal electrodes becomes thinner. This leads to a decrease in the number of particles forming the dielectric layer, and the number of grain boundaries between the internal electrodes also decreases. For this reason, it becomes difficult to ensure insulation when the thickness of the dielectric layer is reduced. The proposal in Patent Document 1 does not address such problems, and there is room for improvement.

[0005] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to ensure insulation between internal electrodes regardless of the number of grain boundaries of particles forming a dielectric layer disposed between the internal electrodes. [Means for solving the problem]

[0006] In order to achieve the above-mentioned object, a multilayer ceramic electronic component can include a ceramic body in which dielectric layers and internal electrodes are alternately stacked along a first axial direction, the ceramic body having a pair of main surfaces opposing each other along the first axial direction, a pair of side surfaces opposing each other in a second axial direction perpendicular to the first axial direction, and a pair of end faces opposing each other in a third axial direction perpendicular to the first axial direction and the second axial direction, and an external electrode provided at an end of the ceramic body in the third axial direction and provided so as to be conductive with the internal electrode extended to a different end face of the ceramic body in the third axial direction, and the grains forming the dielectric layer can have a segregation portion within grain boundaries containing a rare earth element and / or a transition metal element different from a main component of the dielectric layer.

[0007] In the monolithic ceramic electronic component having the above configuration, the segregation portions may include at least one element selected from the group consisting of rare earth elements, first transition metal elements, and second transition metal elements.

[0008] Furthermore, in the multilayer ceramic electronic component having the above-described configuration, the ceramic body can include a ceramic multilayer chip in which the dielectric layers and the internal electrodes are alternately stacked, and a side margin portion covering the ceramic multilayer chip from the second axial direction, and the segregation portion can be formed within the grain located in a region of the dielectric layer adjacent to the side margin portion.

[0009] The segregation portion may be formed in the grain located in a region including a center point of the ceramic body in the second axial direction.

[0010] In the monolithic ceramic electronic component having the above configuration, the particles forming the dielectric layers may have a median particle size of 0.2 μm or more and 0.8 μm or less.

[0011] In addition, in the multilayer ceramic electronic component having the above configuration, the dielectric layer and the side margin portion contain Ti and Si elements, and a ratio of the Ti element to the Si element in the side margin portion can be higher than a ratio of the Ti element to the Si element in the dielectric layer.

[0012] Furthermore, in the multilayer ceramic electronic component having the above configuration, the dielectric layer and the side margin portion contain the Ti element and the Si element, and the ratio of the Ti element to the Si element in the side margin portion can be at least twice the ratio of the Ti element to the Si element in the dielectric layer.

[0013] Moreover, in the multilayer ceramic electronic component having the above configuration, the dielectric layer and the side margin portion contain the Ti element and the Si element, and the ratio of the Ti element to the Si element in the side margin portion can be four or more times the ratio of the Ti element to the Si element in the dielectric layer.

[0014] In the monolithic ceramic electronic component having the above configuration, the side margin portion may contain elemental Si, and the amount of the elemental Si in the side margin portion may be 1 at % or more.

[0015] In the multilayer ceramic electronic component having the above configuration, the thickness of the dielectric layers along the first axis direction can be 0.3 μm or more and 0.7 μm or less.

[0016] In the monolithic ceramic electronic component configured as described above, the segregation portion may have a length within one grain in the cross section of the dielectric layer that is 50% or more of the grain size of the grain.

[0017] In order to achieve the above object, a manufacturing method for a multilayer ceramic electronic component can include the steps of: producing an unsintered ceramic multilayer chip in which dielectric layers containing Si and internal electrodes are alternately stacked along a first axial direction, and the chip has a capacitance forming portion in which the internal electrodes are exposed from a side surface facing a second axial direction perpendicular to the first axial direction; producing an unsintered ceramic body by forming a side margin portion on the side surface of the ceramic multilayer chip, the side margin portion having a higher Si element content than the dielectric layers; firing the ceramic body; and forming external electrodes on the fired ceramic body.

[0018] In the method for manufacturing a multilayer ceramic electronic component having the above-mentioned configuration, the dielectric layer and the side margin portion may contain Ti and Si elements, and a ratio of the Ti element to the Si element in the side margin portion may be higher than a ratio of the Ti element to the Si element in the dielectric layer. Effect of the Invention

[0019] According to the present invention, insulation between internal electrodes can be ensured regardless of the number of grain boundaries of particles forming a dielectric layer disposed between internal electrodes. [Brief description of the drawings]

[0020] [Figure 1] FIG. 1 is a perspective view of a multilayer ceramic capacitor according to one embodiment of the present invention. [Diagram 2] FIG. 2 is a cross-sectional view taken along the line AA′ of the multilayer ceramic capacitor in FIG. [Diagram 3] FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor taken along line BB' in FIG. [Figure 4] FIG. 4 is a partially enlarged cross-sectional view of the multilayer ceramic capacitor according to the embodiment. [Diagram 5] Fig. 5(A) is a schematic diagram showing the state of particles forming a dielectric layer, and Fig. 5(B) is a diagram showing the state of a dielectric layer in a multilayer ceramic capacitor according to an embodiment. [Figure 6] FIG. 6 is a diagram showing a schematic view of one particle forming a dielectric layer. [Figure 7] FIG. 7 is a flowchart showing an example of a method for manufacturing the multilayer ceramic capacitor according to the embodiment. [Figure 8] FIG. 8 is a perspective view showing a manufacturing process of the multilayer ceramic capacitor according to the embodiment. [Figure 9] FIG. 9 is a perspective view showing a manufacturing process of the multilayer ceramic capacitor according to the embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing process of the multilayer ceramic capacitor according to the embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing process of the multilayer ceramic capacitor according to the embodiment. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing process of the multilayer ceramic capacitor according to the embodiment. [Figure 13] FIG. 13 is a perspective view showing a manufacturing process of the multilayer ceramic capacitor according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, an X-axis, a Y-axis, and a Z-axis that are mutually orthogonal are shown as appropriate. The X-axis, the Y-axis, and the Z-axis are common to all the drawings. The X-axis direction corresponds to the third axis direction, the Y-axis direction corresponds to the second axis direction, and the Z-axis direction corresponds to the first axis direction.

[0022] [Overall configuration of multilayer ceramic capacitor 10] 1 to 4 are diagrams showing a multilayer ceramic capacitor 10 according to a first embodiment of the present invention. Fig. 1 is a perspective view of the multilayer ceramic capacitor 10. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line AA' in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line BB' in Fig. 1. Fig. 4 is an enlarged cross-sectional view of a portion of the multilayer ceramic capacitor 10.

[0023] The multilayer ceramic capacitor 10 includes a ceramic body 11 and two external electrodes 14a, 14b. The two external electrodes 14a, 14b are formed on the surfaces of the ceramic body 11, respectively.

[0024] The ceramic body 11 has a capacitance forming portion 16 and a protective portion 17. The protective portion 17 constitutes the peripheral portion of the ceramic body 11 and has two end faces 11a facing the X-axis direction, two side faces 11b facing the Y-axis direction, and two main faces 11c facing the Z-axis direction. The side faces 11b and the main faces 11c constitute a plurality of peripheral surfaces. The end faces 11a, the side faces 11b, and the main faces 11c are, for example, substantially flat surfaces, but may be rounded.

[0025] In detail, the protective portion 17 has a cover portion 18 located outside the capacitance forming portion 16 in the Z-axis direction, a side margin portion 19 located outside the capacitance forming portion 16 in the Y-axis direction, and an end margin portion 20 located outside the capacitance forming portion 16 in the X-axis direction.

[0026] The capacitance forming portion 16 is disposed inside the protective portion 17 and constitutes a functional portion. In the capacitance forming portion 16, a plurality of first internal electrodes 12 and a plurality of second internal electrodes 13 are laminated in the Z-axis direction via a dielectric layer 15 (see FIG. 2). The internal electrodes 12, 13 are both sheet-shaped extending along the XY plane and are alternately disposed along the Z-axis direction. The configuration of the dielectric layer 15 will be described in detail later.

[0027] The internal electrodes 12, 13 are each made of a good electrical conductor and function as internal electrodes of the multilayer ceramic capacitor 10. Examples of good electrical conductors that can be used to form the internal electrodes 12, 13 include metals and alloys containing nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), or the like as a main component.

[0028] 2, the first internal electrode 12 is extended to, for example, one end face 11a of the ceramic body 11 and connected to one external electrode 14a. The second internal electrode 13 is extended to the other end face 11a and connected to the other external electrode 14b.

[0029] The dielectric layers 15 are made of dielectric ceramics. In the multilayer ceramic capacitor 10, a dielectric ceramic with a high dielectric constant is used to increase the capacitance of each dielectric layer 15 between the internal electrodes 12 and 13. Examples of dielectric ceramics with a high dielectric constant include materials with a perovskite structure containing barium (Ba) and titanium (Ti), such as barium titanate (BaTiO3).

[0030] In addition to barium titanate, the dielectric ceramics may be strontium titanate (SrTiO3), calcium titanate (CaTiO3), magnesium titanate (MgTiO3), calcium zirconate (CaZrO3), calcium zirconate titanate (Ca(Zr,Ti)O3), barium zirconate (BaZrO3), titanium oxide (TiO2), etc. The dielectric ceramics listed here are the main components of the dielectric layer 15.

[0031] The dielectric layer 15 contains Si (silicon) element in addition to the above-mentioned main components. The dielectric layer 15 also contains at least one element selected from rare earth elements, first transition metal elements, or second transition metal elements in addition to the above-mentioned main components. When selected from rare earth elements, they are selected from Sc (scandium), Y (yttrium), La (lanthanum), Ce (cerium), Pr (praseodymium), Nd (neodymium), Pm (promethium), Sm (samarium), Eu (eurobium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), and Yb (ytterbium). Although the enumeration is omitted here, they may be selected from first transition metal elements or second transition metal elements.

[0032] The protective portion 17 is also made of a dielectric ceramic. Of the protective portion 17, the cover portion 18 and the end margin portion 20 preferably have the same main component composition as the dielectric layer 15 from the viewpoint of suppressing internal stress. This also improves manufacturing efficiency. The cover portion 18 and the end margin portion 20 do not need to contain rare earth elements, first transition metal elements, or second transition metal elements.

[0033] Of the protective portion 17, the side margin portion 19 has the same main component as the dielectric layer 15 and contains Si element. However, the amount of Si element is greater than the amount of Si element in the dielectric layer 15. The amount of Si element is compared in the following manner, as an example. Here, a case where the B-site element of the material having the perovskite structure forming the protective layer 17 is Ti element will be described. Even when a material having another element as the B-site element is used, the amount of Si element can be compared in a similar manner. The ratio Ra

[15] of Ti element and Si element in the dielectric layer 15 is calculated. Similarly, the ratio Ra

[19] of Ti element and Si element in the side margin portion 19 is calculated. Then, the ratio Ra

[15] and the ratio Ra

[19] are compared. In this embodiment, the amount of Si element in the dielectric layer 15 and the amount of Si element in the side margin portion 19 are determined so that the ratio Ra

[19] is greater than the ratio Ra

[15] . By making the ratio Ra

[19] larger than the ratio Ra

[15] , grains 151 (see FIGS. 5(A) to 6) that form the dielectric layer 15 grow in the manufacturing process of the multilayer ceramic capacitor 10. As a result, segregation portions 153 formed by the concentration of rare earth elements, first transition metal elements, and second transition metal elements are formed in the grown grains 151. The segregation portions 153 will be described in detail later.

[0034] Each of the external electrodes 14a, 14b has an undercoat film 21 formed so as to cover the end face 11a, and a plating film 22 formed on the undercoat film 21. The undercoat film 21 is formed, for example, of a baked film formed by baking a conductive paste, a sputtered film, or the like. The plating film 22 is a film formed by electrolytic plating. Each of the films of the external electrodes 14a, 14b is formed of a metal or an alloy containing, for example, nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), or the like as a main component.

[0035] [Detailed configuration of dielectric layer 15] Fig. 4 is a partially enlarged cross-sectional view of the multilayer ceramic capacitor 10. Fig. 5(A) is a diagram showing the state of particles forming the dielectric layer 15. Fig. 5(B) is a line diagram showing the state of the dielectric layer in the multilayer ceramic capacitor. Fig. 6 is a diagram showing the state of one particle forming the dielectric layer. Fig. 5(A) shows a diagram of the internal electrodes 12 and 13, and one dielectric layer 15 formed between them.

[0036] The thickness t

[15] of one dielectric layer 15 shown in FIG. 4 can be set in the range of 0.3 μm or more and 0.7 μm or less. By setting the thickness t

[15] in this range, the multilayer ceramic capacitor 10 can be multi-layered. The particle size of the particles 151 forming the dielectric layer 15 can be set in the range of 0.2 μm or more and 0.8 μm or less as the median value. By setting the particle size of the particles 151 in this range, the thickness t

[15] of one dielectric layer 15 can be made thinner.

[0037] 5(A) and 5(B), the particles 151 forming the dielectric layer 15 have grain boundaries 152. The particles 151 are barium titanate particles. The grain boundaries 152 are depicted by solid lines in FIG. 5(A) and dashed lines in FIG. 5(B). The grain boundaries 152 are shared between adjacent particles 151. Within each particle 151, a segregation portion 153 depicted by dotted lines in FIG. 5(A) and FIG. 5(B) is formed. Note that the closer the value of the grain size and the value of the thickness t

[15] are, the fewer the number of grain boundaries 152 existing between the internal electrodes 12 and 13.

[0038] The segregation portion 153 is considered to be a portion where the rare earth element, the first transition metal element, or the second transition metal element added as a component of the dielectric layer 15 segregates within one grain. The segregation portion 153 can be observed by mapping the element to be measured using, for example, a transmission electron microscope-energy dispersive X-ray spectroscopy (TEM-EDS). For example, when the added transition metal element is Mn, the segregation portion 153 can be visualized by mapping the Mn element. With reference to FIG. 6, the concentration of the target element in the segregation portion 153 is higher than the concentration of the target element in the portions other than the segregation portion 153, such as the regions 151a, 151b, and 151c in the particle 151. The segregation portion 153 can exhibit insulating properties. Therefore, even if the thickness t

[15] of the dielectric layer 15 is thin and the number of grain boundaries 152 existing between the internal electrodes 12 and 13 is small, the insulation between the internal electrodes 12 and 13 can be ensured.

[0039] Here, the position of the segregation portion 153 can be identified by, for example, comparing the signal value (output value) of the segregation portion 153 with the surroundings in the above-mentioned analysis using TEM-EDS. The surroundings of the segregation portion 153 are, for example, the regions 151a, 151b, and 151c in the particle 151. The signal value changes depending on the concentration of the rare earth element, the first transition metal element, or the second transition metal element added as a component of the dielectric layer 15. The position of the segregation portion 153 can be identified by plotting the location where the signal value is higher than the surroundings. The difference in the signal value between the segregation portion 153 and its surroundings for identifying the segregation portion 153 can be appropriately set in consideration of the influence of noise, etc. in the signal value detection. For example, the position where the signal value in the segregation portion 153 is 10 times or more compared to the surrounding signal value can be determined as the segregation portion 153. Note that the signal value of 10 times or more is just an example, and other multiples may be used.

[0040] The segregation portion 153 is formed in the grains 151 located in a region Ar2 adjacent to the side margin portion 19 shown in Fig. 4. The segregation portion 153 is also formed in the grains 151 located in a region Ar3 (see Fig. 3) including a center line Cn of the ceramic body 11 in the Y-axis direction. The center line Cn includes the center point of the ceramic body 11 in the Y-axis direction. On the other hand, the segregation portion 153 is not formed in the grains located in the region Ar1 shown in Fig. 4, that is, the region included in the side margin portion 19.

[0041] The segregation parts 153 may be scattered in the cross section of the dielectric layer 15. Even in this case, the segregation parts 153 can exhibit insulating properties. FIG. 5(A) and FIG. 5(B) show the cross section of the dielectric layer 15. Therefore, the segregation parts 153 shown in FIG. 5(A) and FIG. 5(B) are considered to form a wall structure that is continuous on the front side or the back side of the paper, that is, in the X-axis direction. The segregation parts 153 may have a length of 50% or more of the particle diameter of one particle 151 in the cross section of the dielectric layer 15. The segregation parts 153 may have one end in contact with the grain boundary 152 and the other end in contact with another part of the grain boundary 152. By adopting such a form, a wall structure that is continuous in the Y-axis direction is formed, and insulating properties are improved. The segregation parts 153 that appear in the cross section may not only be linear, but may also be bent or meandering.

[0042] Here, the conditions for forming the segregation region 153 will be considered. First, the case where the amount of Si element in the side margin region 19 is made larger than that in the ceramic body 11 will be considered. In this case, a liquid phase mainly composed of Si element moves from the side margin region 19 side to the region adjacent to the side margin region 19, that is, the region Ar2 shown in FIG. 4. When the amount of Si element increases, the additive elements such as rare earth elements are less likely to volumetrically diffuse in the particles 151 mainly composed of BT, and are no longer homogeneously dissolved. When annealing is performed in this state to increase the grain size, the segregation region 153 is formed.

[0043] Next, consider the case where the amount of Si in the side margin 19 is made less than that in the ceramic body 11. In this case, a liquid phase mainly composed of Si elements moves from the region adjacent to the side margin 19, i.e., region Ar2 shown in FIG. 4, to the side margin 19. When the amount of Si elements is small, additive elements such as rare earth elements are more likely to volumetrically diffuse in the particles 151 mainly composed of BT, and form a homogeneous solid solution. When annealing is performed in this state, the grain size increases, but segregation regions 153 are not formed.

[0044] These conditions will be explained in detail with reference to Table 1.

[0045] [Table 1]

[0046] Table 1 shows the ratio of the amount of Si element in the side margin portion 19 to the amount of Si element in the dielectric layer 15. This ratio is a value obtained by comparing the above-mentioned ratio Ra

[15] and ratio Ra

[19] , and is hereinafter expressed as ratio Ra

[15] / ratio Ra

[19] . In preparing this Table 1, the amount of Si in the dielectric layer 15 was fixed at 1 at%.

[0047] The ratio Ra

[15] / ratio Ra

[19] under condition 1 in Table 1 is 0.8. No segregation portion 153 was formed under condition 1. Note that under condition 1, the median grain size in region Ar2 was 340 nm.

[0048] The ratio Ra

[15] / ratio Ra

[19] under condition 2 in Table 1 is 1.0. No segregation portion 153 was formed under condition 2. Note that under condition 2, the median grain size in region Ar2 was 360 nm.

[0049] In this manner, when the ratio Ra

[15] / ratio Ra

[19] was 1 or less, the segregation portion 153 was not formed.

[0050] The ratio Ra

[15] / ratio Ra

[19] under condition 3 in Table 1 is 1.5. Under condition 3, a segregation portion 153 was formed. Note that under condition 3, the median grain size in region Ar2 was 340 nm.

[0051] The ratio Ra

[15] / ratio Ra

[19] under condition 4 in Table 1 is 2. Under condition 4, a segregation portion 153 was formed. Note that under condition 4, the median grain size in region Ar2 was 350 nm.

[0052] The ratio Ra

[15] / ratio Ra

[19] under condition 5 in Table 1 is 3. Under condition 5, a segregation portion 153 was formed. Note that under condition 5, the median grain size in region Ar2 was 350 nm.

[0053] The ratio Ra

[15] / ratio Ra

[19] under condition 6 in Table 1 is 4. Under condition 6, a segregation portion 153 was formed. Note that under condition 4, the median grain size in region Ar2 was 340 nm.

[0054] The ratio Ra

[15] / ratio Ra

[19] under condition 7 in Table 1 is 5. Under condition 7, a segregation portion 153 was formed. Note that under condition 4, the median grain size in region Ar2 was 360 nm.

[0055] In this manner, the segregation portion 153 was formed when the ratio Ra

[15] / ratio Ra

[19] was greater than 1. According to Table 1, in order to form the segregation portion 153, the ratio Ra

[15] / ratio Ra

[19] is preferably 2 or greater, and more preferably 4 or greater.

[0056] As described above, in creating Table 1, the amount of Si in the dielectric layer 15 is fixed at 1 at%. Therefore, under condition 1, the amount of Si element in the side margin portion 19 is 0.8 at%. Similarly, under condition 2, the amount of Si element in the side margin portion 19 is 1 at%. Under condition 3, the amount of Si element in the side margin portion 19 is 1.5 at%. Under condition 4, the amount of Si element in the side margin portion 19 is 2 at%. Under condition 5, the amount of Si element in the side margin portion 19 is 3 at%. Under condition 6, the amount of Si element in the side margin portion 19 is 4 at%. Under condition 7, the amount of Si element in the side margin portion 19 is 5 at%.

[0057] [Method of manufacturing multilayer ceramic capacitor 10] Fig. 7 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 10. Figs. 8 to 13 are diagrams that typically show the manufacturing process of the multilayer ceramic capacitor 10. The method for manufacturing the multilayer ceramic capacitor 10 will be described below along Fig. 9 with appropriate reference to Figs. 8 to 13.

[0058] (Step S01: Fabrication of ceramic laminated chip C) In step S01, the ceramic sheets 101 and 102 for forming the capacitance forming portion 16 and the ceramic sheet 103 for forming the cover portion 18 are laminated and cut to produce an unfired ceramic laminated chip (laminated chip) C.

[0059] The ceramic sheets 101, 102, and 103 shown in FIG. 8 are configured as unfired dielectric green sheets containing a ceramic material made of dielectric ceramics, an organic binder, and other additives. An unfired first internal electrode 112 corresponding to the first internal electrode 12 is formed in the ceramic sheet 101. An unfired second internal electrode 113 corresponding to the second internal electrode 13 is formed in the ceramic sheet 102. No internal electrode is formed in the ceramic sheet 103. In addition, the desired rare earth element, first transition metal element, and second transition metal element are added to the ceramic sheets 101 and 102 for the capacitance forming portion 16. In addition, an appropriate amount of Si element is added to the ceramic sheets 101 and 102.

[0060] Each of the internal electrodes 112, 113 has a plurality of strip-shaped electrode patterns that cross a cutting line Lx parallel to the X-axis direction and extend along a cutting line Ly parallel to the Y-axis direction. These internal electrodes 112, 113 are formed by applying a conductive paste to the ceramic sheets 101, 102 by a printing method or the like.

[0061] The ceramic sheets 101 and 102 are alternately stacked in the Z-axis direction as shown in Fig. 8. The stack of the ceramic sheets 101 and 102 corresponds to the capacitance forming portion 16 and the end margin portion 20. The ceramic sheet 103 is stacked on the top and bottom surfaces in the Z-axis direction of the stack of the ceramic sheets 101 and 102. The stack of the ceramic sheets 103 corresponds to the cover portion 18. The number of stacked ceramic sheets 101, 102, and 103 can be adjusted as appropriate.

[0062] Next, the laminate of the ceramic sheets 101, 102, and 103 is pressed from the Z-axis direction and cut along the cutting lines Lx and Ly, thereby producing the laminated chip C shown in FIG.

[0063] The laminated chip C has an unsintered capacitance forming portion 116 on which unsintered internal electrodes 112, 113 are formed, an unsintered cover portion 118, and an unsintered end margin portion 120. The laminated chip C has a side surface Cb which is a cut surface corresponding to the cutting line Lx, and an end surface Ca which is a cut surface corresponding to the cutting line Ly. Ends of the unsintered internal electrodes 112, 113 are exposed from the side surface Cb.

[0064] (Step S02: Forming side margin portion 119) In step S02, side margin portions 119 are formed on the side surfaces Cb of the stacked chips C. An example of a forming method will be described below.

[0065] First, the ceramic sheet 104 for the side margin portion 119 is prepared. The ceramic sheet 104 is configured as an unfired dielectric green sheet containing a ceramic material made of a dielectric ceramic, an organic binder, and other additives. The amount of Si element added to the ceramic sheet 104 is greater than the amount of Si element added to the ceramic sheets 101 and 102. The amount of Si element added is determined to be an amount that will form a segregation portion 153 in the particle 151 after firing, with reference to the conditions shown in Table 1.

[0066] In order to form the side margin portion 119 by the ceramic sheet 104, first, the ceramic sheet 104 is placed on a flat elastic member E as shown in Fig. 10. Then, one side surface Cb of the laminated chip C, the other side surface Cb of which is held by the tape T, is made to face the ceramic sheet 104.

[0067] 11, the ceramic sheet 104 is punched out at the side Cb of the laminated chip C, thereby attaching the ceramic sheet 104 to the side Cb. Specifically, the laminated chip C is strongly pressed in the Y-axis direction against the ceramic sheet 104. This causes the laminated chip C and the ceramic sheet 104 to locally sink deeply into the elastic member E. At this time, a shear force acts on the ceramic sheet 104 along the outer edge of the side Cb, and when this shear force reaches or exceeds the shear strength of the ceramic sheet 104, the ceramic sheet 104 is punched out.

[0068] 12, the part of the ceramic sheet 104 that has sunk together with the laminated chip C is cut off, thereby forming a side margin portion 119 on the side surface Cb.

[0069] Then, a side margin 119 is formed similarly on the other side surface Cb, thereby producing the unsintered ceramic body 111 shown in FIG.

[0070] (Step S03: Firing) In step S03, the ceramic body 111 obtained in step S02 is fired to produce the ceramic body 11 of the multilayer ceramic capacitor 10 shown in FIG. 1. The firing temperature in step S03 can be determined based on the sintering temperature of the ceramic body 111. The firing can be performed, for example, in a reducing atmosphere or a low oxygen partial pressure atmosphere. The firing process may be performed multiple times so that the particles 151 (see FIG. 5(A), etc.) after firing have a desired particle size. In this case, the particle size can be adjusted by adjusting the firing temperature for each time.

[0071] The liquid phase mainly composed of Si element in the side margin portion 119 can move toward the inside of the ceramic body 11, that is, toward the region where the ceramic sheets 101, 102 are laminated. When the liquid phase moves toward the laminated region of the ceramic sheets 101, 102, the rare earth element and the like added to the ceramic sheets 101, 102 are less likely to volumetrically diffuse in the particles 151 and are less likely to form a homogeneous solid solution. When annealing, that is, firing, is performed in this state, the particles 151 grow. At that time, if the additive substance is in a state where it is easy to volumetrically diffuse, it is considered that the added rare earth element and the like diffuses to the grain boundary 152 and forms a part of the grain boundary 152. In contrast, in this embodiment, the additive such as the rare earth element is less likely to volumetrically diffuse and is less likely to form a homogeneous solid solution. For this reason, the additive such as the rare earth element is left in a concentrated state in the particles 151 and forms a segregation portion 153.

[0072] (Step S04: Forming the base film) In step S04, a conductive base film 21 is formed on the end faces 11a, the side faces 11b, and the main face 11c shown in FIG.

[0073] The undercoat film 21 is formed by applying unsintered electrode material to the end faces 11a, the side faces 11b, and the main face 11c. The application method is, for example, a dipping method, but other conventionally known methods such as a printing method or a sputtering method, or a combination of these, may also be used. The unsintered electrode material is then baked. The baking can be performed, for example, in a reducing atmosphere or a low oxygen partial pressure atmosphere.

[0074] (Step S05: Plating film formation) In step S05, electrolytic plating is performed by immersing the multilayer ceramic capacitor 10 on which the undercoat film 21 has been formed in a plating solution for forming the plating film 22. In this way, the plating film 22 is formed.

[0075] In this manner, the multilayer ceramic capacitor 10 shown in FIGS. 1 to 3 is manufactured.

[0076] Although each embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the spirit of the present invention. EXAMPLES

[0077] Next, the results of the HALT test (highly accelerated life test) for the examples will be described together with the comparative examples. The examples correspond to the multilayer ceramic capacitor 10 of the embodiment, and have the following dimensions. The examples have intragranular segregation parts 153. On the other hand, the comparative examples do not have intragranular segregation parts 153. The examples were prepared from Example 1 to Example 9 by combining the thickness t

[15] of the dielectric layer 15 and the particle size of the particles 151 forming the dielectric layer 15. As for the comparative examples, Comparative Examples 1 to 12 were prepared by combining the thickness of the dielectric layer and the particle size of the particles forming the dielectric layer. The particle size was determined by measuring the longest diagonal distance of each particle from a cross-sectional image taken by a SEM (Scanning Electron Microscope), and taking the median value of this measurement.

[0078] The conditions for the impact test are shown below. Test conditions: The temperature inside the furnace is 125°C and the voltage is 8V. Lifespan judgment: The time (minutes: median) until the current value exceeds the threshold is defined as the lifespan. Test item dimensions: 0603 (length x width x height = 0.6 mm x 0.3 mm x 0.3 mm) Number of test subjects: Examples 1 to 9 and Comparative Examples 1 to 12 were each 20 pieces.

[0079] Example 1 The thickness of the dielectric layer in Example 1 is 0.3 μm, and the grain size is 0.32 μm. The HALT result was 312 minutes. Example 2 The thickness of the dielectric layer in Example 2 is 0.3 μm and the grain size is 0.24 μm. The HALT result was 380 minutes. Comparative Example 1 The thickness of the dielectric layer was 0.3 μm and the grain size was 0.33 μm in Comparative Example 1. The HALT result was 87 minutes. Comparative Example 2 The thickness of the dielectric layer is 0.3 μm and the grain size is 0.22 μm in Comparative Example 2. The HALT result was 148 minutes. Comparative Example 3 The thickness of the dielectric layer is 0.3 μm and the grain size is 0.16 μm in Comparative Example 3. The HALT result was 280 minutes.

[0080] Example 3 The thickness of the dielectric layer is 0.5 μm and the grain size is 0.48 μm in Example 3. The HALT result was 484 minutes. Example 4 The thickness of the dielectric layer in Example 4 is 0.5 μm and the grain size is 0.36 μm. The HALT result was 512 minutes. Example 5 The thickness of the dielectric layer in Example 5 is 0.5 μm and the grain size is 0.25 μm. The HALT result was 550 minutes. Comparative Example 4 The thickness of the dielectric layer in Comparative Example 4 is 0.5 μm, and the grain size is 0.48 μm. The HALT result was 22 minutes. Comparative Example 5 The thickness of the dielectric layer in Comparative Example 5 is 0.5 μm, and the grain size is 0.36 μm. The HALT result was 47 minutes. Comparative Example 6 The thickness of the dielectric layer is 0.5 μm and the grain size is 0.25 μm in Comparative Example 6. The HALT result was 139 minutes. Comparative Example 7 The thickness of the dielectric layer is 0.5 μm and the grain size is 0.14 μm in Comparative Example 7. The HALT result was 231 minutes.

[0081] Example 6 The thickness of the dielectric layer is 0.7 μm and the grain size is 0.64 μm in Example 6. The HALT result was 723 minutes. Example 7 The thickness of the dielectric layer in Example 7 is 0.7 μm and the grain size is 0.43 μm. The HALT result was 781 minutes. Example 8 The thickness of the dielectric layer is 0.7 μm and the grain size is 0.33 μm in Example 8. The HALT result was 823 minutes. Example 9 The thickness of the dielectric layer in Example 9 is 0.7 μm and the grain size is 0.23 μm. The HALT result was 845 minutes. Comparative Example 8 The thickness of the dielectric layer in Comparative Example 8 is 0.7 μm and the grain size is 0.66 μm. The HALT result was 12 minutes. Comparative Example 9 The thickness of the dielectric layer in Comparative Example 9 was 0.7 μm and the grain size was 0.43 μm. The HALT result was 27 minutes. Comparative Example 10 The thickness of the dielectric layer in Comparative Example 10 is 0.7 μm, and the grain size is 0.35 μm. The HALT result was 86 minutes. Comparative Example 11 The thickness of the dielectric layer is 0.7 μm and the grain size is 0.23 μm in Comparative Example 11. The HALT result was 187 minutes. Comparative Example 12 The thickness of the dielectric layer is 0.7 μm and the grain size is 0.16 μm in Comparative Example 12. The HALT result was 467 minutes.

[0082] In both the examples and the comparative examples, it can be seen that the larger the particle size, the shorter the lifespan, and the smaller the particle size, the longer the lifespan. This is thought to be because the smaller the particle size, the more grain boundaries there are, making it easier to ensure insulation. However, the difference in lifespan caused by differences in particle size is larger in the comparative examples and smaller in the examples. This is thought to be because in each example, segregation parts 153 are formed within the particles 151, and this segregation part 153 enhances insulation.

[0083] Therefore, in the embodiment, even when the thickness of the dielectric layer and the grain size are almost the same, good life characteristics can be obtained. Even when the thickness t

[15] of the dielectric layer 15 is thin and the number of grains in the thickness direction of the dielectric layer 15 is small, good insulation and therefore good life characteristics can be obtained by providing the segregation portion 153.

[0084] [Table 2]

[0085] In the above embodiment, the multilayer ceramic capacitor 10 has been described as an example of a multilayer ceramic electronic component, but the present invention is applicable to all multilayer ceramic electronic components in which dielectric layers and internal electrodes are laminated. Examples of such multilayer ceramic electronic components include chip varistors, chip thermistors, and multilayer inductors. [Explanation of symbols]

[0086] 10...Multilayer ceramic capacitor 11…Ceramic body 11a...end face 11b...side 11c…main surface 12,13…Internal electrode 14a,14b...External electrode 21...Base film 22...Plating film 151...Particle 152...Grain boundary 153…Segregation area

Claims

1. a ceramic body in which dielectric layers and internal electrodes are alternately stacked along a first axis direction, the ceramic body having a pair of main surfaces opposing each other along the first axis direction, a pair of side surfaces opposing each other in a second axis direction perpendicular to the first axis direction, and a pair of end surfaces opposing each other in a third axis direction perpendicular to the first axis direction and the second axis direction; an external electrode provided at an end of the ceramic body in the third axis direction and electrically connected to the internal electrode extended to a different end surface of the ceramic body in the third axis direction, the particles forming the dielectric layer have segregated portions containing a rare earth element and / or a transition metal element different from the main component of the dielectric layer; Multilayer ceramic electronic components.

2. the segregated portion contains at least one element selected from the group consisting of rare earth elements, first transition metal elements, and second transition metal elements; The multilayer ceramic electronic component according to claim 1 .

3. the ceramic body includes a ceramic laminated chip in which the dielectric layers and the internal electrodes are alternately laminated, and a side margin portion covering the ceramic laminated chip from the second axial direction, the segregation portion is formed in the grain located in a region of the dielectric layer adjacent to the side margin portion, The multilayer ceramic electronic component according to claim 1 .

4. the segregation portion is formed in the grain located in a region including a center point of the ceramic body in the second axis direction. The multilayer ceramic electronic component according to claim 1 .

5. The particles forming the dielectric layer have a median particle size of 0.2 μm or more and 0.8 μm or less. The multilayer ceramic electronic component according to claim 1 .

6. the dielectric layer and the side margin portion contain Ti elements and Si elements, and a ratio of the Ti elements to the Si elements in the side margin portion is higher than a ratio of the Ti elements to the Si elements in the dielectric layer; The multilayer ceramic electronic component according to claim 3 .

7. the dielectric layer and the side margin portion contain the Ti element and the Si element, and the ratio of the Ti element to the Si element in the side margin portion is at least twice the ratio of the Ti element to the Si element in the dielectric layer; The multilayer ceramic electronic component according to claim 6.

8. the dielectric layer and the side margin portion contain the Ti element and the Si element, and the ratio of the Ti element to the Si element in the side margin portion is four times or more the ratio of the Ti element to the Si element in the dielectric layer; The multilayer ceramic electronic component according to claim 6.

9. the side margin portion contains Si elements, and the amount of the Si elements in the side margin portion is 1 at% or more; The multilayer ceramic electronic component according to claim 3 .

10. the thickness of the dielectric layer along the first axis direction is 0.3 μm or more and 0.7 μm or less; The multilayer ceramic electronic component according to claim 1 .

11. the segregation portion has a length within one grain in the cross section of the dielectric layer that is 50% or more of the grain size of the grain. The multilayer ceramic electronic component according to claim 1 .

12. a step of fabricating an unfired ceramic laminated chip in which dielectric layers containing Si elements and internal electrodes are alternately laminated along a first axis direction, the chip having a capacitance forming portion in which the internal electrodes are exposed from a side surface facing a second axis direction perpendicular to the first axis direction; forming a side margin portion having a higher Si content than the dielectric layer on the side surface of the ceramic laminated chip to fabricate an unfired ceramic body; firing the ceramic body; forming external electrodes on the fired ceramic body; A method for manufacturing a multilayer ceramic electronic component comprising:

13. the dielectric layer and the side margin portion contain Ti elements and Si elements, and a ratio of the Ti elements to the Si elements in the side margin portion is higher than a ratio of the Ti elements to the Si elements in the dielectric layer; The method for producing a multilayer ceramic electronic component according to claim 12.

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