Multi-rate burst mode receiver

Abstract

To provide a device and a method for managing a burst mode receiver within an optical line terminal (OLT) in a passive optical network.SOLUTION: An OLT includes a burst mode receiver 111 that decodes an optical burst signal 210 from an optical network unit (ONU) into a decoded output signal 220 by one or more digital signal processing (DSP) circuits 201-204 that process the signal at respective configurable processing speeds. The burst mode receiver includes means 205 for performing obtaining a symbol rate 240 of a next optical burst signal 215, and adjusting 234 configurable processing speeds 230 of the one or more DSP circuits based on the symbol rate 240 of the next optical burst signal 215 during an interval between reception of a valuable symbol in a preceding optical burst signal 211 and reception of a valuable symbol in the next optical burst signal 215.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] Various exemplary embodiments relate to an apparatus and method for managing burst mode receivers in an optical line terminal (OLT) in a passive optical network. [Background technology]

[0002] In a passive optical network (PON), at least one optical line terminal (OLT) on the network side connects to one or more optical network units (ONU) on the user side. The upstream optical burst signal received by the OLT is usually decoded by a burst mode receiver, which usually comprises one or more burst mode receiver components. For example, the burst mode receiver in new PON systems, such as 50G-PON according to the ITU-T G.9804 standard, usually comprises more complex digital burst mode receiver components with digital signal processing functions, such as an equalizer.

[0003] In such new PON systems, ONUs may be enabled to transmit optical burst signals to the OLT at multiple different symbol rates. In other words, the symbol rate of the optical burst signals received by the OLT may vary. Therefore, it is desirable to enable efficient reception of optical burst signals with different symbol rates. Summary of the Invention [Problem to be solved by the invention]

[0004] The scope of protection sought for the various embodiments of the invention is defined by the independent claims. To the extent that any of the embodiments and features described herein are not included in the scope of the independent claims, they are to be interpreted as examples useful for understanding the various embodiments of the invention.

[0005] Among other things, it is an object of embodiments of the invention to enable efficient reception and decoding of optical burst signals with different symbol rates by an optical line termination OLT in a passive optical network PON. [Means for solving the problem]

[0006] This object is achieved according to a first exemplary aspect of the present disclosure by an optical line termination OLT configured to communicate with one or more optical network units ONU in a passive optical network; optical burst signals transmitted by the one or more ONUs have respective symbol rates; the optical line termination comprises a burst mode receiver configured to decode the optical burst signals from the ONUs into a decoded output signal by one or more digital signal processing circuits for processing the signals at respective configurable processing rates. The optical line termination comprises means configured to obtain a symbol rate of a next optical burst signal; and to adjust the configurable processing rate of the one or more digital signal processing circuits based on the symbol rate of the next optical burst signal during an interval between reception of valuable symbols in the preceding optical burst signal and in the next optical burst signal.

[0007] Thus, the optical burst signals received by the OLT may have different symbol rates. Each of one or more ONUs in the network may transmit optical burst signals at a respective predefined symbol rate, i.e., the symbol rate of each ONU may be fixed. Alternatively, the ONUs may transmit optical burst signals at different symbol rates. A burst mode receiver in the OLT is configured to receive and decode the optical burst signals, thereby generating a decoded output signal. In other words, the burst mode receiver processes or converts the optical burst signals into a decoded output signal. To this end, the burst mode receiver comprises one or more digital signal processing circuits that process signals at respective configurable processing rates. The digital signal processing circuit may refer to a burst mode receiver component in the burst mode receiver that includes at least one digital signal processing function. The configurable processing rate of the digital signal processing circuit refers to the rate at which input samples are processed by the digital signal processing circuit and / or the rate at which output samples are generated by the digital signal processing circuit.

[0008] The one or more digital signal processing circuits are interconnected to form a sequence, pipeline, or combination, such that each processing performed by each interconnected digital signal processing circuit contributes to the decoding of the optical burst signal into a decoded output signal. In other words, the one or more digital signal processing circuits form a processing data path for decoding the optical burst signal into a decoded output signal. Thus, each digital signal processing circuit processes an input signal into an output signal at a respective configurable processing rate. The input signal and / or the output signal of the digital signal processing circuit are digital signals. The burst mode receiver may further comprise one or more burst mode receiver components without configurable processing rates, for example fixed-rate analog burst mode receiver components, in the data path for decoding the optical burst signal.

[0009] The next optical burst signal is the next optical burst signal in time received by the OLT, i.e., the first subsequent optical burst signal. The preceding optical burst signal is the optical burst signal last received by the OLT. In other words, the preceding optical burst signal and the next optical burst signal are consecutive in time.

[0010] A valuable symbol in an optical burst signal is a symbol associated with valuable burst data. A valuable symbol may include a symbol corresponding to the payload of the optical burst signal, such as data, error correction data, parity data, control data, and idle data. In addition, a valuable symbol may further include a portion of a symbol in a preamble, a portion of a symbol in a header, or a symbol in a delimiter of the optical burst signal. The location of a symbol in an optical burst signal that is considered valuable may be predetermined or provisioned, for example, according to a network requirement or network protocol.

[0011] By adjusting the configurable processing speed of one or more respective digital signal processing circuits based on the symbol rate of the upcoming optical burst signal, the digital signal processing circuits can be optimized for the symbol rate of the upcoming optical burst signal. This has the advantage that the energy efficiency of the burst mode receiver, and therefore the OLT, is improved since the digital signal processing circuits can operate at an optimal processing speed for the received optical burst signal. In other words, the optical burst signal can be avoided from being oversampled by the digital signal processing circuit, which would consume unnecessary energy. It is a further advantage that the respective configurable processing speed of one or more respective digital signal processing circuits can be adjusted in real time, i.e. between incoming optical burst signals.

[0012] By adjusting the configurable processing speed of one or more respective digital signal processing circuits during intervals between receipt of a symbol of value in successive optical burst signals, it is further possible to avoid erroneous decoding of the symbol of value, since during a period following adjustment of the configurable processing speed, the bit in the decoded output signal may be invalid. This has the advantage that data loss and data corruption may be avoided when switching between the configurable processing speeds.

[0013] According to one example embodiment, the interval may include a guard time between a previous optical burst signal and a next optical burst signal; and / or a portion of a preamble in the next optical burst signal.

[0014] Thus, the interval between receiving a valuable symbol in a previous optical burst signal and receiving a valuable symbol in a next optical burst signal may include a guard time between two successive optical burst signals. The guard time is a period that provides a safety margin against interference between successive optical burst signals. Thus, no valuable burst data is received by the OLT during the guard time. Alternatively, or complementary, a portion of the preamble in the optical burst signal may be substantially free of valuable burst data, for example, the beginning of the preamble may include samples for training a burst mode receiver.

[0015] According to one example embodiment, adjusting the configurable processing speed of the one or more digital signal processing circuits may include adjusting a clock frequency of the one or more digital signal processing circuits.

[0016] Each of the one or more digital signal processing circuits may be applied with a clock signal that causes them to operate at a respective clock frequency, i.e., causes the digital signal processing circuit to process signals at a respective clock frequency or clock speed. In other words, the digital clock of the one or more digital signal processing circuits may determine the configurable processing speed of the digital signal processing circuit. Thus, by adjusting the clock frequency of the digital signal processing circuit, the configurable processing speed of each of the digital signal processing circuits may be adjusted. This may be achieved by modifying the clock signal applied to each of the one or more digital signal processing circuits, for example, by using a clock divisor circuit.

[0017] According to one example embodiment, adjusting the configurable processing speed of the respective digital signal processing circuit may include enabling and / or disabling one or more parallel circuit instances of the respective digital signal processing circuit.

[0018] In other words, each digital signal processing circuit in a burst mode receiver may include one or more parallel circuit instances of said digital signal processing circuit. The parallel circuit instances may operate at a nominal clock speed or frequency, i.e., a fixed processing speed. Thus, by enabling or disabling these parallel circuit instances in the signal data path, the configurable processing speed of each digital signal processing circuit may be increased or decreased, i.e., adjusted.

[0019] According to one exemplary embodiment, the burst mode receiver further comprises at least one downsampling circuit configured to downsample the signal.

[0020] Thus, at least one downsampling circuit may be included in the processing data path of the burst mode receiver for decoding the optical burst signal into a decoded output signal. Downsampling may refer to converting a digital signal at one sample rate into a digital signal at a lower sample rate. The downsampled signal may be the output signal of a preceding interconnected digital signal processing circuit, allowing the rate of the signal to be matched to a configurable processing speed of a subsequent digital signal processing circuit.

[0021] The downsampling circuit may be provided in the processing data path of the burst mode receiver, for example, following a burst mode receiver component having a fixed processing rate. The means of the OLT may be further configured to control the downsampling circuit according to a desired rate of the signal, for example by enabling the downsampling circuit, disabling the downsampling circuit, or modulating the amount of downsampling. In other words, the downsampling circuit may be configurable.

[0022] According to one exemplary embodiment, the burst mode receiver further comprises at least one upsampling circuit configured to upsample the signal.

[0023] Thus, at least one upsampling circuit may be included in the processing data path of the burst mode receiver for decoding the optical burst signal into a decoded output signal. Upsampling may refer to converting a digital signal at one sample rate into a digital signal at a higher sample rate. The upsampled signal may be the output signal of a preceding interconnected digital signal processing circuit, allowing the rate of the signal to be matched to a configurable processing speed of a subsequent digital signal processing circuit.

[0024] The upsampling circuit may be provided at the end of the processing data path or pipeline, so that the decoded output signal can be upsampled to a suitable rate for further circuitry in the OLT, such as higher layer processing circuitry and / or interface circuitry in the OLT, connected to the burst mode receiver. Alternatively, or complementary, the upsampling circuit may be provided before the burst mode receiver component that requires an input signal having a predefined sampling rate. The means of the OLT may be further configured to control the upsampling circuit according to the desired rate of the signal to be upsampled, for example by enabling the upsampling circuit, disabling the upsampling circuit, or modulating the amount of upsampling. In other words, the upsampling circuit may be configurable.

[0025] According to one exemplary embodiment, the burst mode receiver further comprises at least one latency compensator circuit configured to adjust for latency of the signal.

[0026] When adjusting the configurable processing speed of the digital signal processing circuit, the latency or processing delay of the digital signal processing circuit may change. For this purpose, at least one latency compensator circuit may be included in the processing data path of the burst mode receiver. The signal to which the latency adjustment is applied may be an output signal of a preceding interconnected digital signal processing circuit or may be an output signal of a preceding interconnected burst mode receiver component. The latency compensator circuit allows for compensating for changes in latency when adjusting the configurable processing speed of one or more digital signal processing circuits.

[0027] At least one latency compensator circuit can further compensate for changes in end-to-end latency of the burst mode receiver. The end-to-end latency of the burst mode receiver can refer to the processing time for decoding symbols in the optical burst signal into one or more bits or samples in the decoded output signal. This has the advantage that the latency or processing delay of the burst mode receiver can be controlled. This has the further advantage that the latency or processing delay of the burst mode receiver can be substantially stable in time, i.e., kept constant, when adjusting the configurable processing speed of the one or more digital signal processing circuits.

[0028] The means of the OLT may be further configured to control the latency compensator circuit according to a desired latency, for example by enabling the latency compensator circuit, disabling the latency compensator circuit, or modulating an amount of latency adjustment. In other words, the latency compensator circuit may be configurable.

[0029] According to one exemplary embodiment, the latency compensator circuit may be further configured to insert one or more dummy samples into the signal or drop one or more non-payload samples from the signal during an interval between receipt of valuable symbols in the preceding optical burst signal and the next optical burst signal.

[0030] The dummy samples and non-payload samples can be any data units, e.g., dummy bits and non-payload bits; or dummy symbols and non-payload symbols, depending on the signal for which the latency adjustment is performed. By inserting dummy samples or dropping non-payload samples, the change in end-to-end latency can be compensated for without significant impact on the system, e.g., without affecting further circuitry in the OLT connected to the burst mode receiver. It is a further advantage that data loss and data modification can be avoided during latency adjustment, since the insertion of dummy samples or dropping of non-payload samples is performed during an interval in which there is substantially no valuable burst data.

[0031] According to an exemplary embodiment, the means may be further configured to control the at least one downsampling circuit, the at least one upsampling circuit, and / or the at least one latency compensator circuit based on a symbol rate of the next optical burst signal.

[0032] According to an exemplary embodiment, the optical line terminal may be further configured to schedule a guard time between successive optical burst signals with a minimum length such that the decoded output signal includes at least enough non-payload bits to compensate for changes in end-to-end latency of the burst mode receiver associated with adjusting the configurable processing rate between a maximum processing rate supported by the OLT and a minimum processing rate supported by the OLT.

[0033] According to an example embodiment, the upsampling circuit may be further configured to upsample the signal to a predetermined data rate, or the latency compensator circuit is further configured to adjust the latency of the signal to a predetermined latency.

[0034] The predetermined data rate or latency may be determined by a circuit or processing block that receives the upsampled or latency adjusted signal, for example the next analog burst mode receiver component in the data path, the next digital signal processing circuit in the data path, or further circuitry in the OLT such as upper layer processing circuitry, or an interface circuit between the burst mode receiver and the upper layer processing circuitry.

[0035] According to one exemplary embodiment, the one or more digital signal processing circuits are selected from the group consisting of an analog-to-digital converter, a clock data recovery device, an equalizer, and / or a decoder.

[0036] According to an exemplary embodiment, the means of the OLT may be further configured to determine an interval between receipt of valuable symbols in a preceding optical burst signal and a next optical burst signal based on burst timing information of the optical burst signal.

[0037] The burst timing information may be, for example, an upstream transmission schedule that includes the time slots during which each ONU is permitted to transmit an optical burst signal to the OLT.

[0038] According to an example embodiment, obtaining the symbol rate of the next optical burst signal may further include determining the symbol rate based on an upstream transmission schedule.

[0039] The upstream transmission schedule may be determined by the OLT. The OLT may assign a symbol rate to the upstream transmission by each ONU in the passive optical network. Alternatively, or complementary, the OLT may assign the received upstream transmissions, i.e., optical burst signals, to each ONU as part of the upstream transmission schedule. The OLT may know the symbol rate assigned to each ONU. This allows it to obtain the symbol rate of the next optical burst signal.

[0040] According to a second exemplary aspect, a method is disclosed that includes: obtaining a symbol rate of a next optical burst signal; and adjusting a configurable processing rate of one or more digital signal processing circuits in an optical line termination OLT based on the symbol rate of the next optical burst signal during an interval between receiving valuable symbols in the previous optical burst signal and the next optical burst signal. The OLT is configured to communicate with one or more optical network units ONU in a passive optical network; the optical burst signals transmitted by the one or more ONUs have respective symbol rates; and the burst mode receiver is configured to decode the optical burst signals from the ONUs into a decoded output signal by one or more digital signal processing circuits that process the signals at the respective configurable processing rates.

[0041] According to a third exemplary aspect, a computer-implemented method is disclosed that includes obtaining a symbol rate of a next optical burst signal and adjusting a configurable processing rate of one or more digital signal processing circuits in an optical line termination OLT based on the symbol rate of the next optical burst signal during an interval between receiving valuable symbols in a previous optical burst signal and in the next optical burst signal. The OLT is configured to communicate with one or more optical network units ONU in a passive optical network; the optical burst signals transmitted by the one or more ONUs have respective symbol rates; and the burst mode receiver is configured to decode the optical burst signals from the ONUs into a decoded output signal by one or more digital signal processing circuits that process the signals at the respective configurable processing rates.

[0042] According to a fourth exemplary aspect, a computer program product is disclosed that includes computer-executable instructions for performing steps according to the third exemplary aspect when the computer program is executed on a computer.

[0043] According to a fifth exemplary aspect, a data processing system configured to perform a computer-implemented method according to the third exemplary aspect is disclosed. [Brief description of the drawings]

[0044] [Figure 1] 1 is a schematic block diagram of an example passive optical network. [Diagram 2] FIG. 1 illustrates an example embodiment of a burst mode receiver configured to decode an optical burst signal into a decoded output signal by one or more digital signal processing circuits that process the signals at respective configurable processing rates. [Figure 3A] 1 is a diagram of an example embodiment of a burst mode receiver in an OLT where adjusting the configurable processing rate includes adjusting a clock frequency of one or more digital signal processing circuits. [Figure 3B]1 is a diagram of an example embodiment of a burst mode receiver comprising a downsampling circuit configured to downsample a signal. [Figure 4A] 1 is a diagram of an example embodiment of a burst mode receiver comprising an upsampling circuit configured to upsample a signal. [Figure 4B] FIG. 13 is a diagram of an example embodiment of a burst mode receiver in which adjusting the configurable processing rate includes enabling and / or disabling one or more parallel circuit instances of one or more digital signal processing circuits. [Figure 5A] 1 illustrates an example of variation in end-to-end latency of a burst mode receiver by adjusting the configurable processing speed of one or more digital signal processing circuits within the burst mode receiver. [Figure 5B] 4 is a diagram of an example of end-to-end latency adjustment performed by a latency compensator circuit in a burst mode receiver, according to an embodiment. [Figure 6] FIG. 1 illustrates an example embodiment of a computing system suitable for performing one or more steps in embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] 1 shows a schematic block diagram of an exemplary point-to-multipoint optical network 100, in particular a passive optical network PON. The optical network 100 comprises an optical line termination 110 (OLT) and a number of optical network units ONUs 131, 132, 133 connected via an optical distribution network ODN 120. In this example, the OLT 110 is connected to four ONUs 131, 132, 133, 134, although the OLT 110 may be connected to fewer or more endpoints. The ODN 120 has a tree structure comprising an optical feeder fiber 121, one or more passive optical splitters / multiplexers 123, and a number of optical distribution or drop fibers 124, 125, 126, 127 connecting the splitters / multiplexers 123 to the respective ONUs 131, 132, 133, 134. In the downstream direction, the passive optical splitter / multiplexer 123 splits the optical signal coming from the OLT 110 into lower power optical signals for the connected ONUs 131, 132, 133, 134, and in the upstream direction, the passive optical splitter / multiplexer 123 multiplexes the optical signals coming from the connected ONUs 131, 132, 133, 134 into a burst signal for the OLT 110.

[0046] The passive optical network 100 may be a gigabit passive optical network GPON according to the ITU-T G.984 standard, a 10x gigabit passive optical network 10G-PON according to the ITU-T G.987 standard, a 10G symmetric XGS-PON according to the ITU-T G.9807 standard, a 4-channel 10G symmetric NG-PON2 according to the ITU-T G.989 standard, a 25GS-PON according to the ITU-T G.9804 standard, a 50G-PON, or a next-generation passive optical network NG-PON. The passive optical network 100 may perform time division multiplexing TDM or time wavelength division multiplexing TWDM.

[0047] The OLT 110 further comprises a burst mode receiver 111 configured to receive and decode the upstream optical burst signals transmitted by the connected ONUs 131, 132, 133, 134. To this end, the burst mode receiver 111 typically comprises burst mode receiver components. The burst mode receiver components can be analog and / or digital circuits. The burst mode receiver components are typically interconnected to form a sequence or pipeline, such that each burst mode receiver component contributes to the decoding of the optical burst signals. Thus, the burst mode receiver 111 generates a decoded output signal, i.e. a digital signal. The decoded output signal may include, for example, bits, symbols, or log-likelihood ratio values ​​llr. This output signal may be further provided to one or more upper layer circuits in the OLT 110 configured to utilize or process the decoded burst data.

[0048] It may be desirable to enable the ONUs 131-134 in the PON 100 to transmit optical burst signals at multiple different symbol rates to the OLT 110. Thus, the symbol rate of the optical burst signals received by the OLT 110, and thus the burst mode receiver 111, may vary. Typically, the digital burst mode receiver components in the burst mode receiver 111 are configured to operate at a fixed processing rate. The processing rate refers to the rate at which input samples are processed by the respective burst mode receiver components in the burst mode receiver 111 and / or the rate at which output samples are generated by said components. Thus, the processing rate of the burst mode receiver components may determine the throughput of the burst mode receiver 111, i.e., the sample rate of the decoded output signal.

[0049] Receiving multi-rate optical burst signals with a typical fixed-rate digital burst mode receiver component has the problem that the lower rate optical burst signals are oversampled. This has the problem that the burst mode receiver component continues to operate at full processing speed even when the optical burst signals have a lower rate, limiting the energy efficiency of the burst mode receiver 111. Some burst mode receiver components may not be able to process multi-rate optical burst signals, as some require a certain rate of input signal, which is an additional problem. In addition, burst mode receivers in new PON systems, such as 50G-PON according to the ITU-T G.9804 standard, typically include more complex digital burst mode receiver components with digital signal processing functions, e.g., equalizers. Such digital burst mode receiver components with digital signal processing functions may be referred to as digital signal processing (DSP) circuits. A burst mode receiver that includes a DSP circuit, i.e., a digital burst mode receiver component, may be referred to as a digital burst mode receiver.

[0050] Therefore, it is desirable to enable energy-efficient reception and decoding of optical burst signals having different symbol rates. In the following description, an exemplary embodiment of an optical line terminal OLT with a burst mode receiver capable of receiving and decoding multi-rate optical burst signals in an energy-efficient manner is described.

[0051] 2 illustrates an exemplary embodiment of a burst mode receiver 111 configured to decode an optical burst signal 210 originating from an ONU into a decoded output signal 220 by one or more analog circuits 200 and one or more digital signal processing circuits 201, 202, 203, 204 that process signals 210, 207, 208, 209 at respective configurable processing rates within the OLT. The optical burst signal 210 may first be processed by the circuit 200 to convert the optical signal 210 into an analog signal such as a voltage or current. The circuit 200 may comprise, for example, a photodiode and a transimpedance amplifier. The digital signal processing DSP circuits 201, 202, 203, 204 are interconnected such that the respective processing performed by each DSP circuit 201, 202, 203, 204 contributes to the decoding of the optical burst signal 210 into a decoded output signal 220. In other words, the DSP circuits 201 , 202 , 203 , 204 form a data path of functional units for decoding the optical burst signal 210 into a decoded output signal 220 .

[0052] Each DSP circuit 201, 202, 203, 204 processes an input signal into an output signal at a respective configurable processing speed, e.g., DSP circuit 202 processes input signal 207 into output signal 208. The configurable processing speed of DSP circuits 201, 202, 203, 204 refers to the rate at which input samples are processed by the DSP circuit and / or the rate at which output samples are generated. Since DSP circuits 201, 202, 203, 204 form a sequence or pipeline, it will be apparent that the output of a DSP circuit, e.g., output signal 207 of DSP circuit 201, can be the input of the next DSP circuit in the data path, e.g., 202.

[0053] The DSP circuits 201, 202, 203, 204 may be, for example, an analog-to-digital converter 201, a clock data recovery device 202, an equalizer 203, and / or a decoder 204. It will be apparent that the configurable processing speed of a DSP circuit receiving an analog input signal, e.g., an analog-to-digital converter 201, cannot be defined according to the rate at which the input samples are processed by the DSP circuit, since the analog input signal does not include digital samples. The burst mode receiver 111 may further comprise one or more burst mode receiver components without configurable processing speed, e.g., fixed speed analog burst mode receiver components, in the data path for decoding the optical burst signal.

[0054] The burst mode receiver 111 further comprises a means 205 configured for obtaining a symbol rate 240 of the next optical burst signal 215. The next optical burst signal 215 is the next optical burst signal in time received by the OLT, i.e. the first subsequent optical burst signal. The optical burst signal 211 preceding the next optical burst signal 215 is referred to as the preceding optical burst signal 211. In other words, the preceding optical burst signal 211 is the last optical burst signal received. Therefore, the preceding optical burst signal 211 and the next optical burst signal 215 are consecutive in time.

[0055] The optical burst signals 211, 215 may include preambles 212, 216; delimiters 213, 217; and payloads 214, 218. The delimiters 213, 217 indicate the start of the payloads 214, 218. The payloads 214, 218 may include, for example, message data, error correction data, parity data, control data, and idle data. The optical burst signals 211, 215 may have different symbol rates. For example, the burst signal 211 may be a 25G non-return-to-zero NRZ signal; and the burst signal 215 may be a 50G NRZ signal or a 100G PAM4 signal. Thus, the means 205 is configured to obtain a symbol rate 240 of the next optical burst signal 215 expected to arrive at the OLT, i.e., the burst mode receiver 111.

[0056] Obtaining this symbol rate 240 may include determining the symbol rate of the next optical burst signal 215 based on an upstream transmission schedule. The upstream transmission schedule may assign symbol rates to scheduled upstream transmissions, i.e., optical burst signals, originating from ONUs in the network. Since the upstream transmission schedule is typically determined by the OLT or by a scheduler within the OLT, the symbol rate 240 of the next optical burst signal 215 may simply be determined from this schedule. Alternatively, or complementary, the OLT may assign transmission opportunities of the received optical burst signal 210 to the respective ONUs associated with the respective symbol rates. In other words, the OLT may associate the optical burst signal 210 with a particular ONU based on the upstream transmission schedule, and the OLT may know the symbol rate assigned to this ONU, thereby obtaining the symbol rate of the next optical burst signal.

[0057] The means 205 is further configured to adjust 234 a configurable processing speed of the one or more DSP circuits 201, 202, 203, 204 based on the symbol rate 240 of the next optical burst signal 215 during an interval 240 between receipt of valuable symbols in the previous optical burst signal 211 and the next optical burst signal 215.

[0058] Valuable symbols in the optical burst signals 211, 215 are symbols that are associated with valuable burst data 222, 224, i.e., valuable or relevant decoded data. Valuable symbols may include symbols corresponding to the payload 214, 218 and delimiters 213, 217 of the optical burst signals. In addition, valuable symbols may be included within a portion 242 of the preamble 216. The location of symbols considered to be valuable may be predetermined or provisioned, for example, according to network requirements or protocols.

[0059] 2 illustrates an example of a configurable processing rate 230 of DSP circuits 201, 202, 203, 204 over time, where the symbol rate of the next optical burst signal 215 is higher than the symbol rate of the preceding optical burst signal 211. The configurable processing rate 230 is adjusted from a lower configurable processing rate 233 to a higher configurable processing rate 235 in time step 234 based on the symbol rate 240 of the next optical burst signal 215.

[0060] Based on the symbol rate 240 of the upcoming optical burst signal 215, the configurable processing speed of one or more respective DSP circuits 201, 202, 203, 204 can be adjusted to optimize the DSP circuits for the symbol rate of the upcoming optical burst signal. This has the advantage that the DSP circuits can operate at an improved processing speed for the received optical burst signal 210, improving the power consumption of the burst mode receiver 111, and therefore the OLT. In other words, the optical burst signal 210 can be prevented from being processed by the one or more DSP circuits 201, 202, 203, 204 at an excessively high sampling rate, which would consume unnecessary power. It is a further advantage that the configurable processing speed of each of the DSP circuits 201, 202, 203, 204 can be adjusted in real time, i.e., between the incoming optical burst signals 210.

[0061] Adjusting the configurable processing rate occurs during intervals 240 between receipt of valuable symbols in successive optical burst signals 211, 215. Thus, during interval 240, no valuable symbols arrive or are received by the OLT, and thus, the portion of decoded output signal 220 associated with interval 240 may be substantially devoid of valuable burst data, as illustrated by periods 221 and 223 in FIG.

[0062] During the period following adjusting 232, 234 the configurable processing rate, samples in the decoded output signal 220 may be invalid, so that adjusting the configurable processing rate of one or more respective DSP circuits 201, 202, 203, 204 during the interval 240 between receipt of a valuable symbol in successive optical burst signals 211, 215 may avoid erroneous decoding of that valuable symbol. This has the advantage that data loss and data corruption may be avoided when switching between configurable processing rates.

[0063] The interval 240 may include a guard time 241 between the preceding optical signal 211 and the next optical signal 215. The guard time 241 is a period that provides a safety margin against interference between successive optical burst signals 211, 215 arriving at the OLT. Thus, no valuable burst data is received by the OLT during the guard time 241. Alternatively, or complementary, the interval 240 may include a portion of the preamble 216 of the next optical burst signal 215. For example, the beginning portion 242 of the preamble 216 of the optical burst signal 215 may include samples for training the burst mode receiver 111, i.e., worthless symbols where the burst data in the decoded output signal 220 is not relevant or needed.

[0064] The means 205 may further be configured to determine the interval 240 based on burst timing information 250 of the optical burst signal 210. The burst timing information 250 may be, for example, a start time and duration of a burst, which may be included in an upstream transmission schedule of the OLT. The burst timing information may be provided by another circuit in the OLT, for example a scheduler, or an external circuit. This allows for determining when the configurable processing rate adjustment can be performed without data loss.

[0065] The means 205 may comprise at least one processor and at least one memory. A computer program code may be included in the memory, and when executed by the processor, according to an embodiment, causes the means 205 to adjust the configurable processing speed of one or more DSP circuits based on the symbol rate of the next optical burst signal. The means 205 may be, for example, a controller circuit.

[0066] 3A illustrates an example embodiment of a burst mode receiver 111 in an OLT where adjusting the configurable processing speed includes adjusting the clock frequency of one or more DSP circuits 201, 202, 203, 204. The DSP circuits 201, 202, 203, 204 may be applied with a clock signal 302 that causes them to operate at a respective clock frequency, i.e., the clock signal 302 that causes the DSP circuits to process signals at the respective clock frequency. In other words, the clock signal 302 applied to the DSP circuits 201, 202, 203, 204 may determine their configurable processing speed. Thus, adjusting the configurable processing speed of the DSP circuits 201, 202, 203, 204 may include adjusting the respective clock frequency of the respective DSP circuits.

[0067] This can be achieved by modifying 303 clock signal 302 applied to each DSP circuit 201, 202, 203, 204, for example with a clock divisor circuit 301. In other words, the burst mode receiver 111 can comprise a clock divisor circuit 301 configured to adjust or modify the clock signal 302 applied to one or more of the DSP circuits 201, 202, 203, 204. The means 205 can be configured to provide control of the clock divisor circuit 301. This can be achieved by providing a control signal 305 to the clock divisor circuit 301, including a configurable processing rate for processing the next optical burst signal.

[0068] Although Figure 3A illustrates an example embodiment in which the clock signal 302 applied to all DSP circuits 201, 202, 203, 204 is adjusted; it will be apparent that the adjusted clock signal 303 may be applied to any number of DSP circuits 201, 202, 203, 204. For example, Figure 3B illustrates an example embodiment in which the adjusted clock signal 303 is applied only to DSP circuits 202, 203, and 204. An unmodified clock signal 302 is applied to DSP circuit 201 to operate this circuit at a fixed processing speed.

[0069] Thus, the DSP circuit 201 outputs samples 312 at a fixed rate. To allow the other DSP circuits 202, 203, 204 to operate at a lower configurable processing rate, the burst mode receiver 111 may further comprise at least one downsampling circuit 311. The circuit 311 may be configured to downsample the signal 312, i.e. convert the signal 312 having a certain sampling rate into a signal 313 having a lower sampling rate that matches the configurable processing rate of the subsequent DSP circuit 202, 203, 204. The downsampled signal 312 may be the output of a preceding interconnected DSP circuit 201.

[0070] The means 205 may be further configured to control the downsampling circuit 311 according to a desired rate of the signal 313 based on the configurable processing speed of the DSP circuits 202, 203, 204. This may be achieved by providing the downsampling circuit 311 with a control signal 305 including a configurable processing speed for processing the next optical burst signal. The downsampling circuit 311 may be controlled, for example, by enabling the downsampling circuit, disabling the downsampling circuit, or modulating the amount of downsampling. In other words, the downsampling circuit 311 may be configurable.

[0071] FIG. 4A shows an example embodiment of a burst mode receiver 111 in an OLT, including at least one upsampling circuit 401. The upsampling circuit 401 may be configured to upsample a signal 402, i.e. convert a signal 402 having a certain sampling rate to a signal 403 having a higher sampling rate. In the example embodiment shown in FIG. 4A, the upsampling circuit is provided at the end of a processing data path or pipeline. This allows the signal 402 to be upsampled to a suitable rate for further circuitry 404 in the OLT, e.g. for higher layer processing circuitry and / or interface circuitry in the OLT, which is connected to the burst mode receiver 111. Alternatively or complementary, the upsampling circuit 401 may be provided before a burst mode receiver component or DSP circuit that requires an input signal at a predetermined rate, e.g. between the DSP circuit 201 and the DSP circuit 202. In other words, the upsampling circuit may be configured to upsample a signal to a predetermined sampling rate that depends on the receiving side of the upsampled signal, e.g. the further circuitry 404, the burst mode receiver component, or the DSP circuit.

[0072] The means 205 may further be configured to control the upsampling circuit 401 according to a desired rate of the signal 403. This may be achieved by providing the upsampling circuit 401 with a control signal 305 including a configurable processing rate for processing the next optical burst signal. The upsampling circuit 401 may be controlled, for example, by enabling the upsampling circuit, disabling the upsampling circuit, or modulating the amount of upsampling. In other words, the upsampling circuit 401 may be configurable.

[0073] The upsampling circuit 401 may be further configured to upsample the signal to a predetermined sampling rate, which may be determined by a circuit or processing block that receives the upsampled signal 403, such as the next burst mode receiver component in the data path, the next DSP circuit 201, 202, 203, 204 in the data path, upper layer processing circuit 404 in the OLT, or an interface circuit 404 between the burst mode receiver and upper layer processing circuitry in the OLT.

[0074] FIG. 4B shows an example embodiment of a burst mode receiver 111 in an OLT where adjusting the configurable processing rate includes enabling and / or disabling one or more parallel circuit instances 201a, 201b, 201c, 202a, 202b, 202c, 203a, 203b, 203c, 204a, 204b, 204c of one or more DSP circuits 201, 202, 203, 204.

[0075] In other words, each DSP circuit 201, 202, 203, 204 in the burst mode receiver 111 may include one or more parallel circuit instances of the digital signal processing circuit. Each parallel circuit instance 201a, 201b, 201c, 202a, 202b, 202c, 203a, 203b, 203c, 204a, 204b, 204c may operate at a nominal clock speed or frequency, i.e., a fixed processing speed. Thus, by enabling or disabling the parallel circuit instance of each DSP circuit in the signal data path, the configurable processing speed of each digital signal processing circuit may be increased or decreased, respectively. That is, the configurable processing speed of the DSP circuits 201, 202, 203, 204 may be adjusted.

[0076] For example, enabling all three parallel circuit instances 204a, 204b, 204c of the DSP circuit 204 causes the DSP circuit 204 to operate at a maximum configurable processing speed. Disabling one parallel circuit instance, e.g., 204a, can reduce the configurable processing speed by one third, and disabling two parallel circuit instances, e.g., 204a and 204b, can reduce the configurable processing speed by two thirds.

[0077] It will be apparent that the configurable processing speed of one or more DSP circuits 201, 202, 203, 204 in the burst mode receiver 111 can be adjusted by adjusting the clock frequency as described in connection with Figures 3A and 3B; and the configurable processing speed of other DSP circuits 201, 202, 203, 204 in the receiver 111 can be adjusted by enabling and / or disabling parallel circuit instances as described in connection with Figure 4B. It will further be apparent that the configurable processing speed of a DSP circuit, e.g., 202, can be adjusted by a combination of adjusting the clock frequency of that DSP circuit and enabling and / or disabling parallel circuit instances 202a, 202b, 202c of that DSP circuit.

[0078] When adjusting the configurable processing speed of the DSP circuit 201, 202, 203, 204, the latency or processing delay of the DSP circuit 201, 202, 203, 204 may change. For example, increasing the configurable processing speed may decrease the latency. Thus, the burst mode receiver 111 may further comprise at least one latency compensator circuit 401, 410 configured to adjust the latency of the signal 402, 411, i.e., to increase and / or decrease the latency of the signal 402, 411. This may compensate for changes in latency when adjusting the configurable processing speed of one or more DSP circuits 201, 202, 203, 204. It will be apparent that the circuit 401 of FIG. 4A may be a latency compensator circuit instead of or in addition to an upsampling circuit.

[0079] In the exemplary embodiment shown in Figures 4A and 4B, the latency compensator circuit 401, 410 is provided at the end of the processing data path or pipeline of the burst mode receiver 111. This can compensate for changes in the end-to-end latency of the burst mode receiver 111 associated with adjusting the configurable processing rate of one or more DSP circuits 201, 202, 203, 204. The end-to-end latency of the digital burst mode receiver 111 can refer to the processing time for decoding a symbol in the optical burst signal 210 into one or more bits in the decoded output signal 220. This has the advantage that the latency or processing delay of the burst mode receiver 111 can be controlled. This has the further advantage that the latency or processing delay of the burst mode receiver 111 can be substantially stable in time, i.e., kept constant, when adjusting the configurable processing rate of one or more DSP circuits 201, 202, 203, 204. The latency compensator circuits 401, 410 may be further configured to adjust the latency of the signal to a predetermined latency based on the recipient of the latency adjusted signal, for example the further circuitry 404, or a DSP circuit.

[0080] FIG. 5A illustrates an example of a change in end-to-end latency 551a, 552a, 553a of a burst mode receiver by adjusting configurable processing rates 561, 562, 563 of one or more DSP circuits in the burst mode receiver without a latency compensator circuit. At time step 571, i.e., during the interval between receipt of valuable symbols in the preceding optical burst signal 510 and the next optical burst signal 520, the configurable processing rate 230 of one or more DSP circuits may be decreased from processing rate 561 to processing rate 562. As a result, a change in end-to-end latency from latency 551a to latency 552a, i.e., an increase in processing delay, is caused. Similarly, increasing the configurable processing rate 230 of one or more DSP circuits from processing rate 562 to processing rate 563 at time step 572 may result in a change in end-to-end latency from latency 552a to latency 553a, i.e., a decrease in processing delay.

[0081] 5B illustrates an example of a latency adjustment performed by the latency compensator circuit 410. The latency compensator circuit may be configured to drop 554 one or more non-payload samples 543 from the decoded output signal 220 during an interval between receipt of a symbol of value in the preceding optical burst signal 510 and the next optical burst signal 520. The non-payload samples 543 may be samples or bits included in the portion, i.e., portion 543, of the decoded output signal 220 associated with the interval. In this way, the end-to-end latency 551b, 552b can be maintained when adjusting the configurable processing rate. This allows changes in the end-to-end latency to be compensated for without significant impact on the system, for example without impacting additional circuitry in the OLT connected to the burst mode receiver 111.

[0082] The latency compensator circuit 410 may further be configured to insert one or more dummy samples 555 in the decoded output signal 220 during an interval between receipt of a valuable symbol in the preceding optical burst signal 520 and the next optical burst signal 530. Thus, the dummy samples 555 may be inserted in a portion of the decoded output signal 220 associated with the interval, i.e., the portion 545. In this way, the end-to-end latency 552b, 553b may be maintained when adjusting the configurable processing rate. This allows the end-to-end latency change to be compensated for without significant impact on the system, e.g., without affecting downstream circuitry in the OLT connected to the burst mode receiver 111.

[0083] It is a further advantage that the insertion of dummy samples 554 or the dropping of non-payload samples 555 is performed during intervals without valuable symbols, so that data loss and data corruption may be avoided during latency adjustment.

[0084] Adjusting the configurable processing rate of one or more DSP circuits between the highest and lowest processing rates supported by the OLT may result in the largest change in the end-to-end latency of the burst mode receiver. Therefore, the OLT may be further configured to schedule a guard time 580 between successive optical burst signals 510, 520 with a minimum length such that the decoded output signal 220 includes at least enough non-payload bits 545 to compensate for the change in the end-to-end latency of the burst mode receiver associated with adjusting the configurable processing rate between the highest and lowest processing rates supported by the OLT. In other words, the guard time 580 may be scheduled such that this largest change in the end-to-end latency can be compensated for by dropping all necessary samples within the guard time.

[0085] Returning to FIG. 4B, it will be apparent that the latency compensator circuit 410 may also be provided at another location within the processing data path or pipeline of the burst mode receiver 111, for example between the DSP circuits 202 and 203.

[0086] Thus, the dummy samples inserted by the latency compensator circuit 410 can be any data unit depending on the signal for which the latency adjustment is being made. For example, when inserting dummy samples in the decoded output signal 220, the dummy samples can be dummy bits or dummy symbols depending on whether the decoded output signal includes bits or symbols. Similarly, the non-payload samples dropped by the latency compensator circuit 410 can be any data unit, e.g., non-payload bits or non-payload symbols, depending on the signal for which the latency adjustment is being made.

[0087] The means 205 may be further configured to control the latency compensator circuit 410 according to a desired signal latency, for example by enabling the latency compensator circuit, disabling the latency compensator circuit, or modulating an amount of latency adjustment. In other words, the latency compensator circuit may be configurable.

[0088] FIG. 6 illustrates a suitable computing system 600 that allows for implementing an embodiment of a method for managing the coordination of one or more burst mode receiver components in an optical line termination. The computing system 600 may generally be formed as a suitable general-purpose computer and includes a bus 610, a processor 602, a local memory 604, one or more optional input interfaces 614, one or more optional output interfaces 616, a communication interface 612, a storage element interface 606, and one or more storage elements 608. The bus 610 may include one or more conductors that allow communication between the components of the computing system 600. The processor 602 may include any type of conventional processor or microprocessor that interprets and executes program instructions. The local memory 604 may include a random access memory (RAM) or other type of dynamic storage device that stores information and instructions for execution by the processor 602, and / or a read-only memory (ROM) or other type of static storage device that stores static information and instructions for use by the processor 602. The input interface 614 may comprise one or more conventional mechanisms that allow an operator or user to input information into the computing device 600, such as a keyboard 620, a mouse 630, a pen, a voice recognition and / or biometric mechanism, a camera, etc. The output interface 616 may comprise one or more conventional mechanisms that output information to an operator or user, such as a display 640. The communication interface 612 may comprise any transceiver-like mechanism, such as, for example, one or more Ethernet interfaces, that allows the computing system 500 to communicate with other devices and / or systems, such as, for example, one or more DSP circuits 201, 202, 203, 204. The communication interface 612 of the computing system 600 may be connected to such other computing systems by a local area network (LAN) or a wide area network (WAN), such as, for example, the Internet.The storage element interface 606 comprises a storage interface, such as a Serial Advanced Technology Attachment (SATA) interface or a Small Computer System Interface (SCSI), for connecting the bus 610 to one or more storage elements 608, such as one or more local disks, such as Serial Advanced Technology Attachment (SATA) disk drives, and can control the writing of data to and / or reading of data from these storage elements 608. Although the storage elements 608 above are described as local disks, in general, any other suitable computer-readable medium may be used, such as a removable magnetic disk, an optical storage medium such as a CD or DVD,-ROM disk, a solid-state drive, a flash memory card, etc. Thus, the computing system 600 may correspond to the controller circuit 205 in the embodiment shown by FIG. 2.

[0089] As used in this application, the term "circuitry" may refer to one or more or all of the following: (a) A purely hardware circuit implementation, such as an implementation in purely analog and / or digital circuits. (b) A combination of hardware circuitry and software, as applicable, that includes the following: (i) A combination of analog and / or digital hardware circuitry and software / firmware. (ii) Any portion of a hardware processor (including a digital signal processor), software, and memory together with software that work together to cause a device, such as a mobile phone or server, to perform various functions. (c) A hardware circuit and / or processor, such as a microprocessor or part of a microprocessor, that requires software (e.g., firmware) to operate, but that software may not be present when it is not necessary for operation.

[0090] This definition of circuitry applies to all uses of the term in this application, including the claims. In a further example, the term circuitry, as used in this application, also covers merely a hardware circuit or processor (or processors), or a portion of a hardware circuit or processor, and its (or their) accompanying software and / or firmware implementations. The term circuitry, for example, and where applicable to certain claim elements, also covers baseband or processor integrated circuits for mobile devices, or similar integrated circuits in servers, cellular network devices, or other computing or network devices.

[0091] Although the present invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that the present invention is not limited to the details of the foregoing exemplary embodiments, and that the present invention may be embodied in various changes and modifications without departing from its scope. The present embodiments are therefore considered to be illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims, rather than by the foregoing description, and therefore all changes that come within the meaning and range of equivalents of the claims are intended to be embraced therein. In other words, it is intended to cover any and all modifications, variations, or equivalents that are within the scope of the basic fundamental principles and whose essential attributes are claimed in this patent application.

[0092] The reader of this patent application will further understand that the words "comprising" or "comprises" do not exclude other elements or steps, that the words "a" or "an" do not exclude a plurality, and that a single element, such as a computer system, processor, or other integrated unit, may perform the functionality of several means recited in the claims. Any reference signs in the claims shall not be construed as limiting the respective related claims. The terms "first", "second", "third", "a", "b", "c", and the like, when used in the present specification or claims, are introduced to distinguish between similar elements or steps and do not necessarily describe a sequential or chronological order. Similarly, the terms "top", "bottom", "over", "under", and the like, are introduced for explanatory purposes and do not necessarily indicate a relative position. That is, it is to be understood that the terms so used are interchangeable under appropriate circumstances, and that embodiments of the invention are capable of operating in accordance with the invention in other sequences or directions other than those described or illustrated above. [Explanation of symbols]

[0093] 100 Passive Optical Networks 110 Optical Line Terminal (OLT) 111 Burst Mode Receiver 120 Optical Distribution Network (ODN) 121 Optical feeder fiber 123 Passive Optical Splitter / Multiplexer 124, 125, 126, 127 Optical distribution or drop fiber 131, 132, 133, 134 Optical network unit ONU 200 Analog Circuits 201a, 201b, 201c, 202a, 202b, 202c, 203a, 203b, 203c, 204a, 204b, 204c Parallel circuit instances 205 means 207 Input Signal 208 Output Signal 209, 312, 402 signals 210 Optical Burst Signal 211, 510 Leading optical burst signal 212, 216 Preamble 213, 217 Delimiter 214, 218 Payload 215, 520th order optical burst signal 220 Decoded output signal 221, 223 period 222, 224 Valuable Burst Data 230 configurable processing speeds 232 Adjustment 233 Low configurable processing speed 234 Adjusting, Time Step 235 High configurable processing speed 241, 580 Guard Time Part of the 242 Preamble 250 Burst Timing Information 301 Clock Divider Circuit 302 Clock Signal 303 Adjusting the clock frequency 305 Control Signal 311 Downsampling Circuit 313 Signals with lower sampling rates 401 Upsampling circuit, latency compensator circuit Signals with sampling rates higher than 403 404 Further circuits, upper layer processing circuits, interface circuits 410 Latency Compensator Circuit 411 Signal 543 non-payload samples 545 non-payload bits 551a, 552a, 553a, 551b, 552b, 553b End-to-end latency 561, 562, 563 Configurable Processing Speed 571, 572 time steps 600 Computing Systems 602 Processor 604 Local Memory 606 Storage Element Interface 608 Memory Element 610 Bus 612 Communication Interface 614 Input Interface 616 Output Interface 620 Keyboard 630 Mouse

Claims

1. An optical line terminal (110) OLT configured to communicate in a passive optical network (100) with one or more optical network units (131-134) ONUs, wherein optical burst signals (210) transmitted by the one or more ONUs have respective symbol rates, the optical line terminal comprising a burst mode receiver (111) configured to decode the optical burst signals from the ONUs into a decoded output signal (220) by one or more digital signal processing circuits (201, 202, 203, 204) that process the signals at respective configurable processing rates, the optical line terminal comprising: obtaining the symbol rate (240) of the next optical burst signal (215); - adjusting (234) a configurable processing speed (230) of one or more digital signal processing circuits based on a symbol rate (240) of the next optical burst signal (215) during an interval (240) between receipt of valuable symbols in the preceding optical burst signal (211) and the next optical burst signal (215); An optical line terminal (110) OLT comprising means (205) configured to perform the following:

2. 2. The optical line terminal OLT of claim 1, wherein the interval (240) includes a guard time (241) between the preceding optical burst signal (211) and the next optical burst signal (215) and / or a portion (242) of a preamble (216) in the next optical burst signal (215).

3. The optical line terminal OLT according to claim 1 or 2, wherein adjusting the configurable processing speed of the one or more digital signal processing circuits comprises adjusting (303) a clock frequency of the one or more digital signal processing circuits.

4. 3. The optical line terminal OLT of claim 1 or 2, wherein adjusting the configurable processing speed of each digital signal processing circuit (202) comprises enabling and / or disabling one or more parallel circuit instances (202a, 202b, 202c) of each digital signal processing circuit.

5. The optical line terminal OLT according to claim 1 or 2, wherein the burst mode receiver (111) further comprises at least one downsampling circuit (311) configured to downsample the signal (312).

6. The optical line terminal OLT according to claim 1 or 2, wherein the burst mode receiver (111) further comprises at least one upsampling circuit (401) configured to upsample the signal (402).

7. The optical line terminal OLT according to claim 1 or 2, wherein the burst mode receiver (111) further comprises at least one latency compensator circuit (410) configured to adjust the latency of the signal (411).

8. 8. The optical line terminal OLT of claim 7, wherein the latency compensator circuit (410) is further configured to insert one or more dummy samples (554) into the signal (220) or drop one or more non-payload samples (545) from the signal (220) during an interval between receipt of valuable symbols in the preceding optical burst signal (510) and the next optical burst signal (520).

9. The optical line terminal OLT according to claim 5, wherein the means (205) is further configured to control at least one downsampling circuit (311) based on a symbol rate (240) of the next optical burst signal.

10. The optical line termination OLT of claim 6, wherein the means (205) is further configured to control at least one upsampling circuit (401) based on the symbol rate (240) of the next optical burst signal.

11. The optical line termination OLT of claim 7, wherein the means (205) is further configured to control at least one latency compensator circuit (410) based on a symbol rate (240) of the next optical burst signal.

12. The optical line terminal OLT of claim 6, wherein the upsampling circuit (401) is further configured to upsample the signal (402) to a predetermined data rate.

13. The optical line termination OLT of claim 7, wherein the latency compensator circuit (410) is further configured to adjust the latency of the signal (411) to a predetermined latency.

14. The optical line terminal OLT according to claim 1 or 2, wherein the one or more digital signal processing circuits are selected from the group consisting of an analog-to-digital converter (201), a clock data recovery device (202), an equalizer (203), and / or a decoder (204).

15. 3. The optical line terminal OLT according to claim 1 or 2, wherein the means (205) is further configured to determine an interval (240) between reception of valuable symbols in a preceding optical burst signal (211) and in a next optical burst signal (215) based on burst timing information (250) of the optical burst signals (211, 215).

16. The optical line terminal OLT according to claim 1 or 2, wherein obtaining a symbol rate (240) of the next optical burst signal further comprises determining the symbol rate based on an upstream transmission schedule.

17. obtaining the symbol rate (240) of the next optical burst signal (215); adjusting (234) a configurable processing rate (230) of one or more digital signal processing circuits (201, 202, 203) in the optical line termination (110) OLT based on the symbol rate of the next optical burst signal during an interval (240) between receipt of valuable symbols in the preceding optical burst signal (211) and the next optical burst signal (215); Including, 1. A method in which an OLT is configured to communicate with one or more optical network units (131-134) ONUs in a passive optical network, optical burst signals (210) transmitted by the one or more ONUs having respective symbol rates, and a burst mode receiver is configured to decode the optical burst signals from the ONUs into a decoded output signal (220) by one or more digital signal processing circuits that process the signals at respective configurable processing rates.

18. 1. A computer-implemented method comprising: obtaining a symbol rate of a next optical burst signal; - adjusting (232, 234) a configurable processing speed (230) of one or more digital signal processing circuits in the optical line termination (110) OLT based on the symbol rate of the next optical burst signal during an interval (240) between receipt of valuable symbols in the preceding optical burst signal (211) and in the next optical burst signal (215); Including, A computer-implemented method in which an OLT is configured to communicate with one or more optical network units (131-134) ONUs in a point-to-multipoint optical network, optical burst signals (210) transmitted by the one or more ONUs having respective symbol rates, and a burst mode receiver is configured to decode the optical burst signals from the ONUs into a decoded output signal (220) by one or more digital signal processing circuits that process the signals at respective configurable processing rates.

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