Display device and method for manufacturing the same

Abstract

To reduce the manufacturing cost of a display device.SOLUTION: A method for manufacturing a display device includes forming a lower electrode above a substrate, forming an inorganic insulating layer having an opening overlapping the lower electrode, preparing a processing substrate on which a partition wall including a lower portion located on the inorganic insulating layer and an upper portion located on the lower portion and protruding from a side surface of the lower portion is formed, forming an organic layer including a light-emitting layer on the lower electrode in the opening, forming an upper electrode on the organic layer, forming a cap layer on the upper electrode, forming a first sealing layer covering the cap layer and the partition wall, and forming a resin layer covering the first sealing layer. The process of forming the organic layer, the upper electrode, and the cap layer is a deposition process using the partition wall as a mask in a vacuum environment, and the process of forming the resin layer includes a process of applying a resin material in an atmospheric atmosphere.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a display device and a method for manufacturing a display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have been put to practical use. This display element includes a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer that covers the lower electrode, and an upper electrode that covers the organic layer. The organic layer includes functional layers such as a hole transport layer and an electron transport layer in addition to a light-emitting layer. There is a demand for reducing the manufacturing costs of display devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device and a method for manufacturing a display device that can reduce manufacturing costs. [Means for solving the problem]

[0005] According to one embodiment, a method for manufacturing a display device includes the steps of: a process substrate on which a lower electrode is formed above a substrate, an inorganic insulating layer having an opening overlapping with the lower electrode is formed, and a partition including a lower portion located on the inorganic insulating layer and an upper portion located on the lower portion and protruding from a side surface of the lower portion is formed, an organic layer including a light-emitting layer is formed on the lower electrode in the opening, an upper electrode is formed on the organic layer, a cap layer is formed on the upper electrode, a first sealing layer is formed to cover the cap layer and the partition, and a resin layer is formed to cover the first sealing layer; the steps of forming the organic layer, the upper electrode, and the cap layer are deposition steps using the partition as a mask in a vacuum environment, and the step of forming the resin layer includes a step of applying a resin material in an atmospheric atmosphere.

[0006] According to one embodiment, the display device comprises: a substrate; a lower electrode disposed above the substrate; an inorganic insulating layer having an opening overlapping the lower electrode; an organic layer disposed on the lower electrode at the opening and including an emitting layer; an upper electrode disposed on the organic layer; a cap layer disposed on the upper electrode; a lower portion disposed on the inorganic insulating layer and in contact with the upper electrode and formed of a conductive material; and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion, the substrate comprising: a partition surrounding the organic layer, the upper electrode, and the cap layer; and a first sealing layer disposed on the cap layer surrounded by the partition, in contact with the side surface of the partition, and formed of an inorganic insulating material, the first sealing layer extending above the partition and spaced apart from the upper portion of the partition. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. [Diagram 2] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG. [Figure 4] FIG. 4 is a diagram showing an example of a configuration of the display element 20. As shown in FIG. [Diagram 5] FIG. 5 is a diagram for explaining an outline of the manufacturing apparatus. [Figure 6A] FIG. 6A is a diagram showing an example of a configuration of the vapor deposition apparatus 100 shown in FIG. [Figure 6B] FIG. 6B is a diagram showing another configuration example of the vapor deposition apparatus 100 shown in FIG. [Figure 7] FIG. 7 is a flowchart for explaining a method of manufacturing the display device DSP. [Figure 8] FIG. 8 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 9] FIG. 9 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 10] FIG. 10 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 11] FIG. 11 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 12] FIG. 12 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 13] FIG. 13 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 14] FIG. 14 is a diagram for explaining a manufacturing method of the display device DSP. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0009] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Viewing various elements parallel to the third direction Z is called a planar view.

[0010] The display device according to this embodiment is an organic electroluminescence display device having an organic light emitting diode (OLED) as a display element, and can be mounted on televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0011] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA, on an insulating substrate 10. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. The pixels PX include a plurality of subpixels SP. In one example, the pixel PX includes a subpixel SP1 of a first color, a subpixel SP2 of a second color, and a subpixel SP3 of a third color. The first color, the second color, and the third color are different from each other. The pixel PX may include a subpixel SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0014] The subpixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0015] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20.

[0016] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0017] The display element 20 is an organic light-emitting diode (OLED) as a light-emitting element, and may be called an organic EL element.

[0018] Although not described in detail, terminals for connecting an IC chip and a flexible printed circuit board are provided in the peripheral area SA.

[0019] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. 2, the subpixels SP2 and SP3 are aligned in the second direction Y. The subpixels SP1 and SP2 are aligned in the first direction X, and the subpixels SP1 and SP3 are aligned in the first direction X.

[0020] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y, and a column in which a plurality of subpixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0021] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0022] In the display region DA, an inorganic insulating layer 5 and a partition wall 6 are disposed. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib. The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6 has openings in the subpixels SP1, SP2, and SP3, similar to the inorganic insulating layer 5.

[0023] The sub-pixels SP1, SP2, and SP3 include display elements 201, 202, and 203 as the display element 20, respectively.

[0024] The display element 201 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each of which overlaps with the aperture AP1. The peripheral portion of the lower electrode LE1 is covered with an inorganic insulating layer 5. The display element 201 including the lower electrode LE1, the organic layer OR1, and the upper electrode UE1 is surrounded by a partition wall 6 in a planar view. The peripheral portions of each of the organic layer OR1 and the upper electrode UE1 overlap the inorganic insulating layer 5 in a planar view. The organic layer OR1 includes a light-emitting layer that emits light in, for example, a blue wavelength region.

[0025] The display element 202 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the aperture AP2. The peripheral portion of the lower electrode LE2 is covered with an inorganic insulating layer 5. The display element 202, which includes the lower electrode LE2, the organic layer OR2, and the upper electrode UE2, is surrounded by a partition wall 6 in a planar view. The peripheral portions of each of the organic layer OR2 and the upper electrode UE2 overlap the inorganic insulating layer 5 in a planar view. The organic layer OR2 includes a light-emitting layer that emits light in, for example, a green wavelength region.

[0026] The display element 203 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each of which overlaps with the aperture AP3. The peripheral portion of the lower electrode LE3 is covered with an inorganic insulating layer 5. The display element 203 including the lower electrode LE3, the organic layer OR3, and the upper electrode UE3 is surrounded by a partition wall 6 in a planar view. The peripheral portions of each of the organic layer OR3 and the upper electrode UE3 overlap the inorganic insulating layer 5 in a planar view. The organic layer OR3 includes a light-emitting layer that emits light in, for example, a red wavelength region.

[0027] 2, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes shown in the figure do not necessarily reflect the exact shapes.

[0028] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of display elements, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes of display elements or a common electrode.

[0029] The lower electrode LE1 is connected to the pixel circuit 1 of the subpixel SP1 (see FIG. 1) through a contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the subpixel SP2 through a contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the subpixel SP3 through a contact hole CH3.

[0030] 2, the areas of the openings AP1, AP2, and AP3 are different from one another. The area of ​​the openings AP1 is larger than the area of ​​the openings AP2, and the area of ​​the openings AP2 is larger than the area of ​​the openings AP3. In other words, the area of ​​the lower electrode LE1 exposed from the opening AP1 is larger than the area of ​​the lower electrode LE2 exposed from the opening AP2, and the area of ​​the lower electrode LE2 exposed from the opening AP2 is larger than the area of ​​the lower electrode LE3 exposed from the opening AP3.

[0031] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG.

[0032] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Fig. 1, and various wirings such as the scanning line GL, the signal line SL, and the power supply line PL. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is an organic insulating layer that flattens unevenness caused by the circuit layer 11.

[0033] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and are spaced apart from each other. The inorganic insulating layer 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The opening AP1 of the inorganic insulating layer 5 overlaps the lower electrode LE1, the opening AP2 overlaps the lower electrode LE2, and the opening AP3 overlaps the lower electrode LE3. The periphery of the lower electrodes LE1, LE2, and LE3 is covered with the inorganic insulating layer 5. Between the lower electrodes LE1, LE2, and LE3 adjacent to each other, the insulating layer 12 is covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3 through contact holes provided in the insulating layer 12. The contact holes in the insulating layer 12 are omitted in FIG. 3, but correspond to CH1, CH2, and CH3 in FIG. 2.

[0034] The partition 6 includes a conductive lower portion (stem) 61 disposed on the inorganic insulating layer 5, and an upper portion (cap) 62 disposed on the lower portion 61. The lower portion 61 of the partition 6 shown on the right side of the figure is located between the opening AP1 and the opening AP2. The lower portion 61 of the partition 6 shown on the left side of the figure is located between the opening AP2 and the opening AP3. The upper portion 62 has a width greater than that of the lower portion 61. Both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition 6 is called an overhang shape.

[0035] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has a peripheral portion located on the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower portion 61.

[0036] The organic layer OR2 is in contact with the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has a peripheral portion located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower portion 61.

[0037] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has a peripheral portion located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower portion 61.

[0038] 3, the subpixel SP1 has a cap layer CP1 and a sealing layer SE1, the subpixel SP2 has a cap layer CP2 and a sealing layer SE2, and the subpixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 function as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0039] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP2 is disposed on the upper electrode UE2. The cap layer CP3 is disposed on the upper electrode UE3.

[0040] The sealing layer SE1 is disposed on the cap layer CP1, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP1. The sealing layer SE2 is disposed on the cap layer CP2, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP2. The sealing layer SE3 is disposed on the cap layer CP3, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP3.

[0041] The sealing layers SE1, SE2, and SE3 all extend above the partition wall 6 and are spaced apart from an upper portion 62 of the partition wall 6. That is, a gap GP is formed between the sealing layers SE1, SE2, and SE3 and the upper portion 62. Ends of the sealing layers SE1, SE2, and SE3 are spaced apart from the upper portion 62. That is, the gap GP is open below each end of the sealing layers SE1, SE2, and SE3.

[0042] Parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 may be located on the partition wall 6 around the subpixel SP1. However, these parts are separated from the parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 that are located in the aperture AP1 (parts that form the display element 201). Similarly, portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 may be located on the partition 6 surrounding the subpixel SP2, but these portions are spaced apart from the portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 that are located in the opening AP2 (the portions that constitute the display element 202). Similarly, portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 may be located on the partition 6 surrounding the subpixel SP3, but these portions are spaced apart from the portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 that are located in the opening AP3 (the portions that constitute the display element 203).

[0043] Ends of the sealing layers SE1, SE2, and SE3 are located on the partition wall 6. In the example of Fig. 3, the ends of the sealing layers SE1 and SE2 located on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart, and the ends of the sealing layers SE2 and SE3 located on the partition wall 6 between the subpixels SP2 and SP3 are spaced apart.

[0044] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is filled in a gap GP surrounded by the upper portion 62 of the partition wall 6 and the sealing layer SE1, a gap GP surrounded by the upper portion 62 and the sealing layer SE2, and a gap GP surrounded by the upper portion 62 and the sealing layer SE3. Note that there may be cases where the gap GP is not completely filled with the resin layer 13, and a void exists in part of the gap GP. The resin layer 13 is covered with a sealing layer 14 . The sealing layer 14 is disposed on the overcoat layer 15 .

[0045] The inorganic insulating layer 5, the sealing layers SE1, SE2, SE3, and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). The resin layer 13 and the overcoat layer 15 are made of the same resin material.

[0046] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may be formed of an insulating material. The lower portion 61 and the upper portion 62 are formed of a material different from each other.

[0047] The lower electrodes LE1, LE2, and LE3 are, for example, multilayer bodies including a transparent electrode made of an oxide conductive material such as indium tin oxide (ITO) and a metal electrode made of a metal material such as silver.

[0048] The organic layer OR1 includes an emitting layer EM1. The organic layer OR2 includes an emitting layer EM2. The organic layer OR3 includes an emitting layer EM3. The emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the emitting layer EM1 is formed of a material that emits light in a blue wavelength range, the emitting layer EM2 is formed of a material that emits light in a green wavelength range, and the emitting layer EM3 is formed of a material that emits light in a red wavelength range. In addition, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers, such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0049] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0050] The cap layers CP1, CP2, and CP3 are multilayer structures made up of a plurality of thin films, all of which are transparent and have different refractive indices.

[0051] In the above configuration example, for example, the sealing layer SE1 corresponds to the first sealing layer, and the sealing layer 14 corresponds to the second sealing layer.

[0052] Next, a configuration example of the display element 20 will be described.

[0053] FIG. 4 is a diagram showing an example of a configuration of the display element 20. As shown in FIG. The display element 20 shown in FIG. 4 may correspond to any of the display elements 201, 202, and 203 described above. In this example, the lower electrode LE corresponds to the anode, and the upper electrode UE corresponds to the cathode.

[0054] The display element 20 includes organic layers OR (OR1, OR2, OR3) between a lower electrode LE (LE1, LE2, LE3) and an upper electrode UE (UE1, UE2, UE3).

[0055] In the organic layer OR, a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, an emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are laminated in this order. In addition to the above-mentioned functional layers, the organic layer OR may include other functional layers such as a carrier generating layer as necessary, or at least one of the above-mentioned functional layers may be omitted.

[0056] The emitting layer EML corresponds to any one of the emitting layers EM1, EM2, and EM3 shown in FIG.

[0057] The cap layer CP (CP1, CP2, CP3) includes a first transparent layer TL1 and a second transparent layer TL2. The first transparent layer TL1 is disposed on the upper electrode UE. The first transparent layer TL1 is a high-refractive index layer having a refractive index higher than that of the upper electrode UE. The second transparent layer TL2 is disposed on the first transparent layer TL1. The second transparent layer TL2 is a low-refractive index layer having a refractive index lower than that of the first transparent layer TL1. The sealing layer SE (SE1, SE2, SE3) is disposed on the second transparent layer TL2. The cap layer CP may be omitted.

[0058] The configuration of the organic layer OR is not limited to the configuration in which the organic layer OR includes one emitting layer EML as shown in the figure, but may include a plurality of emitting layers.

[0059] Next, an apparatus for manufacturing the display device DSP will be briefly described.

[0060] FIG. 5 is a diagram for explaining an outline of the manufacturing apparatus.

[0061] The substrate stocker 200 stores a plurality of processing substrates under an atmospheric condition. The processing substrate here is a mother substrate for a display device, and is a large substrate having a plurality of panel units. Each of the panel units is extracted by cutting the processing substrate. Each of the extracted panel units corresponds to the display panel PNL shown in FIG. 1, and has a display area DA and a peripheral area SA.

[0062] The in-line deposition apparatus 100 includes a pretreatment section 101, a heating section 102, and a deposition section 103. The deposition apparatus 100, which will be described in detail later, is configured to form a deposition layer on a substrate to be processed in a high vacuum environment.

[0063] The CVD (Chemical Vapor Deposition) apparatus 210 is configured to deposit an inorganic insulating material on a processing substrate in a vacuum environment to form the sealing layers SE1, SE2, SE3, and the sealing layer 14. Note that the degree of vacuum of the CVD apparatus 210 may be lower than the degree of vacuum of the deposition apparatus 100.

[0064] The resist forming device 220 is configured to form a resist having a predetermined shape on the sealing layers SE1, SE2, and SE3 under the atmospheric air.

[0065] The wet etching apparatus 230 is configured to remove a portion of the deposition layer using a resist as a mask in an air atmosphere.

[0066] The dry etching apparatus 240 is configured to remove a part of the deposition layer, a part of the sealing layers SE1, SE2, SE3, and a part of the sealing layer 14 using a resist as a mask under a vacuum environment. Note that the degree of vacuum of the dry etching apparatus 240 may be lower than the degree of vacuum of the deposition apparatus 100.

[0067] The resin forming apparatus 250 is configured to form the resin layer 13 and the overcoat layer 15. The resin forming apparatus 250 includes an application apparatus 251, a drying apparatus 252, and a curing apparatus 253. The application apparatus 251 is configured to apply a resin material in an atmospheric environment. The drying apparatus 252 is configured to dry the resin material in a low vacuum environment that is reduced in pressure below the atmospheric atmosphere. The drying apparatus 252 may be omitted. The curing apparatus 253 is configured to perform a curing process of the resin material. As an example, when the resin material is an ultraviolet curing resin material, the curing apparatus 253 is configured to irradiate the resin material with ultraviolet rays.

[0068] The deposition apparatus 100, the CVD apparatus 210, the resist formation apparatus 220, the wet etching apparatus 230, the dry etching apparatus 240, and the resin formation apparatus 250 are each connected to a substrate stocker 200 via a transport mechanism not described in detail.

[0069] FIG. 6A is a diagram showing an example of a configuration of the vapor deposition apparatus 100 shown in FIG.

[0070] The deposition apparatus 100 is used, for example, in a process of successively forming an organic layer OR, an upper electrode UE, and a cap layer CP shown in Fig. 4. A process substrate SUB carried into the deposition apparatus 100 has, on a substrate 10, a circuit layer 11, an insulating layer 12, lower electrodes LE1, LE2, and LE3, an inorganic insulating layer 5, and a partition wall 6.

[0071] The deposition apparatus 100 includes a pretreatment section 101, a heating section 102, and a deposition section 103. The deposition apparatus 100 is connected to a substrate stocker 200 via a transport mechanism, which will not be described in detail. The deposition apparatus 100 also includes a posture changing section 104 as a part of the transport mechanism.

[0072] The pretreatment section 101 includes a mechanism for performing various pretreatments, such as plasma treatment, on the substrate SUB that is carried in. The heating section 102 includes a mechanism for performing heat treatment on the substrate SUB.

[0073] The attitude conversion unit 104 includes a mechanism for converting the attitude of the processing substrate SUB, a mechanism for fixing the processing substrate SUB to a dedicated carrier by an electrostatic chuck, and a mechanism for releasing the fixing by the electrostatic chuck and removing the processing substrate SUB from the carrier. In one example, the attitude of the processing substrate SUB carried into the pre-treatment unit 101 and the heating unit 102 is horizontal. The attitude of the processing substrate SUB carried out from the pre-treatment unit 101 and the heating unit 102 is converted from the horizontal attitude to a vertical attitude in the attitude conversion unit 104. The attitude of the processing substrate SUB carried into the deposition unit 103 is vertical. The attitude of the processing substrate SUB carried out from the deposition unit 103 is converted from the vertical attitude to a horizontal attitude in the attitude conversion unit 104.

[0074] The deposition unit 103 includes a plurality of deposition chambers EV11 to EV20 and a rotation chamber R11. The pre-treatment unit 101, the heating unit 102, the attitude changing unit 104, the plurality of deposition chambers EV11 to EV20, and the rotation chamber R11 are connected to each other and maintained at a high vacuum.

[0075] The deposition chambers EV11 to EV15 are arranged in a row. The deposition chamber EV11 is connected to the attitude changing unit 104. The deposition chamber EV15 is connected to the rotation chamber R11. The transport path T11 is provided across the deposition chambers EV11 to EV15.

[0076] The deposition chambers EV16 to EV20 are arranged in a row. The deposition chamber EV16 is connected to the rotation chamber R11. The deposition chamber EV20 is connected to the attitude changing unit 104. The transport path T12 is provided across the deposition chambers EV16 to EV20.

[0077] The deposition chamber EV11 includes a deposition source S11. The deposition source S11 is configured to irradiate a material for forming the hole injection layer HIL toward the transport path T11. The deposition chamber EV12 includes a deposition source S12. The deposition source S12 is configured to irradiate a material for forming the hole transport layer HTL toward the transport path T11. The deposition chamber EV13 includes a deposition source S13. The deposition source S13 is configured to irradiate a material for forming the electron blocking layer EBL toward the transport path T11. The deposition chamber EV14 includes a deposition source S14. The deposition source S14 is configured to irradiate a material for forming the emitting layer EML toward the transfer path T11. The deposition chamber EV15 includes a deposition source S15. The deposition source S15 is configured to irradiate a material for forming the hole blocking layer HBL toward the transport path T11.

[0078] The deposition chamber EV16 includes a deposition source S16. The deposition source S16 is configured to irradiate a material for forming the electron transport layer ETL toward the transport path T12. The deposition chamber EV17 includes a deposition source S17. The deposition source S17 is configured to irradiate a material for forming the electron injection layer EIL toward the transport path T12. The deposition chamber EV18 includes a deposition source S18. The deposition source S18 is configured to irradiate a material for forming the upper electrode UE toward the transfer path T12. The deposition chamber EV19 includes a deposition source S19. The deposition source S19 is configured to irradiate a material for forming the first transparent layer TL1 toward the transfer path T12. The deposition chamber EV20 includes a deposition source S20. The deposition source S20 is configured to irradiate a material for forming the second transparent layer TL2 toward the transfer path T12.

[0079] The rotation chamber R11 is configured to transport the processing substrate SUB transported from the transport path T11 to the transport path T12. The rotation chamber R11 includes a rotation mechanism RM11. The rotation mechanism RM11 is configured to hold the processing substrate SUB transported through the transport path T11 and to be rotatable about a rotation axis A11.

[0080] The configuration of the vapor deposition apparatus 100 is not limited to the example shown in the figure.

[0081] FIG. 6B is a diagram showing another configuration example of the vapor deposition apparatus 100 shown in FIG.

[0082] The configuration example shown in FIG. 6B differs from the configuration example shown in FIG. 6A in that deposition chambers for forming the light emitting layers EM1, EM2, and EM3 are provided.

[0083] In the deposition section 103 of the deposition apparatus 100, deposition chambers EV11, EV12, EV13, EV141, EV142, and EV143 are arranged in a row. The deposition chamber EV11 is connected to the attitude changing section 104. The deposition chamber EV143 is connected to the rotation chamber R11. The deposition chambers EV15 to EV20 are arranged in a row. The deposition chamber EV15 is connected to the rotation chamber R11. The deposition chamber EV20 is connected to the attitude changing unit 104.

[0084] The deposition source S11 of the deposition chamber EV11 is configured to emit a material for forming the hole injection layer HIL. The deposition source S12 of the deposition chamber EV12 is configured to emit a material for forming the hole transport layer HTL. The deposition source S13 in the deposition chamber EV13 is configured to emit a material for forming the electron blocking layer EBL.

[0085] The deposition source S141 of the deposition chamber EV141 is configured to emit a material for forming the light-emitting layer EM1. The deposition source S142 of the deposition chamber EV142 is configured to emit a material for forming the light-emitting layer EM2. The deposition source S143 of the deposition chamber EV143 is configured to emit a material for forming the light-emitting layer EM3. The materials emitted from the deposition sources S141, S142, and S143 are luminescent materials that emit different colors.

[0086] The deposition source S15 of the deposition chamber EV15 is configured to emit a material for forming the hole blocking layer HBL.

[0087] The deposition source S16 in the deposition chamber EV16 is configured to emit a material for forming the electron transport layer ETL. The deposition source S17 of the deposition chamber EV17 is configured to emit a material for forming the electron injection layer EIL.

[0088] The deposition source S18 of the deposition chamber EV18 is configured to emit a material for forming the upper electrode UE. The deposition source S19 of the deposition chamber EV19 is configured to emit a material for forming the first transparent layer TL1. The deposition source S20 of the deposition chamber EV20 is configured to emit a material for forming the second transparent layer TL2.

[0089] In such a deposition apparatus 100, when a display element 201 is formed, the processing substrate SUB is transported in a vertical position, and materials are sequentially deposited in the deposition chambers EV11, EV12, EV13, and EV141. Thereafter, the processing substrate SUB is transported in the deposition chambers EV142 and EV143 without any material being deposited thereon. Thereafter, materials are sequentially deposited in the deposition chambers EV15 to EV20.

[0090] When forming the display element 202, the processing substrate SUB is transported in a vertical position while each material is sequentially deposited in the deposition chambers EV11, EV12, and EV13. Then, in the deposition chamber EV141, the processing substrate SUB is transported without the material being deposited thereon. Then, in the deposition chamber EV142, the material is deposited thereon. Then, in the deposition chamber EV143, the processing substrate SUB is transported without the material being deposited thereon. Then, in the deposition chambers EV15 to EV20, each material is sequentially deposited thereon.

[0091] When forming the display element 203, the materials are sequentially deposited in the deposition chambers EV11, EV12, and EV13 while the processing substrate SUB is transported in a vertical position. Thereafter, in the deposition chambers EV141 and EV142, the processing substrate SUB is transported without the materials being deposited thereon. Thereafter, in the deposition chambers EV143, and EV15 to EV20, the materials are sequentially deposited.

[0092] In each of the configuration examples shown in FIGS. 6A and 6B, the deposition unit 103 includes a rotation chamber R11 and is configured to transport the processing substrate SUB in a turn-around manner, but the present invention is not limited to this.

[0093] The deposition device 103 may be configured to omit the rotation chamber R11 and transport the processing substrate SUB in one direction. In this case, for example, in the configuration example shown in Fig. 6A, the deposition chambers EV11, EV12, EV13, EV14, EV15, EV16, EV17, EV18, EV19, and EV20 are lined up in this order along one direction. Also, in the configuration example shown in Fig. 6B, the deposition chambers EV11, EV12, EV13, EV141, EV142, EV143, EV15, EV16, EV17, EV18, EV19, and EV20 are lined up in this order along one direction.

[0094] Next, a method for manufacturing the display device DSP will be described with reference to the flowchart shown in Fig. 7 and the cross-sectional views shown in Fig. 8 to Fig. 14. Note that in Fig. 8 to Fig. 14, the part below the insulating layer 12 is not shown.

[0095] First, a process substrate SUB is prepared (ST1). The process of preparing the process substrate SUB includes the steps of forming, on an insulating layer 12, a lower electrode LE1 of the subpixel SP1, a lower electrode LE2 of the subpixel SP2, and a lower electrode LE3 of the subpixel SP3, forming an inorganic insulating layer 5 having openings AP1, AP2, and AP3 overlapping with the lower electrodes LE1, LE2, and LE3, respectively, and forming a partition wall 6 having a lower portion 61 located on the inorganic insulating layer 5 and an upper portion 62 located on the lower portion 61 and protruding from a side surface of the lower portion 61. The partition wall 6 may be formed after forming the inorganic insulating layer 5 having the openings AP1, AP2, and AP3, or the openings AP1, AP2, and AP3 may be formed after forming the partition wall 6. FIG. 8 shows a cross section of the prepared substrate to be processed SUB.

[0096] Next, the display element 201 is formed.

[0097] First, the processing substrate SUB is carried into the deposition apparatus 100, and a predetermined pre-processing is performed on the processing substrate SUB in the pre-processing section 101 (ST11). Thereafter, if necessary, the processing substrate SUB is subjected to a heating process in the heating section 102, the processing substrate SUB is converted to a vertical posture in the posture conversion section 104, and the processing substrate SUB is carried into the deposition section 103.

[0098] Then, in the deposition section 103, deposition is performed using the partition wall 6 as a mask to form a first deposition layer on the processing substrate SUB (ST12). That is, a hole injection layer HIL is formed on the lower electrode LE1 in the deposition chamber EV11, a hole transport layer HTL is formed on the hole injection layer HIL in the deposition chamber EV12, an electron block layer EBL is formed on the hole transport layer HTL in the deposition chamber EV13, an emitting layer EML is formed on the electron block layer EBL in the deposition chamber EV14, a hole block layer HBL is formed on the emitting layer EML in the deposition chamber EV15, an electron transport layer ETL is formed on the hole block layer HBL in the deposition chamber EV16, and an electron injection layer EIL is formed on the electron transport layer ETL in the deposition chamber EV17. As a result, an organic layer OR1 including an emitting layer EM1 is formed on the lower electrode LE1. Then, an upper electrode UE is formed on the electron injection layer EIL in the deposition chamber EV18. As a result, an upper electrode UE1 is formed on the organic layer OR1. Then, the first transparent layer TL1 is formed on the upper electrode UE in the deposition chamber EV19, and the second transparent layer TL2 is formed on the first transparent layer TL1 in the deposition chamber EV20. In this way, the cap layer CP1 is formed on the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 correspond to a first deposition layer, and are successively formed in a deposition apparatus 100 under a vacuum environment.

[0099] Then, a sealing layer SE1 is formed on the first deposition layer (ST13). That is, the processing substrate SUB is carried out from the deposition section 103, the processing substrate SUB is changed to a horizontal position in the position changing section 104, and the processing substrate SUB is carried into the CVD apparatus 210. In the CVD apparatus 210, an inorganic insulating material is deposited on the processing substrate SUB. As a result, the sealing layer SE1 that continuously covers the cap layer CP1 and the partition wall 6 is formed.

[0100] FIG. 9 shows a cross section of the process substrate SUB on which the organic layer OR1, the upper electrode UE1, the cap layer CP1, and the sealing layer SE1 are formed.

[0101] The organic layer OR1, the upper electrode UE1, the cap layer CP1, and the sealing layer SE1 are formed at least in the entire display area DA, and are disposed not only in the subpixel SP1 but also in the subpixels SP2 and SP3. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are divided by an overhanging partition wall 6.

[0102] When the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by vapor deposition, materials emitted from the vapor deposition source are blocked by the upper part 62. For this reason, parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are laminated on the upper part 62. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 located on the upper part 62 are each spaced apart from the organic layer OR1, the upper electrode UE1, and the cap layer CP1 located immediately above the lower electrode LE1. The sealing layer SE1 covers the cap layer CP1 immediately above the partition wall 6, covers the cap layer CP1 immediately above the lower electrode LE1, and is in contact with the partition wall 6.

[0103] Next, a resist RS patterned into a predetermined shape is formed on the sealing layer SE1 (ST14). The resist RS is formed by a resist forming apparatus 220. FIG. 10 shows a cross section of the process substrate SUB on which the resist RS is formed. The resist RS overlaps the subpixel SP1 and a part of the partition wall 6 around it.

[0104] Next, patterning is performed using the resist RS as a mask (ST15). The patterning is performed in a wet etcher 230 and a dry etcher 240. By performing various etching processes using the resist RS as a mask, the sealing layer SE1, the cap layer CP1, the upper electrode UE1, and the organic layer OR1 exposed from the resist RS are sequentially removed. FIG. 11 shows a cross section of the process substrate SUB after patterning. By such patterning, the lower electrode LE2 of the subpixel SP2 and the lower electrode LE3 of the subpixel SP3 are exposed. In the illustrated example, the organic layer OR1, the upper electrode UE1, and the cap layer CP1 laminated on the partition wall 6 are removed during patterning. As a result, a gap GP is formed between the sealing layer SE1 and the partition wall 6.

[0105] Next, the resist RS is stripped (ST16), thereby forming the display element 201 in the subpixel SP1.

[0106] Next, the display element 202 is formed. The procedure for forming the display element 202 is the same as the procedure for forming the display element 201. That is, a pretreatment is performed on the processing substrate SUB on which the display element 201 is formed (ST21). Then, a second deposition layer is formed on the lower electrode LE2 (ST22). The second deposition layer has an organic layer OR2 including an emission layer EM2, an upper electrode UE2, and a cap layer CP2. Then, a sealing layer SE2 is formed (ST23). Then, a resist is formed on the sealing layer SE2 (ST24). Then, patterning is performed using this resist as a mask (ST25). As a result, the sealing layer SE2, the cap layer CP2, the upper electrode UE2, and the organic layer OR2 exposed from the resist are sequentially removed. Then, the resist is peeled off (ST26). FIG. 12 shows a cross section of the process substrate SUB after patterning. By such patterning, the display element 202 is formed in the subpixel SP2, and the lower electrode LE3 of the subpixel SP3 is exposed. In the illustrated example, the organic layer OR2, the upper electrode UE2, and the cap layer CP2 laminated on the partition wall 6 are removed during patterning, so that a gap GP is formed between the sealing layer SE2 and the partition wall 6.

[0107] Next, the display element 203 is formed. The procedure for forming the display element 203 is the same as the procedure for forming the display element 201. That is, a pretreatment is performed on the processing substrate SUB on which the display element 201 and the display element 202 are formed (ST31). Then, a third deposition layer is formed on the lower electrode LE3 (ST32). The third deposition layer has an organic layer OR3 including an emission layer EM3, an upper electrode UE3, and a cap layer CP3. Then, a sealing layer SE3 is formed (ST33). Then, a resist is formed on the sealing layer SE3 (ST34). Then, patterning is performed using this resist as a mask (ST35). As a result, the sealing layer SE3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3 exposed from the resist are sequentially removed. Then, the resist is peeled off (ST36). FIG. 13 shows a cross section of the process substrate SUB after patterning. By such patterning, a display element 203 is formed in the subpixel SP3. In the illustrated example, the organic layer OR3, the upper electrode UE3, and the cap layer CP3 laminated on the partition wall 6 are removed during patterning, so that a gap GP is formed between the sealing layer SE3 and the partition wall 6.

[0108] In the above manufacturing process, it is assumed that the display element 201 is formed first, then the display element 202 is formed, and finally the display element 203 is formed. However, the order of forming the display elements 201, 202, and 203 is not limited to this example.

[0109] Subsequently, the resin layer 13 is formed in the resin forming apparatus 250 .

[0110] First, the processing substrate SUB is carried into the coating apparatus 251. In the coating apparatus 251, a resin material is applied onto the sealing layers SE1, SE2, and SE3 in the air atmosphere (ST41). Then, the processing substrate SUB is carried into the drying device 252. In the drying device 252, an environment with a reduced pressure lower than the atmospheric pressure is maintained. By placing the processing substrate SUB in the reduced pressure environment, the dissipation of moisture from the resin material is promoted, and the resin material is dried (ST42). At the same time, the resin material is filled into the gap GP. Then, the process substrate SUB is carried into the curing device 253. Then, the resin material is irradiated with ultraviolet rays in the air (ST43). This causes the resin material to harden. Through these steps, the resin layer 13 is formed. Note that after the step of applying the resin material, the drying step (ST42) may be omitted and the resin material may be irradiated with ultraviolet rays. 14 shows a cross section of the process substrate SUB on which the resin layer 13 is formed. In the example shown, the resin layer 13 fills the gap GP, and no voids exist in the gap GP.

[0111] Then, the process substrate SUB is carried into the heating part 102 of the deposition apparatus 100. The process substrate SUB is heated in the heating part 102 (ST44). This removes moisture contained in the resin layer 13. Note that the heating step (ST44) may be omitted.

[0112] Then, the processing substrate SUB is carried into the CVD apparatus 210. In the CVD apparatus 210, an inorganic insulating material is deposited to form the sealing layer 14 that covers the resin layer 13 (ST45).

[0113] Then, the process substrate SUB is carried into the resin forming apparatus 250. In the resin forming apparatus 250, the overcoat layer 15 is formed on the sealing layer SE14 in the same manner as in forming the resin layer 13 (ST46).

[0114] Then, the processing substrate SUB is carried into the dry etching apparatus 240. In the dry etching apparatus 240, the sealing layer 14 is patterned using the overcoat layer 15 as a mask (ST47).

[0115] Through the above steps, the display device DSP is completed.

[0116] According to this embodiment, an overhanging partition wall 6 is provided at the boundary between the subpixels SP1, SP2, and SP3. Such a partition wall 6 surrounds the organic layers OR1, OR2, and OR3, the upper electrodes UE1, UE2, and UE3, and the cap layers CP1, CP2, and CP3 formed by vapor deposition. The display element 201 of the subpixel SP1, the display element 202 of the subpixel SP2, and the display element 203 of the subpixel SP3 are individually separated by the partition wall 6. The display elements 201, 202, and 203 thus separated are individually sealed by sealing layers SE1, SE2, and SE3, respectively. Therefore, even if a defect occurs in any of the display elements due to moisture infiltration, the infiltrated moisture is prevented from diffusing to the adjacent display elements.

[0117] Furthermore, in the structure in which the diffusion of moisture to adjacent display elements is suppressed as described above, the allowable moisture content of resin layer 13 can be increased compared to a structure (comparison example) in which the organic layer is not separated in adjacent display elements.

[0118] That is, in the comparative example, when a crack or the like occurs in the sealing layer, moisture seeps in through the crack and spreads across multiple display elements, damaging many of the display elements. For this reason, the resin layer covering the sealing layer is required to have an extremely low moisture content. For this reason, it is necessary to form the resin layer in a nitrogen atmosphere or clean dry air atmosphere with an extremely low moisture concentration. In one example, the moisture concentration allowed in the atmosphere in which the resin layer is formed in the comparative example is 100 ppm or less. Therefore, in the comparative example, equipment for generating a nitrogen atmosphere or clean dry air is required.

[0119] On the other hand, in this embodiment, the resin layer 13 covering the sealing layers SE1, SE2, and SE3 is allowed to have a large water content. Therefore, the process of applying a resin material to form the resin layer 13 can be performed in an air atmosphere. In one example, the process of applying a resin material can be performed in an air atmosphere in a clean room where the temperature is in the range of 20° C. to 30° C., the humidity is in the range of 40% to 70%, and the oxygen concentration is adjusted to a range of 20% or more. Therefore, equipment for generating an atmosphere with an extremely low water concentration is not required. In addition, the resin layer 13 can be shared with an equipment for forming the overcoat layer 15. Therefore, the manufacturing cost can be reduced. In addition, the scale of the manufacturing equipment can be reduced, and the installation area of ​​the equipment can be reduced.

[0120] Furthermore, after the resin material is applied, a process of drying the resin material under reduced pressure can be added before the resin material is cured. In one example, the reduced pressure drying conditions are a pressure in the range of 100 to 1000 Pa and a drying time in the range of 10 to 150 seconds. This allows the resin material to be filled into the gap GP at the same time as drying the resin material, making it possible to suppress the formation of voids (air bubbles) in the gap GP. Note that if the viscosity of the resin material to be applied is low and the resin material can be sufficiently filled into the gap GP at the stage of application, the reduced pressure drying process may be omitted.

[0121] If there is a concern that the resin material applied under the air atmosphere contains a large amount of moisture, a step of heating the processing substrate SUB can be added after the resin layer is formed. In one example, the heating conditions are a temperature in the range of 90 to 120°C, a pressure in the range of 1000 Pa or less, and a time in the range of 3 to 60 minutes. This can promote dehydration from the resin layer 13. In addition, since the heating step can utilize the existing equipment (heating unit 102) provided in the deposition device 100, there is no need to add a new heating device. This prevents an increase in manufacturing costs. Note that if the moisture content of the resin material is sufficiently low, the heating step may be omitted.

[0122] As described above, according to the present embodiment, it is possible to provide a display device and a method for manufacturing a display device that can reduce manufacturing costs.

[0123] All display devices and manufacturing methods thereof that can be implemented by a person skilled in the art through appropriate design modifications based on the display device and manufacturing method thereof described above as embodiments of the present invention are within the scope of the present invention as long as they include the gist of the present invention.

[0124] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0125] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0126] DSP…display device 10…board 5...Inorganic insulating layer AP1, AP2, AP3...Openings 6...Bulkhead 61...Lower 62...Upper SP1, SP2, SP3...Subpixels 20, 201, 202, 203...Display element (organic EL element) LE, LE1, LE2, LE3...lower electrode UE, UE1, UE2, UE3...upper electrode OR, OR1, OR2, OR3…Organic layer 100...Vapor deposition equipment 250: Resin forming device, 251: Coating device, 252: Drying device, 253: Hardening device

Claims

1. preparing a processing substrate on which a partition wall is formed, the partition wall including a lower portion located on the inorganic insulating layer and an upper portion located on the lower portion and protruding from a side surface of the lower portion; forming an organic layer including a light-emitting layer on the lower electrode in the opening; forming an upper electrode on the organic layer; forming a cap layer on the upper electrode; forming a first sealing layer covering the cap layer and the partition wall; forming a resin layer covering the first sealing layer; the step of forming the organic layer, the upper electrode, and the cap layer is a deposition step using the partition wall as a mask in a vacuum environment; The method for manufacturing a display device, wherein the step of forming the resin layer includes a step of applying a resin material in an air atmosphere.

2. The method for manufacturing a display device according to claim 1 , wherein the step of forming the resin layer includes a step of drying the resin material in an environment with a reduced pressure lower than the atmospheric atmosphere after the step of applying the resin material.

3. The method for manufacturing a display device according to claim 2 , wherein the step of forming the resin layer includes the step of irradiating the resin material with ultraviolet light in an air atmosphere after the step of drying the resin material.

4. The method for manufacturing a display device according to claim 1 , wherein the step of forming the resin layer includes a step of irradiating the resin material with ultraviolet light in an air atmosphere.

5. The method for manufacturing a display device according to claim 3 , further comprising the step of heating the processing substrate after forming the resin layer.

6. Furthermore, a second sealing layer is formed to cover the resin layer, The method for manufacturing a display device according to claim 4 , further comprising forming an overcoat layer on the second sealing layer.

7. 2. The method for manufacturing a display device according to claim 1, wherein the step of applying the resin material is carried out in an atmospheric condition adjusted to a temperature in the range of 20° C. to 30° C., a humidity in the range of 40% to 70%, and an oxygen concentration in the range of 20% or more.

8. forming a patterned resist on the first sealing layer before forming the resin layer; The method for manufacturing a display device according to claim 1 , further comprising the steps of: sequentially removing the first sealing layer, the cap layer, the upper electrode, and the organic layer exposed from the resist by etching.

9. A substrate; a lower electrode disposed above the substrate; an inorganic insulating layer having an opening overlapping the lower electrode; an organic layer disposed on the lower electrode in the opening, the organic layer including a light-emitting layer; an upper electrode disposed over the organic layer; a cap layer disposed on the upper electrode; a partition wall including a lower portion disposed on the inorganic insulating layer and in contact with the upper electrode and made of a conductive material, and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion, the partition wall surrounding the organic layer, the upper electrode, and the cap layer; a first sealing layer that is disposed on the cap layer surrounded by the partition wall, in contact with the side surface of the partition wall, and is formed of an inorganic insulating material; The first sealing layer extends above the partition wall and is spaced apart from the upper portion of the partition wall.

10. Further, a resin layer covering the first sealing layer is provided, The display device according to claim 9 , wherein the resin layer is filled in a gap surrounded by the upper portion and the first sealing layer.

11. a second sealing layer covering the resin layer and made of an inorganic insulating material; The display device according to claim 10 , further comprising: an overcoat layer disposed on the second sealing layer.

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