Display device and manufacturing method of display device

Abstract

To provide a display device and a manufacturing method of a display device, capable of preventing a reduction in reliability.SOLUTION: A display device includes: a substrate; an organic insulating layer arranged above the substrate; a lower electrode arranged on the organic insulating layer; a planarization layer which is arranged on the organic insulating layer and is in contact with a side surface of the lower electrode; an inorganic insulating layer which covers the planarization layer and covers a peripheral portion of the lower electrode; a partition which has a lower portion that is arranged on the inorganic insulating layer and that is formed of a conductive material and an upper portion that is arranged on the lower portion and that protrudes from a side surface of the lower portion; an organic layer which is surrounded by the partition, is arranged on the lower electrode, and includes a light emitting layer; and an upper electrode which is surrounded by the partition, is arranged on the organic layer, and is in contact with the lower portion of the partition.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a display device and a method for manufacturing a display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have been put to practical use. This display element includes a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer that covers the lower electrode, and an upper electrode that covers the organic layer. The organic layer includes functional layers such as a hole transport layer and an electron transport layer in addition to a light-emitting layer. There is a need for a technique for suppressing deterioration in reliability of display elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device and a method for manufacturing the display device that can suppress a decrease in reliability. [Means for solving the problem]

[0005] According to one embodiment, the display device comprises: the organic insulating layer disposed above the substrate; a lower electrode disposed on the organic insulating layer; a planarization layer disposed on the organic insulating layer and in contact with a side surface of the lower electrode; an inorganic insulating layer covering the planarization layer and covering a peripheral portion of the lower electrode; a partition having a lower portion disposed on the inorganic insulating layer and formed of a conductive material, and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion; an organic layer surrounded by the partition and disposed on the lower electrode, the organic layer including a light-emitting layer; and an upper electrode surrounded by the partition, the organic layer, and in contact with the lower portion of the partition.

[0006] According to one embodiment, a method for manufacturing a display device includes the steps of: forming an organic insulating layer above a substrate, forming a lower electrode on the organic insulating layer, applying a positive photosensitive resin covering the organic insulating layer and the lower electrode, patterning the photosensitive resin to form a planarization layer in contact with a side surface of the lower electrode, forming an inorganic insulating layer covering the planarization layer and covering a peripheral portion of the lower electrode, forming a partition having a lower portion located on the inorganic insulating layer and formed of a conductive material, and an upper portion located on the lower portion and protruding from a side surface of the lower portion, forming an organic layer including a light-emitting layer on the lower electrode by deposition using the partition as a mask, and forming an upper electrode located on the organic layer and in contact with the lower portion of the partition by deposition using the partition as a mask. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. [Diagram 2] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG. [Figure 4]FIG. 4 is a plan view showing an example of the planarizing layer 13. As shown in FIG. [Diagram 5] FIG. 5 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 6] FIG. 6 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 7] FIG. 7 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 8] FIG. 8 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 9] FIG. 9 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 10] FIG. 10 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 11] FIG. 11 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 12] FIG. 12 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 13] FIG. 13 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 14] FIG. 14 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 15] FIG. 15 is a diagram for explaining one method for forming the flattening layer 13. As shown in FIG. [Figure 16] FIG. 16 is a diagram for explaining another method for forming the flattening layer 13. In FIG. [Figure 17] FIG. 17 is a diagram for explaining another method for forming the flattening layer 13. In FIG. [Figure 18] FIG. 18 is a diagram showing an example of the cross-sectional shape of the planarizing layer 13. As shown in FIG. [Figure 19] FIG. 19 is a diagram showing another example of the cross-sectional shape of the planarizing layer 13. In FIG. [Figure 20] FIG. 20 is a diagram for explaining a process of selectively forming the flattening layer 13 in the display area DA. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0009] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Viewing various elements parallel to the third direction Z is called a planar view.

[0010] The display device according to this embodiment is an organic electroluminescence display device having an organic light emitting diode (OLED) as a display element, and can be mounted on televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0011] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA, on an insulating substrate 10. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. The pixels PX include a plurality of subpixels SP. In one example, the pixel PX includes a subpixel SP1 of a first color, a subpixel SP2 of a second color, and a subpixel SP3 of a third color. The first color, the second color, and the third color are different from each other. The pixel PX may include a subpixel SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0014] The subpixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0015] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20.

[0016] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0017] The display element 20 is an organic light-emitting diode (OLED) as a light-emitting element, and may be called an organic EL element.

[0018] The peripheral area SA is provided with terminals TE for connecting an IC chip or a flexible printed circuit board.

[0019] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. 2, the subpixels SP2 and SP3 are aligned in the second direction Y. The subpixels SP1 and SP2 are aligned in the first direction X, and the subpixels SP1 and SP3 are aligned in the first direction X.

[0020] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y, and a column in which a plurality of subpixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0021] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0022] In the display region DA, an inorganic insulating layer 5 and a partition wall 6 are disposed. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib. The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6 has openings in the subpixels SP1, SP2, and SP3, similar to the inorganic insulating layer 5.

[0023] The sub-pixels SP1, SP2, and SP3 include display elements 201, 202, and 203 as the display element 20, respectively.

[0024] The display element 201 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each of which overlaps with the aperture AP1. The peripheral portion of the lower electrode LE1 is covered with an inorganic insulating layer 5. The display element 201 including the lower electrode LE1, the organic layer OR1, and the upper electrode UE1 is surrounded by a partition wall 6 in a planar view. The peripheral portions of each of the organic layer OR1 and the upper electrode UE1 overlap the inorganic insulating layer 5 in a planar view. The organic layer OR1 includes a light-emitting layer that emits light in, for example, a blue wavelength region.

[0025] The display element 202 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the aperture AP2. The peripheral portion of the lower electrode LE2 is covered with an inorganic insulating layer 5. The display element 202, which includes the lower electrode LE2, the organic layer OR2, and the upper electrode UE2, is surrounded by a partition wall 6 in a planar view. The peripheral portions of each of the organic layer OR2 and the upper electrode UE2 overlap the inorganic insulating layer 5 in a planar view. The organic layer OR2 includes a light-emitting layer that emits light in, for example, a green wavelength region.

[0026] The display element 203 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each of which overlaps with the aperture AP3. The peripheral portion of the lower electrode LE3 is covered with an inorganic insulating layer 5. The display element 203 including the lower electrode LE3, the organic layer OR3, and the upper electrode UE3 is surrounded by a partition wall 6 in a planar view. The peripheral portions of each of the organic layer OR3 and the upper electrode UE3 overlap the inorganic insulating layer 5 in a planar view. The organic layer OR3 includes a light-emitting layer that emits light in, for example, a red wavelength region.

[0027] 2, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes shown in the figure do not necessarily reflect the exact shapes.

[0028] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of display elements, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes of display elements or a common electrode.

[0029] The lower electrode LE1 is connected to the pixel circuit 1 of the subpixel SP1 (see FIG. 1) through a contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the subpixel SP2 through a contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the subpixel SP3 through a contact hole CH3.

[0030] 2, the areas of the openings AP1, AP2, and AP3 are different from one another. The area of ​​the openings AP1 is larger than the area of ​​the openings AP2, and the area of ​​the openings AP2 is larger than the area of ​​the openings AP3. In other words, the area of ​​the lower electrode LE1 exposed from the opening AP1 is larger than the area of ​​the lower electrode LE2 exposed from the opening AP2, and the area of ​​the lower electrode LE2 exposed from the opening AP2 is larger than the area of ​​the lower electrode LE3 exposed from the opening AP3.

[0031] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG.

[0032] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Fig. 1, and various wirings such as the scanning line GL, the signal line SL, and the power supply line PL. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is an organic insulating layer that flattens unevenness caused by the circuit layer 11.

[0033] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and are spaced apart from each other. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively, through contact holes provided in the insulating layer 12. Note that the contact holes in the insulating layer 12 are omitted in Fig. 3 but correspond to CH1, CH2, and CH3 in Fig. 2.

[0034] The planarization layer 13 is disposed on the insulating layer 12, exposes the upper surfaces of the lower electrodes LE1, LE2, and LE3, and is in contact with the side surfaces of the lower electrodes LE1, LE2, and LE3. The planarization layer 13 has a thickness equal to that of each of the lower electrodes LE1, LE2, and LE3. In one example, the thickness of the planarization layer 13 is 50 to 100 nm.

[0035] The inorganic insulating layer 5 covers the planarizing layer 13 and also covers the peripheral portions of the lower electrodes LE1, LE2, and LE3. The opening AP1 in the inorganic insulating layer 5 overlaps with the lower electrode LE1, the opening AP2 overlaps with the lower electrode LE2, and the opening AP3 overlaps with the lower electrode LE3.

[0036] The partition wall 6 has a conductive lower portion (stem) 61 disposed on the inorganic insulating layer 5, and an upper portion (cap) 62 disposed on the lower portion 61. The lower portion 61 of the partition wall 6 shown on the right side of the figure is located between the openings AP1 and AP2. The lower portion 61 of the partition wall 6 shown on the left side of the figure is located between the openings AP2 and AP3. The upper portion 62 has a width greater than that of the lower portion 61. Both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhang shape.

[0037] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has a peripheral portion located on the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower portion 61.

[0038] The organic layer OR2 is in contact with the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has a peripheral portion located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower portion 61.

[0039] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has a peripheral portion located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower portion 61.

[0040] 3, the subpixel SP1 has a cap layer CP1 and a sealing layer SE1, the subpixel SP2 has a cap layer CP2 and a sealing layer SE2, and the subpixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 function as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0041] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP2 is disposed on the upper electrode UE2. The cap layer CP3 is disposed on the upper electrode UE3. The cap layers CP1, CP2, and CP3 may be omitted.

[0042] The sealing layer SE1 is disposed on the cap layer CP1, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP1. The sealing layer SE2 is disposed on the cap layer CP2, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP2. The sealing layer SE3 is disposed on the cap layer CP3, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP3.

[0043] 3, parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are located on the partition wall 6 around the subpixel SP1. These parts are separated from parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 that are located in the aperture AP1 (parts that form the display element 201). Similarly, portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 are located on the partition 6 surrounding the subpixel SP2, and these portions are spaced apart from portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 that are located in the opening AP2 (portions that constitute the display element 202). Similarly, portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 are located on the partition 6 surrounding the subpixel SP3, and these portions are spaced apart from portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 that are located in the opening AP3 (portions that constitute the display element 203).

[0044] Ends of the sealing layers SE1, SE2, and SE3 are located on the partition wall 6. In the example of Fig. 3, the ends of the sealing layers SE1 and SE2 located on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart, and the ends of the sealing layers SE2 and SE3 located on the partition wall 6 between the subpixels SP2 and SP3 are spaced apart.

[0045] The sealing layers SE1, SE2, and SE3 are covered with a resin layer RL1. The resin layer RL1 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer RL2.

[0046] The inorganic insulating layer 5, the sealing layers SE1, SE2, SE3, and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0047] The insulating layer 12 is made of a resin. The planarizing layer 13 is made of a positive photosensitive resin. The planarizing layer 13 may be made of a material different from that of the insulating layer 12, or may be made of the same material as that of the insulating layer 12.

[0048] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may be formed of an insulating material. The lower portion 61 and the upper portion 62 are formed of a material different from each other.

[0049] The lower electrodes LE1, LE2, and LE3 are, for example, a multilayer body including a transparent electrode made of an oxide conductive material such as indium tin oxide (ITO) and a metal electrode (reflective electrode) made of a metal material such as silver.

[0050] The organic layer OR1 includes an emitting layer EM1. The organic layer OR2 includes an emitting layer EM2. The organic layer OR3 includes an emitting layer EM3. The emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the emitting layer EM1 is formed of a material that emits light in a blue wavelength range, the emitting layer EM2 is formed of a material that emits light in a green wavelength range, and the emitting layer EM3 is formed of a material that emits light in a red wavelength range. In addition, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers, such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0051] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0052] The cap layers CP1, CP2, and CP3 are multilayer structures made up of a plurality of thin films, all of which are transparent and have different refractive indices.

[0053] FIG. 4 is a plan view showing an example of the planarizing layer 13. As shown in FIG. The planarization layer 13 is formed in a lattice shape in a planar view. Each of the lower electrodes LE1, LE2, and LE3 is surrounded by the planarization layer 13. That is, the side surface of the lower electrode LE1 is in contact with the planarization layer 13 over the entire periphery. Similarly, the side surface of the lower electrode LE2 is in contact with the planarization layer 13 over the entire periphery, and the side surface of the lower electrode LE3 is also in contact with the planarization layer 13 over the entire periphery. As a result, the planarization layer 13 reduces the steps between the adjacent lower electrodes LE1, LE2, and LE3.

[0054] In this manner, the planarization layer 13 reduces the steps between the lower electrodes LE1, LE2, and LE3, so that the upper surfaces of the inorganic insulating layer 5 overlapping the planarization layer 13 and the lower electrodes LE1, LE2, and LE3 are planarized. This suppresses the occurrence of cracks in the inorganic insulating layer 5 due to the steps between the lower electrodes LE1, LE2, and LE3.

[0055] The cracks in the inorganic insulating layer 5 can become a route for dissipation of moisture contained in the insulating layer 12. Therefore, if a crack penetrates the inorganic insulating layer 5, there is a risk that the moisture contained in the insulating layer 12 will travel along the end of the lower electrode LE and permeate the crack. In this case, the organic layer OR located on the inorganic insulating layer 5 will be damaged by the moisture that has permeated the crack, resulting in a decrease in light-emitting performance.

[0056] As described above, according to the present embodiment, the occurrence of cracks in the inorganic insulating layer 5 is suppressed, and therefore the route of dissipation of moisture contained in the insulating layer 12 is blocked. This suppresses deterioration of the organic layer OR located on the inorganic insulating layer 5 due to moisture. Therefore, deterioration of reliability can be suppressed.

[0057] Furthermore, since the surface of the inorganic insulating layer 5 that serves as the base of the partition walls 6 is flattened, the partition walls 6 can be formed in a desired shape.

[0058] In addition, assuming that a crack will occur in the inorganic insulating layer 5, the area contributing to the display of each sub-pixel can be increased compared to the case where the width of the lower portion 61 of the partition wall 6 is expanded to cover the crack.

[0059] In addition, assuming that cracks will occur in the inorganic insulating layer 5, adjacent lower electrodes LE are arranged close to each other, and electrical insulation between adjacent lower electrodes LE can be ensured compared to the case where the ends of each lower electrode LE are located directly below the lower portion 61.

[0060] In addition, the planarization layer 13 formed of resin is covered by the inorganic insulating layer 5 and is not exposed from the inorganic insulating layer 5. This prevents contact between the organic layer OR and the planarization layer 13. This makes it possible to suppress deterioration of the organic layer OR due to moisture contained in the planarization layer 13.

[0061] Next, a method for manufacturing the display device DSP will be described with reference to Fig. 5 to Fig. 14. Note that in Fig. 5 to Fig. 14, illustration of the part below the insulating layer 12 is omitted.

[0062] First, a process substrate SUB is prepared as shown in Fig. 5. The process of preparing the process substrate SUB includes a step of forming an insulating layer 12, and a step of forming a lower electrode LE1 of subpixel SP1, a lower electrode LE2 of subpixel SP2, and a lower electrode LE3 of subpixel SP3 on the insulating layer 12. The process of forming the lower electrodes LE1, LE2, and LE3 includes a step of forming a transparent conductive layer, a step of forming a metal layer, and a step of collectively patterning the conductive layer and the metal layer.

[0063] 6, a planarization layer 13 is formed on the insulating layer 12. The process of forming the planarization layer 13 will be described in detail later, but includes a process of applying a photosensitive resin that covers the insulating layer 12 and the lower electrodes LE1, LE2, and LE3, and a process of patterning the photosensitive resin.

[0064] 7, an inorganic insulating layer 5 is formed to cover the lower electrodes LE1, LE2, LE3 and the planarizing layer 13. In one example, silicon oxynitride is deposited over the entire display area DA by a CVD (Chemical Vapor Deposition) method.

[0065] 8, a partition wall 6 is formed on the inorganic insulating layer 5. The process of forming the partition wall 6 includes the steps of forming a metal layer on the inorganic insulating layer 5, forming a thin film on the metal layer, forming a resist on the thin film corresponding to the shape of the partition wall 6, sequentially etching the thin film and the metal layer using the resist as a mask, and removing the resist. The metal layer is patterned to form a lower portion 61 located on the inorganic insulating layer 5. Furthermore, the thin film is patterned to form an upper portion 62 located on the lower portion 61 and protruding from a side surface of the lower portion 61.

[0066] 9, openings AP1, AP2, and AP3 are formed in the inorganic insulating layer 5. The opening AP1 overlaps the lower electrode LE1, the opening AP2 overlaps the lower electrode LE2, and the opening AP3 overlaps the lower electrode LE3. The inorganic insulating layer 5 thus formed covers the planarizing layer 13 and covers the periphery of each of the lower electrodes LE1, LE2, and LE3. In the above example, the openings AP1, AP2, and AP3 are formed after the partition 6 is formed, but this is not limiting, and the partition 6 may be formed after the inorganic insulating layer 5 having the openings AP1, AP2, and AP3 is formed.

[0067] Next, the display element 201 is formed. First, as shown in FIG. 10, using the partition 6 as a mask, materials for forming each layer, such as a hole injection layer, a hole transport layer, an electron blocking layer, an emitting layer (EM1), a hole blocking layer, an electron transport layer, and an electron injection layer, are sequentially evaporated onto the lower electrode LE1 to form an organic layer OR1. Thereafter, a mixture of magnesium and silver is evaporated onto the organic layer OR1 using the partition wall 6 as a mask to form the upper electrode UE1. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower portion 61. Then, using the partition 6 as a mask, a high refractive index material for forming the first transparent layer TL1 and a low refractive index material for forming the second transparent layer TL2 are sequentially evaporated on the upper electrode UE1 to form the cap layer CP1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are successively formed while maintaining a vacuum environment.

[0068] Thereafter, the sealing layer SE1 is formed by CVD so as to continuously cover the cap layer CP1 and the partition wall 6.

[0069] The organic layer OR1, the upper electrode UE1, the cap layer CP1, and the sealing layer SE1 are formed at least in the entire display area DA, and are disposed not only in the subpixel SP1 but also in the subpixels SP2 and SP3. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are divided by an overhanging partition wall 6.

[0070] When the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by vapor deposition, materials emitted from the vapor deposition source are blocked by the upper part 62. For this reason, parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are laminated on the upper part 62. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 located on the upper part 62 are each spaced apart from the organic layer OR1, the upper electrode UE1, and the cap layer CP1 located immediately above the lower electrode LE1. The sealing layer SE1 covers the cap layer CP1 immediately above the partition wall 6, and also covers the cap layer CP1 immediately above the lower electrode LE1.

[0071] 11, a resist RS patterned into a predetermined shape is formed on the sealing layer SE1. The resist RS overlaps the sub-pixel SP1 and a part of the partition wall 6 around it.

[0072] 12, the sealing layer SE1, the cap layer CP1, the upper electrode UE1, and the organic layer OR1 exposed from the resist RS are sequentially removed by etching using the resist RS as a mask, thereby exposing the lower electrode LE2 of the subpixel SP2 and the lower electrode LE3 of the subpixel SP3. Thereafter, the resist RS is removed, thereby forming the display element 201 in the subpixel SP1.

[0073] 13, the display element 202 is formed. The procedure for forming the display element 202 is the same as that for forming the display element 201. That is, an organic layer OR2 including an emission layer EM2, an upper electrode UE2, a cap layer CP2, and a sealing layer SE2 are formed in this order on the lower electrode LE2. Thereafter, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cap layer CP2, the upper electrode UE2, and the organic layer OR2 are patterned in this order by etching using the resist as a mask. After this patterning, the resist is removed. As a result, the display element 202 is formed in the subpixel SP2, and the lower electrode LE3 of the subpixel SP3 is exposed.

[0074] Next, as shown in FIG. 14, the display element 203 is formed. The procedure for forming the display element 203 is the same as the procedure for forming the display element 201. That is, an organic layer OR3 including an emission layer EM3, an upper electrode UE3, a cap layer CP3, and a sealing layer SE3 are formed in this order on the lower electrode LE3. Thereafter, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3 are patterned in this order by etching using the resist as a mask. After this patterning, the resist is removed. As a result, the display element 203 is formed in the subpixel SP3.

[0075] Thereafter, the resin layer RL1, the sealing layer 14, and the resin layer RL2 shown in Fig. 3 are formed in this order, thereby completing the display device DSP.

[0076] In the above manufacturing process, it is assumed that the display element 201 is formed first, then the display element 202 is formed, and finally the display element 203 is formed. However, the order of forming the display elements 201, 202, and 203 is not limited to this example.

[0077] Next, several techniques for forming the planarization layer 13 will be described.

[0078] FIG. 15 is a diagram for explaining one method for forming the flattening layer 13. As shown in FIG.

[0079] First, as shown in the upper part, a positive photosensitive resin PR is applied to cover the insulating layer 12 and the plurality of lower electrodes LE. The plurality of lower electrodes LE here correspond to any one of the lower electrodes LE1, LE2, and LE3 shown in FIG. 3. Each of the lower electrodes LE is a multilayer body of a first layer L1, a second layer L2, and a third layer L3. The first layer L1 and the third layer are both transparent electrodes. The second layer L2 is a metal electrode such as silver. In other words, each of the lower electrodes LE has a metal electrode that can be a reflective electrode between a pair of transparent electrodes.

[0080] Next, as shown in the middle, the entire surface of the photosensitive resin PR is exposed to light without using a mask. The area of ​​the photosensitive resin PR that overlaps with the lower electrode LE is exposed to light irradiated from a light source of an exposure device and also to light reflected by the second layer L2 of the lower electrode LE. The area of ​​the photosensitive resin PR that does not overlap with the lower electrode LE (or the area that overlaps between adjacent lower electrodes LE) is exposed to light irradiated from the light source. Therefore, the surface layer of the photosensitive resin PR is exposed and changes to become soluble in a developer.

[0081] Next, as shown in the lower part, the photosensitive resin PR is developed. By developing the photosensitive resin PR, the surface layer of the photosensitive resin PR is removed, the upper surfaces of the lower electrodes LE are exposed, and the photosensitive resin PR remains between the lower electrodes LE. Thereafter, the photosensitive resin PR is baked, which removes moisture from the photosensitive resin PR and forms the planarizing layer 13.

[0082] Fig. 16 is a diagram for explaining another method for forming the flattening layer 13. Note that explanations that overlap with the contents explained with reference to Fig. 15 will be omitted as appropriate.

[0083] First, a positive photosensitive resin PR is applied to cover the insulating layer 12 and the plurality of lower electrodes LE.

[0084] Next, the photosensitive resin PR is exposed using a mask M1. The mask M1 has an opening OP and a low-transmittance portion LT having a transmittance lower than that of the opening OP. The opening OP has a shape corresponding to the lower electrode LE. The low-transmittance portion LT has a shape corresponding to the region where the planarization layer 13 is to be formed (a region not overlapping the lower electrode LE). The low-transmittance portion LT has a width larger than the interval between adjacent lower electrodes LE and overlaps the end of the lower electrode LE. When the photosensitive resin PR is exposed through such a mask M1, an exposure condition is realized in which the exposure amount of the region overlapping the lower electrode LE is greater than the exposure amount of the region not overlapping the lower electrode LE. The area of ​​the photosensitive resin PR that overlaps with the lower electrode LE is exposed to the light that has passed through the opening OP and is also exposed to the light that has been reflected by the second layer L2 of the lower electrode LE. The area of ​​the photosensitive resin PR that does not overlap with the lower electrode LE is exposed to the light that has passed through the low-transmittance portion LT and is also exposed to the diffused light that has been reflected by the second layer L2 of the lower electrode LE. Therefore, the surface layer of the photosensitive resin PR is exposed and changes to become soluble in the developer.

[0085] Subsequently, the photosensitive resin PR is developed and then baked, thereby forming the planarizing layer 13.

[0086] Fig. 17 is a diagram for explaining another method for forming the flattening layer 13. Note that explanations that overlap with the contents explained with reference to Fig. 15 will be omitted as appropriate.

[0087] First, a positive photosensitive resin PR is applied to cover the insulating layer 12 and the plurality of lower electrodes LE.

[0088] Next, the entire surface of the photosensitive resin PR is exposed to light without using a mask.

[0089] Next, the photosensitive resin PR is exposed using a mask M2. The mask M2 has an opening OP and a light-shielding portion LS. The opening OP has a shape corresponding to the lower electrode LE. The light-shielding portion LS has a shape corresponding to the region where the planarizing layer 13 is to be formed (a region that does not overlap the lower electrode LE). The light-shielding portion LS has a width larger than the interval between adjacent lower electrodes LE, and overlaps the end of the lower electrode LE. The region of the photosensitive resin PR that overlaps with the lower electrode LE is exposed in the previous full-surface exposure process, and is also exposed to light transmitted through the opening OP in the exposure process using the mask M2. The region of the photosensitive resin PR that does not overlap with the lower electrode LE is exposed in the previous full-surface exposure process, but is shielded by the light-shielding portion LS in the exposure process using the mask M2. By forming such a difference in the amount of exposure, the photosensitive resin PR in the region that overlaps with the lower electrode LE is exposed so as to be reliably removable, and the photosensitive resin PR in the region that does not overlap with the lower electrode LE is exposed so as to make the surface layer removable and the bottom portion remain.

[0090] Subsequently, the photosensitive resin PR is developed and then baked, thereby forming the planarizing layer 13.

[0091] Next, a cross-sectional shape in which the planarizing layer 13 can be formed will be described.

[0092] FIG. 18 is a diagram showing an example of the cross-sectional shape of the planarizing layer 13. As shown in FIG. The upper surface US13 of the planarization layer 13 protrudes more than the upper surface US1 of the lower electrode LE1 and the upper surface US2 of the lower electrode LE2. In the illustrated example, the entire upper surface US13 protrudes more than the upper surface US1, etc., forming a convex surface. There may be cases where a part of the upper surface US13 protrudes more than the upper surface US1, etc. Note that although the lower electrode LE3 is not illustrated in FIG. 18, at least a part of the upper surface US13 protrudes more than the upper surfaces of the lower electrodes LE1, LE2, and L3. In one example, the thickness of the planarization layer 13 is maximum at a midpoint that is approximately equidistant from adjacent lower electrodes LE.

[0093] FIG. 19 is a diagram showing another example of the cross-sectional shape of the planarizing layer 13. In FIG. The upper surface US13 of the planarization layer 13 is recessed from the upper surface US1 of the lower electrode LE1 and the upper surface US2 of the lower electrode LE2. In the illustrated example, the entire upper surface US13 is recessed from the upper surface US1, etc., forming a concave surface. There may be cases where a part of the upper surface US13 is recessed from the upper surface US1, etc. Note that although the lower electrode LE3 is not illustrated in FIG. 19, at least a part of the upper surface US13 is recessed from the respective upper surfaces of the lower electrodes LE1, LE2, and L3. In one example, the thickness of the planarization layer 13 is minimum at a midpoint that is approximately equidistant from adjacent lower electrodes LE.

[0094] FIG. 20 is a diagram for explaining a process of selectively forming the flattening layer 13 in the display area DA.

[0095] First, as shown in the upper part, a positive photosensitive resin PR is applied to cover the insulating layer 12 and the lower electrodes LE. At this time, the photosensitive resin PR is applied not only to the display area DA but also to the peripheral area SA.

[0096] Next, as shown in the middle, the photosensitive resin PR is exposed using a mask M1. The mask M1 has an opening OP and a low-transmittance portion LT having a transmittance lower than that of the opening OP. The opening OP has a shape corresponding to the lower electrode LE and also has a shape corresponding to the peripheral region SA. The low-transmittance portion LT has a shape corresponding to the region where the planarizing layer 13 is to be formed (a region not overlapping the lower electrode LE). When the photosensitive resin PR is exposed through such a mask M1, an exposure condition is realized in which the exposure amount of the region overlapping the lower electrode LE and the peripheral region SA is greater than the exposure amount of the region not overlapping the lower electrode LE in the display region DA. The area of ​​the photosensitive resin PR that overlaps with the lower electrode LE and the peripheral area SA are exposed to light that has passed through the opening OP. The area of ​​the photosensitive resin PR that does not overlap with the lower electrode LE in the display area DA is exposed to light that has passed through the low-transmittance portion LT. Thus, the surface layer of the photosensitive resin PR located in the display area DA is exposed, and the entire photosensitive resin PR located in the peripheral area SA is exposed. The exposed area of ​​the photosensitive resin PR changes to become soluble in a developer.

[0097] Next, as shown in the lower part, the photosensitive resin PR is developed and then baked. As a result, the planarization layer 13 is formed. Also, the photosensitive resin PR is removed from the peripheral region SA. As a result, the terminals TE and the like shown in FIG. 1 are exposed from the planarization layer 13 in the peripheral region SA.

[0098] Figure 20 describes the case where the photosensitive resin PR in the peripheral area SA is removed using the mask M1 shown in Figure 16, but the photosensitive resin PR in the peripheral area SA can also be removed using the mask M2 shown in Figure 17, or the photosensitive resin PR in the peripheral area SA can also be removed by applying the full-surface exposure process shown in Figure 15.

[0099] As described above, according to the present embodiment, it is possible to provide a display device and a manufacturing method thereof that are capable of suppressing a decrease in reliability.

[0100] All display devices and manufacturing methods thereof that can be implemented by a person skilled in the art through appropriate design modifications based on the display device and manufacturing method thereof described above as embodiments of the present invention are within the scope of the present invention as long as they include the gist of the present invention.

[0101] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0102] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0103] DSP…display device 10…board 5...Inorganic insulating layer AP1, AP2, AP3...Openings 6...Bulkhead 61...Lower 62...Upper 12...insulating layer (organic insulating layer) 13...planarizing layer SP1, SP2, SP3...Subpixels 20, 201, 202, 203...Display element (organic EL element) LE, LE1, LE2, LE3...lower electrode UE, UE1, UE2, UE3...upper electrode OR, OR1, OR2, OR3…Organic layer

Claims

1. A substrate; an organic insulating layer disposed above the substrate; a lower electrode disposed on the organic insulating layer; a planarization layer disposed on the organic insulating layer and in contact with a side surface of the lower electrode; an inorganic insulating layer that covers the planarizing layer and covers a peripheral portion of the lower electrode; a partition wall having a lower portion formed of a conductive material and disposed on the inorganic insulating layer, and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion; an organic layer including a light-emitting layer, the organic layer being surrounded by the partition and disposed on the lower electrode; an upper electrode surrounded by the partition wall, disposed on the organic layer, and in contact with the lower portion of the partition wall; A display device comprising:

2. The display device according to claim 1 , wherein the planarizing layer is formed in a lattice shape in a plan view.

3. The display device according to claim 1 , wherein at least a part of an upper surface of the planarizing layer protrudes beyond an upper surface of the lower electrode.

4. The display device according to claim 1 , wherein at least a part of an upper surface of the planarization layer is recessed from an upper surface of the lower electrode.

5. The display device according to claim 1 , wherein the planarization layer is made of a positive photosensitive resin.

6. a cap layer disposed on the upper electrode; a sealing layer disposed on the cap layer and formed of an inorganic insulating material; The display device according to claim 1 , wherein the sealing layer covers the cap layer directly above the lower electrode and is in contact with the partition wall.

7. forming an organic insulating layer over the substrate; forming a lower electrode on the organic insulating layer; applying a positive photosensitive resin covering the organic insulating layer and the lower electrode; The photosensitive resin is patterned to form a planarization layer in contact with a side surface of the lower electrode; forming an inorganic insulating layer that covers the planarizing layer and also covers a peripheral portion of the lower electrode; forming a partition wall having a lower portion located on the inorganic insulating layer and made of a conductive material, and an upper portion located on the lower portion and protruding from a side surface of the lower portion; forming an organic layer including a light-emitting layer on the lower electrode by deposition using the partition as a mask; forming an upper electrode located on the organic layer and in contact with the lower portion of the partition wall by deposition using the partition wall as a mask;

8. The step of patterning the photosensitive resin includes: exposing the entire surface of the photosensitive resin to light without using a mask; developing the photosensitive resin; The method for manufacturing a display device according to claim 7 , further comprising the step of baking the photosensitive resin.

9. The step of patterning the photosensitive resin includes: exposing the photosensitive resin under exposure conditions in which the amount of exposure of a region overlapping the lower electrode is greater than the amount of exposure of a region not overlapping the lower electrode; developing the photosensitive resin; The method for manufacturing a display device according to claim 7 , further comprising the step of baking the photosensitive resin.

10. The step of patterning the photosensitive resin includes: exposing the entire surface of the photosensitive resin to light without using a mask; exposing the photosensitive resin to light using a mask having an opening in an area overlapping the lower electrode and blocking an area not overlapping the lower electrode; developing the photosensitive resin; The method for manufacturing a display device according to claim 7 , further comprising the step of baking the photosensitive resin.

11. Furthermore, after forming the upper electrode, forming a cap layer on the upper electrode; forming a sealing layer on the cap layer using an inorganic insulating material; The method for manufacturing a display device according to claim 7 , wherein the sealing layer covers the cap layer directly above the lower electrode and is in contact with the partition wall.

12. Furthermore, after forming the sealing layer, a patterned resist is formed on the sealing layer; The method for manufacturing a display device according to claim 11 , wherein the sealing layer, the cap layer, the upper electrode, and the organic layer exposed from the resist are sequentially removed by etching.

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