Display device

Abstract

To improve display quality of a display device.SOLUTION: A display device includes: a first conductive layer provided on a first substrate and extending in a first direction; a first insulating film provided on the first conductive layer; a second conductive layer provided on the first insulating film and extending in a second direction intersecting the first direction; a second insulating film provided on the second conductive layer and extending in the first and second directions; a first transparent conductive layer provided on the second insulating layer and extending in the first and second directions; a third insulating film provided on the first transparent conductive layer; and a second substrate facing the first substrate. The second insulating film includes a first projection part projected above from the surface of the first transparent conductive layer; the first transparent conductive layer has a first opening surrounding the first projection part; the third insulating film has a second opening surrounding the first projection part; and the first projection part is provided so as to maintain a gap between the first and second substrates.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, transparent displays that allow the background on one side to be visible from the other side have been developed (see Patent Documents 1 and 2). With a transparent display, images can be seen from both the front and back, so images or characters can be seen from two opposing directions with the transparent display in between.

[0003] Generally, in a liquid crystal display device, a spacer is provided to maintain a cell gap between an array substrate and an opposing substrate, and the spacer is disposed at an intersection of a gate line and a source line so as not to reduce the aperture ratio of the pixel. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-160254 A [Patent Document 2] International Publication No. 2022 / 153665 [Patent Document 3] International Publication No. 2018 / 130920 Summary of the Invention [Problem to be solved by the invention]

[0005] In display devices such as transparent displays, conductive layers of various thicknesses are laminated on an array substrate. Laminating the conductive layers may cause unevenness on the top surface of the array substrate. When multiple spacers provided on the opposing substrate come into contact with the unevenness on the top surface of the array substrate, the cell gap becomes uneven. This reduces the display quality of the display device.

[0006] An object of one embodiment of the present invention is to improve the display quality of a display device. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention has a first conductive layer provided on a first substrate and extending in a first direction, a first insulating film provided on the first conductive layer, a second conductive layer provided on the first insulating film and extending in a second direction intersecting the first direction, a second insulating film provided on the second conductive layer and extending in the first and second directions, a first transparent conductive layer provided on the second insulating film and extending in the first and second directions, a third insulating film provided on the first transparent conductive layer, and a second substrate facing the first substrate, wherein the second insulating film has a first protrusion protruding above a surface of the first transparent conductive layer, a first opening is provided in the first transparent conductive layer to surround the first protrusion, and a second opening is provided in the third insulating film to surround the first protrusion, and the first protrusion is arranged to maintain a gap between the first substrate and the second substrate. [Brief description of the drawings]

[0008] [Figure 1] 1 is a perspective view illustrating an overview of a display device according to an embodiment of the present invention. [Diagram 2] 2 is a cross-sectional view showing a structure corresponding to a section A1-A2 of the display device shown in FIG. [Diagram 3] FIG. 1 is a plan view illustrating a configuration of a display device according to an embodiment of the present invention. [Figure 4] 1 is a circuit diagram illustrating a pixel in a display device according to an embodiment of the present invention. [Diagram 5] 4 is a timing chart of a pixel in a display device according to one embodiment of the present invention. [Figure 6] 1 is a planar layout of pixels in a display device according to an embodiment of the present invention. [Figure 7] 1 is a cross-sectional view of a pixel in a display device according to one embodiment of the present invention. [Figure 8]2 is an enlarged view of a planar layout of pixels in a display device according to one embodiment of the present invention; FIG. [Figure 9] 2 is an enlarged view of a planar layout of pixels in a display device according to one embodiment of the present invention; FIG. [Figure 10] 2 is an enlarged view of a planar layout of pixels in a display device according to one embodiment of the present invention; FIG. [Figure 11] 2 is an enlarged view of a planar layout of pixels in a display device according to one embodiment of the present invention; FIG. [Figure 12] 2 is an enlarged view of a planar layout of pixels in a display device according to one embodiment of the present invention; FIG. [Figure 13] 13 is a cross-sectional view taken along line B1-B2 shown in FIG. 12 in the display device according to the embodiment of the present invention. [Figure 14] 13 is a cross-sectional view taken along line C1-C2 shown in FIG. 12 in the display device according to one embodiment of the present invention. [Figure 15] 4 is a cross-sectional view of the vicinity of a sealing material in the peripheral region in a display device according to one embodiment of the present invention. FIG. [Figure 16] 4 is a cross-sectional view of the vicinity of a sealing material in the peripheral region in a display device according to one embodiment of the present invention. FIG. [Figure 17A] 1A to 1C are diagrams illustrating a manufacturing method of a display device according to an embodiment of the present invention. [Figure 17B] 1A to 1C are diagrams illustrating a manufacturing method of a display device according to an embodiment of the present invention. [Figure 18A] 1A to 1C are diagrams illustrating a manufacturing method of a display device according to an embodiment of the present invention. [Figure 18B] 1A to 1C are diagrams illustrating a manufacturing method of a display device according to an embodiment of the present invention. [Figure 19A] 1A to 1C are diagrams illustrating a manufacturing method of a display device according to an embodiment of the present invention. [Figure 19B] 1A to 1C are diagrams illustrating a manufacturing method of a display device according to an embodiment of the present invention. [Figure 20A] 1A to 1C are diagrams illustrating a manufacturing method of a display device according to an embodiment of the present invention. [Figure 20B]1A to 1C are diagrams illustrating a manufacturing method of a display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. However, the present invention can be implemented in various forms without departing from the gist of the present invention, and should not be interpreted as being limited to the description of the embodiments exemplified below. In addition, in the drawings, the width, thickness, shape, etc. of each part may be shown in a schematic manner compared to the actual form in order to make the explanation clearer, but these schematic drawings are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each figure, elements that are the same or similar to those described in the previous figures may be given the same reference numerals, and duplicate explanations may be omitted. In this specification, etc., ordinal numbers are given for convenience in distinguishing parts, parts, etc., and do not indicate priority or order.

[0010] In the present invention, when a single film is processed to form multiple films, these multiple films may have different functions and roles. However, these multiple films originate from a film formed as the same layer in the same process, and have the same layer structure and the same material. Therefore, these multiple films are defined as existing in the same layer. In addition, when a single film is processed to form multiple films, they may be distinguished and described as -1, -2, etc. in this specification.

[0011] In this specification, expressions such as "above" and "below" express the relative positional relationship between a structure of interest and another structure. In this specification, the direction from a first substrate to a pixel electrode, which will be described later, is defined as "above" in a side view, and the opposite direction is defined as "below". In this specification and claims, when expressing a mode in which another structure is disposed on a certain structure, the term "above" is used to include both a case in which another structure is disposed directly above the certain structure so as to be in contact with the certain structure, and a case in which another structure is disposed above the certain structure via another structure, unless otherwise specified.

[0012] In this specification, bottom gate driving refers to on / off control by a gate electrode arranged below the semiconductor layer. In this specification, top gate driving refers to on / off control by a gate electrode arranged above the semiconductor layer. In this specification, dual gate driving refers to on / off control by inputting the same control signal to gate electrodes arranged above and below the semiconductor layer.

[0013] (First embodiment) A display device 10 according to one embodiment of the present invention will be described with reference to FIGS.

[0014] <Display device overview> 1 shows a perspective view of a display device 10 according to an embodiment of the present invention. The display device 10 includes an array substrate 150 (also referred to as a first substrate), a counter substrate 152 (also referred to as a second substrate), a liquid crystal layer (not shown) between the array substrate 150 and the counter substrate 152, a display panel 102 including a gate driving circuit 28 and a source driving circuit 38, a light source 104, and a first transparent substrate 151A and a second transparent substrate 151B sandwiching the display panel 102. In the following description with reference to FIG. 1, one direction of the plane of the display panel 102 is defined as a D1 direction, a direction perpendicular to the D1 direction is defined as a D2 direction, and a direction perpendicular to the D1-D2 plane is defined as a D3 direction.

[0015] The array substrate 150 and the counter substrate 152 are translucent. The array substrate 150 and the counter substrate 152 are preferably transparent to visible light. The counter substrate 152 is disposed in the direction D3 so as to face the array substrate 150. The array substrate 150 and the counter substrate 152 are bonded together by a sealant 154 in a state in which they are disposed facing each other with a gap therebetween. A liquid crystal layer (not shown) is provided in the gap between the array substrate 150 and the counter substrate 152.

[0016] The display panel 102 has a display area 12 and a peripheral area 14 outside the display area 12. In the display area 12, a plurality of pixels PIX are arranged in row and column directions. Here, the row direction refers to a direction parallel to the D1 direction, and the column direction refers to a direction parallel to the D2 direction. In the display area 12, m pixels are arranged in the row direction, and n pixels are arranged in the column direction. The values ​​of m and n are appropriately set according to the display resolution in the vertical direction and the display resolution in the horizontal direction. In the display area 12, gate wiring (also called scanning signal lines) are arranged in the D1 direction, and source wiring (also called data signal lines) are arranged in the D2 direction.

[0017] A gate driving circuit 28 and a source driving circuit 38 are provided in the peripheral region 14 of the array substrate 150. Fig. 1 shows an embodiment in which the gate driving circuit 28 and the source driving circuit 38 are provided as an integrated circuit (IC) and mounted on the array substrate 150 by a COG (Chip on Glass) method. The gate driving circuit 28 and the source driving circuit 38 are not limited to the embodiment shown in the figure, and may be mounted by a COF (Chip on Film) method or may be formed by a thin film transistor (TFT: Thin Film Transistor) of the array substrate 150.

[0018] In the peripheral region 14, a gate wiring region 32, a common wiring region 22, and a source wiring region 42 are arranged. The gate wiring region 32 is an area where a pattern formed by wiring that connects the gate driving circuit 28 and the gate wiring GL arranged in the display region 12 is provided. The common wiring region 22 is an area where a pattern formed by common wiring is provided. In terms of circuitry, the common wiring region 22 is used as wiring that applies a common voltage to a common electrode 218 (see FIG. 7) provided on the counter substrate 152. The source wiring region 42 is an area where a pattern formed by wiring that connects the source driving circuit 38 and the data signal line SL arranged in the display region 12 is provided.

[0019] The light source 104 has a structure along the D1 direction. The light source 104 is composed of, for example, light emitting diodes (LEDs) arranged along the D1 direction. The detailed structure of the light source 104 is not limited, and in addition to the light emitting diodes arranged in the D1 direction, optical members such as a reflector, a diffuser, and a lens may be included. The light source 104 and the light emission control circuit 110 that controls the light source 104 may be provided as separate members independent of the display panel 102. The light source 104 may be controlled in terms of light emission timing by the light emission control circuit 110 that is synchronized with the gate drive circuit 28 and the source drive circuit 38. The light emission control circuit 110 that controls the light source 104 may be provided as a separate member like the light source 104, separate from the display panel 102, or may be mounted on the array substrate 150 as an individual component, or may be incorporated in the gate drive circuit 28 or the source drive circuit 38.

[0020] The first transparent substrate 151A and the second transparent substrate 151B are provided to sandwich the display region 12 and the peripheral region 14. The first transparent substrate 151A and the second transparent substrate 151B function as protective members for the display panel 102. As will be described with reference to FIG. 2, the first transparent substrate 151A and the second transparent substrate 151B function as light guide plates that introduce light emitted from the light source 104 to the display panel 102.

[0021] 2 shows a cross-sectional structure of the display device 10 corresponding to the A1-A2 area shown in FIG. 1. As shown in FIG. 2, a first transparent substrate 151A is provided on the array substrate 150 side of the display panel 102, and a second transparent substrate 151B is provided on the counter substrate 152 side. The first transparent substrate 151A and the second transparent substrate 151B are made of glass or plastic. The first transparent substrate 151A and the second transparent substrate 151B preferably have the same refractive index as the array substrate 150 and the counter substrate 152. The array substrate 150 and the first transparent substrate 151A, and the counter substrate 152 and the second transparent substrate 151B are bonded with a transparent adhesive (not shown).

[0022] The display panel 102 is arranged such that an array substrate 150 and a counter substrate 152 face each other, with a liquid crystal layer 210 provided between them. The array substrate 150 is larger than the counter substrate 152, and has a size such that a part of the peripheral region 14 is exposed from the counter substrate 152. A drive circuit (source drive circuit 38 in FIG. 2) is mounted on the array substrate 150. In addition, a flexible printed circuit 34 is attached to the peripheral edge of the array substrate 150.

[0023] The light source 104 is disposed adjacent to one side surface of the first transparent substrate 151A or the second transparent substrate 151B. Fig. 2 shows a configuration in which the light source 104 is disposed along one side surface of the second transparent substrate 151B. Fig. 2 also shows a configuration in which the light source 104 is attached to the array substrate 150, but the configuration in which the light source 104 is disposed is not limited, and the attachment structure is not limited as long as the attachment position can be fixed. The light source 104 may be supported by a housing surrounding the display panel 102, for example.

[0024] As shown in Fig. 2, the light source 104 is disposed along the first side surface 15C of the second transparent substrate 151B. As shown in Fig. 2, the light source 104 irradiates light L to the first side surface 15C of the second transparent substrate 151B. The light source 104 is sometimes called a side light source because it emits light L toward the first side surface 15C. The first side surface 15C of the second transparent substrate 151B facing the light source 104 serves as a light incident surface.

[0025] As shown in FIG. 2, the light L incident from the first side surface 15C of the second transparent substrate 151B propagates in a direction away from the first side surface 15C (direction D2) while being reflected by the second plane 15B of the second transparent substrate 151B and the first plane 15A of the first transparent substrate 151A. When the light L travels from the first plane 15A of the first transparent substrate 151A and the second plane 15B of the second transparent substrate 151B to the outside, it travels from a medium with a large refractive index to a medium with a small refractive index. At this time, if the angle of incidence of the light L incident on the first plane 15A and the second plane 15B is larger than the critical angle, it is totally reflected and is guided in the direction D2 while being reflected by the first plane 15A and the second plane 15B.

[0026] The liquid crystal layer 210 is made of polymer-dispersed liquid crystal. The liquid crystal layer 210 made of polymer-dispersed liquid crystal is controlled to be in a scattering state or a non-scattering state for each pixel PIX (see FIG. 1). As shown in FIG. 2, when there is a pixel in which the liquid crystal layer 210 is in a scattering state, at least a part of the light L propagating while being reflected by the first plane 15A and the second plane 15B is scattered, and the incident angle of the scattered light becomes smaller than the critical angle, and the scattered light LA, LB is emitted to the outside from the first plane 15A and the second plane 15B, respectively, and the emitted scattered light LA, LB is observed by the observer. In the display panel 102, the area other than the area where the scattered light LA, LB is emitted is substantially transparent because the array substrate 150, the counter substrate 152, the first transparent substrate 151A, and the second transparent substrate 151B have translucency (transparent to visible light) and the liquid crystal layer 210 is in a non-scattering state, and the observer can view the back side through the display panel 102.

[0027] 3 is a plan view illustrating a configuration of an array substrate 150 of a display device according to an embodiment of the present invention. As shown in FIG.

[0028] The display area 12 has a plurality of pixels PIX arranged in a matrix. Each of the pixels PIX has a plurality of transistors and a liquid crystal element.

[0029] The peripheral region 14 is provided to surround the display region 12. The peripheral region 14 refers to the region on the array substrate 150 from the display region 12 to the edge of the array substrate 150. In other words, the peripheral region 14 refers to the region on the array substrate 150 other than where the display region 12 is provided (i.e., the region outside the display region 12).

[0030] In addition to the gate driving circuit 28 and the source driving circuit 38, the peripheral region 14 is provided with a gate wiring region 32, a source wiring region 42, common wirings 16, 18, terminal portions 26, 36, flexible printed circuits 24, 34, and various inspection circuits. The terminal portions 26, 36 are disposed along one side of the array substrate 150.

[0031] The flexible printed circuit 24 is connected to the terminal section 26. The flexible printed circuit 24 supplies various signals to the gate drive circuit 28, the common wirings 16 and 18, the ESD protection circuit 59, and the QD pad 56. The gate drive circuit 28 is connected to a plurality of gate lines GL, and each of the plurality of gate lines GL is electrically connected to each of the plurality of pixels PIX in the display area 12. In FIG. 3, the area in which the plurality of gate lines GL are provided is represented as a gate line area 32, and the detailed arrangement of the plurality of gate lines GL is omitted. The number of gate lines GL connected to the two gate drive circuits 28 corresponds to the number of rows of the pixels PIX in the display area 12. Note that, in FIG. 3, the gate line area 32 is shown as being provided at a distance from the display area 12, but in reality, the gate lines GL and the pixels PIX are electrically connected.

[0032] The terminal section 36 is connected to a flexible printed circuit 34. The flexible printed circuit 34 supplies a video signal to a source driving circuit 38. The source driving circuit 38 is connected to a plurality of source lines SL, and each of the plurality of source lines SL is electrically connected to each of the plurality of pixels PIX in the display area 12. In FIG. 3, the region in which the plurality of source lines SL are provided is represented as a source line region 42, and the detailed arrangement of the plurality of source lines SL is omitted. The number of source lines SL connected to the eight source driving circuits 38 corresponds to at least three times the number of columns of the pixels PIX in the display area 12. In this embodiment, the case where the number of source lines SL is four times the number of columns of the pixels PIX in the display area 12 will be described. Note that in FIG. 3, the source line region 42 is shown to be provided at a distance from the display area 12, but in reality, the source lines SL and the pixels PIX are electrically connected.

[0033] Between the gate wiring region 32 and the display region 12, there are provided a common wiring 18, an ESD protection circuit 46, a gate inspection circuit 48, and an inspection line 54. Between the source wiring region 42 and the display region 12, there are provided a common wiring 18, an ESD protection circuit 46, a source inspection circuit 52, and an inspection line 54. The inspection line 54 is connected to the ESD protection circuit 58 and the QD pad 56. In addition, the common wiring 18 is connected to an ESD protection circuit 59.

[0034] The common wiring 16 is provided so as to surround the peripheral region 14 of the array substrate 150, and signals are supplied to the common wiring 16 from two flexible printed circuits 24. The common wiring 16 is also electrically connected to a common wiring region 22 formed of a mesh-shaped electrode.

[0035] The display device 10 is not limited to a high-speed driving panel such as the transparent display shown in Figures 1 and 2. The display device 10 can be applied to a large panel used in a display device that is not a transparent display.

[0036] <Pixel circuit> FIG. 4 is a diagram for explaining a pixel circuit of a pixel PIX included in a display device 10 according to an embodiment of the present invention. In this embodiment, a display device 10 capable of simultaneously supplying an ON voltage to four gate lines GL and simultaneously charging four pixels PIX arranged in a column direction by four source lines SL will be described. This allows one horizontal period to be longer than a line-sequential horizontal period. In other words, the time required to scan all pixel lines arranged in the display area 12 can be reduced to 1 / 4. Therefore, in a high-speed driving panel such as a transparent display or a large panel, a sufficient charging period for the pixel PIX can be ensured. The configuration of the pixel PIX in this embodiment will be described in detail below.

[0037] In FIG. 4, four pixels PIX1 to PIX4 are arranged in the column direction (D2 direction). Each of the four pixels PIX1 to PIX4 is electrically connected to each of the four gate lines GL1 to GL4. Each of the four pixels PIX1 to PIX4 is electrically connected to each of the four source lines SL1 to SL4. Each of the four pixels PIX1 to PIX4 is connected to a capacitance line CW. In the following description, when there is no need to distinguish between the pixels PIX1 to PIX4, they are referred to as pixels PIX. When there is no need to distinguish between the gate lines GL1 to GL4 and the source lines SL1 to SL4, they are referred to as gate lines GL and source lines SL.

[0038] The pixel PIX has a transistor Tr, a liquid crystal element LE, and a storage capacitor C. The gate of the transistor Tr is connected to a gate line GL, the source of the transistor Tr is connected to a source line SL, and the drain of the transistor Tr is connected to one electrode of the liquid crystal element LE and one electrode of the storage capacitor C. The other electrode of the liquid crystal element LE is connected to a common electrode 218 (FIG. 7). The other electrode of the storage capacitor C is connected to a capacitance line CW.

[0039] The transistor Tr has a function of controlling the time for writing the video signal supplied from the source line SL to the pixel PIX by switching between an on state and an off state. By turning the transistor Tr on, a potential corresponding to the video signal supplied from the source line SL can be written to the storage capacitor C electrically connected to the transistor Tr. In addition, by turning the transistor Tr off, the potential held in the storage capacitor C can be maintained.

[0040] 5 is a timing chart of a display device 10 according to an embodiment of the present invention. Normally, an on-voltage is supplied to the gate lines GL one row at a time, and pixel columns aligned in the D2 direction are sequentially charged by the same source line SL. In contrast, in this embodiment, an on-voltage is supplied to the four gate lines GL simultaneously, and the transistors Tr of the four pixels PIX are simultaneously turned on. In this state, video signals are simultaneously supplied to the different source lines SL1 to SL4. This makes it possible to simultaneously drive the four pixels aligned in the D2 direction.

[0041] <Plane layout of pixels> The planar layout of pixels PIX in a display device 10 according to an embodiment of the present invention will be described with reference to Fig. 6. Fig. 6 shows a configuration of PIX-A1, PIX-A2, PIX-B1, and PIX-B2 in plan view.

[0042] 6, gate lines GLn-1 to GLn+1 are arranged along the direction D1. Source lines SL1 to SL4 are arranged along the direction D2. The aperture region of pixel PIX-B1 is a region surrounded by adjacent gate lines GLn-1, GLn, source lines SL1, and source lines SL4.

[0043] 6, source lines SL1 and SL3, and source lines SL2 and SL4 are provided to sandwich one column of pixels PIX-B1 and PIX-B2. In other words, four source lines SL1 to SL4 are disposed between one column of pixels PIX-A1 and PIX-A2 and one column of pixels PIX-B1 and PIX-B2.

[0044] A transistor Tr is provided in a region 250 where the gate line GL and the source lines SL1 to SL4 intersect. The transistor Tr is connected to a pixel electrode. The pixel electrode is provided in an opening region of the pixel PIX-B1. As shown in FIG. 6, a plurality of spacers SP are arranged at intersections of the pixels PIX arranged in a matrix. Alternatively, the plurality of spacers SP are arranged so as to have regularity with respect to the intersections of the pixels PIX arranged in a matrix. For example, the plurality of spacers may be arranged in every other row and every other column of the pixels PIX. In other words, the spacers SP may not be arranged at an intersection adjacent to the intersection where the spacer SP is arranged.

[0045] 6, in the region 250 where the gate line GL and the source lines SL1 to SL4 intersect, the source line SL2 and the source line SL4 are adjacent to the pixels PIX-A1 and PIX-A2, and the source line SL1 and the source line SL3 are adjacent to the pixels PIX-B1 and PIX-B2. To explain the position where the spacer SP is arranged in detail, the spacer SP overlaps with the source line SL3 adjacent to the pixels PIX-B1 and PIX-B2, and the source line SL2 adjacent to the pixels PIX-A1 and PIX-A2. The spacer SP overlaps with the source line SL4 adjacent to the pixels PIX-B2 and PIX-B3 (not shown), and the source line SL3 adjacent to the pixels PIX-C2 and PIX-C3 (not shown).

[0046] The spacer SP is disposed on two source lines sandwiched between two source lines adjacent to the pixel, among the source lines SL1 to SL4 that intersect with the gate line GL and are provided adjacent to each other.

[0047] Fig. 7 is a cross-sectional view of the display device 10. In Fig. 7, the order in which the layers are stacked when the display device 10 is viewed in cross section will be described.

[0048] As shown in FIG. 7, a conductive layer 202-1 is provided on the array substrate 150. A gate insulating film 203 is provided on the conductive layer 202-1. An oxide semiconductor layer 204-1 is provided on the gate insulating film 203. The oxide semiconductor layer 204-1 is provided opposite the conductive layer 202-1 via the gate insulating film 203. Conductive layers 206-3 and 206-4 are provided on the oxide semiconductor layer 204-1. An insulating film 205 is provided on the conductive layers 206-3 and 206-4. A conductive layer 208-1 is provided on the insulating film 205.

[0049] In this embodiment, the conductive layer 202-1 functions as a gate wiring GL (gate electrode). The conductive layer 206-3 functions as a drain electrode, and the conductive layer 206-4 functions as a source wiring SL (source electrode). The conductive layer 208-1 functions as a back gate. The conductive layer 202-1, the oxide semiconductor layer 204-1, the insulating film 205, and the conductive layers 206-3 and 206-4 function as a transistor Tr. In this embodiment, the transistor Tr is described as a bottom-gate driven transistor, but is not limited thereto, and may be a top-gate driven transistor or a dual-gate driven transistor.

[0050] In this embodiment, the gate insulating film 203 has a nitride insulating film 203a and an oxide insulating film 203b that are stacked. The insulating film 205 has an oxide insulating film 205a and a nitride insulating film 205b that are stacked. The oxide semiconductor layer 204-1 is sandwiched between the oxide insulating film 203b and the oxide insulating film 205a. During the process of the oxide insulating film 205a and the oxide insulating film 203b, oxygen is released from the oxide insulating film 203b and the oxide insulating film 205a. The released oxygen can be supplied to the oxide semiconductor layer 204-1. This is preferable because oxygen defects in the oxide semiconductor layer 204-1 can be repaired.

[0051] A planarization film 207 is provided on the conductive layer 208-1 and the insulating film 205. The planarization film 207 is provided to reduce unevenness of various wirings constituting the transistor Tr. When the display device 10 is applied to a transparent display, it is preferable to remove the planarization film 207 in the aperture region of the pixel PIX. This makes it possible to suppress light absorption by the planarization film 207 in the aperture region. In FIG. 6, the planarization film 207 is provided at a position overlapping with the gate wirings GLn-1 to GLn+1 and the source wirings SL1 to SL4. In FIG. 7, the planarization film 207 is provided in a region overlapping with the conductive layer 206-4 and the transistor Tr. Since the planarization film 207 is removed in the aperture region of the pixel PIX, the planarization film 207 is not provided between the conductive layer 206-3 and the pixel electrode 216-1.

[0052] A transparent conductive layer 212 is provided on the planarization film 207. A conductive layer 214 is provided in contact with the transparent conductive layer 212. The transparent conductive layer 212 and the conductive layer 214 function as a capacitance line CW. The transparent conductive layer 212 and the conductive layer 214 are provided at positions overlapping with the gate lines GLn-1 to GLn+1 and the source lines SL1 to SL4 shown in FIG. 6. The conductive layer 214 also functions as a light blocking layer. In this embodiment, a configuration in which the conductive layer 214 is provided on the transparent conductive layer 212 will be described, but a configuration in which the transparent conductive layer 212 is provided on the conductive layer 214 may also be used. An insulating film 209 is provided on the conductive layer 214. Since the planarization film 207 is removed in the opening region, the insulating film 209 is in contact with the insulating film 205 in the opening region. A pixel electrode 216-1 is provided on the insulating film 209. The pixel electrode 216-1 is connected to the conductive layer 206-3 through a contact hole provided in the insulating films 205 and 209. The pixel electrode 216-1 is provided in an opening region of the pixel PIX. The pixel electrode 216-1 does not cover the source line SL and the transistor Tr, but covers a part of the conductive layer 206-3.

[0053] 7, on the planarization film 207 overlapping with the transistor Tr, an end of the transparent conductive layer 212 is provided between an end of the conductive layer 214 and the pixel electrode 216-1. By disposing in this manner, the transistor Tr can be shielded from light and the light transmittance in the opening region can be improved.

[0054] The counter substrate 152 is provided to face the array substrate 150. The counter substrate 152 is provided with a light-shielding layer 219, a common electrode 218, and an insulating film 221. The light-shielding layer 219 functions as a black matrix. In the structure shown in FIG. 7, the light-shielding layer 219 is provided in a region overlapping with the conductive layer 206-4. The light-shielding layer 219 is arranged in a lattice shape so as to cover the gate lines GLn-1 to GLn+1 and the source lines SL1 to SL4. The common electrode 218 has a size that spreads over the entire display area 112. The light-shielding layer 160 may be formed of a metal film, and functions as an auxiliary electrode by being provided in contact with the common electrode 218 formed of a transparent conductive film. A liquid crystal layer 210 is provided between the array substrate 150 and the counter substrate 152, and is sealed by a sealant 154 (see FIG. 1). The pixel electrode 216-1, the liquid crystal layer 210, and the common electrode 218 form a liquid crystal element LE.

[0055] As described above, in a display device, conductive layers of various thicknesses are laminated on the array substrate 150, which may cause unevenness on the top surface of the array substrate 150. When a plurality of spacers provided on the counter substrate 152 come into contact with the unevenness on the top surface of the array substrate 150, the cell gap varies. This reduces the display quality of the display device.

[0056] In addition, in the display region, the planarization film 207 is formed thick in order to suppress the formation of parasitic capacitance by the gate wiring GL and the source wiring SL and the conductive layer 214. The planarization film 207 is arranged in a lattice shape so as to cover the gate wiring GL and the source wiring SL. That is, the planarization film 207 is removed in the opening region of the pixel. When the thickness of the planarization film 207 exceeds 2 μm, if a resist is applied as a mask for processing the conductive film or insulating film formed on the planarization film 207, the applied resist may flow from above the planarization film 207 to the opening region. As a result, the thickness of the resist placed on the top of the planarization film 207 becomes thin, causing uneven application of the resist. If such a resist mask is used to process the conductive film or insulating film, processing defects occur in the conductive film or insulating film.

[0057] In order to suppress unevenness in the application of the resist formed on the top of the planarization film 207, the resist can be prevented from flowing from the top of the planarization film 207 to the opening region by increasing the thickness of the resist. This allows the resist to cover the top of the planarization film 207. However, it is difficult to remove a resist with a thick film thickness, and it is also difficult to fine the pattern. In addition, by applying the resist thickly, the concentration of the solvent in the resist changes according to the film thickness direction. For example, the concentration of the solvent is low on the surface of the resist and high on the bottom. The resist becomes harder when the concentration of the solvent is low, making it difficult to remove the resist, and the resist becomes softer when the concentration of the solvent is high, making it easier to remove the resist. Therefore, when the concentration of the solvent changes according to the film thickness direction of the resist, the shape of the mask deteriorates when the resist is exposed and developed. When applying the resist thickly, if the concentration of the solvent contained in the resist is reduced, unevenness in the concentration of the solvent in the film thickness direction of the resist is suppressed. It is possible to improve the shape of the resist by reducing the concentration of the solvent contained in the resist and extending the reduced pressure drying time after applying the resist. However, the processing time of the photolithography process is long, making it unsuitable for mass production.

[0058] In this way, it is difficult to form a resist mask with high accuracy on the thick and processed planarization film. Furthermore, a defective shape of the resist mask may cause processing defects of the conductive film and the insulating film, which may cause display defects of the display device.

[0059] Furthermore, in the case where an oxide semiconductor layer is used for a transistor in a display device, moisture contained in the planarizing film 207 may enter the oxide semiconductor layer, which may deteriorate the characteristics of the transistor. Therefore, it is necessary to remove moisture contained in the planarizing film.

[0060] In the display device 10 according to one embodiment of the present invention, the planarization film 207 reduces the parasitic capacitance between the gate wiring and the source wiring and the conductive layer 214, and improves the transmittance of the opening region. In this case, the planarization film 207 is provided with a protruding portion that protrudes above the surface of the transparent conductive layer provided on the planarization film, and the protruding portion functions as a spacer. The cell gap between the array substrate 150 and the counter substrate 152 is maintained by the protruding portion.

[0061] This allows the spacers, which are less affected by the unevenness of the conductive layers of various thicknesses formed on the array substrate 150, to come into contact with the counter substrate 152. This makes it possible to suppress the variation in the cell gap caused by the unevenness of the top surface of the array substrate 150. This makes it possible to improve the display quality of the display device. Also, the spacer formation process on the counter substrate 152 can be omitted.

[0062] Furthermore, by providing a protrusion on the planarization film 207, even if resist is applied, the resist is not applied to the upper part of the protrusion, but is applied to the region other than the protrusion. By removing the conductive film or insulating film on the upper part of the protrusion using such a resist mask, the upper part of the protrusion can be exposed from the conductive film or insulating film. This allows moisture contained in the planarization film 207 to be released from the exposed upper part of the protrusion during heat treatment in the manufacturing process of the display device. This makes it possible to suppress the moisture contained in the planarization film from penetrating into the oxide semiconductor layer, and to suppress deterioration of the characteristics of the transistor Tr.

[0063] In the following description, the region 250 where the gate line GL and the source lines SL1 to SL4 intersect will be described with reference to Figures 8 to 13. In Figures 8 to 13, the source lines SL2 and SL4 are column lines that drive the pixels PIX-A1 and PIX-A2, and the source lines SL1 and SL3 are column lines that drive the pixels PIX-B1 and PIX-B2.

[0064] FIG. 8 is a planar layout of the conductive layers 202-1 to 202-9, the oxide semiconductor layers 204-1 to 204-4, and the conductive layers 206-1 to 206-11 in the region 250. The conductive layers 202-1 to 202-9 are provided on the array substrate 150. The conductive layer 202-1 extends in the D1 direction, but has a region branching in the D2 direction. The conductive layers 202-2 to 202-9 extend in the D2 direction. The oxide semiconductor layers 204-1 to 204-4 are provided on the conductive layer 202-1 via the gate insulating film 203 (see FIG. 7). The oxide semiconductor layers 204-1 to 204-4 are arranged side by side in the D2 direction. In this embodiment, an example in which a transistor Tr is configured with four oxide semiconductor layers 204-1 to 204-4 is shown. The oxide semiconductor layer can be divided into a plurality of oxide semiconductor layers 204-1 to 204-4 to reduce the effect of heat generation. The number of oxide semiconductor layers is not particularly limited. In the oxide semiconductor layers 204-1 to 204-4, the conductive layer 202-1 reflects light guided through the glass substrate (array substrate 150) from the conductive layer 202-1 side toward the oxide semiconductor layers 204-1 to 204-4, making it difficult for light leakage to occur in the oxide semiconductor layers 204-1 to 204-4. The conductive layers 206-1 to 206-11 are provided on the gate insulating film 203 and the oxide semiconductor layers 204-1 to 204-4. The conductive layers 206-1, 206-2, and 206-11 extend in the D1 direction, and the conductive layers 206-3 to 206-10 extend in the D2 direction.

[0065] The conductive layer 202-1 overlaps with the conductive layers 206-1, 206-2, and 206-11. The conductive layer 202-1 is connected to the conductive layer 206-1 through a contact hole 213-1 provided in the gate insulating film 203, and is connected to the conductive layer 206-2 through a contact hole 213-2 provided in the gate insulating film 203. A region of the conductive layer 202-1 extending in the D1 direction functions as a gate wiring. A region of the conductive layer 202-1 extending in the D2 direction functions as a gate electrode.

[0066] The conductive layers 202-2 and 202-3 overlap with the conductive layer 206-4. The conductive layer 202-2 is connected to the conductive layer 206-4 through a contact hole 213-3 provided in the gate insulating film 203. The conductive layer 202-3 is connected to the conductive layer 206-4 through a contact hole 213-4 provided in the gate insulating film 203. The conductive layer 206-4 intersects with the conductive layer 202-1. The conductive layer 206-4 functions as a first source wiring SL1. In addition, a region of the conductive layer 206-4 that does not overlap with the conductive layers 202-2 and 202-3 functions as a source electrode of the transistor Tr. The conductive layer 206-3 functions as a drain electrode of the transistor Tr.

[0067] The conductive layer 202-4 overlaps with the conductive layer 206-5 and is connected to the conductive layer 206-5 through a contact hole 213-5 provided in the gate insulating film 203. The conductive layer 202-5 overlaps with the conductive layer 206-6 and is connected to the conductive layer 206-6 through a contact hole 213-6 provided in the gate insulating film 203. The conductive layer 206-5 is connected to the conductive layer 206-6 through the conductive layer 208-2 (see FIG. 9). As a result, the conductive layer 206-5, the conductive layer 206-6, and the conductive layer 208-2 function as a third source wiring SL3.

[0068] The conductive layer 202-6 overlaps with the conductive layer 206-7 and is connected to the conductive layer 206-7 through a contact hole 213-7 provided in the gate insulating film 203. The conductive layer 202-7 overlaps with the conductive layer 206-8 and is connected to the conductive layer 206-8 through a contact hole 213-8 provided in the gate insulating film 203. The conductive layer 206-7 is connected to the conductive layer 206-8 through a conductive layer 208-3 (see FIG. 9). The conductive layers 206-7, 206-8, and 208-3 function as a second source wiring SL2.

[0069] The conductive layer 202-8 overlaps with the conductive layer 206-9 and is connected to the conductive layer 206-9 through a contact hole 213-9 provided in the gate insulating film 203. The conductive layer 202-9 overlaps with the conductive layer 206-9 and the conductive layer 206-10. The conductive layer 202-9 is connected to the conductive layer 206-9 through a contact hole 213-10 provided in the gate insulating film 203. The conductive layer 202-9 is connected to the conductive layer 206-10 through a contact hole 213-11 provided in the gate insulating film 203. The conductive layer 206-9 has a region that intersects with the conductive layer 202-1. The conductive layer 206-9 and the conductive layer 206-10 function as a fourth source wiring SL4.

[0070] The conductive layer 202-1 overlaps with the conductive layer 206-11 and is connected to the conductive layer 206-11 through a contact hole 213-12 provided in the gate insulating film 203.

[0071] The conductive layer 202-9 and the conductive layer 206-8 have a bent region. The conductive layer 202-9 has a region where it overlaps with and intersects with the conductive layer 206-8. That is, the conductive layer 202-9 has a region where the second source wiring SL2 and the fourth source wiring SL4 intersect with each other.

[0072] 6, the conductive layer 202-2 and the conductive layer 206-5 have bent regions. The conductive layer 202-2 overlaps with the conductive layer 206-5 and has a region where they intersect. In other words, the first source wiring SL1 has a region where they intersect with the third source wiring SL3.

[0073] As shown in FIG. 8, the gate line GLn is configured by laminating a conductive layer 202-1 and conductive layers 206-1 and 206-2. The conductive layer 202-1 extends along the D1 direction. In the region where the gate line GLn intersects with the source lines SL1 to SL4, only the conductive layer 202-1 is provided, and the conductive layer 206-1 and the conductive layer 206-2 are provided separately. In the source line SL1, the conductive layers 202-2, 202-3, and the conductive layer 206-4 are provided separately. In the region where the source line SL1 intersects with the gate line GLn, only the conductive layer 206-4 is provided, and the conductive layer 202-2 and the conductive layer 202-3 are provided separately. As a result, even if static electricity occurs during the manufacturing process of the display region 12 and the peripheral region 14 of the array substrate 150, the static electricity can be released, and the occurrence of defects caused by static electricity can be suppressed.

[0074] 9 is a planar layout of the conductive layers 206-1 to 206-11 and the conductive layers 208-1 to 208-3 in the region 250. The conductive layers 206-1 to 206-11 are as described in FIG. 8. The conductive layers 208-1 to 208-3 are provided on the insulating film 205 (see FIG. 7). The conductive layer 208-1 has a region extending in the D2 direction and a region extending in the D1 direction. The region extending in the D2 direction overlaps with the oxide semiconductor layers 204-1 to 204-5. The region extending in the D1 direction overlaps with the conductive layer 206-11 and is connected to the conductive layer 206-11 via a contact hole 215-7 provided in the insulating film 205. The conductive layer 208-2 extends in the D2 direction. The conductive layer 208-2 overlaps with the conductive layer 206-5 and the conductive layer 206-6, and is connected to the conductive layer 206-5 and the conductive layer 206-6 via contact holes 215-3 and 215-4 provided in the insulating film 205. The conductive layer 208-3 extends in the D2 direction. The conductive layer 208-3 overlaps with the conductive layer 206-7 and the conductive layer 206-8, and is connected to the conductive layer 206-7 and the conductive layer 206-8 via contact holes 215-5 and 215-6 provided in the insulating film 205.

[0075] FIG. 10 is a planar layout of the planarization film 207, the transparent conductive layer 212, and the conductive layer 214 in the region 250. The planarization film 207 is removed in the opening regions of the pixels PIX1 to PIX4 as shown in FIG. 7. That is, the planarization film 207 is provided on the gate wiring GL and the source wirings SL1 to SL4. The transparent conductive layer 212 is provided on the planarization film 207. Furthermore, the conductive layer 214 is provided on the transparent conductive layer 212. The transparent conductive layer 212 and the conductive layer 214 function as the capacitance wiring CW. The transparent conductive layer 212 is provided on the conductive layers 206-1 to 206-11 via the planarization film 207. Therefore, the source wirings SL1 to SL4 and the capacitance wiring CW are provided at a distance from each other, so that the conductive layer 214 is less susceptible to the effect of the potential from the capacitance wiring CW. Furthermore, the electrical resistance of the conductive layer 214 is smaller than the electrical resistance of the transparent conductive layer 212. This suppresses the variation in the potential of the capacitance wiring CW depending on the position of the pixel PIX in the display region 12. The transparent conductive layer 212 has an opening 223, and the conductive layer 214 has an opening 225. The opening 223 and the opening 225 are arranged to overlap each other. Inside the opening 223, the planarizing film 207 is exposed, and a spacer SP is arranged.

[0076] The transparent conductive layer 212 and the conductive layer 214 are provided in a lattice pattern so as to cover the gate lines GLn and the source lines SL1 to SL4. This reduces the storage capacitance C between the pixel electrodes 216 and the region where the transparent conductive layer 212 is not provided. The storage capacitance C is adjusted according to the size of the region where the transparent conductive layer 212 is not provided. The transparent conductive layer 212 may be provided over the entire surface instead of in a lattice pattern. The conductive layer 214 is provided so as to cover the transistor Tr. This makes it possible to suppress light leakage from the transistor Tr.

[0077] Although an example in which the conductive layer 214 is provided on the transparent conductive layer 212 is shown, the conductive layer 214 may be provided under the transparent conductive layer 212. The conductive layer 214 may be laminated with the transparent conductive layer 212. The conductive layer 214 has a light-shielding property. Therefore, the gate line GLn and the source lines SL1 to SL4 can be shielded from light. The width of the conductive layer 214 may be set to be larger than the combined width of the source lines SL1 to SL4 in a plan view. The width of the conductive layer 214 may be set to be larger than the combined width of the gate lines GLn in a plan view. This makes it possible to suppress the reflected light reflected at the edges of the source lines SL1 to SL4 from being emitted by the display panel 11. The width of the conductive layer 214 or the combined width of the source lines SL1 to SL4 refers to the length in the direction (D1 direction) intersecting the direction in which the source lines SL1 to SL4 extend. The width of the gate line GLn refers to the length in the direction (D2 direction) intersecting the direction in which the gate line GLn extends.

[0078] FIG. 11 shows a planar layout of the conductive layers 206-1 to 206-11 and the pixel electrodes 216-1 to 216-4 in the region 250. The conductive layers 206-1 to 206-11 are as described in FIG. 8. The pixel electrodes 216-1 to 216-4 are provided on the insulating film 209. The pixel electrodes 216-1 to 216-4 are provided in the aperture region of the pixel PIX. The pixel electrode 216-1 is connected to the conductive layer 206-3 via contact holes 217-1 and 217-2 provided in the insulating film 209 and contact holes 215-1 and 215-2 (see FIG. 9) provided in the insulating film 205. The insulating film 209 has an opening 217-3. The opening 217-3 is arranged to surround the spacer SP. Moreover, the opening 217-3 is provided so as to overlap with the opening 223 and the opening 225 (see FIG. 10). By providing the openings 223, 225, and the opening 217-3 on the planarization film 207, moisture contained in the planarization film 207 can be released from the exposed planarization film 207.

[0079] In the display area 12, the gate lines GL1 to GL4 and the source lines SL1 to SL4 are arranged so that the conductive layers 202 and 206 are stacked and extended. By arranging the source lines SL1 to SL4 so that the conductive layers 202 and 206 are stacked and extended, it is possible to equalize the resistance of the source lines SL1 to SL4 and the wiring capacitance. In addition, the source lines SL1 and SL3 can be arranged to cross each other, and the source lines SL2 and SL4 can be arranged to cross each other.

[0080] 12 is a diagram showing the overlapping of the conductive layer 202, the conductive layer 206, the conductive layer 208, the conductive layer 214, and the spacer SP in the region 250. FIG. 13 is a cross-sectional view taken along the line B1-B2 in FIG. 12 in the display region. FIG. 14 is a cross-sectional view taken along the line C1-C2 in FIG. 12 in the display region. At the intersection of the gate line GLn and the source line SL where the spacer SP is arranged, the gate line GLn is made of a conductive layer 202-1 having a thick film thickness, but the source line SL is made of conductive layers 208-2 and 208-3 having a thinner film thickness than the conductive layer 202 and the conductive layer 206 without providing a conductive layer having a thick film thickness. This allows the gate line GLn and the source line SL to cross each other without the conductive layers having a thick film thickness crossing each other.

[0081] As shown in FIG. 13 and FIG. 14, the spacer SP is disposed in a region where the conductive layer 202-1 intersects with the conductive layers 208-2 and 208-3. The spacer SP is a part of the planarization film 207, and is provided so that a part of the planarization film 207 protrudes upward from the surface of the transparent conductive layer 212. In the transparent conductive layer 212, an opening 223 is provided so as to surround the spacer SP. In the conductive layer 214, an opening 225 is provided so as to surround the spacer SP. Here, the end of the opening 225 is located outside the end of the opening 223. In the insulating film 209, an opening 217-3 is provided so as to surround the spacer SP. The insulating film 209 is in contact with the side surface of the spacer SP. Here, the area of ​​the opening 217-3 is smaller than the areas of the openings 223 and 225. Here, the thickness of the planarization film 207 from the surface of the nitride insulating film 205b to the upper surface of the protruding portion is defined as a thickness T1. Moreover, the thickness T2 is the thickness from the surface of the nitride insulating film 205b to the transparent conductive layer 212. The thickness T1 is about 3 μm, and the thickness T2 is about 2 μm.

[0082] The spacer SP is provided so as to be in contact with the surface of the counter substrate 152. The spacer SP may be in contact with the counter substrate 152 via a conductive film or an insulating film provided on the counter substrate 152. A light-shielding layer 219 is provided on the counter substrate 152. A common electrode 218 is provided in contact with the light-shielding layer 219. An insulating film 221 is provided in contact with the common electrode 218. An opening 232 is provided in the insulating film 221. By providing the opening 232 in the insulating film 221 and bringing the common electrode 218 and the spacer SP into contact with each other inside the opening 232, it is possible to improve the adhesion between the spacer SP and the common electrode 218. The area of ​​the opening 232 may be larger than the area of ​​the opening 217-3.

[0083] 8 and 12, the source wiring SL3 has a region where the conductive layer 202-4 and the conductive layer 206-5 overlap, and a region where the conductive layer 202-5 and the conductive layer 206-6 overlap. The conductive layer 206-5 is connected to the conductive layer 202-4 through a contact hole 213-5 provided in the gate insulating film 203. The conductive layer 206-6 is connected to the conductive layer 202-5 through a contact hole 213-6 provided in the gate insulating film 203. Here, the spacer SP is preferably provided in a region that does not overlap with the conductive layers 206-5, 206-6, 206-7, and 206-8.

[0084] Moreover, the spacer SP does not overlap the transistor Tr of the pixel PIX-B1 adjacent to the region where the conductive layer 202-1 intersects with the conductive layers 208-2 and 208-3. The transistor Tr is composed of a gate line GLn, a source line SL1, a conductive layer 206-3 (drain electrode), and an oxide semiconductor layer 204. Therefore, when the gate line GLn, the source line SL1, and the oxide semiconductor layer 204 overlap, unevenness occurs on the surface of the planarization film 207 provided on the transistor Tr. By not disposing the spacer SP on the transistor Tr, it is possible to reduce the variation in the cell gap.

[0085] In this embodiment, an example in which a plurality of spacers SP are arranged at all intersections of pixels arranged in a matrix has been described, but an embodiment of the present invention is not limited to this. A plurality of spacers SP may be arranged so as to have regularity with respect to the intersections of pixels arranged in a matrix. For example, the spacers SP may be arranged regularly so that one of the intersections is provided at one location. The spacers SP may also be provided in an area other than the intersections of the pixels. The heights of the plurality of spacers SP may all be the same, or the spacers SP of different heights may be provided among the plurality of spacers SP. For example, a main spacer SP that contacts the counter substrate 152 side and a sub spacer SP whose height is smaller than the cell gap may be provided.

[0086] <Surrounding Areas> Next, the spacers arranged in the peripheral region 14 of the display device 10 will be described with reference to FIGS.

[0087] FIG. 15 is a cross-sectional view of the display device 10 when the sealant 154 arranged in the peripheral area 14 near the common wiring area 22 is cut in the direction D1.

[0088] In FIG. 15, conductive layers 202-21, 202-22, and 202-23 are provided on the array substrate 150. A nitride insulating film 203a, an oxide insulating film 203b, an oxide insulating film 205a, and a nitride insulating film 205b are provided on the conductive layers 202-21, 202-22, and 202-23. A planarizing film 207 is disposed in an area overlapping with the conductive layers 202-21, 202-22, and 202-23, and the planarizing film 207 is provided with protruding portions that function as spacers SP-1, SP-2, and SP-3. Each of the spacers SP-1 to SP-3 protrudes from the surface of the transparent conductive layer 212. An opening of the transparent conductive layer 212 is disposed so as to surround the spacer SP-1 of the planarizing film 207, and an opening of the conductive layer 214 is disposed. Moreover, an opening is arranged in the transparent conductive layer 212 so as to surround the spacer SP-2, and an opening is arranged in the transparent conductive layer 212 so as to surround the spacer SP-3. The spacer SP-1, the spacers SP-2, and SP-3 contact the common electrode 218. The spacer SP-1 is arranged at a position where the sealant 154 is provided.

[0089] FIG. 16 is a cross-sectional view of the display device 10 when the sealant 154 arranged in the peripheral region 14 near the terminal portion 36 is cut in the direction D2.

[0090] In FIG. 16, conductive layers 202-24, 202-25, 202-26, and 202-27 are provided on the array substrate 150. A nitride insulating film 203a, an oxide insulating film 203b, an oxide insulating film 205a, and a nitride insulating film 205b are provided on the conductive layers 202-24, 202-25, 202-26, and 202-27. The planarizing film 207 is different from the planarizing film 207 shown in FIG. 15 in that the planarizing film 207 is provided overlapping the multiple conductive layers 202-24, 202-25, and 202-26. In addition, the planarizing film 207 overlapping the conductive layers 202-24 to 202-26 has protruding portions that function as spacers SP-4 and spacers SP-5. The spacers SP-4 and SP-5 protrude above the surface of the transparent conductive layer 212. Two openings are arranged in the transparent conductive layer 212 so as to surround the spacers SP-4 and SP-5 of the planarization film 207, and two openings are arranged in the conductive layer 214. A protrusion functioning as the spacer SP-5 is provided in the planarization film 207 overlapping with the conductive layer 202-27. An opening is arranged in the transparent conductive layer 212 so as to surround the spacer SP-5.

[0091] 15 and 16, the planarization film 207, the transparent conductive layer 212, and the conductive layer 214 are arranged in a lattice pattern on various wirings. On the array substrate 150, the planarization film 207 may be formed as a single layer, or may be divided into multiple layers. Similarly, each of the transparent conductive layer 212 and the conductive layer 214 may be formed as a single layer, or may be divided into multiple layers.

[0092] In this embodiment, the spacers SP arranged in the peripheral region are formed to have approximately the same height, but the embodiment of the present invention is not limited to this. In the peripheral region, among the multiple spacers SP, spacers SP of different heights may be provided. For example, a main spacer SP that contacts the counter substrate 152 side and a sub spacer SP whose height is smaller than the cell gap may be provided.

[0093] Usually, a display device is manufactured using a large mother substrate. At this time, after forming a plurality of display regions on the mother substrate, a sealant is applied and the mother substrate is bonded to the counter substrate. Then, the mother substrate and the counter substrate are cut between adjacent display regions to cut out individual display panels. At this time, a planarizing film and a protruding portion are formed using an organic resin along a cut line for cutting the mother substrate and the counter substrate. Both the planarizing film and the protruding portion provided along the cut line are, for example, line-shaped. Alternatively, the planarizing film may be line-shaped, and the protruding portion may be dot-shaped. By providing the planarizing film and the protruding portion along the cut line, they function as a liquid crystal contamination prevention wall.

[0094] <Method of forming planarizing film and spacer> Next, a method for manufacturing a display device according to an embodiment of the present invention will be described with reference to Fig. 17A to Fig. 20B. Specifically, a method for forming a planarizing film 207 and spacers SP, and forming a transparent conductive layer 212, a conductive layer 214, an insulating film 209, and a pixel electrode 216 will be described. First, a method for forming the planarizing film 207 and spacers SP using an organic resin will be described with reference to Fig. 17A to Fig. 18A.

[0095] 17A to 18A are diagrams for explaining the process of applying an organic resin 242 that will become the planarization film 207 onto the array substrate 150 and performing multi-tone exposure. Here, the conductive layer, insulating film, and oxide semiconductor layer provided under the organic resin 242 are omitted from the illustration. As shown in FIG. 17A, the organic resin 242 is applied onto the array substrate 150. A positive organic resin is used as the material of the organic resin 242 that functions as the planarization film 207. The positive organic resin is softened by irradiation with light (mainly ultraviolet light). Here, the film thickness of the organic resin 242 is about 3.0 μm.

[0096] As shown in FIG. 17B, the organic resin 242 is exposed to light using a multi-tone mask 240. A gray-tone mask or a half-tone mask may be used as the multi-tone mask 240. The gray-tone mask has a light-shielding portion, a transmission portion, and a gray-tone portion. The gray-tone portion has a slit that is equal to or smaller than the resolution of the exposure machine, thereby adjusting the amount of light transmitted. The half-tone mask has a function of adjusting the amount of light transmitted by a semi-transmitting film. By performing exposure using the multi-tone mask 240, an unexposed region 244, an intermediately exposed region 246, and an exposed region 248 can be formed in the organic resin 242. Here, the unexposed region 244 corresponds to the region where the spacer SP is formed, and the intermediately exposed region 246 corresponds to the region where the planarizing film 207 is formed. In the intermediately exposed region 246, a film thickness of 25% to 30% from the surface of the organic resin 242 is exposed to light.

[0097] Next, the exposed organic resin 242 is developed, thereby removing the organic resin in the intermediate exposed region 246 and the organic resin in the exposed region 248. This makes it possible to form spacers SP, part of which protrudes from the planarization film 207, as shown in Fig. 18. At this time, the planarization film 207 has a thickness T1 of about 3 µm, a thickness T2 of the region covering the gate wiring GL and the source wiring SL of about 2 µm, and a thickness T3 of the protruding portion functioning as the spacer SP of about 1 µm.

[0098] In one embodiment of the present invention, the method of forming the planarizing film 207 and the spacers SP is not limited to the method using the multi-tone mask 240. For example, two exposures may be performed, such as exposing the organic resin 242 with a mask having an opening corresponding to the shape of the spacers, and then exposing with a mask having an opening corresponding to the shape of the planarizing film. Alternatively, two photolithography steps may be performed, in which the planarizing film 207 is formed using a first layer of organic resin, a second layer of organic resin is further applied on the planarizing film 207, and spacers are formed on the planarizing film 207 using the second layer of organic resin.

[0099] Next, a method for forming the transparent conductive layer 212 to the pixel electrode 216 will be described with reference to FIGS. 18B to 20B.

[0100] FIG. 18B is a diagram for explaining the process of forming the transparent conductive layer 212 and the conductive layer 214. First, the transparent conductive layer 212 is formed on the insulating film 205 and the planarization film 207. An opening is formed in the transparent conductive layer 212 so as to surround the spacer SP. The conductive layer 214 is formed on the transparent conductive layer 212. An opening is formed in the conductive layer 214 so as to surround the spacer SP. After forming the transparent conductive layer 212, a heat treatment may be performed with the conductive film formed, or the conductive film may be etched to form the conductive layer 214, and then the heat treatment may be performed. Moisture can be released from the area where the planarization film 207 is exposed.

[0101] 19A is a diagram illustrating a process of forming an insulating film 209 so as to cover the transparent conductive layer 212, the conductive layer 214, and the spacer SP. The insulating film 209 is formed so as to cover the side and upper portion of the spacer SP. Although not shown, the insulating film 209 has a region in contact with the insulating film 205. In other words, in the opening region of the pixel, the insulating film 209 is in contact with the insulating film 205.

[0102] 19B is a diagram illustrating a process of forming a resist mask 252 on the insulating film 209. As described above, depending on the thickness of the resist mask 252, there may be regions where the upper part of the insulating film 209 is not formed and regions where it is formed. In this embodiment, the insulating film 209 on the upper part of the spacer SP is exposed by removing the resist mask 252 formed on the upper part of the spacer SP.

[0103] 20A is a diagram illustrating a process of performing an etching process using a resist mask 252. By performing the etching process, the insulating film 209 exposed on the upper part of the spacer SP can be removed. This makes it possible to expose the upper part of the spacer SP. After that, the resist mask 252 is removed. An opening in the transparent conductive layer 212, an opening in the conductive layer 214, and an opening in the insulating film 209 are arranged so as to surround the spacer SP. By performing a heat treatment in this state, moisture contained in the planarizing film 207 can be released from the exposed area of ​​the spacer SP.

[0104] 20B is a diagram illustrating a process of forming a pixel electrode 216 on the insulating film 209. The pixel electrode 216 is provided in an opening region of a pixel. In other words, the pixel electrode 216 is provided in a region from which the planarizing film 207 has been removed. After forming the pixel electrode 216, a heat treatment may be performed to release moisture contained in the planarizing film 207 from the exposed region of the spacer SP. Finally, a post-bake may be performed.

[0105] As described above, protrusions functioning as spacers SP can be formed on the planarization film 207. The transparent conductive layer 212, the conductive layer 214, and the insulating film 209 formed on the planarization film 207 block the release of moisture contained in the planarization film 207. Therefore, by exposing the upper portion of the spacer SP, the moisture contained in the planarization film 207 can be released by repeated heat treatment. This makes it possible to prevent moisture from penetrating into the oxide semiconductor layer formed under the planarization film 207. Therefore, it is possible to prevent deterioration of the transistor characteristics.

[0106] <Materials of the Components of the Display Device 10> The array substrate 150 and the counter substrate 152 may be rigid substrates that are light-transmitting and not flexible, such as a glass substrate, a quartz substrate, and a sapphire substrate. On the other hand, when the array substrate 150 and the counter substrate 152 need to be flexible, the array substrate 150 and the counter substrate 152 may be flexible substrates that contain resin and have flexibility, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate. In order to improve the heat resistance of the array substrate 150 and the counter substrate 152, impurities may be introduced into the above resin. In addition, when the display device 10 is applied to a transparent display or a large display, it is preferable to use glass substrates as the array substrate 150 and the counter substrate 152. In addition, the first transparent substrate 151A and the second transparent substrate 151B are provided to protect the array substrate 150 and the counter substrate 152. Therefore, it is preferable to use, for example, a light-transmitting glass substrate, a plastic substrate, or the like.

[0107] The gate insulating film 203, the insulating film 205, and the insulating film 209 are made of silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), Aluminum Nitride (AlN x ), aluminum oxide nitride (AlN x O y ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ) is used as a single layer or a laminated structure. In this embodiment, the gate insulating film 203 is composed of a laminated structure of a nitride insulating film 203a and an oxide insulating film 203b. The insulating film 205 is composed of an oxide insulating film 205a and a nitride insulating film 205b. Silicon nitride is used as the nitride insulating films 203a, 205b and the insulating film 209. The silicon nitride film is formed by, for example, chemical vapor deposition. Silicon oxide is used as the oxide insulating films 203b, 205a.

[0108] The above SiO x N y and AlO x N y is a silicon compound and an aluminum compound that contains a smaller ratio (x>y) of nitrogen (N) than oxygen (O). Also, SiN x O y and AlN x O y are silicon and aluminum compounds that contain a smaller proportion of oxygen than nitrogen (x>y).

[0109] The planarization film 207 can be made of an organic insulating material such as a polyimide resin, an acrylic resin, an epoxy resin, a silicone resin, a fluorine resin, or a siloxane resin.

[0110] Common metal materials can be used for the conductive layers 202, 206, 208 and the conductive layer 214. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof can be used for these members. The above materials may be used in a single layer or in a multilayer structure for the above members.

[0111] An oxide semiconductor having semiconductor properties can be used as the oxide semiconductor layer 204. The oxide semiconductor layer 204 has light-transmitting properties. For example, an oxide semiconductor containing two or more metals including indium (In) is used as the oxide semiconductor layer 204. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) may be used as the oxide semiconductor layer 204. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4 may be used. However, the oxide semiconductor layer 204 used in this embodiment is not limited to the above composition, and an oxide semiconductor having a composition different from the above may be used.

[0112] The transparent conductive layer 212, the pixel electrode 216, and the common electrode 218 can be made of a mixture of indium oxide and tin oxide (ITO) and a mixture of indium oxide and zinc oxide (IZO). Materials other than the above may be used for the transparent conductive layer. The light-shielding layer 219 used for the black matrix BM can be made of a black resin or metal material. The black matrix BM is formed in contact with the common electrode 218 (see FIG. 8). By forming the black matrix BM from a metal material, the common electrode 218, which is made of a transparent conductive film, can be made to function as an auxiliary electrode for reducing resistance loss. As the metal material for forming the black matrix BM, chromium, molybdenum, titanium, etc., which have a relatively low reflectance compared to aluminum, may be used in a single layer or in a laminated layer.

[0113] When the display device 10 is applied to a transparent display, it is preferable to use a polymer-dispersed liquid crystal as the liquid crystal layer 210. The polymer-dispersed liquid crystal includes a bulk and fine particles. The orientation of the fine particles changes in the bulk depending on the potential difference between the pixel electrode 216 and the common electrode 218. The potential of the pixel electrode 216 is individually controlled for each pixel PIX, so that at least the degree of either the light transmission or the light dispersion is controlled for each pixel PIX. The degree of scattering of the liquid crystal layer (fine particles) is controlled depending on the voltage of each pixel electrode 216 and the voltage of the common electrode 218. For example, the liquid crystal layer may use a polymer-dispersed liquid crystal in which the degree of scattering increases as the voltage between each pixel PIX and the common electrode 218 increases, or the degree of scattering increases as the voltage between each pixel electrode 216 and the common electrode 218 decreases.

[0114] In the liquid crystal layer 210, the ordinary light refractive index of the bulk and the particles are equal to each other. When no voltage is applied between the pixel electrode 216 and the common electrode 218, the difference in refractive index between the bulk and the particles is zero in all directions. The liquid crystal layer 210 is in a non-scattering state in which it does not scatter the light emitted from the light source. The light emitted from the light source propagates in a direction away from the light source (light emitting section) while being reflected by the first main surface of the array substrate 150 and the first main surface of the counter substrate 152. When the liquid crystal layer 210 is in a non-scattering state in which it does not scatter the light L emitted from the light source, the background of the counter substrate 152 is visible from the array substrate 150, and the background of the array substrate 150 is visible from the counter substrate 152.

[0115] Between the pixel electrode 216 and the common electrode 218 to which a voltage is applied, the optical axis of the particles is tilted by the electric field generated between the pixel electrode 216 and the common electrode 218. Since the optical axis of the bulk does not change due to the electric field, the directions of the optical axis of the bulk and the optical axis of the particles are different from each other. In the pixel PIX having the pixel electrode 216 to which a voltage is applied, the light emitted from the light source is scattered. As described above, a part of the scattered light emitted from the light source is radiated to the outside from the first main surface of the array substrate 150 or the first main surface of the counter substrate 152, and the light is observed by the observer.

[0116] In a pixel PIX having a pixel electrode 216 to which no voltage is applied, the background on the first main surface side of the counter substrate 152 is visible from the first main surface of the array substrate 150, and the background on the first main surface side of the array substrate 150 is visible from the first main surface of the counter substrate 152. When a video signal is input to the display device 10 of this embodiment, a voltage is applied to the pixel electrode 216 of the pixel PIX where an image is displayed, and the image based on the video signal is visible together with the background. In this way, when the polymer dispersed liquid crystal is in a scattering state, an image is displayed in the display region.

[0117] Although the preferred embodiment has been described above, the present disclosure is not limited to such an embodiment. The contents disclosed in the embodiment are merely examples, and various modifications are possible within the scope of the present disclosure. Appropriate modifications made within the scope of the present disclosure also naturally belong to the technical scope of the present disclosure. [Explanation of symbols]

[0118] 10: display device, 11: display panel, 12: display area, 14: peripheral area, 15A: first plane, 15B: second plane, 15C: first side, 16: common wiring, 18: common wiring, 22: common wiring area, 24: flexible printed circuit, 26: terminal section, 28: gate drive circuit, 32: gate wiring area, 34: flexible printed circuit, 36: terminal section, 38: source drive circuit, 42: source wiring area region, 46: ESD protection circuit, 48: gate inspection circuit, 52: source inspection circuit, 54: inspection line, 56: QD pad, 58: ESD protection circuit, 59: ESD protection circuit, 102: display panel, 104: light source, 110: light emission control circuit, 112: display region, 150: array substrate, 151A: first transparent substrate, 151B: second transparent substrate, 152: opposing substrate, 154: seal material, 160: light shielding layer, 202 : Conductive layer, 202: Conductive layer, 203: Gate insulating film, 204: Oxide semiconductor layer, 205: Insulating film, 206: Conductive layer, 207: Planarizing film, 208: Conductive layer, 209: Insulating film, 210: Liquid crystal layer, 212: Transparent conductive layer, 213: Contact hole, 214: Conductive layer, 215: Contact hole, 216: Pixel electrode, 217-1, 217-2: Contact hole, 217-3: Opening, 218: Common electrode , 219: light shielding layer, 221: insulating film, 223: opening, 225: opening, 232: opening, 240: multi-tone mask, 242: organic resin, 244: unexposed region, 246: intermediately exposed region, 248: exposed region, 250: region, 252: resist mask, BM: black matrix, C: storage capacitance, CW: capacitance wiring, GL: gate wiring, LE: liquid crystal element, PIX: pixel, SL: source wiring, SP: spacer

Claims

1. a first conductive layer provided on a first substrate and extending in a first direction; A first insulating film provided on the first conductive layer; a second conductive layer provided on the first insulating film and extending in a second direction intersecting the first direction; a second insulating film provided on the second conductive layer and extending in the first direction and the second direction; a first transparent conductive layer provided on the second insulating film and extending in the first direction and the second direction; a third insulating film provided on the first transparent conductive layer; a second substrate facing the first substrate, the second insulating film has a first protruding portion protruding above a surface of the first transparent conductive layer, a first opening surrounding the first protruding portion is provided in the first transparent conductive layer; a second opening portion surrounding the first protruding portion is provided in the third insulating film; A display device, wherein the first protrusion is provided to maintain a gap between the first substrate and the second substrate.

2. The display device according to claim 1 , wherein the third insulating film is in contact with a side surface of the first protruding portion.

3. The display device according to claim 1 , wherein the third insulating film has a second region in contact with the first insulating film.

4. The display device according to claim 1 , wherein the second conductive layer has a thickness smaller than a thickness of the first conductive layer.

5. a third conductive layer provided between the first transparent conductive layer and the third insulating film; a third opening is provided in the third conductive layer to surround the first protruding portion; The display device according to claim 1 , wherein an end of the third opening is positioned outside an end of the first opening.

6. The display device according to claim 1 , wherein the first protrusion is provided in a first region where the first conductive layer intersects with the second conductive layer.

7. The display device according to claim 6 , wherein the first protrusion does not overlap a transistor of a pixel provided adjacent to the first region.

8. a fourth conductive layer provided on the first substrate and formed of the same layer as the first conductive layer; the second insulating film has a second protruding portion protruding above a surface of the first transparent conductive layer, a fourth opening surrounding the second protruding portion is provided in the first transparent conductive layer; a fifth opening is provided in the third insulating film to surround the second protruding portion; The display device according to claim 1 , wherein the second protrusion is in contact with a front surface side of the second substrate.

9. A seal material is further provided at a peripheral portion of the first substrate to bond the second substrate to the first substrate, The display device according to claim 8 , wherein the sealing material is in contact with the second protruding portion.

10. a liquid crystal layer provided between the first substrate and the second substrate; The display device according to claim 1 , further comprising: a light source arranged so that light enters toward a side surface of the first substrate or a side surface of the second substrate.

11. the liquid crystal layer is a polymer dispersed liquid crystal; When the polymer dispersed liquid crystal is in a scattering state, an image is displayed in a display area; The display device according to claim 10 , wherein when the polymer dispersed liquid crystal is in a non-scattering state, in the display area, the background of the second substrate is visible from the first substrate, and the background of the first substrate is visible from the second substrate.

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