Cache controller and arithmetic processing device

Abstract

To provide a cache controller that effectively utilizes capacity of a cache memory to improve a cache hit ratio.SOLUTION: In a multi-core processing device 10, a control module 31 compresses, when an address range is specified by a CPU 30, data in an address range and stores the compressed data in an LLC (Last Level Cache) 3; stores, when the address range is not specified by the CPU 30, the data in the LLC 3 without compressing it; increases, when the number of compressed ways, which indicates the number of entries in which the number of divided ways and the compression ratio of data are equal, is less than a threshold value, the number of divided ways; and, when the number of compressed ways is equal to or greater than the threshold value, compresses unused divided ways as non-divided ways, or stores uncompressed data in the LLC 3 without dividing the data.SELECTED DRAWING: Figure 3

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