Digital phase shift circuit and digital phase shifter

Abstract

To provide a digital phase shift circuit and a digital phase shifter that are smaller than conventional ones and can achieve desired phase shift characteristics.SOLUTION: A digital phase shift circuit B includes: a signal line 10; a first line 21 including a first parallel line 21p1; a second line 22 including a second parallel line 22p2; a third line 23 connected to one end of the second parallel line 22p2 and including a first crossing line 23c1, a third parallel line 23p3, and a second crossing line 23c2; a first ground conductor 31; a second ground conductor 32; a first electronic switch 41; and a second electronic switch 42. The signal line 10 is located between the first parallel line 21p1 and the second parallel line 22p2. A cross-sectional area of the third line 23 is smaller than cross-sectional areas of the signal line 10, the first line 21, and the second line 22.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a digital phase shift circuit and a digital phase shifter. [Background technology]

[0002] The following Non-Patent Document 1 discloses a digitally controlled phase shift circuit (digital phase shift circuit) for microwaves, quasi-millimeter waves, or millimeter waves. As shown in FIG. 2 of Non-Patent Document 1, this digital phase shift circuit includes a signal line, a pair of inner lines, a pair of outer lines, a first ground bar, a second ground bar, and a pair of NMOS switches. The pair of inner lines are provided on both sides of the signal line. The pair of outer lines are provided outside the pair of inner lines. The first ground bar is connected to one end of each of the inner lines and each of the outer lines. The second ground bar is connected to the other end of each of the outer lines. Each NMOS switch is provided between the other end of each of the inner lines and the second ground bar.

[0003] Such a digital phase shift circuit switches the operation mode between a low delay mode and a high delay mode by switching the return current flowing in the pair of inner lines or the pair of outer lines due to the transmission of a signal wave in the signal line depending on whether the pair of NMOS switches are open or closed. That is, the digital phase shift circuit operates in the low delay mode when the return current flows in the pair of inner lines, and in the high delay mode when the return current flows in the pair of outer lines. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] A Ka-band Digitally-Controlled Phase Shifter with sub-degree Phase Precision (2016,IEEE,RFIC) Summary of the Invention [Problem to be solved by the invention]

[0005] In the digital phase shift circuit described above, in order to secure the amount of phase shift in a limited area, it is desirable to make the inductance, which is one of the circuit constants, sufficiently larger in the high delay mode than in the low delay mode. However, in the conventional digital phase shift circuit described above, in order to increase the inductance value in the high delay mode, it is necessary to separate the outer line from the signal line (or increase the length of the outer line), which increases the size. Since the digital phase shifter is configured by cascading a plurality of digital phase shift circuits, there is a problem that the digital phase shifter becomes large when the size of the digital phase shift circuit increases.

[0006] The present invention has been made in consideration of the above circumstances, and has an object to provide a digital phase shift circuit and a digital phase shifter that are smaller than conventional ones and can achieve desired phase shift characteristics. [Means for solving the problem]

[0007] In order to solve the above problem, a digital phase shift circuit (B, B', B'') according to a first aspect of the present invention includes a signal line (10), a first line (21) including a first parallel line (21p1) extending parallel to the signal line, a second line (22) including a second parallel line (22p2) extending parallel to the signal line, a first crossing line (23c1) connected to one end of the second parallel line and extending away from the signal line in a crossing direction (Y) that crosses a longitudinal direction of the signal line from one end of the second parallel line in a plan view, a third parallel line (23p3) extending parallel to the signal line from one end of the first crossing line, and a third parallel line (23p4) extending parallel to the signal line from one end of the third parallel line in the crossing direction. the first parallel line and the second parallel line; a first ground conductor (31) electrically connected to one end of the first parallel line and one end of the second parallel line; a second ground conductor (32) electrically connected to one end of the third line; a first electronic switch (41) provided between the other end of the first parallel line and the second ground conductor; and a second electronic switch (42) provided between the other end of the second parallel line and the second ground conductor, wherein the signal line is located between the first parallel line and the second parallel line, and a cross-sectional area of ​​the third line is smaller than cross-sectional areas of the signal line, the first line, and the second line.

[0008] In the digital phase shift circuit according to the first aspect of the present invention, in a low delay mode in which the first electronic switch and the second electronic switch are set to a closed state, a first return current flows in the first parallel line that is a part of the first line, and a second return current flows in the second parallel line that is a part of the second line. In contrast, in a high delay mode in which the first electronic switch and the second electronic switch are set to an off state, a third return current flows in a third line (the second crossing line, the third parallel line, and the first crossing line) whose cross-sectional area is smaller than the cross-sectional areas of the signal line, the second line, and the second line. This allows the inductance value to be increased, making it possible to achieve desired phase shift characteristics in a smaller size than before.

[0009] A digital phase shift circuit according to a second aspect of the present invention is the digital phase shift circuit according to the first aspect of the present invention, wherein the third line has a thickness smaller than that of the signal line, the first line, and the second line.

[0010] A digital phase shift circuit according to a third aspect of the present invention is the digital phase shift circuit according to the first or second aspect of the present invention, wherein the third line is formed in an inner layer than the first line and the second line.

[0011] A digital phase shift circuit according to a fourth aspect of the present invention is a digital phase shift circuit according to any one of the first to third aspects of the present invention, wherein the third line has a plurality of holes (H) formed along the third line.

[0012] A digital phase shift circuit according to a fifth aspect of the present invention is a digital phase shift circuit according to any one of the first to fourth aspects of the present invention, further comprising a capacitor (60) connected to one end of the signal line and a third electronic switch (43) provided between the capacitor and the first ground conductor, one end of the first ground conductor extending away from the signal line in the crossing direction and connected to the third electronic switch.

[0013] A digital phase shift circuit according to a sixth aspect of the present invention is the digital phase shift circuit according to the fifth aspect of the present invention, wherein the first electronic switch, the second electronic switch and the third electronic switch are field effect transistors, and the size of the field effect transistors constituting the first electronic switch and the second electronic switch is at least twice the size of the field effect transistor constituting the third electronic switch.

[0014] A digital phase shift circuit according to a seventh aspect of the present invention is a digital phase shift circuit according to any one of the first to sixth aspects of the present invention, further comprising a first upper pad (21d2) provided at the other end of the first parallel line and a second upper pad (22d2) provided at the other end of the second parallel line, wherein the maximum value of the dimension of the first upper pad in the intersecting direction is greater than the width of the first parallel line, and the maximum value of the dimension of the second upper pad in the intersecting direction is greater than the width of the second parallel line.

[0015] A digital phase shift circuit according to an eighth aspect of the present invention is the digital phase shift circuit according to the seventh aspect of the present invention, further comprising a first lower pad (33a) connected to the first upper pad via a via (50) and to which the first electronic switch is connected, and a second lower pad (33b) connected to the second upper pad via a via (50) and to which the second electronic switch is connected, wherein a maximum value of a dimension of the first lower pad in the cross direction is greater than a maximum value of a dimension of the first upper pad in the cross direction, and a maximum value of a dimension of the second lower pad in the cross direction is greater than a maximum value of a dimension of the second upper pad in the cross direction.

[0016] A digital phase shift circuit according to a ninth aspect of the present invention is the digital phase shift circuit according to any one of the first to eighth aspects of the present invention, further comprising a fourth electronic switch (44) provided between one end of the signal line and the first ground conductor.

[0017] The digital phase shifter according to the first aspect of the present invention includes a plurality of digital phase shift circuits (B1 to B n ) are connected in cascade, each of the digital phase shift circuits is a digital phase shift circuit according to any one of the first to ninth aspects, and in a portion where the digital phase shift circuits are adjacent to each other, the first ground conductor and the second ground conductor are common, and the first intersecting line and the second intersecting line are crank-shaped.

[0018] A digital phase shifter according to a second aspect of the present invention is a digital phase shifter according to the first aspect of the present invention, wherein at least one of the digital phase shift circuits has a distance (D1) between a center line of the second parallel line and a center line of the third parallel line in the intersecting direction different from the other digital phase shift circuits.

[0019] The digital phase shifter according to the third aspect of the present invention includes a plurality of digital phase shift circuits (B1 to B n ) are cascade-connected, at least two of the digital phase shift circuits being specific digital phase shift circuits are digital phase shift circuits according to the fourth aspect, and in a portion where the digital phase shift circuits are adjacent to each other, the first ground conductor and the second ground conductor are common, and the first intersecting line and the second intersecting line are crank-shaped.

[0020] A digital phase shifter according to a fourth aspect of the present invention is the digital phase shifter according to the first aspect of the present invention, wherein the third lines of the digital phase shifting circuits are formed in the same layer.

[0021] A digital phase shifter according to a fifth aspect of the present invention is the digital phase shifter according to the first aspect of the present invention, wherein the third line of at least one of the digital phase shift circuits is formed in a layer different from the third line of the other digital phase shift circuits. Effect of the Invention

[0022] According to the present invention, it is possible to realize a desired phase shift characteristic in a smaller size than before. [Brief description of the drawings]

[0023] [Figure 1] 1 is a plan view showing a basic configuration of a digital phase shift circuit according to a first embodiment of the present invention. [Diagram 2] 2 is a cross-sectional view taken along line II-II in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line III-III in FIG. [Figure 4] 2 is a plan view showing the connection relationship between connection pads and first and second electronic switches in the digital phase shift circuit according to the first embodiment of the present invention. FIG. [Diagram 5] 1 is a plan view showing a configuration of a main part of a digital phase shifter according to a first embodiment of the present invention. [Figure 6] FIG. 11 is a plan view showing a basic configuration of a digital phase shift circuit according to a second embodiment of the present invention. [Figure 7] FIG. 11 is a plan view showing a configuration of a main part of a digital phase shifter according to a second embodiment of the present invention. [Figure 8] FIG. 11 is a plan view showing a basic configuration of a digital phase shift circuit according to a third embodiment of the present invention. [Figure 9] FIG. 11 is a plan view showing a configuration of a main part of a digital phase shifter according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Hereinafter, a digital phase shift circuit and a digital phase shifter according to an embodiment of the present invention will be described in detail with reference to the drawings. In addition, in the drawings referred to below, the dimensions of each component are appropriately changed as necessary to facilitate understanding.

[0025] [First embodiment] Digital phase shift circuit Fig. 1 is a plan view showing a basic configuration of a digital phase shift circuit according to a first embodiment of the present invention, Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1, and Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1.

[0026] As shown in FIG. 1, the digital phase shift circuit B includes a signal line 10, a first line 21, a second line 22, a third line 23, an upper pad 24, an upper pad 25, a first ground conductor 31, and a second ground conductor 32. The first line 21 in this embodiment includes a first parallel line 21p1 and a pair of upper pads 21d1 and 21d2. The second line 22 in this embodiment includes a second parallel line 22p2 and a pair of upper pads 22d1 and 22d2. The third line 23 in this embodiment includes a first cross line 23c1, a third parallel line 23p3, a bent line 23b, and a second cross line 23c2. Moreover, the digital phase shift circuit B in this embodiment includes four electronic switches 41 to 44, a plurality of connection conductors 50, a capacitor 60, and a plurality of connection pads P1 to P4 (see also FIGS. 2 and 3).

[0027] As shown in Fig. 1, the signal line 10 is a linear strip-shaped conductor extending in one direction. That is, the signal line 10 is a long, plate-shaped conductor having a constant width, a constant thickness, and a predetermined length. A signal current flows through the signal line 10 from the left side of the paper in Fig. 1 to the right side of the paper, that is, from the end (input end) on the left side of the paper to the end (output end) on the right side of the paper. This signal current is a high-frequency signal having a wavelength range of the microwave, quasi-millimeter wave, or millimeter wave described above.

[0028] Here, in this embodiment, the longitudinal direction of the signal line 10 (the direction in which the signal line 10 extends) is simply referred to as the longitudinal direction X. The direction from the input end to the output end of the signal line 10 along the longitudinal direction X is referred to as the +X direction or rightward. The direction opposite to the rightward is referred to as the leftward or -X direction. The direction intersecting (e.g., perpendicular to) the signal line 10 is referred to as the crossing direction Y. One direction along the crossing direction Y is referred to as the back side or +Y direction. The direction opposite to the back side is referred to as the front side or -Y direction. The direction intersecting (e.g., perpendicular to) both the longitudinal direction X and the crossing direction Y is referred to as the up-down direction Z. One direction along the up-down direction Z is referred to as the up-down direction or +Z direction. The direction opposite to up is called down or -Z direction. Viewing from the up-down direction Z is called planar view.

[0029] The signal line 10 has an inductance L1 as a lumped constant circuit element electrically. This inductance L1 is a parasitic inductance having a size according to the shape of the signal line 10, such as the length of the signal line 10. The signal line 10 also has a capacitance C1 as a lumped constant circuit element electrically. This capacitance C1 is a parasitic capacitance between the signal line 10 and a first parallel line 21p1 (described in detail below), between the signal line 10 and a second parallel line 22p2 (described in detail below), between the signal line 10 and a third parallel line 23p3 (described in detail below), between the signal line 10 and a silicon substrate (not shown), or the like.

[0030] The first parallel line 21p1 is a linear strip-shaped conductor provided on the other side (-Y side) of the signal line 10. The first parallel line 21p1 is a long plate-shaped conductor having a constant width, a constant thickness, and a predetermined length. The first parallel line 21p1 extends parallel to the signal line 10 (longitudinal direction X). The first parallel line 21p1 and the signal line 10 are arranged at an interval in the intersecting direction Y.

[0031] The upper pad 21d1 is a rectangular flat plate conductor connected to one end (-X side) of the first parallel line 21p1. The long side of the upper pad 21d1 extends in the cross direction Y, and the short side of the upper pad 21d1 extends in the longitudinal direction X. One short side (+Y side) of the upper pad 21d1 is located at approximately the same position in the cross direction Y as one side edge (+Y side) of the first parallel line 21p1. The other short side (-Y side) of the upper pad 21d1 is located closer to the front (-Y side) than the other side edge (-Y side) of the first parallel line 21p1. That is, the dimension of the upper pad 21d1 in the cross direction Y is larger than the width (dimension in the cross direction Y) of the first parallel line 21p1.

[0032] The upper pad 21d2 is a rectangular flat plate conductor connected to the other end (+X side) of the first parallel line 21p1. The long side of the upper pad 21d2 extends in the cross direction Y, and the short side of the upper pad 21d2 extends in the longitudinal direction X. One short side (+Y side) of the upper pad 21d2 is located at approximately the same position in the cross direction Y as one side edge (+Y side) of the first parallel line 21p1. The other short side (-Y side) of the upper pad 21d2 is located closer to the front (-Y side) than the other side edge (-Y side) of the first parallel line 21p1. That is, the dimension of the upper pad 21d2 in the cross direction Y is larger than the width (dimension in the cross direction Y) of the first parallel line 21p1.

[0033] The second parallel line 22p2 is a linear strip-shaped conductor provided on one side (+Y side) of the signal line 10. The second parallel line 22p2 is a long plate-shaped conductor having a constant width, a constant thickness, and a predetermined length. The second parallel line 22p2 extends parallel to the signal line 10 (longitudinal direction X). The second parallel line 22p2 and the signal line 10 are arranged with a gap between them in the intersecting direction Y.

[0034] The second parallel line 22p2 is provided on the opposite side of the signal line 10 to the first parallel line 21p1. In other words, the second parallel line 22p2 is disposed such that the signal line 10 is located between the first parallel line 21p1 and the second parallel line 22p2 in the cross direction Y.

[0035] The upper pad 22d1 is a rectangular flat conductor connected to one end (-X side) of the second parallel line 22p2. The long side of the upper pad 22d1 extends in the cross direction Y, and the short side of the upper pad 22d1 extends in the longitudinal direction X. The other short side (-Y side) of the upper pad 22d1 is located at approximately the same position in the cross direction Y as the other side edge (-Y side) of the second parallel line 22p2. In addition, one short side (+Y side) of the upper pad 22d1 is located on the back side (+Y side) of one side edge (+Y side) of the second parallel line 22p2. In other words, the dimension of the upper pad 22d1 in the cross direction Y is larger than the width (dimension in the cross direction Y) of the second parallel line 22p2.

[0036] The upper pad 22d2 is a rectangular flat plate conductor connected to the other end (+X side) of the second parallel line 22p2. The long side of the upper pad 22d2 extends in the cross direction Y, and the short side of the upper pad 22d2 extends in the longitudinal direction X. The other short side (-Y side) of the upper pad 22d2 is located at approximately the same position in the cross direction Y as the other side edge (-Y side) of the second parallel line 22p2. In addition, one short side (+Y side) of the upper pad 22d2 is located on the back side (+Y side) of one side edge (+Y side) of the second parallel line 22p2. In other words, the dimension of the upper pad 22d2 in the cross direction Y is larger than the width (dimension in the cross direction Y) of the second parallel line 22p2.

[0037] The third line 23 is formed on a layer different from the layer on which the signal line 10, the first line 21, the second line 22, the upper pad 24, and the upper pad 25 are formed, and the layer on which the first ground conductor 31 and the second ground conductor 32 are formed. For example, the third line 23 is formed on a layer on which the second intermediate pads 71b, 72b, 73b, and 74b (details will be described later) shown in Figures 2 and 3 are formed. The third line 23 may be formed on a layer on which the third intermediate pads 71c, 72c, 73c, and 74c (details will be described later) shown in Figures 2 and 3 are formed.

[0038] The reason for forming the third line 23 in such a layer is to make the thickness (cross-sectional area) of the third line 23 smaller than the thickness (cross-sectional area) of the signal line 10, the first line 21, and the second line 22. In general, in a semiconductor having a multi-layer structure, the thickness of the wiring is formed to be smaller from the surface to the inner layer. For this reason, in this embodiment, the third line 23 is formed in a layer lower than the layer in which the signal line 10, the first line 21, the second line 22, the upper pad 24, and the upper pad 25 are formed, thereby making the thickness (cross-sectional area) of the third line 23 smaller than the thickness (cross-sectional area) of the signal line 10, the first line 21, and the second line 22.

[0039] Although details will be described later, the reason why the thickness of the third line 23 is made smaller than the thicknesses of the signal line 10, the first line 21, and the second line 22 is to increase the strength of the magnetic field generated by the current (third return current) flowing through the third line 23 and to increase the resistance of the third line 23. It is desirable to set the thickness of the third line 23 so that the cross-sectional area of ​​the third line 23 is less than 1 / 5 of the cross-sectional areas of the signal line 10, the first line 21, and the second line 22.

[0040] The first cross line 23c1 is a strip-shaped conductor electrically connected to one end (-X side) of the second parallel line 22p2. A bent portion CR1 is formed in the first cross line 23c1, and a side closer to the second parallel line 22p2 (for example, a side closer to the second parallel line 22p2 than the midpoint of the first cross line 23c1 in the Y direction) is crank-shaped. In a plan view, the first cross line 23c1 extends from one end (-X side) of the second parallel line 22p2 so as to move away from the signal line 10 in the cross direction Y, bends to the right (+X side) at the bent portion CR1, and then extends again so as to move away from the signal line 10 in the cross direction Y.

[0041] The third parallel line 23p3 is a linear strip-shaped conductor connected to one end (+Y end) of the first cross line 23c1. The third parallel line 23p3 is a long plate-shaped conductor having a constant width, a constant thickness, and a predetermined length. The third parallel line 23p3 extends from one end (+Y side) of the first cross line 23c1 in parallel (longitudinal direction X) with the signal line 10. That is, the third parallel line 23p3 in this embodiment extends from one end (+Y side) of the first cross line 23c1 toward the right side (+X side). The length of the third parallel line 23p3 is shorter than the length of the second parallel line 22p2.

[0042] The third parallel line 23p3 is provided on one side (+Y side) of the signal line 10, at a position farther from the signal line 10 than the second parallel line 22p2. In other words, the third parallel line 23p3 is disposed such that the second parallel line 22p2 is located between the signal line 10 and the third parallel line 23p3 in the cross direction Y.

[0043] As shown in FIG. 1, in the intersecting direction Y, the distance D1 between the center line of the second parallel line 22p2 and the center line of the third parallel line 23p3 is greater than the distance D2 between the center line of the second parallel line 22p2 and the far outer edge (the outer edge on the third parallel line 23p3 side) of the first ground conductor 31 (described later).

[0044] The bent line 23b is a strip-shaped conductor connected to one end (+X side) of the third parallel line 23p3 and having a bent portion CR. The bent line 23b is composed of a partial line 23b1 extending from one end (+X side) of the third parallel line 23p3 in the crossing direction Y so as to approach the signal line 10, and a partial line 23b2 extending from one end (-Y side) of the partial line 23b1 in parallel (longitudinal direction X) with the signal line 10. The partial lines 23b1 and 23b2 constituting the bent line 23b are long plate-shaped conductors having a constant width, a constant thickness, and a predetermined length. The length of the partial line 23b1 is shorter than the length of the first cross line 23c1. The bent line 23b may have a plurality of bent portions CR.

[0045] The second crossing line 23c2 is a strip-shaped conductor connected to one end (+X side) of the partial line 23b2 constituting the bent line 23b. The second crossing line 23c2 has a bent portion CR2, and the side closer to the second parallel line 22p2 (for example, the second parallel line 22p2 side of the midpoint of the second crossing line 23c2 in the Y direction) is crank-shaped. In a plan view, the second crossing line 23c2 extends from one end (+X side) of the partial line 23b2 constituting the bent line 23b so as to approach the signal line 10 in the crossing direction Y, bends to the right (+X side) at the bent portion CR2, and then extends again so as to approach the signal line 10 in the crossing direction Y.

[0046] In this embodiment, one end edge (-Y side) of the second intersecting line 23c2 is located at approximately the same position in the intersecting direction Y as one short side (-Y side) of the upper pads 22d1, 22d2 and one side edge (-Y side) of the second parallel line 22p2. The upper pad 22d2 and the second intersecting line 23c2 are arranged with an interval between them in the longitudinal direction X.

[0047] In addition, one end (-Y side) of the second cross line 23c2 in this embodiment is constantly electrically connected to the second ground conductor 32 (described later) by a conductor (not shown). In other words, one end of the third line 23 is constantly electrically connected to the second ground conductor 32 by a conductor (not shown).

[0048] The first intersecting line 23c1, the third parallel line 23p3, the bent line 23b, and the second intersecting line 23c2 described above configure a loop line that is convex toward the rear side (+Y side). In other words, the third line 23 is a loop line that is convex toward the rear side (+Y side).

[0049] The upper pad 24 is a rectangular flat plate conductor similar to the upper pads 21d1 and 21d2 that form a part of the first line 21. The long side of the upper pad 24 extends in the cross direction Y, and the short side of the upper pad 24 extends in the longitudinal direction X. One short side (+Y side) of the upper pad 24 is located at approximately the same position in the cross direction Y as one side edge (+Y side) of the first parallel line 21p1. The other short side (-Y side) of the upper pad 24 is located closer to the front (-Y side) than the other side edge (-Y side) of the first parallel line 21p1. That is, the dimension of the upper pad 24 in the cross direction Y is larger than the width (dimension in the cross direction Y) of the first parallel line 21p1, similar to the upper pads 21d1 and 21d2 that form a part of the first line 21. Similarly to one end (-Y side) of the second cross line 23c2, the upper pad 24 is constantly electrically connected to the second ground conductor 32 via a conductor (not shown).

[0050] The upper pad 25 is a rectangular flat plate conductor similar to the upper pads 22d1 and 22d2 that form a part of the second line 22. The long side of the upper pad 25 extends in the cross direction Y, and the short side of the upper pad 25 extends in the longitudinal direction X. The other short side (-Y side) of the upper pad 25 is located at approximately the same position in the cross direction Y as the other side edge (-Y side) of the second parallel line 22p2. In addition, one short side (+Y side) of the upper pad 25 is located on the inner side (+Y side) of one side edge (+Y side) of the second parallel line 22p2. In other words, the dimension of the upper pad 25 in the cross direction Y is larger than the width (dimension in the cross direction Y) of the second parallel line 22p2, similar to the upper pads 22d1 and 22d2 that form a part of the second line 22. Similarly to one end (-Y side) of the second cross line 23c2, the upper pad 25 is constantly electrically connected to the second ground conductor 32 by a conductor (not shown).

[0051] The first ground conductor 31 is a plate-shaped conductor provided on the input end side (-X side) of the signal line 10. The first ground conductor 31 is electrically grounded. The first ground conductor 31 has a rectangular shape with long sides extending in the cross direction Y and short sides extending in the longitudinal direction X. The first ground conductor 31 overlaps with the front side (-Y side) ends of the upper pads 21d1 and 22d1 and the first cross line 23c1 in the up-down direction Z. As shown in FIG. 2, the first ground conductor 31 is located below (-Z side) the signal line 10, the first line 21 (upper pad 21d1), the second line 22 (upper pad 22d1), and the third line 23 (first cross line 23c1).

[0052] The second ground conductor 32 is a plate-shaped conductor provided on the output end side (+X side) of the signal line 10. The second ground conductor 32 is electrically grounded. Although detailed illustration is omitted, the second ground conductor 32 is located below (on the -Z side) the signal line 10, the first line 21, the second line 22, the third line 23, and the upper pads 24 and 25.

[0053] 2, the first connection pad P1 includes the above-mentioned upper pad 21d1, the first intermediate pad 71a, the second intermediate pad 71b, the third intermediate pad 71c, and the first ground conductor 31. The upper pad 21d1, the first intermediate pad 71a, the second intermediate pad 71b, the third intermediate pad 71c, and the first ground conductor 31 overlap one another in a plan view. The upper pad 21d1, the first intermediate pad 71a, the second intermediate pad 71b, the third intermediate pad 71c, and the first ground conductor 31 are arranged in this order from the upper side (+Z side) to the lower side (-Z side) and are spaced apart in the up-down direction Z.

[0054] 2, the upper pad 21d1 and the first intermediate pad 71a are electrically and mechanically connected by a plurality of connection conductors 50. The first intermediate pad 71a and the second intermediate pad 71b are electrically and mechanically connected by a plurality of connection conductors 50. The second intermediate pad 71b and the third intermediate pad 71c are electrically and mechanically connected by a plurality of connection conductors 50. The third intermediate pad 71c and the first ground conductor 31 are electrically and mechanically connected by a plurality of connection conductors 50. As a result, the first connection pad P1 constantly electrically connects one end (-X side) of the first parallel line 21p1 and the first ground conductor 31.

[0055] In this specification, the "connection conductor 50" is a conductor extending in the vertical direction Z, and is a member that electrically and mechanically connects a member connected to the upper end of the connection conductor 50 and a member connected to the lower end of the connection conductor 50. The connection conductor 50 is, for example, a via that penetrates an insulating layer (not shown) in the vertical direction Z.

[0056] 2, the second connection pad P2 includes an upper pad 22d1, a first intermediate pad 72a, a second intermediate pad 72b, a third intermediate pad 72c, and a first ground conductor 31. The upper pad 22d1, the first intermediate pad 72a, the second intermediate pad 72b, the third intermediate pad 72c, and the first ground conductor 31 overlap one another in a plan view. The upper pad 22d1, the first intermediate pad 72a, the second intermediate pad 72b, the third intermediate pad 72c, and the first ground conductor 31 are arranged in this order from the upper side (+Z side) to the lower side (-Z side) and are spaced apart in the up-down direction Z.

[0057] 2, the upper pad 22d1 and the first intermediate pad 72a are electrically and mechanically connected by a plurality of connection conductors 50. The first intermediate pad 72a and the second intermediate pad 72b are electrically and mechanically connected by a plurality of connection conductors 50. The second intermediate pad 72b and the third intermediate pad 72c are electrically and mechanically connected by a plurality of connection conductors 50. The third intermediate pad 72c and the first ground conductor 31 are electrically and mechanically connected by a plurality of connection conductors 50. As a result, the second connection pad P2 constantly electrically connects one end (-X side) of the second parallel line 22p2 and the first ground conductor 31.

[0058] 2, a front side (-Y side) end of the first intersecting line 23c1 is connected to the second intermediate pad 72b included in the second connection pad P2. As a result, the second connection pad P2 constantly electrically connects the third line 23 and the first ground conductor 31. The front side (-Y side) end of the first intersecting line 23c1 may be connected to the third intermediate pad 72c included in the second connection pad P2.

[0059] 3, the third connection pad P3 includes the above-mentioned upper pad 21d2, the first intermediate pad 73a, the second intermediate pad 73b, the third intermediate pad 73c, and the lower pad 33a. The upper pad 21d2, the first intermediate pad 73a, the second intermediate pad 73b, the third intermediate pad 73c, and the lower pad 33a overlap each other in a plan view. The upper pad 21d2, the first intermediate pad 73a, the second intermediate pad 73b, the third intermediate pad 73c, and the lower pad 33a are arranged in this order from the upper side (+Z side) to the lower side (-Z side), and are arranged at intervals in the vertical direction Z.

[0060] 1, the lower pad 33a is a rectangular flat conductor whose long sides extend in the intersecting direction Y and whose short sides extend in the longitudinal direction X. The lower pad 33a is provided separately from the second ground conductor 32. The lower pad 33a and the second ground conductor 32 are electrically connected or not connected depending on the state of a first electronic switch 41 (described later). Therefore, the lower pad 33a is electrically grounded or not connected depending on the state of the first electronic switch 41.

[0061] 3, the upper pad 21d2 and the first intermediate pad 73a are electrically and mechanically connected by a plurality of connection conductors 50. The first intermediate pad 73a and the second intermediate pad 73b are electrically and mechanically connected by a plurality of connection conductors 50. The second intermediate pad 73b and the third intermediate pad 73c are electrically and mechanically connected by a plurality of connection conductors 50. The third intermediate pad 73c and the lower pad 33a are electrically and mechanically connected by a plurality of connection conductors 50. As a result, the third connection pad P3 constantly electrically connects the other end (+X side) of the first parallel line 21p1 and the first electronic switch 41.

[0062] 3, the fourth connection pad P4 includes the above-mentioned upper pad 22d2, the first intermediate pad 74a, the second intermediate pad 74b, the third intermediate pad 74c, and the lower pad 33b. The upper pad 22d2, the first intermediate pad 74a, the second intermediate pad 74b, the third intermediate pad 74c, and the lower pad 33b overlap each other in a plan view. The upper pad 22d2, the first intermediate pad 74a, the second intermediate pad 74b, the third intermediate pad 74c, and the lower pad 33b are arranged in this order from the upper side (+Z side) to the lower side (-Z side) and are arranged at intervals in the vertical direction Z.

[0063] 1, the lower pad 33b is a rectangular flat conductor whose long sides extend in the intersecting direction Y and whose short sides extend in the longitudinal direction X. The lower pad 33b is provided separately from the second ground conductor 32 and the lower pad 33a. The lower pad 33b and the second ground conductor 32 are electrically connected or not connected depending on the state of a second electronic switch 42 (described later). Therefore, the lower pad 33b is electrically grounded or not connected depending on the state of the second electronic switch 42.

[0064] 3, the upper pad 22d2 and the first intermediate pad 74a are electrically and mechanically connected by a plurality of connection conductors 50. The first intermediate pad 74a and the second intermediate pad 74b are electrically and mechanically connected by a plurality of connection conductors 50. The second intermediate pad 74b and the third intermediate pad 74c are electrically and mechanically connected by a plurality of connection conductors 50. The third intermediate pad 74c and the lower pad 33b are electrically and mechanically connected by a plurality of connection conductors 50. As a result, the fourth connection pad P4 constantly electrically connects the other end (+X side) of the second parallel line 22p2 and the second electronic switch 42.

[0065] 3, the dimension D12 in the cross direction Y of the lower pad 33a forming part of the connection pad P3 is larger than the dimension D11 in the cross direction Y of the upper pad 21d2 forming part of the connection pad P3. Also, the dimension D22 in the cross direction Y of the lower pad 33b forming part of the connection pad P4 is larger than the dimension D21 in the cross direction Y of the upper pad 22d2 forming part of the connection pad P4. As will be described in detail later, this is due to the fact that the sizes of the first electronic switch 41 and the second electronic switch 42 connected to the lower pads 33a and 33b are increased in order to reduce loss of high-frequency signals.

[0066] 2, the capacitor 60 is a parallel plate having an upper electrode connected to the signal line 10 and a lower electrode connected to the first ground conductor 31 via the third electronic switch 43. The capacitor 60 has a capacitance Ca according to the opposing area of ​​the parallel plates. In other words, the capacitance Ca is a circuit constant provided between the signal line 10 and the first ground conductor 31. However, the capacitor 60 may be a comb-type capacitor.

[0067] 1, the first electronic switch 41 is a transistor that freely opens and closes between the lower pad 33a of the third connection pad P3 and the second ground conductor 32. As shown in FIG. 1, the first electronic switch 41 in this embodiment is, for example, a MOS type FET, with a drain terminal connected to the lower pad 33a of the third connection pad P3, a source terminal connected to the second ground conductor 32, and a gate terminal connected to the switch control unit 80.

[0068] The first electronic switch 41 switches the conductive state between the drain terminal and the source terminal to an open state or a closed state based on a gate signal input to the gate terminal from the switch control unit 80. That is, the first electronic switch 41, by the switch control unit 80, brings the other end (+X side) of the first parallel line 21p1 and the second ground conductor 32 into a conductive state or a cut-off state.

[0069] 1, the second electronic switch 42 is a transistor that freely opens and closes between the lower pad 33b of the fourth connection pad P4 and the second ground conductor 32. As shown in FIG 1, the second electronic switch 42 in this embodiment is, for example, a MOS type FET, with a drain terminal connected to the lower pad 33b of the fourth connection pad P4, a source terminal connected to the second ground conductor 32, and a gate terminal connected to the switch control unit 80.

[0070] The second electronic switch 42 switches the conductive state between the drain terminal and the source terminal to an open state or a closed state based on a gate signal input to the gate terminal from the switch control unit 80. That is, the second electronic switch 42 switches the conductive state or the cut-off state between the other end (+X side) of the second parallel line 22p2 and the second ground conductor 32 by the switch control unit 80.

[0071] Fig. 4 is a plan view showing the connection relationship between the connection pads and the first and second electronic switches in the digital phase shift circuit according to the first embodiment of the present invention. As shown in Fig. 4, the first electronic switch 41 and the second electronic switch 42 are, for example, MOS type FETs having a rectangular shape in a plan view, and have a drain terminal DT and a source terminal ST. Note that the gate terminals are not shown in Fig. 4.

[0072] As described above, the first electronic switch 41 and the second electronic switch 42 are increased in size (specifically, the gate width W) to reduce the loss of high-frequency signals. When the sizes of the first electronic switch 41 and the second electronic switch 42 are increased, the lengths of the drain terminal DT and the source terminal ST in the Y direction also increase, as shown in FIG.

[0073] When the dimension D12 (see FIG. 3) of the lower pad 33a in the cross direction Y is approximately equal to the dimension D11 of the upper pad 21d2 in the cross direction Y, only a portion of the drain terminal DT of the first electronic switch 41 is connected to the lower pad 33a. Similarly, when the dimension D22 (see FIG. 3) of the lower pad 33b in the cross direction Y is approximately equal to the dimension D21 of the upper pad 22d2 in the cross direction Y, only a portion of the drain terminal DT of the second electronic switch 42 is connected to the lower pad 33b.

[0074] In this embodiment, the dimension D12 of the lower pad 33a in the cross direction Y is made longer to match the length in the Y direction of the drain terminal DT of the first electronic switch 41. In other words, the dimension D12 of the lower pad 33a in the cross direction Y is made larger than the dimension D11 of the upper pad 21d2 in the cross direction Y. This allows the entire drain terminal DT of the first electronic switch 41 to be connected to the lower pad 33a.

[0075] Similarly, the dimension D22 of the lower pad 33b in the cross direction Y is made longer to match the length in the Y direction of the drain terminal DT of the second electronic switch 42. In other words, the dimension D22 of the lower pad 33b in the cross direction Y is made larger than the dimension D21 of the upper pad 22d2 in the cross direction Y. This enables the entire drain terminal DT of the second electronic switch 42 to be connected to the lower pad 33b.

[0076] The other short side (-Y side) of the second ground conductor 32 is located at approximately the same position in the cross direction Y as the other short side (-Y side) of the lower pad 33a. That is, the second ground conductor 32 extends in the Y direction from one short side (+Y side) of the lower pad 33b to the other short side (-Y side) of the lower pad 33a. Therefore, as shown in FIG. 4, the source terminals ST of the first electronic switch 41 and the second electronic switch 42 are also entirely connected to the second ground conductor 32.

[0077] 2, the third electronic switch 43 is a transistor that freely opens and closes the lower electrode of the capacitor 60 and the first ground conductor 31. The third electronic switch 43 is, for example, a MOS type FET, and has a drain terminal connected to the lower electrode of the capacitor 60, a source terminal connected to the first ground conductor 31, and a gate terminal connected to the switch control unit 80.

[0078] 2, the third electronic switch 43 is disposed at a position away from the signal line 10 toward the rear (+Y side). One end (+Y side) of the first ground conductor 31 extends away from the signal line 10 in the cross direction Y and is connected to the third electronic switch 43. The reason for this arrangement is that there are design rule restrictions on the connection of the lower electrode of the capacitor 60 in a particular semiconductor manufacturing process.

[0079] Specifically, the lower electrode of the capacitor 60 must be once connected to an upper wiring layer (for example, a layer in which the signal line 10 is formed) through a connection wiring and a via, and then connected from that wiring layer to a lower wiring layer through a via. In FIG. 2, the connection path between the lower electrode of the capacitor 60 and the third electronic switch 43 is illustrated in a simplified manner. Due to this constraint, the third electronic switch 43 cannot be disposed near the position where the capacitor 60 is formed (for example, the input end side (-X side) of the signal line 10 shown in FIG. 1), and must be disposed at a position away from the signal line 10 toward the rear side (+Y side). The first ground conductor 31 extends away from the signal line 10 in the cross direction Y in order to be connected to the source terminal of the third electronic switch 43 disposed at such a position.

[0080] The third electronic switch 43 switches the conductive state between the drain terminal and the source terminal to an open state or a closed state based on a gate signal input to the gate terminal from the switch control unit 80. That is, the third electronic switch 43 brings the lower electrode of the capacitor 60 and the first ground conductor 31 into a conductive state or a cut-off state by the switch control unit 80.

[0081] Here, the size (gate width) of the first electronic switch 41 and the second electronic switch 42 is set to, for example, at least twice the size (gate width) of the third electronic switch 43. It is preferable that the size (gate width) of the first electronic switch 41 and the second electronic switch 42 is at least five times the size (gate width) of the third electronic switch 43.

[0082] Although the details will be described later, in this embodiment, the loss of the high frequency signal in the high delay mode can be significantly reduced. Since it is desirable that the difference between the loss of the high frequency signal in the high delay mode and the loss of the high frequency signal in the low delay mode is as small as possible, if the loss of the high frequency signal in the high delay mode is reduced, the loss of the high frequency signal in the low delay mode must also be reduced. For this reason, the sizes of the first electronic switch 41 and the second electronic switch 42 are made larger than the size of the third electronic switch 43.

[0083] In order to reduce the difference between the high frequency signal loss in the high delay mode and the low delay mode, it is necessary to set the size of the first electronic switch 41 and the second electronic switch 42 to at least twice the size of the third electronic switch 43. Furthermore, if the size of the first electronic switch 41 and the second electronic switch 42 is set to five times the size of the third electronic switch 43 or more, the high frequency signal loss in the high delay mode and the low delay mode can be made to be approximately the same.

[0084] 2, the fourth electronic switch 44 is a transistor that can freely open and close between the input end side (-X side) of the signal line 10 and the first ground conductor 31. Like the above-mentioned first electronic switch 41, second electronic switch 42, and third electronic switch 43, this fourth electronic switch 44 is a MOS type FET, with a drain terminal connected to the input end side (-X side) of the signal line 10, a source terminal connected to the first ground conductor 31, and a gate terminal connected to the switch control unit 80. Note that the fourth electronic switch 44 may be provided between the output end side (+X side) of the signal line 10 and the second ground conductor 32, instead of between the input end side (-X side) of the signal line 10 and the first ground conductor 31.

[0085] The fourth electronic switch 44 switches the conduction state between the drain terminal and the source terminal to an open state or a closed state based on a gate signal input to the gate terminal from the switch control unit 80. That is, the fourth electronic switch 44 brings the connection between the input end side (-X side) of the signal line 10 and the first ground conductor 31 into a conductive state or a cut-off state by the switch control unit 80.

[0086] The switch control unit 80 is a control circuit that controls the above-mentioned first electronic switch 41, second electronic switch 42, third electronic switch 43, and fourth electronic switch 44. The switch control unit 80 has four output ports, and outputs gate signals from each output port to the gate terminals of the first electronic switch 41, second electronic switch 42, third electronic switch 43, and fourth electronic switch 44 individually. That is, the switch control unit 80 opens or closes the first electronic switch 41, second electronic switch 42, third electronic switch 43, and fourth electronic switch 44 by the gate signals.

[0087] Next, the operation of the digital phase shift circuit B configured as above will be described.

[0088] In the digital phase shift circuit B in this embodiment, the operation mode is switched depending on the conductive states of the first to third electronic switches 41 to 43. That is, the operation modes of the digital phase shift circuit B include a low delay mode in which the first electronic switch 41 and the second electronic switch 42 are set to a closed state and the third electronic switch 43 is set to an open state by the switch control unit 80, and a high delay mode in which the first electronic switch 41 and the second electronic switch 42 are set to an open state and the third electronic switch 43 is set to a closed state by the switch control unit 80.

[0089] In the low delay mode, the switch control unit 80 sets the first electronic switch 41 and the second electronic switch 42 to a closed state, and sets the third electronic switch 43 to an open state. That is, in the low delay mode, the first propagation delay time TL Thus, the phase at the output end (right end) is the second phase θ H A first phase θ smaller than L The low latency mode will be explained in more detail below.

[0090] By setting the first electronic switch 41 to a closed state, the other end (+X side) of the first parallel line 21p1 is connected to the second ground conductor 32 via the third connection pad P3 (see FIG. 1). On the other hand, one end (-X side) of the first parallel line 21p1 is constantly connected to the first ground conductor 31 via the first connection pad P1 (see FIGS. 1 and 2). Therefore, by connecting the other end (+X side) of the first parallel line 21p1 to the second ground conductor 32 via the first electronic switch 41, a first current path is formed through which a current can flow between the one end (-X side) and the other end (+X side).

[0091] Moreover, by setting the second electronic switch 42 to a closed state, the other end (+X side) of the second parallel line 22p2 is connected to the second ground conductor 32 via the fourth connection pad P4 (see FIG. 1). On the other hand, one end (-X side) of the second parallel line 22p2 is constantly connected to the first ground conductor 31 via the second connection pad P2 (see FIGS. 1 and 2). Therefore, by connecting the other end (+X side) of the second parallel line 22p2 to the second ground conductor 32 via the second electronic switch 42, a second current path is formed through which a current can flow between the one end (-X side) and the other end (+X side).

[0092] When a signal current flows from the input end to the output end of the signal line 10 in a state where both ends of the first parallel line 21p1 and the second parallel line 22p2 are connected, a return current is generated in the first parallel line 21p1 and the second parallel line 22p2 due to the propagation of the signal current. The return current flows through the first parallel line 21p1 and the second parallel line 22p2 from the other end (+X side) to one end (-X side).

[0093] That is, a first return current flows in the first parallel line 21p1 forming the first current path in a direction opposite to the direction of the signal current due to the passage of the signal current in the signal line 10. Also, a second return current flows in the second parallel line 22p2 forming the second current path in a direction opposite to the direction of the signal current, i.e., in the same direction as the first return current, due to the passage of the signal current in the signal line 10.

[0094] Here, the first return current flowing through the first parallel line 21p1 and the second return current flowing through the second parallel line 22p2 are both opposite to the direction of the signal current. Therefore, the first return current and the second return current act to reduce the overall inductance of the digital phase shift circuit B due to the electromagnetic coupling (mutual induction) between the signal line 10 and the first parallel line 21p1 and the electromagnetic coupling (mutual induction) between the signal line 10 and the second parallel line 22p2. When the inductance of the signal line 10 is reduced to Ls low , the inductance of the return path (the first parallel line 21p1 and the second parallel line 22p2) is Lg low , the mutual inductance between the signal line 10 and the return path is M low The total inductance L of the digital phase shift circuit B in the low delay mode is low , Ls low +Lg low -M low It becomes.

[0095] As described above, the signal line 10 has the capacitance C1 as a parasitic capacitance. In the low delay mode, the third electronic switch 43 is set to an open state, and therefore the capacitor 60 is not connected between the signal line 10 and the first ground conductor 31. That is, the capacitance Ca of the capacitor 60 does not affect the high-frequency signal propagating through the signal line 10. Therefore, the high-frequency signal propagating through the signal line 10 has the following capacitance: (L low ×C1) 1 / 2 The first propagation delay time T is proportional to L comes into effect.

[0096] The high-frequency signal at the output end of the signal line 10 has a first propagation delay time TL As a result, the phase of the high-frequency signal at the input end of the signal line 10 becomes a first phase θ L That is, in the low delay mode, the total inductance of the digital phase shift circuit B is delayed by an inductance L low This reduces the propagation delay time.

[0097] On the other hand, in the high delay mode, the switch control unit 80 sets the first electronic switch 41 and the second electronic switch 42 to an open state, and sets the third electronic switch 43 to a closed state. The fourth electronic switch 44 is set to an open state. That is, in the high delay mode, the second propagation delay time T H Thus, the phase at the output end (right end) is the first phase θ L A second phase θ larger than H The high latency mode will be explained in more detail below.

[0098] As described above, in the high delay mode, the first electronic switch 41 and the second electronic switch 42 are set to the open state. Therefore, the first conductive path described above is not formed in the first parallel line 21p1, and the second conductive path described above is not formed in the second parallel line 22p2. Therefore, the first return current flowing in the first parallel line 21p1 becomes extremely small, and the second return current flowing in the second parallel line 22p2 becomes extremely small.

[0099] On the other hand, the near side (-Y side) end of the first crossing line 23c1 forming a part of the third line 23 is always connected to the first ground conductor 31 via the second connection pad P2 (see FIG. 2). Also, one end (-Y side) of the second crossing line 23c2 forming a part of the third line 23 is always connected to the second ground conductor 32 as described above. Therefore, in the third line 23, a third current path through which a current can flow between one end (-Y side) of the second crossing line 23c2 and the near side (-Y side) end of the first crossing line 23c1 is formed in advance. Therefore, in the high delay mode, due to the signal current in the signal line 10, a third return current flows from one end (-Y side) of the second crossing line 23c2 to the near side (-Y side) end of the first crossing line 23c1 via the bent line 23b and the third parallel line 23p3.

[0100] Here, the third return current flows in the third parallel line 23p3 and the partial line 23b2 of the bent line 23b, which are parallel to the signal line 10, in a direction opposite to the direction of current flow of the signal current in the signal line 10. In addition, the partial line 23b1 of the bent line 23b, the third parallel line 23p3, and the first crossing line 23c1 form a loop line that is convex on the opposite side (+Y side) from the signal line 10. Therefore, the inductance of the return path (path through which the third return current flows) can be increased compared to a conventional configuration in which the return path does not form a loop line. Moreover, in this embodiment, the thickness of the third line 23 (the thickness of the first crossing line 23c1, the third parallel line 23p3, the bent line 23b, and the second crossing line 23c2) is smaller than the thicknesses of the signal line 10, the first line 21, and the second line 22.

[0101] This allows the overall inductance of the digital phase shift circuit B to be significantly increased, and a desired phase shift amount can be ensured even at low frequencies where the phase shift amount is small. high The inductance of the return path (the second crossing line 23c2, the bent line 23b, the third parallel line 23p3, and the first crossing line 23c1) is Lg high , the mutual inductance between the signal line 10 and the return path is M high In addition, Ls high=Ls low The total inductance L of the digital phase shift circuit B in the high delay mode high , Ls high +Lg high -M high Here, obviously, Lg low <Lg high and M low >M high Since this holds, L high >L low holds true.

[0102] The principle by which the third return current acts to increase the inductance of the return path can be explained as follows. That is, the magnetic field generated when the third return current flows through the partial line 23b1 of the bent line 23b, the magnetic field generated when the third return current flows through the third parallel line 23p3, and the magnetic field generated when the third return current flows through the first intersecting line 23c1 all have the same direction (+Z direction) in the above-mentioned loop line. Therefore, these magnetic fields reinforce each other. Therefore, compared with the conventional configuration in which the line through which the third return current flows does not form a loop line, it is possible to increase the magnetic field generated by the third return current and increase the inductance of the return path. In addition, the value of the inductance of the return path can be changed significantly by adjusting the height of the loop (i.e., the position of the third parallel line 23p3 in the intersecting direction Y, and the first intersecting line 23c1 and the partial line 23b1 of the bent line 23b).

[0103] On the other hand, the signal line 10 has a capacitance C1 as a parasitic capacitance. In the high delay mode, the third electronic switch 43 is set to a closed state, and therefore the capacitor 60 is connected between the signal line 10 and the first ground conductor 31. That is, the signal line 10 has a capacitance Cb which is a sum of the capacitance Ca of the capacitor 60 and the capacitance C1 (parasitic capacitance). Therefore, the high-frequency signal propagating through the signal line 10 has a second propagation delay time T H comes into effect.

[0104] The high-frequency signal at the output end of the signal line 10 has a second propagation delay time T H As a result, the phase of the high-frequency signal at the input end of the signal line 10 becomes a second phase θ H That is, in the high delay mode, the inductance of the transmission system is increased due to the third return current, and thus the propagation delay time increases.

[0105] Here, in the high delay mode, the loss in the signal line 10 may be intentionally increased by setting the electronic switch 44 to a closed state. This loss is intended to make the loss of the high frequency signal in the high delay mode approximately the same as the loss of the high frequency signal in the low delay mode.

[0106] Digital Phase Shifter 5 is a plan view showing a configuration of a main part of a digital phase shifter according to a first embodiment of the present invention. As shown in FIG. 5, a digital phase shifter A1 of this embodiment includes a plurality of digital phase shift circuits B1, B2, B3, ..., B n-1 ,B n are connected in series in the longitudinal direction X. The digital phase shift circuits B1, B2, B3, ..., B n-1 ,B n The basic configuration is the same as that of the digital phase shift circuit B described with reference to FIGS.

[0107] The digital phase shifter A1 receives the high-frequency signal input from the digital phase shift circuit B1 and outputs it to the digital phase shift circuit B n Output from digital phase shift circuit B n The high-frequency signal input from the digital phase shift circuit B1 is output from the digital phase shift circuit B2. n 5, an example in which the first electronic switch 41, the second electronic switch 42, and the switch control unit 80 are omitted for ease of viewing.

[0108] 5, the digital phase shifter A1 is cascaded in the longitudinal direction X such that the first line 21 is located only on the other side (-Y side) of the signal line 10, and the second line 22 and the third line 23 are located only on one side (+Y side) of the signal line 10. In other words, the digital phase shifter A1 is configured such that a loop line is disposed only on one side (+Y side) of the signal line 10. The reason for this configuration is to reduce the size of the digital phase shifter A1.

[0109] In the digital phase shifter A1 according to this embodiment, the digital phase shift circuits B1 to B n-1 The digital phase shift circuits B2 to B n In the digital phase shifter A1 according to the embodiment, the digital phase shift circuits B2 to B n The digital phase shift circuits B1 to B2 adjacent to each other on the left side (-X side) n-1 It can also be said that a part of the wire is connected to the other wire.

[0110] More specifically, in a portion where the digital phase shift circuits are adjacent to each other, the first ground conductor 31 and the second ground conductor 32 are commonized, a part of the first cross line 23c1 and a part of the second cross line 23c2 are commonized, the upper pad 21d1 and the upper pad 24 are commonized, and the upper pad 22d1 and the upper pad 25 are commonized. In the example shown in Fig. 5, for example, the second ground conductor 32 of the digital phase shift circuit B1 and the first ground conductor 31 of the digital phase shift circuit B2 are commonized, a part of the second cross line 23c2 of the digital phase shift circuit B1 and a part of the first cross line 23c1 of the digital phase shift circuit B2 are commonized, the upper pad 24 of the digital phase shift circuit B1 and the upper pad 21d1 of the digital phase shift circuit B2 are commonized, and the upper pad 25 of the digital phase shift circuit B1 and the upper pad 22d1 of the digital phase shift circuit B2 are commonized.

[0111] Therefore, the first ground conductor 31 of the digital phase shift circuit B2 also functions as the second ground conductor 32 of the digital phase shift circuit B1. A part of the first cross line 23c1 of the digital phase shift circuit B2 also functions as a part of the second cross line 23c2 of the digital phase shift circuit B1. The upper pad 21d1 of the digital phase shift circuit B2 also functions as the upper pad 24 of the digital phase shift circuit B1. The upper pad 22d1 of the digital phase shift circuit B2 also functions as the upper pad 25 of the digital phase shift circuit B1.

[0112] Here, a bent portion CR1 is formed in the first crossing line 23c1 constituting the third line 23, and the side closer to the second parallel line 22p2 is crank-shaped. A bent portion CR2 is formed in the second crossing line 23c2 constituting the third line 23, and the side closer to the second parallel line 22p2 is crank-shaped. Therefore, in a portion where the digital phase shift circuits B are adjacent to each other, the shared first crossing line 23c1 and second crossing line 23c2 extend from one end (-X side) of the second parallel line 22p2 in the crossing direction Y in a plan view so as to move away from the signal line 10, bend to the right (+X side) at the bent portion CR1, and bend to the left (-X side) at the bent portion CR2, forming a T-shape.

[0113] Such a connection can reduce the degradation of the magnetic field caused by mutual interference between adjacent digital phase shift circuits B. As a result, the mutual inductance between adjacent digital phase shift circuits B can be reduced.

[0114] In this manner, in the digital phase shifter A1 of the present embodiment, as described above, the digital phase shift circuits B1 to B nIn each of the above, the line through which the third return current flows forms a loop line that is convex on the opposite side (+Y side) to the signal line 10, and the thickness (cross-sectional area) is smaller than the thicknesses (cross-sectional areas) of the signal line 10, the first line 21, and the second line 22. This makes it possible to significantly improve the efficiency of generating a magnetic field compared to the conventional technique. Furthermore, in the digital phase shifter A1 of this embodiment, as described above, it is possible to reduce the mutual inductance between adjacent digital phase shift circuits B. As a result, the digital phase shifter A1 of this embodiment can ensure a required amount of phase shift even in a configuration in which a loop line is arranged only on one side (+Y side) of the signal line 10.

[0115] In addition, in the digital phase shifter A1 of this embodiment, for example, when the adjacent digital phase shift circuits, except for the digital phase shift circuit B1, are set to the high delay mode, the third return current flows through a path that does not pass through the second connection pad P2. For example, if the digital phase shift circuits B1 to B3 are set to the high delay mode, the third return current flows through the path PT in the figure without passing through obstacles with large losses, such as the second connection pad P2 of the digital phase shift circuits B2 and B3 and the first ground conductor 31 (second ground conductor 32). Therefore, the digital phase shifter A1 of this embodiment can significantly reduce the loss of the high-frequency signal in the high delay mode.

[0116] In this way, the digital phase shifter A1 of this embodiment can significantly reduce the loss of the high frequency signal in the high delay mode. As a result, the size of the first electronic switch 41 and the second electronic switch 42 arranged in the current path of the first return current and the second return current in the low delay mode can be increased. This is because it is desirable that the difference between the loss of the high frequency signal in the high delay mode and the loss of the high frequency signal in the low delay mode is as small as possible, and therefore if the loss of the high frequency signal in the high delay mode is reduced, the loss of the high frequency signal in the low delay mode must also be reduced. In this way, the digital phase shifter A1 of this embodiment can reduce the loss of the high frequency signal as a whole.

[0117] As described above, the digital phase shifter A1 of the present embodiment includes a plurality of cascaded digital phase shift circuits B1 to B n A phase shifter having a plurality of digital phase shift circuits B1 to B n each includes a signal line 10, a first line 21, a second line 22, a third line 23, a first ground conductor 31, a second ground conductor 32, a first electronic switch 41, and a second electronic switch 42. The first line 21 includes a first parallel line 21p1 extending parallel to the signal line 10. The second line 22 includes a second parallel line 22p2 extending parallel to the signal line 10. The third line 23 is connected to one end of the second parallel line 22p2, and includes, in a planar view, a first intersecting line 23c1 extending from one end of the second parallel line 22p2 away from the signal line 10 in a crossing direction that crosses the longitudinal direction of the signal line 10, a third parallel line 23p3 extending parallel to the signal line 10 from one end of the first intersecting line 23c1, and a second intersecting line 23c2 extending from one end of the third parallel line 23p3 toward the signal line 10 in the crossing direction.

[0118] In addition, a plurality of digital phase shift circuits B1 to B n Each of the third line 23 includes a first ground conductor 31, a second ground conductor 32, a first electronic switch 41, and a second electronic switch 42. The first ground conductor 31 is electrically connected to one end of the first parallel line 21p1 and one end of the second parallel line 22p2, and the second ground conductor 32 is connected to one end of the third line 23. The first electronic switch 41 is provided between the other end of the first parallel line 21p1 and the second ground conductor 32, and the second electronic switch 42 is provided between the other end of the second parallel line 22p2 and the second ground conductor 32.

[0119] In addition, a plurality of digital phase shift circuits B1 to B n In each of the third lines 23, the signal line 10 is located between the first parallel line 21p1 and the second parallel line 22p2. The cross-sectional area of ​​the third line 23 is smaller than the cross-sectional areas of the signal line 10, the first line 21, and the second line 22. The first crossing line 23c1 and the second crossing line 23c2 included in the third line 23 have a crank shape on the side closer to the second parallel line 22p2.

[0120] In the digital phase shifter A1 of this embodiment, the first ground conductor 31 and the second ground conductor 32 are common in the portion where the digital phase shift circuits are adjacent to each other. In addition, in the portion where the digital phase shift circuits are adjacent to each other, the second cross line 23c2 of the third line 23 is connected to the first cross line 23c1 of the third line 23 in the adjacent digital phase shift circuit. With the above configuration, it is possible to realize a desired phase shift characteristic with a smaller size than the conventional one. In addition, in this embodiment, it is possible to ensure a desired phase shift amount even at a low frequency.

[0121] Second Embodiment Digital phase shift circuit Fig. 6 is a plan view showing the basic configuration of a digital phase shift circuit according to a second embodiment of the present invention. In Fig. 6, the same components as those shown in Fig. 1 are denoted by the same reference numerals. As shown in Fig. 6, a digital phase shift circuit B' according to this embodiment has a configuration substantially similar to that of the digital phase shift circuit B shown in Fig. 1, but differs in the configuration of the third line 23. Specifically, the third line 23 does not include the bent line 23b shown in Fig. 1, and is composed of a first cross line 23c1, a third parallel line 23p3, and a second cross line 23c2. Such a digital phase shift circuit B' is compatible with higher frequencies (e.g., 39 GHz).

[0122] Specifically, in this embodiment, the first intersecting line 23c1 constituting the third line 23 has a length in the Y direction shorter than that of the first intersecting line 23c1 shown in Fig. 1 because the bent line 23b is omitted. Since the bent line 23b is omitted, the third parallel line 23p3 extends so as to connect the end on the far side (+Y side) of the first intersecting line 23c1 and the end on the far side (+Y side) of the second intersecting line 23c2.

[0123] Therefore, the distance D1 between the center line of the second parallel line 22p2 and the center line of the third parallel line 23p3 in this embodiment is smaller than the distance D1 between the center line of the second parallel line 22p2 and the center line of the third parallel line 23p3 in the first embodiment. The distance D2 between the center line of the second parallel line 22p2 and the outer edge on the far side of the first ground conductor 31 (the outer edge on the third parallel line 23p3 side) is the same as in the first embodiment.

[0124] Digital Phase Shifter 7 is a plan view showing a configuration of a main part of a digital phase shifter according to a second embodiment of the present invention. As shown in FIG. 7, a digital phase shifter A2 of this embodiment includes a plurality of digital phase shift circuits B1, B2, B3, ..., B n-1 ,B n are connected in series in the longitudinal direction X. The digital phase shift circuits B1, B2, B3, ..., B n-1 ,B n The basic configuration of the digital phase shift circuit B′ is the same as that of the digital phase shift circuit B′ described with reference to Fig. 6. Note that in Fig. 7, similarly to Fig. 5, the first electronic switch 41, the second electronic switch 42, and the switch control section 80 are not shown.

[0125] The digital phase shifter A2 shown in FIG. 7 is different from the digital phase shifter A1 shown in FIG. 5 in that the digital phase shifter A2 includes digital phase shift circuits B1, B2, B3, . . . , B n-1 ,B n 5. The third line 23 is different from that of the digital phase shifter A1 shown in FIG. 5. Therefore, in the digital phase shifter A2 of this embodiment, when the adjacent digital phase shift circuits except for the digital phase shift circuit B1 are set to the high delay mode, the third return current flows through a path that does not pass through the second connection pad P2. For example, when the digital phase shift circuits B1 to B3 are set to the high delay mode, the third return current flows through the path PT in the figure. Therefore, the digital phase shifter A2 of this embodiment can significantly reduce the loss of the high frequency signal in the high delay mode, similar to the digital phase shifter A1 shown in FIG. 5.

[0126] As a result, in the digital phase shifter A2 of this embodiment, the sizes of the first electronic switch 41 and the second electronic switch 42 arranged in the current paths of the first return current and the second return current in the low delay mode can also be increased. This is because it is desirable for the difference between the loss of the high frequency signal in the high delay mode and the loss of the high frequency signal in the low delay mode to be as small as possible, and therefore if the loss of the high frequency signal in the high delay mode is reduced, it is necessary to reduce the loss of the high frequency signal in the low delay mode as well. In this way, the digital phase shifter A2 of this embodiment can also reduce the loss of the high frequency signal as a whole.

[0127] As described above, the digital phase shifter A2 of this embodiment differs from the digital phase shifter A1 shown in FIG. n-1 ,B n 5. Therefore, the digital phase shifter A2 of this embodiment can also achieve a desired phase shift characteristic with a smaller size than the conventional one. Moreover, in this embodiment, a desired phase shift amount can be ensured even if the frequency becomes high.

[0128] Third Embodiment Digital phase shift circuit FIG. 8 is a plan view showing the basic configuration of a digital phase shift circuit according to a third embodiment of the present invention. In FIG. 8, the same components as those shown in FIG. 1 are denoted by the same reference numerals. As shown in FIG. 8, a digital phase shift circuit B″ according to this embodiment has a configuration generally similar to that of the digital phase shift circuit B shown in FIG. 1, but the configuration of the third line 23 is different. Specifically, in the digital phase shift circuit B″ according to this embodiment, a plurality of holes H are formed in the third line 23 along the third line 23. The holes H are formed in order to increase the resistance of the third line 23.

[0129] Digital Phase Shifter In the digital phase shifter A3 of this embodiment, the digital phase shift circuit B″ described with reference to FIG. 8 is replaced with digital phase shift circuits B1, B2, B3, . . . , B n-1 ,B n 4, which are connected in series in the longitudinal direction X. For this reason, a detailed description thereof will be omitted here.

[0130] As described above, the digital phase shift circuit B″ and digital phase shifter A3 of this embodiment have the same configuration as the digital phase shift circuit B shown in FIG. 1 and the digital phase shifter A1 shown in FIG. 5, except that a hole H is formed in the third line 23. For this reason, this embodiment, like the digital phase shifter A1 shown in FIG. 5, can achieve desired phase shift characteristics in a smaller size than conventional devices.

[0131] Incidentally, the digital phase shift circuit B″ according to the present embodiment has a configuration in which the third line 23 included in the digital phase shift circuit B shown in FIG. 1 is provided with a plurality of holes H formed along the third line 23. However, the digital phase shift circuit B′ shown in FIG. 6 may have a configuration in which the third line 23 included in the digital phase shift circuit B′ is provided with a plurality of holes H formed along the third line 23.

[0132] In addition, digital phase shift circuits B1, B2, B3, ..., B n-1 ,B n It is not necessary that all of the digital phase shift circuits B" are digital phase shift circuits B1, B2, B3, ..., B n-1 ,B n At least two of them (specific digital phase shift circuits) may be digital phase shift circuits B". For example, digital phase shift circuits B" may be provided periodically (for example, every other circuit, every third circuit, etc.). In this way, the difference in loss between the low delay mode and the high delay mode can be reduced.

[0133] [Fourth embodiment] Digital Phase Shifter 9 is a plan view showing the main configuration of a digital phase shifter according to a fourth embodiment of the present invention. As shown in FIG. 9, a digital phase shifter A4 of this embodiment has a configuration similar to that of the digital phase shifter A1 shown in FIG. 5, but digital phase shift circuits B1, B2, B3, ..., B n-1 ,B n The configuration is slightly different from that shown in FIG.

[0134] Specifically, in this embodiment, the digital phase shift circuits B1, B2, B3, . . . , B n-1 ,B n In the embodiment, the distance D1 (see FIG. 1) between the center line of the second parallel line 22p2 and the center line of the third parallel line 23p3 in the cross direction Y is different between adjacent digital phase shift circuits. For example, the distance D1 in the even-numbered digital phase shift circuits (digital phase shift circuits B2, B4, B6, ...) is set shorter than the distance D1 in the odd-numbered digital phase shift circuits (digital phase shift circuits B1, B3, B5, ...). As a result, the digital phase shifter A4 of this embodiment can achieve a larger phase shift amount than the digital phase shifter A1 of the first embodiment.

[0135] As described above, the digital phase shifter A4 of this embodiment has a different distance D1 (see FIG. 1) between the center line of the second parallel line 22p2 and the center line of the third parallel line 23p3 in the intersecting direction Y in adjacent digital phase shift circuits, but is basically configured in the same manner as the digital phase shifter A1 shown in FIG 5. Therefore, like the digital phase shifter A1 shown in FIG 5, it is possible to achieve desired phase shift characteristics with a smaller size than conventional ones.

[0136] In the digital phase shifter A4 shown in FIG. 9, the distance D1 (see FIG. 1) between the center line of the second parallel line 22p2 and the center line of the third parallel line 23p3 in the cross direction Y is different in adjacent digital phase shift circuits. However, the distance D1 does not necessarily need to be different in adjacent digital phase shift circuits. It is sufficient that the distance D1 in at least one digital phase shift circuit is different from the distance D1 in the other digital phase shift circuits. Also, the distance D1 is not limited to two types, and may be three or more types.

[0137] 5. The digital phase shifter A4 of this embodiment is similar to the digital phase shifter A1 shown in FIG. n-1 ,B n However, the digital phase shift circuits B1, B2, B3, ..., B n-1 ,B n Regarding the above, the distance D1 may be varied.

[0138] Although the digital phase shift circuit and the digital phase shifter according to the embodiment of the present invention have been described above, the present invention is not limited to the above embodiment and can be freely modified within the scope of the present invention. For example, in the above embodiment, the thickness of the third line 23 is made smaller than the thicknesses of the signal line 10, the first line 21, and the second line 22, so that the cross-sectional area of ​​the third line 23 is made smaller than the cross-sectional areas of the signal line 10, the first line 21, and the second line 22. However, the width (width in a plan view) of the third line 23 may be made smaller than the widths of the signal line 10, the first line 21, and the second line 22, so that the cross-sectional area of ​​the third line 23 is made smaller than the cross-sectional areas of the signal line 10, the first line 21, and the second line 22.

[0139] In the above-described embodiment, an example has been described in which the third line 23 is formed in a layer different from the layer in which the signal line 10, the first line 21, the second line 22, etc. are formed and the layer in which the first ground conductor 31 and the second ground conductor 32 are formed. However, as long as the cross-sectional area of ​​the third line 23 can be made smaller than the cross-sectional areas of the signal line 10, the first line 21, and the second line 22, the third line 23 may be formed in the same layer as the layer in which the signal line 10, the first line 21, and the second line 22 are formed.

[0140] In addition, the digital phase shift circuits B1 to B2 constituting the digital phase shifters A1 to A4 according to the first to fourth embodiments described above n All the third lines 23 may be formed in the same layer. In this way, when the adjacent digital phase shift circuits are set to the high delay mode, the return current does not pass through an obstacle, so that loss can be reduced.

[0141] In addition, the digital phase shift circuits B1 to B2 constituting the digital phase shifters A1 to A4 according to the first to fourth embodiments described above n The third line 23 of at least one of the digital phase shift circuits may be formed in a layer different from the third line 23 of the other digital phase shift circuits. For example, the third line 23 of the digital phase shift circuit B1 may be formed in the second intermediate pad 72b (see FIG. 2), and the third line 23 of the other digital phase shift circuits B2 to B3 may be formed in a layer different from the third line 23 of the other digital phase shift circuits. n 2, the third line 23 is formed in the third intermediate pad 72c (see FIG. 2). [Explanation of symbols]

[0142] 10...signal line, 21...first line, 21d2...upper pad, 21p1...first parallel line, 22...second line, 22d2...upper pad, 22p2...second parallel line, 23...third line, 23c1...first cross line, 23c2...second cross line, 23p3...third parallel line, 31...first ground conductor, 32...second ground conductor, 33a, 33b...lower pad, 41...first electronic switch, 42...second electronic switch, 43...third electronic switch, 44...fourth electronic switch, 50...connecting conductor, 60...capacitor, A1 to A4...digital phase shifter, B, B', B'', B1 to B n ...digital phase shift circuit, CR1, CR2...bends, D1...distance, Y...crossing direction

Claims

1. A signal line; a first line including a first parallel line extending parallel to the signal line; a second line including a second parallel line extending parallel to the signal line; a third line including: a first intersecting line connected to one end of the second parallel line and extending from one end of the second parallel line in a crossing direction crossing a longitudinal direction of the signal line in a plan view so as to move away from the signal line; a third parallel line extending from one end of the first intersecting line in parallel to the signal line; and a second intersecting line extending from one end of the third parallel line so as to move closer to the signal line in the crossing direction; a first ground conductor electrically connected to one end of the first parallel line and one end of the second parallel line; a second ground conductor electrically connected to one end of the third line; a first electronic switch provided between the other end of the first parallel line and the second ground conductor; a second electronic switch provided between the other end of the second parallel line and the second ground conductor; the signal line is located between the first parallel line and the second parallel line, A cross-sectional area of ​​the third line is smaller than cross-sectional areas of the signal line, the first line, and the second line. Digital phase shift circuit.

2. The digital phase shift circuit according to claim 1 , wherein the third line has a thickness smaller than that of the signal line, the first line, and the second line.

3. The digital phase shift circuit according to claim 1 , wherein the third line is formed in an inner layer than the first line and the second line.

4. 2. The digital phase shift circuit according to claim 1, wherein the third line has a plurality of holes formed therein along the third line.

5. A capacitor connected to one end of the signal line; a third electronic switch disposed between the capacitor and the first ground conductor; Further comprising: One end of the first ground conductor extends away from the signal line in the crossing direction and is connected to the third electronic switch.

2. The digital phase shift circuit according to claim 1.

6. the first electronic switch, the second electronic switch, and the third electronic switch are field effect transistors; a size of a field effect transistor constituting the first electronic switch and the second electronic switch is at least twice as large as a size of a field effect transistor constituting the third electronic switch; 6. The digital phase shift circuit according to claim 5.

7. a first upper pad provided at the other end of the first parallel line; a second upper pad provided at the other end of the second parallel line; Further comprising: a maximum value of a dimension of the first upper pad in the intersecting direction is greater than a width of the first parallel line; a maximum value of a dimension of the second upper pad in the intersecting direction is greater than a width of the second parallel line; 2. The digital phase shift circuit according to claim 1.

8. a first lower pad connected to the first upper pad through a via and to which the first electronic switch is connected; a second lower pad connected to the second upper pad through a via and to which the second electronic switch is connected; Further comprising: a maximum value of a dimension of the first lower pad in the cross direction is greater than a maximum value of a dimension of the first upper pad in the cross direction; a maximum value of a dimension of the second lower pad in the cross direction is greater than a maximum value of a dimension of the second upper pad in the cross direction; 8. The digital phase shift circuit according to claim 7.

9. 2. The digital phase shift circuit according to claim 1, further comprising a fourth electronic switch provided between one end of said signal line and said first ground conductor.

10. A digital phase shifter in which a plurality of digital phase shift circuits are cascaded, Each of the digital phase shift circuits is a digital phase shift circuit according to any one of claims 1 to 9, the first ground conductor and the second ground conductor are common in a portion where the digital phase shift circuits are adjacent to each other; The first intersecting line and the second intersecting line are crank-shaped. Digital phase shifter.

11. 11. The digital phase shifter according to claim 10, wherein at least one of the digital phase shift circuits is different from the other digital phase shift circuits in a distance between a center line of the second parallel line and a center line of the third parallel line in the intersecting direction.

12. A digital phase shifter in which a plurality of digital phase shift circuits are cascaded, The specific digital phase shift circuits, which are at least two of the digital phase shift circuits, are the digital phase shift circuits according to claim 4, the first ground conductor and the second ground conductor are common in a portion where the digital phase shift circuits are adjacent to each other; The first intersecting line and the second intersecting line are crank-shaped. Digital phase shifter.

13. The digital phase shifter according to claim 10 , wherein the third lines of the digital phase shift circuit are formed in the same layer.

14. 11. The digital phase shifter according to claim 10, wherein the third line of at least one of the digital phase shift circuits is formed in a layer different from the third lines of the other digital phase shift circuits.

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