Manufacturing method of display device and display device

Abstract

To provide a manufacturing method of a display device and a display device, capable of preventing a reduction in reliability.SOLUTION: A manufacturing method of a display device includes: forming a lower electrode; forming an inorganic insulating layer covering the lower electrode; forming, on the inorganic insulating layer, a partition which includes a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion; forming a patterned resist on the inorganic insulating layer using a photo mask which includes an aperture with a pair of first straight sections extending in a first direction, a pair of second straight sections extending in a second direction that intersects the first direction, and four arc-shaped corners connecting the first straight section and the second straight section adjacent to each other; and forming a rib having a pixel aperture which overlaps the lower electrode, by removing a portion, of the inorganic insulating layer, exposed from the resist.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] An embodiment of the present invention relates to a manufacturing method for a display device and a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. The display elements include a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0003] In manufacturing such display devices, a technique for suppressing deterioration in reliability is required. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device and a manufacturing method thereof that are capable of suppressing a decrease in reliability. [Means for solving the problem]

[0006] A method for manufacturing a display device according to one embodiment includes forming a lower electrode, forming an inorganic insulating layer covering the lower electrode, forming a partition on the inorganic insulating layer, the partition including a conductive lower portion and an upper portion having an end portion protruding from a side of the lower portion, forming a resist patterned using a photomask having an opening having a pair of first straight portions extending in a first direction, a pair of second straight portions extending in a second direction intersecting the first direction, and four arc-shaped corner portions connecting adjacent first straight portions and second straight portions, on the inorganic insulating layer, and removing portions of the inorganic insulating layer exposed from the resist to form a rib having a pixel opening that overlaps with the lower electrode.

[0007] A display device according to one embodiment comprises a lower electrode, a rib having a pixel opening overlapping the lower electrode, a partition including a conductive lower portion arranged on the rib and an upper portion having an end protruding from a side of the lower portion, a laminate film including an organic layer contacting the lower electrode through the pixel opening and an upper electrode covering the organic layer, and a sealing layer covering the laminate film, wherein the rib has a tapered end around the entire circumference of the pixel opening. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of a layout of sub-pixels. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display panel taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view showing the planar shape of a pixel aperture according to the embodiment. [Diagram 5] FIG. 5 is a diagram showing an example of a structure that can be applied to a rib having a pixel opening according to the embodiment. [Figure 6] FIG. 6 is a schematic plan view showing a part of the photomask according to the embodiment. [Figure 7]FIG. 7 is a schematic plan view showing a part of the photomask according to the embodiment. [Figure 8] FIG. 8 is a view for explaining a step of forming a pixel aperture in the manufacturing method according to the embodiment. [Figure 9] FIG. 9 is a view for explaining a step of forming a pixel aperture in the manufacturing method according to the same embodiment. [Figure 10] FIG. 10 is a schematic plan view showing a part of a photomask used in a manufacturing method according to a comparative example. [Figure 11] FIG. 11 is a diagram for explaining a step of forming a pixel opening in a manufacturing method according to a comparative example. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a part of a display device manufactured by a manufacturing method according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings. In addition, the disclosure is merely an example, and the invention is not limited to the contents described in the following embodiments. Modifications that a person skilled in the art can easily conceive are naturally included in the scope of the disclosure. In order to make the explanation clearer, the size, shape, etc. of each part may be changed from the actual embodiment and shown diagrammatically. In multiple drawings, corresponding elements may be given the same reference numerals, and detailed explanations may be omitted.

[0010] In the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the first direction, the direction along the Y-axis is called the second direction, and the direction along the Z-axis is called the third direction. The third direction Z is a normal direction to a plane that includes the first direction X and the second direction Y. Moreover, viewing various elements parallel to the third direction Z is called planar view.

[0011] The display device according to this embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be mounted in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0012] 1 is a diagram showing a configuration example of a display device DSP according to this embodiment. The display device DSP includes a display panel PNL including an insulating substrate 10. The display panel PNL has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0013] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0014] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. Each pixel PX includes a plurality of subpixels SP. In one example, the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. The pixel PX may include a subpixel SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0015] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0016] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0017] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in a first direction X. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in a second direction Y.

[0019] When the subpixels SP1, SP2, and SP3 are laid out in this manner, a column in which the subpixels SP2 and SP3 are alternately arranged in the second direction Y, and a column in which a plurality of subpixels SP1 are repeatedly arranged in the second direction Y are formed in the display area DA. These columns are arranged alternately in the first direction X. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG.

[0020] A rib 5 is disposed in the display area DA. The rib 5 has pixel apertures AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, the pixel aperture AP1 is larger than the pixel aperture AP2, and the pixel aperture AP2 is larger than the pixel aperture AP3.

[0021] The subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap the pixel aperture AP1. The subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap the pixel aperture AP2. The subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap the pixel aperture AP3.

[0022] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 overlapping with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 overlapping with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 overlapping with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib 5 surrounds each of these display elements DE1, DE2, and DE3.

[0023] The lower electrode LE1 is connected to the pixel circuit 1 of the subpixel SP1 (see FIG. 1) through a contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the subpixel SP2 through a contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the subpixel SP3 through a contact hole CH3.

[0024] The partition walls 6 are disposed on the ribs 5. The partition walls 6 overlap the ribs 5 as a whole, and have the same planar shape as the ribs 5. That is, the partition walls 6 have openings AP61, AP62, and AP63 in the subpixels SP1, SP2, and SP3, respectively. From another perspective, the ribs 5 and the partition walls 6 are disposed between the display elements DE1, DE2, and DE3, and have a lattice shape in plan view.

[0025] Fig. 3 is a schematic cross-sectional view of the display panel PNL (display device DSP) taken along line III-III in Fig. 2. A circuit layer 11 is disposed on the above-mentioned substrate 10. The circuit layer 11 includes various circuits and wiring such as the pixel circuits 1, scanning lines GL, signal lines SL, and power lines PL shown in Fig. 1.

[0026] The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11. Although not shown in the cross section of FIG. 3, the above-mentioned contact holes CH1, CH2, and CH3 are provided in the organic insulating layer 12.

[0027] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. Ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5.

[0028] The partition 6 includes a conductive lower portion 61 disposed on the rib 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition 6 is called an overhang shape.

[0029] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6.

[0030] 3, a cap layer CP1 is disposed on the upper electrode UE1, a cap layer CP2 is disposed on the upper electrode UE2, and a cap layer CP3 is disposed on the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0031] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as a laminate film FL3.

[0032] A part of the laminated film FL1 is located on the upper part 62. This part is separated from a part of the laminated film FL1 located below the partition wall 6 (a part that constitutes the display element DE1). Similarly, a part of the laminated film FL2 is located on the upper part 62, and this part is separated from a part of the laminated film FL2 located below the partition wall 6 (a part that constitutes the display element DE2). Furthermore, a part of the laminated film FL3 is located on the upper part 62, and this part is separated from a part of the laminated film FL3 located below the partition wall 6 (a part that constitutes the display element DE3).

[0033] Sealing layers SE1, SE2, and SE3 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE1 continuously covers the laminated film FL1 and the partition wall 6 around the subpixel SP1. The sealing layer SE2 continuously covers the laminated film FL2 and the partition wall 6 around the subpixel SP2. The sealing layer SE3 continuously covers the laminated film FL3 and the partition wall 6 around the subpixel SP3.

[0034] 3, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP2 are separated from the stacked film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP3 are separated from the stacked film FL3 and the sealing layer SE3 on the partition wall 6.

[0035] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15. The resin layers 13, 15, and the sealing layer 14 are provided continuously at least throughout the display area DA, and a portion of them extends into the peripheral area SA.

[0036] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer 15. Such a cover member may be adhered to the resin layer 15 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0037] The organic insulating layer 12 is formed of an organic insulating material. The rib 5 and the sealing layers 14, SE1, SE2, and SE3 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). In one example, the rib 5 is formed of silicon oxynitride, and the sealing layers 14, SE1, SE2, and SE3 are formed of silicon nitride. The resin layers 13 and 15 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0038] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver (Ag) and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0039] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0040] The organic layers OR1, OR2, and OR3 each have a stacked structure of, for example, a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer. The organic layers OR1, OR2, and OR3 may have a so-called tandem structure including a plurality of light emitting layers.

[0041] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, a plurality of transparent thin films are stacked. The plurality of thin films may include a thin film formed of an inorganic material and a thin film formed of an organic material. The plurality of thin films have different refractive indices. The material of these thin films is different from the material of the upper electrodes UE1, UE2, and UE3, and also different from the material of the sealing layers SE1, SE2, and SE3. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0042] The lower portion 61 of the partition wall 6 is formed of, for example, aluminum. The lower portion 61 may be formed of an aluminum alloy such as an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY) or an aluminum-silicon alloy (AlSi), or may have a laminated structure of an aluminum layer and an aluminum alloy layer. Furthermore, the lower portion 61 may have a bottom layer formed of a metal material different from aluminum or an aluminum alloy under the aluminum layer or the aluminum alloy layer. Examples of the metal material that may be used to form such a bottom layer include molybdenum (Mo), titanium nitride (TiN), a molybdenum-tungsten alloy (MoW) and a molybdenum-niobium alloy (MoNb).

[0043] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. The metal material forming the lower layer may be, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy. The conductive oxide forming the upper layer may be, for example, ITO or IZO. The upper portion 62 may have a single-layer structure of a metal material.

[0044] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the side surfaces of the lower portion 61. A pixel voltage is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 included in each of the subpixels SP1, SP2, and SP3.

[0045] The organic layers OR1, OR2, and OR3 emit light in response to the application of a voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength region. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength region. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength region.

[0046] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0047] 4 is a schematic plan view showing the planar shape of the pixel aperture AP1 of the subpixel SP1. Note that although the pixel aperture AP1 of the subpixel SP1 is shown in this drawing, the pixel aperture AP2 of the subpixel SP2 and the pixel aperture AP3 of the subpixel SP3 also have a similar planar shape.

[0048] 4, the pixel opening AP1 has a pair of first straight line portions LX1 extending in the first direction X, a pair of second straight line portions LY1 extending in the second direction Y, and four corner portions CN1 formed in an arc shape. Each of the corner portions CN1 connects the adjacent first straight line portion LX1 and second straight line portion LY1. Although details will be described later, the pixel opening AP1 has a planar shape similar to that of a mask opening formed in a photomask for patterning a resist placed when forming the pixel opening AP1. Note that the opening AP61 in the partition wall 6 surrounding the pixel opening AP1 has a rectangular shape as shown in Fig. 4. That is, the pixel opening AP1 of the subpixel SP1 and the opening AP61 in the partition wall 6 around the subpixel SP1 have different planar shapes.

[0049] 5 is a diagram showing an example of a structure that can be applied to a rib 5 having a pixel opening. Note that, although this diagram shows a rib 5 having a pixel opening AP1, a similar structure can also be applied to a rib 5 having a pixel opening AP2 for subpixel SP2 and a rib 5 having a pixel opening AP3 for subpixel SP3.

[0050] 5, the end of the lower electrode LE1 is located below the lower portion 61. As a result, the step of the rib 5 caused by the lower electrode LE1 is covered by the lower portion 61.

[0051] 5, as described above, the upper electrode UE1 included in the laminated film FL1 is in contact with the side surface of the lower portion 61. The organic layer OR1 included in the laminated film FL1 is not in contact with the side surface of the lower portion 61, and is entirely covered with the upper electrode UE1. The cap layer CP1 included in the laminated film FL1 may or may not be in contact with the side surface of the lower portion 61.

[0052] 5, the end 51 of the rib 5 near the pixel aperture AP1 is gently inclined at an angle θ1 with respect to the upper surface of the lower electrode LE1. In other words, the end 51 of the rib 5 has a tapered shape (more specifically, a forward tapered shape in which the width of the rib 5 decreases toward the upper side along the third direction Z).

[0053] It is desirable that the angle θ1 (more specifically, the inclination angle θ1 of the end 51 with respect to the upper surface of the lower electrode LE1) be a value of 45° or less. In other words, it is desirable that the horizontal length L1 of the end 51 of the rib 5 is longer than the film thickness L2 of the rib 5. With this structure, it is possible to prevent the stacked film FL1 (the upper electrode UE1, the organic layer OR1, and the cap layer CP1) from being cut in a step at the end 51 of the rib 5 near the pixel opening AP1, and to prevent the sealing layer SE1 from being cut (the occurrence of defects such as cracks in the sealing layer SE1).

[0054] The end 51 of the rib 5 has the structure shown in Fig. 5 all around the pixel aperture AP1. That is, the end 51 of the rib 5 has the structure shown in Fig. 5 in the vicinity of the first straight line portion LX1, the second straight line portion LY1, and the corner portion CN1 of the pixel aperture AP1. As described above, the end 51 of the rib 5 also has the same structure all around the pixel aperture AP2 of the subpixel SP2 and the pixel aperture AP3 of the subpixel SP3.

[0055] 6 is a schematic plan view showing a part of a photomask PM for patterning a resist placed when forming pixel openings. The photomask PM is made of, for example, chromium (Cr). Note that in this figure, a part of the photomask PM corresponding to the pixel opening AP1 of the subpixel SP1 (i.e., the part corresponding to the pixel opening AP1 shown in FIG. 4) is shown, but the same is true for the parts corresponding to the pixel opening AP2 of the subpixel SP2 and the pixel opening AP3 of the subpixel SP3.

[0056] 6, the photomask PM has a mask opening AP1m corresponding to the pixel opening AP1. The mask opening AP1m has a pair of first straight line portions LX1m extending in the first direction X, a pair of second straight line portions LY1m extending in the second direction Y, and four corner portions CN1m formed in an arc shape. Each of the corner portions CN1m connects the adjacent first straight line portion LX1m and second straight line portion LY1m.

[0057] 5, that is, a structure in which the length L1 of the end 51 of the rib 5 is longer than the film thickness L2 of the rib 5 (in other words, a structure in which the end 51 of the rib 5 is gently inclined at an angle of 45° or less with respect to the upper surface of the lower electrode LE1), it is desirable to set the radius of curvature R1 of each of the corners CN1m to a value of 3 μm or more. More preferably, it is desirable to set the radius of curvature R1 of each of the corners CN1m to a value of 5 μm or more. In this way, it is possible to realize the structure shown in FIG. 5, the details of which will be described later.

[0058] In the example of Figure 6, each of the corners CN1m of the mask opening AP1m is shown to be an R-chamfered R surface (curved surface), but each of the corners CN1m may be a C-chamfered C surface (a surface along a straight line portion that connects the first straight line portion LX1m and the second straight line portion LY1m by a straight line portion inclined at 45° with respect to the first straight line portion LX1m or the second straight line portion LY1m).

[0059] The value of the R surface (radius of curvature) and the value of the C surface (dimension) are set based on the height of the partition 6 (lower part 61 and upper part 62) surrounding the pixel aperture AP1 and the distance from the opening AP61 of the partition 6 to the pixel aperture AP1.

[0060] 7 is a schematic plan view showing a part of another photomask PM for patterning a resist to be placed when forming pixel openings. The photomask PM shown in FIG. 7 has a first region r Cr and a second region r in which a halftone film is arranged instead of the above-mentioned chrome film. HT 6 in that it includes the following.

[0061] The shaded area in Figure 7 is the first area r Cr The dotted area in FIG. 7 corresponds to the second area r HT The second region r HT As shown in FIG. 7, the first region r Cr The light transmittance of the first region r where the halftone film is arranged is 0%, HT The light transmittance of the first region r is about 30% to 40%. The resist arranged at the position overlapping with the mask opening AP1m is removed by patterning, and the first region r Cr The resist disposed in the position overlapping with the second region r is not removed by patterning, and HT The resist disposed at a position overlapping the resist is partially removed by patterning.

[0062] 5, that is, a structure in which the length L1 of the end 51 of the rib 5 is longer than the film thickness L2 of the rib 5 (in other words, a structure in which the end 51 of the rib 5 is gently inclined at an angle of 45° or less with respect to the upper surface of the lower electrode LE1), the second region r HT It is desirable to set the width W1 to a value of 4 μm or more. By doing so, it is possible to realize the structure shown in FIG. 5 in the same way as in the case where the photomask PM shown in FIG.

[0063] As in the photomask PM shown in FIG. 6, each corner CN1m of the mask opening AP1m may be an R-chamfered R surface (curved surface) or a C-chamfered C surface.

[0064] Next, a process for forming a pixel aperture AP1 in the manufacturing method according to the present embodiment will be described with reference to Figures 8 and 9. Note that, although these figures show the formation of the pixel aperture AP1 of the subpixel SP1, the pixel aperture AP2 of the subpixel SP2 and the pixel aperture AP3 of the subpixel SP3 are also formed in the same process.

[0065] Although detailed illustration is omitted here, in manufacturing the display device DSP, first, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10. Next, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12. After that, an inorganic insulating layer 5a for processing into the rib 5 is formed so as to entirely cover the lower electrodes LE1, LE2, and LE3. Furthermore, a conductive first layer 61a for processing into the lower portion 61 is formed on the inorganic insulating layer 5a, and a second layer 62a for processing into the upper portion 62 is formed on the first layer 61a.

[0066] Next, the first layer 61a and the second layer 62a are patterned. This patterning includes etching to process the second layer 62a into the shape of the upper portion 62, and etching to process the first layer 61a into the shape of the lower portion 61. By these etchings, the partition wall 6 including the lower portion 61 and the upper portion 62 is formed on the inorganic insulating layer 5a.

[0067] After the partition 6 is formed, as shown in Fig. 8, a resist RG1 patterned into the planar shape of the rib 5 via the photomask PM shown in Fig. 6 or 7 is placed on the inorganic insulating layer 5a. By using the photomask PM shown in Fig. 6 or 7, the resist RG1 is patterned into an inclined shape near the portion where the pixel opening AP1 is formed, as shown in Fig. 8. Although not shown here, the shapes of the resist RG1 near the portion where the pixel opening AP2 is formed and near the portion where the pixel opening AP3 is formed are also similar.

[0068] 9, of the inorganic insulating layer 5a to be processed into the rib 5, the portion exposed from the resist RG1 is removed by etching. As a result, as shown in FIG. 9, the rib 5 having the pixel opening AP1 (and the pixel openings AP2 and AP3) and the gently tapered end portion 51 is formed.

[0069] Thereafter, the steps for forming the display elements DE1, DE2, and DE3 are performed in order. This results in the manufacture of a display device DSP having the structure shown in Fig. 5. That is, the display device DSP is manufactured in such a manner that the length L1 of the end 51 of the rib 5 is longer than the film thickness L2 of the rib 5 over the entire periphery of the pixel aperture AP1 (and the pixel apertures AP2 and AP3) (in other words, the end 51 of the rib 5 is gently inclined at an angle of 45° or less with respect to the upper surface of the lower electrode LE1).

[0070] Hereinafter, the effects of the manufacturing method and the display device DSP according to the present embodiment will be described using a comparative example. Note that the comparative example is intended to explain some of the effects that the manufacturing method and the display device DSP according to the present embodiment can achieve, and does not exclude the effects common to the present embodiment and the comparative example from the scope of the present invention.

[0071] 10 is a schematic plan view showing a part of a photomask PM' used in a manufacturing method according to a comparative example. Note that in this figure, the part of the photomask PM' corresponding to the pixel aperture AP1 of the subpixel SP1 is shown, but the parts corresponding to the pixel aperture AP2 of the subpixel SP2 and the pixel aperture AP3 of the subpixel SP3 are also similar.

[0072] The photomask PM' of the comparative example differs from the photomask PM of the present embodiment in that, as shown in FIG. 10, the planar shape of the mask opening AP1m is rectangular having a pair of first straight line portions LX1m extending in the first direction X and a pair of second straight line portions LY1m extending in the second direction Y.

[0073] Fig. 11 is a diagram for explaining a step of forming a pixel aperture AP1 in the manufacturing method according to the comparative example, and Fig. 12 is a schematic cross-sectional view showing a part of a display device DSP' manufactured by the manufacturing method according to the comparative example. In the manufacturing method according to the comparative example, when the partition wall 6 is formed by the same steps as in the manufacturing method according to the present embodiment, the resist RG1 patterned using the photomask PM' shown in Fig. 10 is disposed on the inorganic insulating layer 5a. As a result, the resist RG1 disposed mainly at the position overlapping with the vicinity of the corner of the rectangular mask opening AP1m is patterned into a steep shape, as shown in Fig. 11, and is not patterned into an inclined shape. Therefore, the end 51 of the rib 5 formed as a result of patterning using the resist RG1 as a mask also has a steep shape.

[0074] 12, the laminated film FL1 (organic layer OR1, upper electrode UE1, and cap layer CP1) evaporated on the lower electrode LE1 in the process of forming the display element DE1 may be cut at the end 51 of the rib 5. Furthermore, as shown in FIG. 12, the sealing layer SE1 covering the laminated film FL1 may be cut at the end 51 of the rib 5 (that is, defects such as cracks may occur in the sealing layer SE1). Such cuts in the laminated film FL1 and defects in the sealing layer SE1 may reduce the luminance of the display device, reduce the moisture resistance of the display device, and otherwise reduce the reliability of the display device.

[0075] In contrast, in the manufacturing method according to the present embodiment, the resist RG1 is patterned using the photomask PM shown in FIG. 6 or FIG. 7, and the resist RG1 arranged at a position overlapping with the vicinity of the corner CN1m of the mask opening AP1m can be patterned into an inclined shape (see FIG. 8). As a result of patterning using the resist RG1 as a mask, the end 51 of the rib 5 formed can be made into an inclined shape over the entire circumference of the pixel opening AP1, as shown in FIG. 9. This makes it possible to prevent the stacked film FL1 (upper electrode UE1, organic layer OR1, and cap layer CP1) from being cut at the end 51 of the rib 5, and to prevent the sealing layer SE1 from being cut (causing defects such as cracks in the sealing layer SE1). In other words, it is possible to suppress a decrease in the reliability of the display device.

[0076] According to the embodiment described above, it is possible to provide a display device and a manufacturing method thereof that are capable of suppressing a decrease in reliability.

[0077] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0078] DSP...display device, LE1, LE2, LE3...lower electrode, AP1, AP2, AP3...pixel aperture, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, FL1, FL2, FL3...laminated film, SE1, SE2, SE3...sealing layer, RG1...resist, 5...rib, 51...edge, 6...partition wall, 61...lower part, 62...upper part.

Claims

1. Forming a lower electrode; forming an inorganic insulating layer covering the lower electrode; forming a partition wall on the inorganic insulating layer, the partition wall including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion; forming a resist patterned using a photomask having an opening having a pair of first straight line portions extending in a first direction, a pair of second straight line portions extending in a second direction intersecting the first direction, and four arc-shaped corner portions connecting adjacent first straight line portions and second straight line portions on the inorganic insulating layer; a rib having a pixel opening overlapping with the lower electrode is formed by removing a portion of the inorganic insulating layer exposed from the resist; A method for manufacturing a display device.

2. the rib has a tapered end portion around the entire periphery of the pixel opening; The method for manufacturing the display device according to claim 1 .

3. The inclination angle of the end of the rib is 45° or less. The method for manufacturing the display device according to claim 2 .

4. The radius of curvature of each of the corners is 3 μm or more. The method for manufacturing the display device according to claim 1 .

5. the photomask includes a halftone film disposed in areas corresponding to the corners, and a chrome film disposed in the areas corresponding to the corners and in areas other than the openings; The method for manufacturing the display device according to claim 1 .

6. The width of the half-tone film is 4 μm or more. The method for manufacturing the display device according to claim 5 .

7. forming an organic layer that covers the lower electrode and emits light in response to application of a voltage; forming an upper electrode covering the organic layer and in contact with the lower portion; The method for manufacturing a display device according to any one of claims 1 to 6, further comprising:

8. forming a sealing layer that continuously covers the stacked film including the organic layer and the upper electrode and the partition wall; The method for manufacturing a display device according to claim 7 , further comprising:

9. A lower electrode; a rib having a pixel opening overlapping the lower electrode; a partition wall including a conductive lower portion disposed on the rib and an upper portion having an end portion protruding from a side surface of the lower portion; a laminated film including an organic layer in contact with the lower electrode through the pixel opening and an upper electrode covering the organic layer; a sealing layer covering the laminated film; Equipped with the rib has a tapered end portion around the entire periphery of the pixel opening; Display device.

10. The inclination angle of the end of the rib is 45° or less. The display device according to claim 9.

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