Wiring board and method for manufacturing wiring board

Abstract

To provide a wiring board and a method for manufacturing the wiring board capable of suppressing a decrease in connection reliability.SOLUTION: A wiring board has a wiring layer, a first insulating layer provided on the wiring layer, a second insulating layer provided on the first insulating layer, a first opening formed in the first insulating layer and reaching the wiring layer, a second opening formed in the second insulating layer, with a lower end connected to an upper end of the first opening, a third opening formed in the second insulating layer, with a lower end connected to an upper end of the second opening, and connection terminals formed in the first opening, the second opening, and the third opening and in contact with an upper surface of the wiring layer. A diameter of the lower end of the second opening is equal to a diameter of the upper end of the first opening, and a diameter of the lower end of the third opening is larger than a diameter of the upper end of the second opening.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] The wiring board has connection terminals to which semiconductor elements etc. are connected. When forming the connection terminals, the following steps are performed: forming an insulating layer that covers the wiring layer, forming openings in the insulating layer, forming the connection terminals in the openings using a growth mask, forming a solder resist layer that covers the insulating layer and the connection terminals, forming openings in the solder resist layer, and surface treating the connection terminals by electroless plating. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-192885 A Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional wiring boards, the growth mask used to form the connection terminals may be misaligned, or the openings in the solder resist layer may be misaligned. As a result, as miniaturization progresses, there is a risk of a decrease in connection reliability due to these misalignments. For example, there is a risk of poor electrical continuity or short circuits between adjacent connection terminals.

[0005] An object of the present disclosure is to provide a wiring board capable of suppressing a decrease in connection reliability and a method for manufacturing the wiring board. [Means for solving the problem]

[0006] According to one embodiment of the present disclosure, there is provided a wiring substrate having a wiring layer, a first insulating layer provided on the wiring layer, a second insulating layer provided on the first insulating layer, a first opening formed in the first insulating layer and reaching the wiring layer, a second opening formed in the second insulating layer and having a lower end connected to an upper end of the first opening, a third opening formed in the second insulating layer and having a lower end connected to an upper end of the second opening, and connection terminals formed in the first opening, the second opening, and the third opening and in contact with an upper surface of the wiring layer, wherein a diameter of the lower end of the second opening is equal to a diameter of the upper end of the first opening, and a diameter of the lower end of the third opening is larger than a diameter of the upper end of the second opening. Effect of the Invention

[0007] According to the disclosed technology, it is possible to suppress a decrease in connection reliability. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a wiring board according to a first embodiment. [Diagram 2] 1A to 1C are cross-sectional views (part 1) illustrating the method for manufacturing a wiring board according to a first embodiment. [Diagram 3] 5A to 5C are cross-sectional views (part 2) illustrating the method for manufacturing the wiring board according to the first embodiment. [Figure 4] 5A to 5C are cross-sectional views (part 3) illustrating the method for manufacturing the wiring board according to the first embodiment. [Diagram 5] FIG. 2 is a schematic diagram showing an example of a laser light irradiation method. [Figure 6] FIG. 11 is a cross-sectional view showing a wiring board according to a second embodiment. [Figure 7] 6A to 6C are cross-sectional views showing a method for manufacturing a wiring board according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configurations are denoted by the same reference numerals, and redundant description may be omitted.

[0010] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a wiring board.

[0011] [Wiring board structure] A description will now be given of the structure of the wiring board according to the first embodiment. Fig. 1 is a cross-sectional view showing the wiring board according to the first embodiment.

[0012] As shown in FIG. 1, the wiring board 1 according to the first embodiment has, for example, a wiring layer 11, an insulating layer 12, a solder resist layer 13, a connection terminal 30, and a solder bump 14. In this disclosure, for convenience, the solder resist layer 13 side is referred to as the upper side or one side, and the opposite side is referred to as the lower side or other side, based on the wiring layer 11. In addition, the upper surface of each part is referred to as one side or top surface, and the lower surface is referred to as the other side or bottom surface. However, the wiring board 1 can be used upside down or placed at any angle. FIG. 1 illustrates the vicinity of one side (top surface) of the wiring board 1. In addition, a plan view refers to viewing an object from the normal direction of one side of the solder resist layer 13.

[0013] The wiring board 1 has a plurality of wiring layers 11 and insulating layers 12. The wiring layer 11 is provided between two insulating layers 12 adjacent to each other in the thickness direction. The wiring layers 11 adjacent to each other in the thickness direction are electrically connected to each other through conductive vias in via holes formed in the insulating layers 12 between them. The material of the wiring layer 11 is, for example, copper (Cu) or the like. The material of the insulating layer 12 is, for example, an insulating resin mainly composed of an epoxy resin or a polyimide resin. The insulating layer 12 may contain a filler such as silica (SiO2). The wiring board 1 may have a core layer containing glass epoxy or the like.

[0014] Focusing on the uppermost pair of wiring layer 11 and insulating layer 12 (hereinafter sometimes referred to as wiring layer 11A and insulating layer 12A, respectively), insulating layer 12A is provided on wiring layer 11A and covers wiring layer 11A. Solder resist layer 13 is provided on insulating layer 12A and covers insulating layer 12A. Insulating layer 12A is an example of a first insulating layer, and solder resist layer 13 is an example of a second insulating layer.

[0015] A first opening 21 reaching the wiring layer 11A is formed in the insulating layer 12A. The upper end of the first opening 21 is on the upper surface of the insulating layer 12A. A second opening 22 and a third opening 23 are formed in the solder resist layer 13. The second opening 22 is formed below the third opening 23, the lower end of the second opening 22 is on the lower surface of the solder resist layer 13, and the upper end of the third opening 23 is on the upper surface of the solder resist layer 13. A plurality of sets of the first opening 21, the second opening 22, and the third opening 23 are formed.

[0016] The lower end of the second opening 22 is connected to the upper end of the first opening 21, and the lower end of the third opening 23 is connected to the upper end of the second opening 22. The diameter of the lower end of the second opening 22 is equal to the diameter of the upper end of the first opening 21, and the diameter of the lower end of the third opening 23 is larger than the diameter of the upper end of the second opening 22. The inner wall surface of the first opening 21 and the inner wall surface of the second opening 22 are connected over the entire circumference. The inner wall surface of the second opening 22 and the bottom surface 43 of the third opening 23 are connected over the entire circumference, and in a plan view, the inner wall surface of the second opening 22 is inside the inner wall surface 42 of the third opening 23 over the entire circumference.

[0017] The angle θ between the bottom surface 43 of the third opening 23 and the inner wall surface 42 of the third opening 23 is, for example, 85° or more and 95° or less, preferably 87° or more and 92° or less, and more preferably 89° or more and 91° or less.

[0018] The connection terminal 30 is formed in the first opening 21, the second opening 22, and the third opening 23. In other words, the connection terminal 30 is formed for each set of the first opening 21, the second opening 22, and the third opening 23. The connection terminal 30 has a via region 31 and a pad region 32. The via region 31 is in the first opening 21 and the second opening 22, and the pad region 32 is in the third opening 23. The via region 31 and the pad region 32 are formed integrally. The diameter of the lower end of the pad region 32 is larger than the diameter of the upper end of the via region 31. The side surface 41 of the pad region 32 contacts the inner wall surface 42 of the third opening 23. The pad region 32 has a surface 35 that contacts the bottom surface 43 of the third opening 23. The solder resist layer 13 is not in contact with the upper surface of the pad region 32, and the entire upper surface of the pad region 32 is exposed from the third opening 23. When the angle θ is equal to or greater than 90°, the upper surface of the pad region 32 is not covered with the solder resist layer 13 .

[0019] The connection terminal 30 has a first layer 51 and a second layer 52. The first layer 51 contacts the solder resist layer 13, the insulating layer 12A, and the wiring layer 11A. The second layer 52 is provided inside the first layer 51. The electrical resistivity of the material constituting the second layer 52 is lower than that of the material constituting the first layer 51. In addition, the adhesion between the material constituting the first layer 51 and the solder resist layer 13 is higher than that between the material constituting the second layer 52 and the solder resist layer 13. The first layer 51 functions as an adhesion layer. For example, the first layer 51 contains titanium (Ti), and the second layer 52 contains copper (Cu). The first layer 51 may be a titanium layer or a copper-nickel-titanium (Cu-Ni-Ti) alloy layer, and the second layer 52 may be a copper layer. The second layer 52 may be thicker than the first layer 51.

[0020] For example, the upper end surface of the first layer 51 may be flush with the upper surface of the solder resist layer 13 , and the upper surface of the second layer 52 may be lower than the upper surface of the solder resist layer 13 .

[0021] The solder bumps 14 are provided on the connection terminals 30. Examples of materials for the solder bumps 14 include lead-free solders such as tin-silver (SnAg) alloys, tin-zinc (SnZn) alloys, and tin-copper (SnCu) alloys, as well as lead-containing solders such as lead-tin (PbSn) alloys. The solder bumps 14 are in contact with the upper surfaces of the connection terminals 30. Part of the solder bumps 14 may be in contact with the upper surface of the solder resist layer 13.

[0022] [Method of manufacturing wiring board] Next, a method for manufacturing the wiring board according to the first embodiment will be described. Figures 2 to 4 are cross-sectional views showing the method for manufacturing the wiring board according to the first embodiment.

[0023] 2(a), a laminate is formed including a plurality of insulating layers 12 and a plurality of wiring layers 11. The laminate can be formed by, for example, a build-up method. The wiring layers 11 can be formed by, for example, a semi-additive method or a subtractive method.

[0024] Next, as shown in FIG. 2(b), a solder resist layer 13 is formed on the uppermost insulating layer 12A among the multiple insulating layers 12.

[0025] Thereafter, as shown in FIG. 2(c), the second opening 22 and the third opening 23 are formed in the solder resist layer 13, and the first opening 21 is formed in the insulating layer 12A. The second opening 22 is formed so that the diameter of its lower end is equal to the diameter of the upper end of the first opening 21, and the third opening 23 is formed so that the diameter of its lower end is larger than the diameter of the upper end of the second opening 22. The first opening 21, the second opening 22, and the third opening 23 can be formed by irradiation of a laser beam such as an excimer laser beam. In the third opening 23 formed by irradiation of the laser beam, the angle θ between the bottom surface 43 and the inner wall surface 42 is likely to be 85° or more and 95° or less. After the formation of the first opening 21, the second opening 22, and the third opening 23, a plasma treatment may be performed as a descum treatment. When the plasma treatment is performed, the angle θ becomes closer to 90°.

[0026] For example, as shown in FIG. 5, the first opening 21, the second opening 22, and the third opening 23 can be formed at the same time by using a mask 70 that weakens the intensity of the laser light 60 to lower the intensity of the laser light 60B irradiated to the region where the third opening 23 is to be formed than the intensity of the laser light 60A irradiated to the region where the first opening 21 and the second opening 22 are to be formed. The mask 70 has a first light-transmitting portion 71, a second light-transmitting portion 72, and a light-shielding portion 73. The intensity of the laser light passing through the second light-transmitting portion 72 is lower than the intensity of the laser light passing through the first light-transmitting portion 71. Alternatively, the third opening 23 and the first opening 21 and the second opening 22 may be formed separately by irradiating the laser light with different intensities twice without using the mask 70.

[0027] 3(a), a first layer 51 is formed on the wiring layer 11A, the insulating layer 12A, and the solder resist layer 13 by sputtering, and a plating seed layer 53 is formed on the first layer 51. For example, the first layer 51 is a titanium layer, and the plating seed layer 53 is a copper layer. For example, the thickness of the first layer 51 is 10 nm to 100 nm, and the thickness of the plating seed layer 53 is 100 nm to 500 nm.

[0028] 3(b), a plating layer is formed by electrolytic plating using the plating seed layer 53 as a power supply path, thereby forming a second layer 52 including the plating seed layer 53. At this time, the second layer 52 is formed so that the upper surface of the second layer 52 is located above the upper surface of the solder resist layer 13.

[0029] Thereafter, as shown in FIG. 3(c), the second layer 52, the first layer 51, and the solder resist layer 13 are subjected to chemical mechanical polishing (CMP) so that the upper surface of the second layer 52, the upper end surface of the first layer 51, and the upper surface of the solder resist layer 13 are made flush with each other.

[0030] 4(a), the surface portion of the second layer 52 is etched so that the upper surface of the second layer 52 is positioned lower than the upper surface of the solder resist layer 13. In this manner, the connection terminal 30 is formed, which has the first layer 51 and the second layer 52. After etching the surface portion of the second layer 52, the upper surface of the connection terminal 30 may be surface-treated by electroless plating.

[0031] Next, as shown in FIG. 4(b), the solder bumps 14 are formed on the connection terminals 30.

[0032] In this manner, the wiring board 1 according to the first embodiment can be manufactured.

[0033] In the wiring board 1, a first opening 21 is formed in the insulating layer 12A, a second opening 22 and a third opening 23 are formed in the solder resist layer 13, and a connection terminal 30 is formed in the first opening 21, the second opening 22, and the third opening 23. The diameter of the lower end of the second opening 22 is equal to the diameter of the upper end of the first opening 21, and the diameter of the lower end of the third opening 23 is larger than the diameter of the upper end of the second opening 22. Therefore, for example, by irradiating a laser beam, the first opening 21, the second opening 22, and the third opening 23 can be formed while suppressing misalignment with each other, and the connection terminal 30 can be formed while suppressing misalignment with respect to the first opening 21, the second opening 22, and the third opening 23. Therefore, it is possible to suppress poor conduction and short circuits between the connection terminals 30, and to suppress a decrease in connection reliability. When the first opening 21, the second opening 22, and the third opening 23 are formed collectively, it is particularly easy to suppress misalignment.

[0034] In addition, since the connection terminal 30 has the first layer 51 that can function as an adhesive layer, even if the upper surface of the connection terminal 30 is surface-treated by electroless plating after etching the surface portion of the second layer 52, the plating solution is unlikely to penetrate between the side surface 41 of the pad region 32 and the inner wall surface 42 of the third opening 23 during the surface treatment. Furthermore, since the pad region 32 has a surface 35 that contacts the bottom surface 43 of the third opening 23 and a part of the solder resist layer 13 is present between the pad region 32 and the insulating layer 12A, even if the plating solution penetrates between the side surface 41 and the inner wall surface 42, the plating solution is unlikely to reach between the solder resist layer 13 and the insulating layer 12A. Therefore, short circuits and haloing due to the penetration of the plating solution can be suppressed.

[0035] Moreover, the first layer 51 functions as an adhesive layer, thereby making it possible to prevent the connection terminals 30 from peeling off or coming off from the solder resist layer 13. Furthermore, when the first layer 51 contains titanium and the second layer 52 contains copper, the first layer 51 can function as a barrier layer that prevents copper migration. Therefore, it is possible to prevent short circuits caused by copper migration.

[0036] In addition, since the interface between the pad region 32 and the solder resist layer 13 is separated from the insulating layer 12A, peeling of the bottom of the pad region 32 due to the difference in the amount of strain between the insulating layer 12A and the solder resist layer 13 is less likely to occur, and high resistance to thermal stress associated with thermal expansion is obtained.

[0037] Second embodiment Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the connection terminals.

[0038] [Wiring board structure] The structure of the wiring board according to the second embodiment will now be described with reference to Fig. 6, which is a cross-sectional view showing the wiring board according to the second embodiment.

[0039] 2, in the wiring board 2 according to the second embodiment, in terms of the area configuration, the connection terminal 30 has a via area 31 and a pad area 32, similarly to the first embodiment. On the other hand, in terms of the layer configuration, the connection terminal 30 has a second layer 52 but does not have a first layer 51. The second layer 52 contacts the solder resist layer 13, the insulating layer 12A, and the wiring layer 11A.

[0040] Other configurations of the second embodiment are similar to those of the first embodiment.

[0041] [Method of manufacturing wiring board] Next, a method for manufacturing a wiring board according to the second embodiment will be described with reference to Fig. 7, which is a cross-sectional view showing the method for manufacturing a wiring board according to the second embodiment.

[0042] First, similarly to the first embodiment, processing is performed up to the formation of the first opening 21, the second opening 22, and the third opening 23 (see FIG. 2(c)). Next, as shown in FIG. 7(a), a plating seed layer 54 is formed on the wiring layer 11A, the insulating layer 12A, and the solder resist layer 13 by electroless plating. For example, the plating seed layer 54 is a copper layer. For example, the thickness of the plating seed layer 54 is 100 nm to 1000 nm.

[0043] 7(b), a plating layer is formed by electrolytic plating using the plating seed layer 54 as a power supply path, thereby forming a second layer 52 including the plating seed layer 54. At this time, similarly to the first embodiment, the second layer 52 is formed so that the upper surface of the second layer 52 is located above the upper surface of the solder resist layer 13.

[0044] 7(c), similarly to the first embodiment, the second layer 52, the first layer 51, and the solder resist layer 13 are subjected to CMP and subsequent processing, and the surface portion of the second layer 52 is etched so that the upper surface of the second layer 52 is positioned lower than the upper surface of the solder resist layer 13. In this manner, the connection terminal 30 is formed. After etching the surface portion of the second layer 52, the upper surface of the connection terminal 30 may be surface-treated by electroless plating.

[0045] Next, similarly to the first embodiment, the solder bumps 14 are formed on the connection terminals 30 (see FIG. 7).

[0046] In this manner, the wiring board 2 according to the second embodiment can be manufactured.

[0047] In the wiring board 2, similarly to the first embodiment, it is possible to suppress poor electrical continuity and short circuits between the connection terminals 30, and to suppress a decrease in connection reliability.

[0048] Although the first layer 51 is not formed, the pad region 32 has a surface 35 that contacts the bottom surface 43 of the third opening 23, and a part of the solder resist layer 13 exists between the pad region 32 and the insulating layer 12A, as in the first embodiment. Therefore, even if a plating solution for surface treatment penetrates between the side surface 41 and the inner wall surface 42, the plating solution is unlikely to reach between the solder resist layer 13 and the insulating layer 12A. Therefore, it is possible to suppress short circuits and haloing due to the penetration of the plating solution.

[0049] Also, in forming the plating seed layer 54 (see FIG. 7(a)), the interface between the solder resist layer 13 and the insulating layer 12A is only exposed at the boundary between the first opening 21 and the second opening 22, so by spraying the plating liquid onto the top surface of the solder resist layer 13 in a direction perpendicular to the top surface, it is possible to prevent the plating liquid from penetrating into the interface between the solder resist layer 13 and the insulating layer 12A.

[0050] Although the preferred embodiments have been described in detail above, the present disclosure is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0051] 1, 2 Wiring board 11, 11A wiring layer 12, 12A insulation layer 13 Solder resist layer 14. Bump 21 First opening 22 Second opening 23 Third Opening 30 Connection terminal 31 Via Area 32 Pad Area 35 sides 41 Side 42 Inner wall surface 43 Bottom 51 1st layer 52 2nd layer 53, 54 Plating seed layer

Claims

1. A wiring layer; a first insulating layer provided on the wiring layer; a second insulating layer provided on the first insulating layer; a first opening formed in the first insulating layer and reaching the wiring layer; a second opening formed in the second insulating layer, the lower end of the second opening being connected to the upper end of the first opening; a third opening formed in the second insulating layer, the lower end of the third opening being connected to the upper end of the second opening; connection terminals formed in the first opening, the second opening, and the third opening and in contact with an upper surface of the wiring layer; having The diameter of the lower end of the second opening is equal to the diameter of the upper end of the first opening, The third opening has a lower end with a larger diameter than an upper end of the second opening.

2. 2. The wiring board according to claim 1, wherein the composition of the first insulating layer is different from the composition of the second insulating layer.

3. 2. The wiring board according to claim 1, wherein the second insulating layer is a solder resist layer.

4. The connection terminal is a first layer in contact with the second insulating layer, the first insulating layer, and the wiring layer; A second layer provided inside the first layer; having the electrical resistivity of the material constituting the second layer is lower than the electrical resistivity of the material constituting the first layer; The wiring board according to claim 1 , wherein the adhesion between the material constituting the first layer and the second insulating layer is higher than the adhesion between the material constituting the second layer and the second insulating layer.

5. the first layer comprises titanium; The wiring board according to claim 4 , wherein the second layer contains copper.

6. The connection terminal is a via region in the first opening and the second opening; a pad area in the third opening; having The wiring board according to claim 1 , wherein the pad region has a surface in contact with a bottom surface of the third opening.

7. The wiring board according to claim 6 , wherein a side surface of the pad region contacts an inner wall surface of the third opening.

8. forming a first insulating layer on the wiring layer; forming a second insulating layer on the first insulating layer; forming a first opening in the first insulating layer, the first opening reaching the wiring layer, and forming a second opening in the second insulating layer, the second opening having a lower end connected to an upper end of the first opening and a third opening having a lower end connected to an upper end of the second opening; forming connection terminals in the first opening, the second opening, and the third opening so as to contact an upper surface of the wiring layer; having The diameter of the lower end of the second opening is equal to the diameter of the upper end of the first opening, A method for manufacturing a wiring substrate, wherein a diameter of a lower end of the third opening is larger than a diameter of an upper end of the second opening.

9. The method for manufacturing a wiring board according to claim 8 , wherein the first opening, the second opening, and the third opening are formed by irradiation with laser light.

10. The method for manufacturing a wiring board according to claim 8 , wherein the first opening, the second opening, and the third opening are formed simultaneously.

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