Memory system, information processing device, information processing system, and data rearrangement method

Abstract

To provide a memory system capable of efficiently resolving the data fragmentation of a file.SOLUTION: According to an embodiment, a memory system comprises a non-volatile memory and a controller. The controller can communicate with a host, and controls the non-volatile memory. The controller receives first information on file data mapping for a logical address space of the memory system from the host, and rearranges the data of the file fragmented in a physical address space in the physical address space so that the data of the file is consecutive in the physical address space on the basis of the received first information and second information recording a correspondence between logical addresses indicative of locations in the logical address space and physical addresses indicative of locations in the physical address space of the non-volatile memory.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] FIELD Embodiments of the present invention relate to a memory system, an information processing device, an information processing system, and a data relocation method. [Background technology]

[0002] In recent years, solid state drives (SSDs) have become widespread as storage devices.

[0003] When a host file system maps file data to the logical address space of an SSD, such as when writing a file to an SSD, the data may become fragmented under certain circumstances. If continuous data such as file data is fragmented and mapped to the logical address space, it is highly likely that it will also be fragmented and mapped to the physical address space of the SSD.

[0004] A file whose data is fragmented in the physical address space tends to degrade the sequential read performance of an SSD compared to a non-fragmented file.

[0005] In order to prevent performance degradation due to fragmentation, typical file systems perform defragmentation as a function to move fragmented continuous data in the logical address space to a continuous area in the logical address space. By performing defragmentation, it is expected that continuous data will also be moved to a continuous area in the physical address space.

[0006] Defragmentation is initiated by an end user's command. During defragmentation, the I / O performance of the SSD decreases. Therefore, end users cannot easily instruct defragmentation. However, unless defragmentation is performed, the SSD cannot recover from the performance degradation caused by fragmentation. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] U.S. Pat. No. 1,104,2317 [Patent Document 2] U.S. Pat. No. 1,520,695 Summary of the Invention [Problem to be solved by the invention]

[0008] One embodiment provides a memory system, an information processing device, an information processing system, and a data relocation method that can efficiently eliminate fragmentation of file data. [Means for solving the problem]

[0009] According to an embodiment, a memory system includes a nonvolatile memory and a controller. The controller is capable of communicating with a host and controls the nonvolatile memory. The controller receives from the host first information regarding mapping of file data to a logical address space of the memory system, and performs relocation of fragmented file data in the physical address space based on the received first information and second information in which a correspondence relationship between a logical address indicating a position in the logical address space and a physical address indicating a position in the physical address space of the nonvolatile memory is recorded, so that the file data becomes contiguous in the physical address space. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of an information processing system according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing a configuration example of a memory die of the memory system according to the first embodiment. [Diagram 3] FIG. 2 is a diagram showing a configuration example of a logical block of the memory system according to the first embodiment. [Figure 4] FIG. 13 is a diagram for explaining a first comparative example regarding data rearrangement. [Diagram 5]FIG. 2 is a diagram for explaining data rearrangement by the memory system according to the first embodiment. [Figure 6] 4 is a flowchart showing a procedure of a data rearrangement process executed by the memory system of the first embodiment. [Figure 7] 13A and 13B are diagrams showing an example of a transition of a file defragmentation state managed by a host in the information processing system of the second embodiment. [Figure 8] FIG. 11 is a diagram showing a communication sequence regarding file defragmentation between a host and a memory system in the information processing system of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments will be described with reference to the drawings.

[0012] (First embodiment) First, the first embodiment will be described.

[0013] FIG. 1 is a diagram illustrating an example of a configuration of an information processing system according to the first embodiment.

[0014] The information processing system includes a memory system 1 and a host 2. Here, an example in which the memory system 1 is realized as an SSD will be described. The memory system 1 is configured to be connectable to the host 2. The host 2 is an information processing device such as a server or a personal computer. FIG. 1 shows a state in which the memory system 1 and the host 2 are connected.

[0015] The memory system 1 includes a controller 11, a dynamic random access memory (DRAM) 12, and a NAND type flash memory (hereinafter, referred to as a flash memory) 13. The memory system 1 is implemented, for example, by a PCI Express TM (PCIe TM ) standard.

[0016] The controller 11 is a device that controls the flash memory 13. For example, the controller 11 controls the writing of data to the flash memory 13 and the reading of data from the flash memory 13 based on a command from the host 2, while using an area of ​​the DRAM 12 as a working area. The controller 11 is, for example, an NVM Express TM (NVMe TM The controller 11 communicates with the host 2 using a protocol conforming to the IEEE 802.11a standard. The controller 11 can be configured as a semiconductor integrated circuit, for example, a System on a Chip (SoC).

[0017] The controller 11 has a data reallocation control unit 111. The data reallocation control unit 111 executes data reallocation for shifting data that is in a fragmented state in the flash memory 13 to a continuous state. The details of the data reallocation control unit 111 will be described later.

[0018] The DRAM 12 is a volatile storage device. Here, an example is shown in which the memory system 1 includes the DRAM 12 as a device that provides a working area to the controller 11. The controller 11 may include a static random access memory (SRAM), and the area of ​​this SRAM may be used as the working area. In other words, as an example of the configuration of the memory system 1, a configuration without the DRAM 12 is also conceivable.

[0019] The flash memory 13 is a non-volatile storage device and includes a plurality of memory dies 131.

[0020] A predetermined number of memory dies 131 out of the multiple memory dies 131 are used as a parallel operation unit of the flash memory 13. The controller 11 selects physical blocks one by one from the predetermined number of memory dies 131 used as the parallel operation unit of the flash memory 13, and configures a logical block including the selected predetermined number of physical blocks. The logical block is an extended management unit configured so that the controller 11 can efficiently use the area of ​​the flash memory 13. The logical block is also called a superblock.

[0021] In addition, when each of the multiple memory dies 131 has multiple planes that can operate in parallel in each memory die 131, the controller 11 selects one physical block from each plane of a predetermined number of memory dies 131 to configure a logical block.

[0022] Here, the logical blocks that the controller 11 constitutes will be described.

[0023] FIG. 2 is a diagram showing an example of the configuration of the memory die 131. As shown in FIG.

[0024] Each memory die 131 includes a plurality of physical blocks 150. Each of the plurality of physical blocks 150 includes a plurality of pages 151. Data is written to and read from the memory die 131 in units of pages 151. Note that in FIG. 2, planes are not shown for ease of understanding.

[0025] FIG. 3 is a diagram showing an example of the configuration of the logic block 200. As shown in FIG.

[0026] For example, a case will be described where N (N is a natural number equal to or greater than 2) memory dies 131 are used as parallel operation units of the flash memory 13. In this case, the controller 11 selects physical blocks 150 one by one from the N memory dies 131, and configures a logical block 200 including the selected N physical blocks 150. Since the N physical blocks 150 included in the logical block 200 are capable of parallel operation, the controller 11 can, for example, write data to the logical block 200 N pages at a time.

[0027] In addition, when each of the multiple memory dies 131 has M (M is a natural number equal to or greater than 2) planes, N memory dies 131×M planes are used as a parallel operation unit of the flash memory 13. In this case, the controller 11 selects one physical block 150 from the M planes for each of the N memory dies 131, and configures a logical block 200 including the selected N×M physical blocks 150. Since the N×M physical blocks 150 included in the logical block 200 can operate in parallel, the controller 11 can, for example, write data to the logical block 200 N×M pages at a time.

[0028] Next, a first comparative example regarding data rearrangement will be described with reference to Fig. 4. This first comparative example is an example in which data rearrangement for eliminating fragmentation of file data is executed by defragmentation using the file system of the host 2.

[0029] Fig. 4(A) shows an example in which fragmentation of file data occurs. Here, writing of file 1 and writing of file 2 are executed in parallel at the same timing. The table indicated by reference numeral 300 in Fig. 4(A) shows a part of mapping information managed by the file system. This mapping information is information regarding mapping of file data to the logical address space (LBA [Logical Block Address] area) of the memory system 1. The mapping information is an example of first information.

[0030] The file system of the host 2 first maps one page of data of file 1 into the logical address space of the memory system 1, and also maps one page of data of file 2. Specifically, the file system maps the first page of data (F1_0) of file 1 to addresses (LBA) 0h-20h in the logical address space, and also maps the first page of data (F2_0) of file 2 to addresses 20h-40h.

[0031] Next, the file system maps data F1_1 of file 1 to addresses 40h-60h, and also maps data F2_1 of file 2 to addresses 60h-80h.

[0032] Similarly, the file system maps data F1_2 of file 1 to addresses 80h-a0h, data F2_2 of file 2 to addresses a0h-c0h, data F1_3 of file 1 to addresses c0h-e0h, and data F2_3 of file 2 to addresses e0h-100h, mapping data to the logical address space of memory system 1.

[0033] That is, the data of both file 1 and file 2 is mapped in a fragmented manner with respect to the logical address space of memory system 1.

[0034] When the data of file 1 and file 2 is written to memory system 1 in the order of mapping to this logical address space, the data is fragmented and allocated in the physical address space of memory system 1, i.e., in flash memory 13, as shown in Fig. 4(A), the details of which will be described later. In other words, the logical address space of memory system 1 corresponds to the physical address space of the area in which flash memory 13 of memory system 1 can store data.

[0035] The correspondence between the logical address space and the physical address space of the memory system 1 is managed by the controller 11 of the memory system 1 using information called a logical-physical conversion table. The logical-physical conversion table is an example of the second information.

[0036] FIG. 4A shows an example in which the logical block 200 is configured with four physical blocks 150 for ease of understanding. For example, the logical block 200 is configured with four physical blocks 150 selected one by one from four memory dies 131 among a plurality of memory dies 131. In this case, the data of the four pages 151 connected to the word line (WL) 0 in each of the four physical blocks 150 can be read in parallel (a1). This is also true for the data of the four pages 151 connected to the word line (WL) 1 in each of the four physical blocks 150. On the other hand, for the data of the multiple pages 151 connected to different word lines, such as the data of the page 151 connected to the word line 0 and the data of the page 151 connected to the word line 1, the data must be read sequentially for each word line even if the data is stored in the same physical block 150 (a2).

[0037] Here, the controller 11 of the memory system 1 manages the mapping of the pages 151 to the physical address space so that the pages 151 of the logical block 200 that can be read and written in parallel are continuous as a single block. Therefore, the data of the file 1 and the file 2 shown in FIG. 4(A) is in a fragmented state in the physical address space, that is, in the flash memory 13.

[0038] In order to eliminate this fragmentation, when defragmentation is started by the file system of host 2, host 2 reads and writes back the data of file 1, and reads and writes back the data of file 2. In this case, as shown in Fig. 4(B), when writing back the data of file 1, the file system maps the data of file 1 to a continuous area in the logical address space, and when writing back the data of file 2, it maps the data of file 2 to a continuous area in the logical address space.

[0039] That is, in defragmentation by the file system of the host 2, the data of file 1 and file 2 is rearranged under the initiative of the host 2. This is expected to eliminate fragmentation in the logical address space as well as in the physical address space. However, in the memory system 1, for example, to preserve data, the controller 11 may write and read data to and from the flash memory 13 as an internal process, without following a command from the host 2. Therefore, under the initiative of the host 2, there is no guarantee that fragmentation in the physical address space will be eliminated along with elimination of fragmentation in the logical address space.

[0040] Note that the logical block 200 in FIG. 4B is different from the logical block 200 in FIG. 4A. Also, in FIG. 4B, for ease of understanding in comparison with FIG. 4A, an example is shown in which the data of file 1 is relocated to the page 151 group connected to word line 0, and the data of file 2 is relocated to the page 151 group connected to word line 1. However, regardless of the position of the word line to which the page group 151 that stored the data of file 1 and file 2 in the logical block 200 before the relocation is connected, the data may be relocated to the page 151 group connected to any word line in the logical block 200 after the relocation.

[0041] Defragmentation is initiated by an instruction from an end user. During the defragmentation period, the I / O performance of the memory system 1 decreases. Therefore, the end user cannot easily instruct defragmentation. However, unless defragmentation is performed, the memory system 1 cannot recover from the performance decrease caused by fragmentation.

[0042] Based on this first comparative example, next, data rearrangement in the memory system 1 of the first embodiment will be described with reference to FIG.

[0043] In the information processing system of the first embodiment, when fragmentation of data of file 1 and file 2 is to be eliminated, the host 2 provides the memory system 1 with a part of the mapping information managed by the file system, the part including at least information related to the data of file 1 and file 2 (b1). Hereinafter, the part of the mapping information provided from the host 2 to the memory system 1 is also referred to as file fragment information. In Fig. 5, the file fragment information includes at least the logical address of the data of file 1 and the logical address of the data of file 2.

[0044] The provision of file fragment information from host 2 to memory system 1 is, for example, NVMe TM This is executed by the host 2 issuing an extension command defined in the standard to the memory system 1. This extension command may be defined as a command by the host 2 requesting the memory system 1 to defragment data.

[0045] The file fragment information is received by the controller 11 of the memory system 1. The data reallocation control unit 111 of the controller 11 executes reallocation of the data of file 1 and the data of file 2 based on the file fragment information and a logical-physical conversion table managed by the controller 11 (b2). At this time, the data reallocation control unit 111 moves the data of file 1 and the data of file 2 so that these data are continuous in the physical address space.

[0046] The data reallocation control unit 111 performs reallocation in the physical address space to eliminate fragmentation of continuous data during an idle period in which processing corresponding to a read command or write command from the host 2 is not being executed. In other words, the data reallocation by the data reallocation control unit 111 is executed as background processing. This makes it possible to avoid a decrease in the I / O performance of the memory system 1.

[0047] Furthermore, since the data reallocation control unit 111 executes data reallocation in the physical address space as an internal process of the memory system 1, the controller 11 updates the logical-physical conversion table it manages, regardless of the management of the host 2. Therefore, there is no need to update the mapping information managed by the file system of the host 2.

[0048] Furthermore, by executing data relocation in the physical address space as an internal process of the memory system 1, fragmentation in the physical address space is reliably eliminated, unlike in cases where the host 2 is the driving force.

[0049] When the data relocation control unit 111 completes the data relocation in the physical address space, the controller 11 notifies the host 2 of the completion of the data relocation as a response to the above-mentioned extension command. Therefore, after providing the file fragment information to the memory system 1 by the extension command, the host 2 need only wait for a response from the memory system 1 without giving any consideration to the progress of the data relocation. In other words, the host 2 need only wait for a response indicating the completion of the data relocation while writing data to the memory system 1 and reading data from the memory system 1 as usual.

[0050] In this manner, in the information processing system of the first embodiment, fragmentation of file data can be efficiently eliminated.

[0051] Incidentally, the flash memory 13 is a non-volatile storage medium that does not allow data to be overwritten onto a page 151 in which data has already been written. Therefore, the controller 11 rewrites data by writing new data to a page 151 other than the page 151 in which the original data is stored, and invalidating the original data. As the number of times data is rewritten increases, the number of pages 151 in which invalid data is stored increases. Therefore, the controller 11 executes garbage collection to reuse a plurality of pages 151 in which invalid data is stored.

[0052] Garbage collection moves valid data from L (L is a natural number equal to or greater than 2) logical blocks 200 to K (K is a natural number equal to or greater than 1 and less than L) logical blocks 200 to generate free space for (LK) logical blocks 200. Of the L logical blocks 200, logical blocks 200 that contain a greater number of pages 151 to which invalidated data is written are preferred.

[0053] The data reallocation control unit 111 may use this garbage collection to execute data reallocation requested by the host 2.

[0054] FIG. 6 is a flowchart showing the procedure of the data rearrangement process executed by the memory system 1 of the first embodiment.

[0055] The controller 11 receives file fragment information from the host 2 (S101). The data relocation control unit 111 of the controller 11 secures a new block for relocating the fragmented file data so that it is physically contiguous (S102). Note that the block in FIG. 6 is a logical block 200.

[0056] The data reallocation control unit 111 identifies the source block from the file fragment information while referring to the logical-physical conversion table (S103). The source block is one or more logical blocks 200 in which the fragmented file data exists.

[0057] The data reallocation control unit 111 moves the fragmented file data from the source block identified in S103 to the new block secured in S102 (S104). When the data movement by the data reallocation control unit 111 is completed, the controller 11 notifies the host 2 of the completion of the data reallocation (S105).

[0058] As described above, the information processing system of the first embodiment can efficiently eliminate fragmentation of file data.

[0059] Second embodiment Next, a second embodiment will be described.

[0060] In the first embodiment, the operation of the memory system 1 has been mainly described with respect to data rearrangement for eliminating fragmentation of continuous data such as file data.

[0061] In the second embodiment, the operation of the host 2, including control of the timing of issuing an extension command requesting data relocation to the memory system 1, will be mainly described.

[0062] FIG. 7 is a diagram showing an example of the transition of the file defragmentation state managed by the host 2 to determine whether data relocation is necessary.

[0063] The host 2 manages the file defragmentation status so as to transition among four states: "Necessary but not executed" (S201), "Not required but executing" (S202), "Necessary but executing" (S203), and "Not required but not executed" (S204). The file defragmentation status is indicated by a combination of whether file defragmentation is required or not, and whether file defragmentation is being executed or not.

[0064] "Necessary but not yet executed" (S201) is a state in which data relocation is necessary and an extended command has not yet been issued to the memory system 1. When the file defragmentation state is "necessary but not yet executed" (S201), the host 2 issues an extended command to the memory system 1 requesting data relocation (file defragmentation) (c1). The file fragment information provided to the memory system 1 by this extended command includes mapping information related to the target file of a file update (c2) that occurred during "unnecessary but not yet executed" (S202) or a file update (c5) that occurred during "unnecessary but not yet executed" (S204), which will be described later.

[0065] When a file is updated, there is a high possibility that the file data will become fragmented. Therefore, when a file is updated, the host 2 issues an extension command to the memory system 1 requesting data relocation (c1).

[0066] When an expansion command is issued to the memory system 1, the host 2 transitions the file defragmentation state to "not required but in progress" (S202) (c1). If a file update occurs before receiving a notification of data relocation completion from the memory system 1, the host 2 transitions the file defragmentation state to "necessary but in progress" (S203) (c2). If a file update occurs during "necessary but in progress" (S203), the host 2 maintains the file defragmentation state at "necessary but in progress" (S203).

[0067] After the state transitions to "required but in progress" (S203), when the host 2 receives a notification from the memory system 1 that data relocation is complete, the host 2 transitions the file defragmentation state to "required but not in progress" (S201) (c3). Therefore, the host 2 will continuously issue the next extended command requesting data relocation to the memory system 1.

[0068] If no file update occurs during "unnecessary and in progress" (S202) and the host 2 receives a notification of data relocation completion from the memory system 1, the host 2 transitions the file defragmentation state to "unnecessary and not yet executed" (S204) (c4). If a file update occurs during "unnecessary and not yet executed" (S204), the host 2 transitions the file defragmentation state to "necessary and not yet executed" (S201) (c5). This causes the host 2 to issue the next extended command to the memory system 1 requesting data relocation.

[0069] By managing the file defragmentation state in this manner, the host 2 can issue an extended command requesting data relocation at an appropriate timing. This eliminates the need for an end user to issue a defragmentation command, and reduces the burden on the end user of having to consider the timing of when to issue a defragmentation command.

[0070] Furthermore, the host 2 may inquire of the memory system 1 about the number of fragments at the physical address corresponding to the logical address to which the data of the target file is mapped, as a pre-processing before issuing an extended command to the memory system 1 requesting data relocation in response to the occurrence of a file update. If the number of fragments notified from the memory system 1 exceeds a threshold, the host 2 may request the memory system 1 to relocate the data. In other words, if the number of fragments notified from the memory system 1 is equal to or less than the threshold, the host 2 may suspend the data relocation at that time. This inquiry about the number of fragments may also be made by, for example, an NVMe TM This is executed by issuing an extended command defined by the standard to the memory system 1.

[0071] FIG. 8 is a diagram showing a communication sequence regarding file defragmentation between the host 2 and the memory system 1 in the information processing system of the second embodiment.

[0072] When the host 2 updates a file, it inquires of the memory system 1 about the number of data fragments at the physical address corresponding to the logical address to which the target file is mapped (d1). At this time, the host 2 notifies the memory system 1 of the logical address of the target file. The memory system 1, while referring to the logical-physical conversion table, obtains the number of data fragments at the physical address of the target file from the file fragment information provided by the host 2, and responds with the obtained number of fragments to the host 2 (d2).

[0073] If the number of fragments obtained from the memory system 1 exceeds the threshold, the host 2 issues an extended command to the memory system 1 requesting data relocation (file defragmentation) to eliminate fragmentation of the data of the target file (d3). After issuing the extended command, the host 2 may write data to the memory system 1 as usual and read data from the memory system 1, regardless of the requested defragmentation.

[0074] The memory system 1 executes the requested data rearrangement as background processing during an idle period during which no processing is being performed in response to a write command or a read command from the host 2. Then, when the data rearrangement is completed, the memory system 1 notifies the host 2 of the completion of the data rearrangement in response to the received extension command (d4).

[0075] As described above, according to the information processing system of the second embodiment, the host 2 and the memory system 1 work together to efficiently eliminate fragmentation of file data.

[0076] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0077] 1...memory system, 2...host, 11...controller, 12...DRAM, 13...flash memory, 111...data relocation control unit, 131...memory die, 150...physical block, 151...page, 200...logical block, 300...mapping information.

Claims

1. A non-volatile memory; A controller capable of communicating with a host and controlling the non-volatile memory; A memory system comprising: The controller: receiving first information from the host regarding a mapping of data of a file to a logical address space of the memory system; relocating, in the physical address space, the data of the file that is fragmented in the physical address space, so that the data of the file becomes contiguous in the physical address space, based on the received first information and second information in which a correspondence relationship between a logical address indicating a position in the logical address space and a physical address indicating a position in the physical address space of the non-volatile memory is recorded; Memory system.

2. 2. The memory system of claim 1, wherein the controller performs the relocation during an idle period in which no data is being read from the non-volatile memory in response to a read command from the host or no data is being written to the non-volatile memory in response to a write command from the host.

3. The controller: executing communication with said host using a protocol conforming to a first standard; receiving the first information from the host using a first command defined as an extended command in the first standard; detect the number of fragments of data of the file in the physical address space based on the first information and the second information in response to the first command, and transmit the number of fragments to the host; 2. The memory system of claim 1.

4. The memory system of claim 3, wherein the controller performs the relocation when, after transmitting the number of fragments to the host, the controller receives from the host a second command defined as an extended command in the first standard and different from the first command.

5. the non-volatile memory has a plurality of blocks, each of which is a data erasure unit; The controller executes the relocation by garbage collection, which moves valid data in L (L is a natural number equal to or greater than 2) blocks to K (K is a natural number equal to or greater than 1 and less than L) blocks to generate a free area of ​​(L-K) blocks.

2. The memory system of claim 1.

6. updating data in a file stored in a non-volatile memory of the memory system; querying the memory system for a number of fragments of the data of the file in a physical address space of the non-volatile memory after updating the data of the file; if the number of fragments obtained from the memory system exceeds a threshold; providing first information to the memory system regarding a mapping of the data of the file to a logical address space of the memory system; instructing the memory system to relocate, in the physical address space, data of the file that is fragmented in the physical address space so that the data of the file is contiguous in the physical address space; Information processing device.

7. The host, a memory system having a non-volatile memory; Equipped with The host is updating data of a file stored in the non-volatile memory of the memory system; querying the memory system for a number of fragments of the data of the file in a physical address space of the non-volatile memory after updating the data of the file; if the number of fragments obtained from the memory system exceeds a threshold; providing first information to the memory system regarding a mapping of the data of the file to a logical address space of the memory system; instructing the memory system to relocate, in the physical address space, data of the file that is fragmented in the physical address space so that the data of the file is continuous in the physical address space; The memory system includes: when receiving the inquiry from the host, detects the number of fragments of data of the file in the physical address space based on the first information and second information in which a correspondence relationship between a logical address indicating a position in the logical address space and a physical address indicating a position in the physical address space is recorded, and transmits the number of fragments to the host; when receiving the instruction from the host after transmitting the number of fragments to the host, relocating the data of the file, which is fragmented in the physical address space, in the physical address space based on the first information and the second information so that the data of the file becomes continuous in the physical address space; Information processing system.

8. A method for rearranging data in a memory system having a non-volatile memory, comprising the steps of: receiving first information from a host regarding a mapping of data of a file to a logical address space of the memory system; relocating the data of the file in the physical address space so that the data of the file is continuous in the physical address space, based on the received first information and second information in which a correspondence relationship between a logical address indicating a position in the logical address space and a physical address indicating a position in the physical address space of the non-volatile memory is recorded; How to rearrange the data.

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