Transformer chip and signal transmission device

Abstract

To reduce a thickness of an element insulating layer while ensuring a required insulating breakdown voltage between a first coil and a second coil.SOLUTION: A transformer chip 50 includes: a first coil disposed near a back side surface in an element insulating layer 52; a second coil 22 disposed near a front side surface 52A in the element insulating layer 52 and facing the first coil in a Z direction; a first inner peripheral pad 57A and a second inner peripheral pad 58A formed on the front side surface 52A; a first inner peripheral connection unit 80A electrically connecting a first inner peripheral end of the first coil and a first inner peripheral pad 57A; and a second inner peripheral connection unit 90A electrically connecting a second inner peripheral end of the second coil 22 and the second inner peripheral pad 58A. In a plan view, the first inner peripheral pad 57A, the second inner peripheral pad 58A, the first inner peripheral connection unit 80A, and the second inner peripheral connection unit 90A are disposed in an inner region 23 surrounded by the first coil and the second coil 22.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a transformer chip and a signal transmission device. [Background technology]

[0002] As an example of a signal transmission device, an insulated gate driver that applies a gate voltage to a gate electrode of a switching element such as a transistor is known. As an example of a transformer chip used in such a gate driver, a structure including a first coil and a second coil disposed in an element insulating layer opposite each other in the thickness direction of the element insulating layer is known (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-28407 A Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, in the transformer chip configured as above, it is preferable to reduce the thickness of the element insulating layer while ensuring the necessary withstand voltage between the first coil and the second coil. [Means for solving the problem]

[0005] A transformer chip that solves the above problem includes an insulating layer formed of a laminated structure of multiple insulating films and including a front surface and a back surface facing opposite each other in a thickness direction, a first coil arranged closer to the back surface in the insulating layer, formed in a ring shape, and including a first inner circumferential end, a second coil arranged closer to the front surface in the insulating layer, formed in a ring shape, including a second inner circumferential end, and facing the first coil in the thickness direction, a first inner circumferential pad and a second inner circumferential pad formed on the front surface, a first inner circumferential connecting portion electrically connecting the first inner circumferential end of the first coil and the first inner circumferential pad, and a second inner circumferential connecting portion electrically connecting the second inner circumferential end of the second coil and the second inner circumferential pad, and when viewed from the thickness direction, the first inner circumferential pad, the second inner circumferential pad, the first inner circumferential connecting portion, and the second inner circumferential connecting portion are arranged in an inner area surrounded by the first coil and the second coil.

[0006] A signal transmission device that solves the above problem comprises the above-mentioned transformer chip, a first circuit, and a second circuit connected to the first circuit via the insulating chip, and the first circuit and the second circuit are configured to transmit signals via the transformer chip. Effect of the Invention

[0007] According to the above transformer chip and signal transmission device, the thickness of the element insulating layer can be reduced while ensuring the necessary withstand voltage between the first coil and the second coil. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram showing a schematic circuit configuration of a signal transmission device according to an embodiment. [Diagram 2] FIG. 2 is a schematic plan view illustrating the signal transmission device of FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view illustrating the signal transmission device of FIG. [Figure 4] FIG. 4 is a schematic plan view showing a transformer chip in a signal transmission device. [Diagram 5] FIG. 5 is a schematic cross-sectional view of the transformer chip taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the transformer chip taken along line F6-F6 in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the transformer chip taken along line F7-F7 in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing an enlarged view of the first inner peripheral connecting portion and its periphery in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing an enlargement of the second inner peripheral connecting portion and its periphery in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view of the transformer chip taken along line F10-F10 in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing an enlargement of the first outer periphery connecting portion and its surroundings in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view of the transformer chip taken along line F12-F12 in FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing an enlargement of the second outer periphery connecting portion and its surroundings in FIG. [Figure 14] FIG. 14 is a schematic plan view showing a transformer chip of a comparative example. [Figure 15] FIG. 15 is a schematic cross-sectional view of the transformer chip taken along line F15-F15 in FIG. [Figure 16] FIG. 16 is a schematic plan view showing a transformer chip according to a modified example. [Figure 17] FIG. 17 is a schematic plan view showing a transformer chip according to a modified example. [Figure 18] FIG. 18 is a schematic plan view showing a transformer chip according to a modified example. [Figure 19] FIG. 19 is a schematic plan view showing one transformer in a transformer chip according to a modified example. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a signal transmission device according to a modified example. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a signal transmission device according to a modified example. [Figure 22] FIG. 22 is a schematic cross-sectional view showing a signal transmission device according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, some embodiments of the insulating chip and the signal transmission device of the present disclosure will be described with reference to the accompanying drawings. Note that, for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] [Signal transmission device configuration] A schematic configuration of a signal transmission device 10 of an embodiment will be described with reference to Figs. 1 to 3. Fig. 1 shows a simplified example of a circuit configuration of the signal transmission device 10 of an embodiment. Fig. 2 shows a schematic planar structure inside the signal transmission device 10 of an embodiment. Fig. 3 shows a simplified view of a portion of the internal structure of the signal transmission device 10 of Fig. 2. Note that hatched lines have been omitted in Fig. 3 to facilitate understanding of the drawing.

[0012] As shown in FIG. 1, the signal transmission device 10 is configured to transmit a pulse signal while electrically insulating between a primary side terminal 11 and a secondary side terminal 12. The signal transmission device 10 is, for example, a digital isolator. An example of a digital isolator is a DC / DC converter. The signal transmission device 10 includes a signal transmission circuit 10A having a primary side circuit 13 electrically connected to the primary side terminal 11, a secondary side circuit 14 electrically connected to the secondary side terminal 12, and a transformer 15 that electrically insulates the primary side circuit 13 and the secondary side circuit 14. Here, in the present disclosure, the primary side circuit 13 corresponds to the "first circuit" and the secondary side circuit 14 corresponds to the "second circuit."

[0013] The primary circuit 13 is configured to operate when a first voltage V1 is applied to it. The primary circuit 13 is electrically connected to, for example, an external control device (not shown). The secondary circuit 14 is configured to operate by application of a second voltage V2 different from the first voltage V1. The first voltage V1 and the second voltage V2 are DC voltages. The secondary circuit 14 is electrically connected to, for example, a drive circuit (not shown) that is controlled by the control device. An example of the drive circuit is a switching circuit including a switching element. Examples of the switching element include SiMOSFET, SiCMOSFET, and IGBT. The secondary circuit 14 is electrically connected to the gate of the switching element. The secondary circuit 14 supplies a gate drive signal to the gate of the switching element.

[0014] In the signal transmission circuit 10A, when a control signal from the control device is input to the primary side circuit 13 via the primary side terminal 11, the signal is transmitted from the primary side circuit 13 to the secondary side circuit 14 via the transformer 15. Then, the signal transmitted to the secondary side circuit 14 is output from the secondary side circuit 14 to the drive circuit via the secondary side terminal 12.

[0015] The signal transmitted from the primary side circuit 13 to the secondary side circuit 14, i.e., the signal output from the primary side circuit 13, is, for example, a signal for driving a switching element. Examples of this signal include a set signal (SET) and a reset signal (RESET). The set signal is a signal that transmits the rising edge of a control signal from a control device, and the reset signal is a signal that transmits the falling edge of a control signal from a control device. The set signal and the reset signal can be said to be signals for generating a gate drive signal for a switching element.

[0016] More specifically, the primary side circuit 13 generates a set signal and a reset signal based on a control signal input from the control device. In one example, the primary side circuit 13 generates a set signal in response to a rising edge of the control signal, and generates a reset signal in response to a falling edge of the control signal. Then, the primary side circuit 13 transmits the generated set signal and reset signal to the secondary side circuit 14.

[0017] The secondary circuit 14 generates a gate drive signal for driving the switching element based on the set signal and reset signal received from the primary circuit 13. The secondary circuit 14 then supplies the gate drive signal to the gate of the switching element. In other words, it can be said that the secondary circuit 14 generates a gate drive signal to be supplied to the gate of the switching element based on the signal output from the primary circuit 13. More specifically, the secondary circuit 14 generates a gate drive signal for turning on the switching element based on the set signal, and then supplies the gate drive signal to the gate of the switching element. On the other hand, the secondary circuit 14 generates a gate drive signal for turning off the switching element based on the reset signal, and then supplies the gate drive signal to the gate of the switching element. In this way, the signal transmission device 10 controls the on / off of the switching element.

[0018] The secondary circuit 14 includes, for example, an RS flip-flop circuit to which a set signal and a reset signal are input, and a driver unit that generates a gate drive signal based on an output signal of the RS flip-flop circuit. However, the specific circuit configuration of the secondary circuit 14 can be changed as desired.

[0019] As described above, the primary circuit 13 and the secondary circuit 14 are electrically insulated by the transformer 15. More specifically, the transformer 15 restricts the transmission of DC voltage between the primary circuit 13 and the secondary circuit 14, while allowing the transmission of various signals such as a set signal and a reset signal.

[0020] In other words, a state in which primary side circuit 13 and secondary side circuit 14 are insulated means a state in which the transmission of DC voltage between primary side circuit 13 and secondary side circuit 14 is blocked, while the transmission of signals between primary side circuit 13 and secondary side circuit 14 is permitted.

[0021] The withstand voltage of the signal transmission device 10 is, for example, 2500 Vrms or more and 7500 Vrms or less. In one example, the withstand voltage of the signal transmission device 10 is about 5000 Vrms. However, the specific value of the withstand voltage of the signal transmission device 10 is not limited to this and can be changed arbitrarily.

[0022] 1, a ground GND1 of the primary circuit 13 and a ground GND2 of the secondary circuit 14 are provided independently. Hereinafter, the potential of the ground GND1 of the primary circuit 13 is referred to as a first reference potential, and the potential of the ground GND2 of the secondary circuit 14 is referred to as a second reference potential. In this case, the first voltage V1 is a voltage from the first reference potential, and the second voltage V2 is a voltage from the second reference potential. The first voltage V1 is, for example, 4.5V or more and 5.5V or less, and the second voltage V2 is, for example, 9V or more and 24V or less.

[0023] Next, the detailed configuration of the signal transmission device 10 will be described. The signal transmission device 10 includes two transformers 15 corresponding to the transmission of two types of signals, a set signal and a reset signal, from the primary side circuit 13 to the secondary side circuit 14. More specifically, the signal transmission device 10 includes a transformer 15 used to transmit a set signal from the primary side circuit 13 to the secondary side circuit 14, and a transformer 15 used to transmit a reset signal from the primary side circuit 13 to the secondary side circuit 14. Hereinafter, for convenience of explanation, the transformer 15 used to transmit the set signal will be referred to as "transformer 15A," and the transformer 15 used to transmit the reset signal will be referred to as "transformer 15B."

[0024] The signal transmission device 10 includes a primary signal line 16A that connects the primary circuit 13 and the transformer 15A, and a primary signal line 16B that connects the primary circuit 13 and the transformer 15B. Therefore, the primary signal line 16A transmits a set signal from the primary circuit 13 to the transformer 15A. The primary signal line 16B transmits a reset signal from the primary circuit 13 to the transformer 15B.

[0025] The signal transmission device 10 includes a secondary signal line 17A that connects the transformer 15A and the secondary circuit 14, and a secondary signal line 17B that connects the transformer 15B and the secondary circuit 14. Therefore, the secondary signal line 17A transmits a set signal from the transformer 15A to the secondary circuit 14. The secondary signal line 17B transmits a reset signal from the transformer 15B to the secondary circuit 14.

[0026] The transformer 15A is configured to electrically insulate the primary side circuit 13 from the secondary side circuit 14 while transmitting a set signal from the primary side circuit 13 to the secondary side circuit 14. The transformer 15B is configured to electrically insulate the primary side circuit 13 from the secondary side circuit 14 while transmitting a reset signal from the primary side circuit 13 to the secondary side circuit 14.

[0027] The transformers 15A and 15B include a first coil 21 and a second coil 22. The first coil 21 and the second coil 22 are electrically insulated from each other and configured to be magnetically coupled to each other.

[0028] The first coils 21 of the transformers 15A and 15B are electrically connected to the primary circuit 13. In one example, a first end of the first coil 21 of the transformer 15A is electrically connected to the primary circuit 13 by a primary signal line 16A, and a second end of the first coil 21 of the transformer 15A is electrically connected to the ground GND1 of the primary circuit 13. A first end of the first coil 21 of the transformer 15B is electrically connected to the primary circuit 13 by a primary signal line 16B, and a second end of the first coil 21 of the transformer 15B is electrically connected to the ground GND1 of the primary circuit 13. Therefore, the potential of the second end of the first coil 21 of the transformers 15A and 15B becomes a first reference potential. The first reference potential is, for example, 0V.

[0029] The second coils 22 of the transformers 15A and 15B are electrically connected to the secondary circuit 14. In one example, a first end of the second coil 22 of the transformer 15A is electrically connected to the secondary circuit 14 by the secondary signal line 17A, and a second end of the second coil 22 of the transformer 15A is electrically connected to the ground GND2 of the secondary circuit 14. A first end of the second coil 22 of the transformer 15B is electrically connected to the secondary circuit 14 by the secondary signal line 17B, and a second end of the second coil 22 of the transformer 15B is electrically connected to the ground GND2 of the secondary circuit 14. Therefore, the potential of the second end of the second coil 22 of the transformers 15A and 15B becomes the second reference potential. The ground GND2 of the secondary circuit 14 is electrically connected to, for example, the source of a switching element in a switching circuit electrically connected to the secondary circuit 14.

[0030] Depending on the usage of the switching circuit, the source of the switching element may vary with the operation of the switching circuit. In this case, the source of the switching element may be, for example, 600 V or more. Therefore, the ground GND2 of the secondary circuit 14, i.e., the second reference potential, may be 600 V or more. For this reason, the transformers 15A and 15B are required to have a withstand voltage according to the first reference potential and the second reference potential.

[0031] In this way, when the second reference potential is 600V or more, the secondary circuit 14 operates at a higher potential than the primary circuit 13, in other words, the second voltage V2 is higher than the first voltage V1, so it can be called a "high-voltage circuit". On the other hand, the primary circuit 13 operates at a lower potential than the secondary circuit 14, in other words, the first voltage V1 is lower than the second voltage V2, so it can be called a "low-voltage circuit". For this reason, the first coil 21 electrically connected to the primary circuit 13 (low-voltage circuit) of the transformers 15A and 15B can be called a "low-voltage coil". In addition, the second coil 22 electrically connected to the secondary circuit 14 (high-voltage circuit) of the transformers 15A and 15B can be called a "high-voltage coil".

[0032] Fig. 2 shows an example of a plan view illustrating the internal configuration of the signal transmission device 10. Note that, since Fig. 1 shows a simplified circuit configuration of the signal transmission device 10, the number of external terminals (primary side terminals 11 and secondary side terminals 12) of the signal transmission device 10 in Fig. 2 is greater than the number of external terminals of the signal transmission device 10 in Fig. 1. In addition, the number of signal lines (the number of wires W1 to W4 described later) that transmit signals from the primary side circuit 13 to the secondary side circuit 14 in the signal transmission device 10 in Fig. 2 is greater than the number of signal lines in the signal transmission device 10 in Fig. 1.

[0033] Fig. 3 shows an example of a cross-sectional view showing the internal configuration of signal transmission device 10. Note that Fig. 3 shows a simplified internal configuration of signal transmission device 10, and therefore the cross-sectional structures of first chip 30, second chip 40, and transformer chip 50 described below are simplified. Therefore, the cross-sectional structure of transformer chip 50 shown in Fig. 3 is different from the cross-sectional structures of transformer chip 50 in Figs. 7 to 13.

[0034] As shown in FIG. 2, the signal transmission device 10 is a semiconductor device in which a plurality of semiconductor chips are packaged together. The package format of the signal transmission device 10 is an SO (Small Outline) type, and in the example of FIG. 2, it is an SOP (Small Outline Package). The signal transmission device 10 includes a first chip 30, a second chip 40, and a transformer chip 50 as semiconductor chips. The signal transmission device 10 also includes a first lead frame 60 on which the first chip 30 is arranged, a second lead frame 70 on which the second chip 40 is arranged, and a sealing resin 130 that seals each of the chips 30, 40, 50 and a part of each of the lead frames 60, 70. The package format of the signal transmission device 10 can be changed arbitrarily. In FIG. 2, the sealing resin 130 is indicated by a two-dot chain line for convenience of explaining the internal structure of the signal transmission device 10.

[0035] The sealing resin 130 is made of a material having electrical insulation properties. In one example, the sealing resin 130 is made of a resin containing, for example, epoxy resin. The sealing resin 130 is formed in a rectangular plate shape with the Z direction as the thickness direction. The sealing resin 130 has four resin side surfaces 131 to 134. The resin side surfaces 131 and 132 constitute both end faces of the sealing resin 130 in the X direction. The resin side surfaces 133 and 134 constitute both end faces of the sealing resin 130 in the Y direction. In the following description, the signal transmission device 10 and its components viewed from the Z direction are referred to as a "planar view". The X direction and the Y direction are directions that intersect with the Z direction in a plan view and are orthogonal to each other. In one example, both the X direction and the Y direction are directions that are orthogonal to the Z direction.

[0036] Each of the first lead frame 60 and the second lead frame 70 is a conductor and is formed of a material containing, for example, Cu (copper), Fe (iron), etc. Each of the lead frames 60, 70 is provided straddling the inside and outside of the sealing resin 130.

[0037] The first lead frame 60 includes a first die pad 61 disposed within the sealing resin 130, and a plurality of first leads 62 disposed across the inside and outside of the sealing resin 130. Each of the first leads 62 constitutes a primary side terminal 11 (see FIG. 1).

[0038] 2, both the first chip 30 and the transformer chip 50 are disposed on the first die pad 61. In a plan view, the first die pad 61 is disposed such that the center in the X direction is closer to the resin side surface 131 than the center in the X direction of the sealing resin 130. In one example, the first die pad 61 is not exposed from the sealing resin 130. The first die pad 61 is formed in a rectangular flat plate shape with the thickness direction being the Z direction. The shape of the first die pad 61 in a plan view is a rectangle with the Y direction as the longitudinal direction and the X direction as the lateral direction.

[0039] The multiple first leads 62 are arranged spaced apart from each other in the Y direction. Of the multiple first leads 62, the first leads 62 arranged at both ends in the Y direction are each integrated with the first die pad 61. A portion of each first lead 62 protrudes from the resin side surface 131 toward the outside of the sealing resin 130.

[0040] The second lead frame 70 includes a second die pad 71 disposed within the sealing resin 130, and a plurality of second leads 72 disposed across the inside and outside of the sealing resin 130. Each of the second leads 72 constitutes a secondary side terminal 12 (see FIG. 1).

[0041] 2, the second chip 40 is disposed on the second die pad 71. In a plan view, the second die pad 71 is disposed closer to the resin side surface 132 than the first die pad 61 and is spaced apart from the first die pad 61 in the X direction. In this manner, the first die pad 61 and the second die pad 71 are arranged in the X direction, and therefore the X direction can be said to be the arrangement direction of the first die pad 61 and the second die pad 71.

[0042] In one example, the second die pad 71 is not exposed from the sealing resin 130. The second die pad 71 is formed in a rectangular flat plate shape with the thickness direction being the Z direction. The shape of the second die pad 71 in a plan view is a rectangle with the Y direction as the longitudinal direction and the X direction as the lateral direction. The dimensions in the X direction of the first die pad 61 and the second die pad 71 are set according to the size and number of the semiconductor chips to be arranged. Therefore, the dimension in the X direction of the first die pad 61 on which the first chip 30 and the transformer chip 50 are arranged is larger than the dimension in the X direction of the second die pad 71 on which the second chip 40 is arranged.

[0043] The multiple second leads 72 are arranged spaced apart from each other in the Y direction. In the example shown in Fig. 2, a pair of second leads 72 among the multiple second leads 72 are integrated with the second die pad 71. The pair of second leads 72 are second leads 72 adjacent in the Y direction to each of the second leads 72 arranged at both ends in the Y direction. A part of each second lead 72 protrudes outward from the resin side surface 132 of the sealing resin 130.

[0044] 2, in a plan view, the multiple first leads 62 are arranged in a direction (Y direction) perpendicular to the arrangement direction (X direction) of the first die pad 61 and the second die pad 71. The multiple second leads 72 are also arranged in a direction (Y direction) perpendicular to the arrangement direction (X direction) of the first die pad 61 and the second die pad 71. Note that the number of the first leads 62 and the number of the second leads 72 can each be changed arbitrarily.

[0045] 2, the first die pad 61 is supported by a pair of first leads 62 integrated with the first die pad 61. The second die pad 71 is supported by a pair of second leads 72 integrated with the second die pad 71. Therefore, each of the die pads 61, 71 is not provided with a suspension lead exposed from the resin side surfaces 133, 134. Therefore, the insulation distance between the first lead frame 60 and the second lead frame 70 can be made large.

[0046] The first chip 30 and the transformer chip 50 are arranged on the first die pad 61 at a distance from each other in the X direction. The second chip 40 is arranged on the opposite side of the transformer chip 50 from the first chip 30 in the X direction. In this way, the first chip 30, the second chip 40, and the transformer chip 50 are arranged at a distance from each other in the X direction. It can be said that the first chip 30, the second chip 40, and the transformer chip 50 are arranged in the same direction as the arrangement direction of the first die pad 61 and the second die pad 71. In the X direction, the first chip 30, the transformer chip 50, and the second chip 40 are arranged in this order from the first lead 62 to the second lead 72. In other words, it can be said that the transformer chip 50 is arranged between the first chip 30 and the second chip 40 in the X direction.

[0047] The first chip 30 includes the primary side circuit 13 shown in FIG. 1. The first chip 30 is formed in a rectangular plate shape with the thickness direction being in the Z direction. The shape of the first chip 30 in a plan view is a rectangle with the short side direction being in the X direction and the long side direction being in the Y direction. As shown in FIG. 3, the first chip 30 has a chip front surface 31 and a chip back surface 32 facing opposite sides to each other in the Z direction. The chip back surface 32 of the first chip 30 is bonded to the first die pad 61 by a conductive bonding material SD. For example, a solder paste or an Ag (silver) paste is used as the conductive bonding material SD.

[0048] A plurality of first electrode pads 33, a plurality of second electrode pads 34, and a plurality of third electrode pads 35 are formed on a chip surface 31 of the first chip 30. The first electrode pads 33, the second electrode pads 34, and the third electrode pads 35 are electrically connected to the primary side circuit 13.

[0049] The multiple first electrode pads 33 are arranged on the chip surface 31 closer to the first lead 62 than the center of the chip surface 31 in the X direction. The multiple first electrode pads 33 are arranged spaced apart from each other in the Y direction. The multiple second electrode pads 34 are arranged at one of both ends of the chip surface 31 in the X direction that is closer to the transformer chip 50. The multiple second electrode pads 34 are arranged spaced apart from each other in the Y direction. The multiple third electrode pads 35 are distributed and arranged at both ends of the chip surface 31 in the Y direction.

[0050] As shown in Fig. 3, the first chip 30 includes a substrate 36 on which the primary side circuit 13 is formed. The substrate 36 is, for example, a semiconductor substrate. One example of a semiconductor substrate is a substrate made of a material containing Si. A wiring layer 37 is formed on the substrate 36. The substrate 36 constitutes the chip rear surface 32, and the wiring layer 37 constitutes the chip front surface 31.

[0051] The wiring layer 37 includes, for example, a plurality of insulating films stacked in the Z direction and a metal layer embedded in the insulating films. The metal layer forms the wiring pattern of the first chip 30. The metal layer electrically connects, for example, the primary side circuit 13 and each of the electrode pads 33 to 35. That is, each of the electrode pads 33 to 35 is electrically connected to the primary side circuit 13 via the wiring layer 37. The metal layer is formed of a material including one or more appropriately selected from, for example, Ti (titanium), TiN (titanium nitride), Au (gold), Ag, Cu, Al (aluminum), and W (tungsten).

[0052] As shown in Fig. 2, the second chip 40 includes the secondary circuit 14 shown in Fig. 1. The second chip 40 is formed into a rectangular plate shape with the thickness direction being in the Z direction. The shape of the second chip 40 in a plan view is a rectangle with the short side direction being in the X direction and the long side direction being in the Y direction. As shown in Fig. 3, the second chip 40 has a chip front surface 41 and a chip back surface 42 facing opposite sides to each other in the Z direction. The chip back surface 42 of the second chip 40 is joined to the second die pad 71 by a conductive bonding material SD.

[0053] A plurality of first electrode pads 43, a plurality of second electrode pads 44, and a plurality of third electrode pads 45 are formed on a chip surface 41 of the second chip 40. The first electrode pads 43, the second electrode pads 44, and the third electrode pads 45 are electrically connected to the secondary side circuit 14.

[0054] The first electrode pads 43 are formed on one of both ends in the X direction of the chip surface 41, which is closer to the transformer chip 50. The first electrode pads 43 are arranged spaced apart from each other in the Y direction. The second electrode pads 44 are formed on one of both ends in the X direction of the chip surface 41, which is closer to the second lead 72. The second electrode pads 44 are arranged spaced apart from each other in the Y direction. The third electrode pads 45 are distributed and arranged at both ends in the Y direction of the chip surface 41.

[0055] As shown in Fig. 3, the second chip 40 includes a substrate 46 on which the secondary side circuit 14 is formed. The substrate 46 is, for example, a semiconductor substrate. One example of a semiconductor substrate is a substrate formed from a material containing Si. A wiring layer 47 is formed on the substrate 46. The substrate 46 constitutes the chip rear surface 42, and the wiring layer 47 constitutes the chip front surface 41.

[0056] The wiring layer 47 includes, for example, a plurality of insulating films stacked in the Z direction and a metal layer embedded in the insulating films. The metal layer forms the wiring pattern of the second chip 40. The metal layer electrically connects, for example, the secondary side circuit 14 and each of the electrode pads 43 to 45. That is, each of the electrode pads 43 to 45 is electrically connected to the secondary side circuit 14 via the wiring layer 47. The metal layer is formed of a material including, for example, one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0057] The transformer chip 50 is a single chip including the transformers 15A and 15B shown in FIG. 1. In other words, the transformer chip 50 is a chip dedicated to the transformers 15A and 15B, separate from the first chip 30 and the second chip 40. The transformer chip 50 has a chip front surface 50A and a chip back surface 50B facing the opposite side to the chip front surface 50A. The chip front surface 50A faces, for example, the same side as the chip front surface 31 of the first chip 30, and the chip back surface 50B faces, for example, the same side as the chip back surface 32 of the first chip 30. The chip back surface 50B of the transformer chip 50 is bonded to the first die pad 61 by a conductive bonding material SD.

[0058] As shown in Figures 2 and 3, a plurality of first electrode pads 57 are formed on the chip surface 50A of the transformer chip 50. The plurality of first electrode pads 57 are formed on one of both ends in the X direction of the chip surface 50A that is closer to the first chip 30. The plurality of first electrode pads 57 are arranged at a distance from each other in the Y direction. A plurality of second electrode pads 58 are formed on the chip surface 50A of the transformer chip 50. The plurality of second electrode pads 58 are arranged at a distance from each other in the Y direction.

[0059] In order to set the dielectric strength voltage of the signal transmission device 10 to a preset dielectric strength voltage, the first die pad 61 and the second die pad 71, which are closest to each other in the lead frames 60 and 70, must be spaced apart from each other. Therefore, the distance between the transformer chip 50 and the second chip 40 in the X direction in a plan view is greater than the distance between the transformer chip 50 and the first chip 30 in the X direction. On the other hand, since the transformer chip 50 and the first chip 30 are disposed on the first die pad 61, they may be disposed closer to each other. Therefore, it can be said that the transformer chip 50 is disposed closer to the first chip 30 than the second chip 40.

[0060] A plurality of wires W1 to W4 are connected to each of the first chip 30, the transformer chip 50, and the second chip 40. Each of the wires W1 to W4 is a bonding wire formed by a wire bonding apparatus, and is made of a conductor including, for example, Au, Al, Cu, or the like.

[0061] The first chip 30 is electrically connected to the first lead frame 60 by the wire W1. More specifically, the first electrode pads 33 and the third electrode pads 35 of the first chip 30 are individually electrically connected to the first leads 62 by the wire W1. The third electrode pads 35 are individually electrically connected to a pair of the first leads 62 that are integrated with the first die pad 61 among the first leads 62 by the wire W1. This electrically connects the primary circuit 13 to the first leads 62 (primary terminals 11). In the example of FIG. 2, the pair of first leads 62 that are integrated with the first die pad 61 constitute a ground terminal, and the primary circuit 13 and the first die pad 61 are electrically connected by the wire W1. Therefore, the first die pad 61 has the same potential as the ground GND1 of the primary circuit 13.

[0062] The second chip 40 is electrically connected to the second lead frame 70 by the wire W4. More specifically, the second electrode pads 44 and the third electrode pads 45 of the second chip 40 are electrically connected to the second leads 72 individually by the wire W4. The third electrode pads 45 are electrically connected to a pair of the second leads 72, which are integrated with the second die pad 71 among the second leads 72, individually by the wire W4. This electrically connects the secondary circuit 14 to the second leads 72 (secondary terminals 12). In the example of FIG. 2, the pair of second leads 72 integrated with the second die pad 71 constitutes a ground terminal, and the secondary circuit 14 and the second die pad 71 are electrically connected to each other by the wire W4. Therefore, the second die pad 71 has the same potential as the ground GND2 of the secondary circuit 14.

[0063] The transformer chip 50 is electrically connected to the first chip 30 by wires W2. The transformer chip 50 is also electrically connected to the second chip 40 by wires W3. More specifically, the first electrode pads 57 of the transformer chip 50 are individually electrically connected to the second electrode pads 34 of the first chip 30 by wires W2. The second electrode pads 58 of the transformer chip 50 are individually electrically connected to the first electrode pads 33 of the second chip 40 by wires W3.

[0064] The first coil 21 (see FIG. 3) of the transformers 15A and 15B is electrically connected to the ground GND1 of the primary circuit 13 via the wire W2, the first chip 30, etc. The second coil 22 (see FIG. 3) of the transformers 15A and 15B is electrically connected to the ground GND2 of the secondary circuit 14 via the wire W3, the second chip 40, etc.

[0065] [Trans chip configuration] An example of the configuration of the transformer chip 50 will be described with reference to FIGS. FIG. 4 shows a schematic diagram of an example of a planar structure of the transformer chip 50. FIG. 5 shows a cross-sectional structure of the transformer chip 50 cut along the line F5-F5 in FIG. 3, and mainly shows the first coil 21 of the transformers 15A and 15B. FIG. 6 shows a cross-sectional structure of the transformer chip 50 cut along the line F6-F6 in FIG. 3, and mainly shows the second coil 22 of the transformers 15A and 15B. FIG. 7 shows a cross-sectional structure of the transformer chip 50 cut along the line F7-F7 in FIG. 4, and mainly shows the cross-sectional structures of the first coil 21 and the second coil 22. FIG. 8 shows a cross-sectional structure of the first electrode pad 57 and its periphery in FIG. 7 in an enlarged manner. FIG. 9 shows a cross-sectional structure of the second electrode pad 58 and its periphery in FIG. 7 in an enlarged manner. FIG. 10 shows a cross-sectional structure of the transformer chip 50 cut along the line F10-F10 in FIG. 4, and mainly shows the connection structure between the first coil 21 and the first electrode pad 57. Fig. 11 shows a cross-sectional structure in which the center part in the Y direction of Fig. 10 is enlarged. Fig. 12 shows a cross-sectional structure of the transformer chip 50 cut along the line F12-F12 of Fig. 4, and mainly shows the connection structure between the second coil 22 and the second electrode pad 58. Fig. 13 shows a cross-sectional structure in which the center part in the Y direction of Fig. 12 is enlarged. In order to make the drawing easier to understand, a resin layer 56 described later is omitted in Fig. 4.

[0066] 3, the transformer chip 50 includes a substrate 51 and an element insulating layer 52 formed on the substrate 51. The element insulating layer 52 is an example of an "insulating layer". The substrate 51 is, for example, a semiconductor substrate. The substrate 51 is, for example, a substrate formed of a material containing Si (silicon). Examples of the Si substrate used for the substrate 51 include a semiconductor substrate made of a single crystal intrinsic semiconductor material, a p-type semiconductor substrate containing an acceptor-type impurity, and an n-type semiconductor substrate containing a donor-type impurity.

[0067] The substrate 51 may be a semiconductor substrate using a wide bandgap semiconductor or a compound semiconductor. Alternatively, the substrate 51 may be an insulating substrate made of a material containing glass, instead of a semiconductor substrate. The wide bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or more. The wide bandgap semiconductor may be SiC (silicon carbide), GaN (gallium nitride), Ga2O3 (gallium oxide), or the like. The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN, and GaAs (gallium arsenide).

[0068] The substrate 51 is formed in a rectangular plate shape with the thickness direction being the Z direction. In one example, the substrate 51 is rectangular with the short side direction being the X direction and the long side direction being the Y direction in a plan view. The substrate 51 includes a substrate front surface 51A and a substrate back surface 51B facing opposite sides in the Z direction. The substrate back surface 51B constitutes the chip back surface 50B of the transformer chip 50. The substrate front surface 51A is the surface in contact with the element insulating layer 52.

[0069] The element insulating layer 52 formed on the substrate surface 51A includes a front surface 52A and a back surface 52B facing opposite directions in the Z direction. The back surface 52B is in contact with the substrate surface 51A. The element insulating layer 52 is supported by the substrate 51. Here, the Z direction is an example of the "thickness direction of the element insulating layer." Therefore, a plan view can be rephrased as "viewed from the thickness direction of the element insulating layer."

[0070] As shown in FIG. 4, the element insulating layer 52 includes element side surfaces 52C to 52F. The element side surfaces 52C to 52F are provided between the front surface 52A and the back surface 52B (see FIG. 3) of the element insulating layer 52 in the Z direction, and connect the front surface 52A and the back surface 52B. The element side surface 52C and the element side surface 52D constitute both end surfaces of the element insulating layer 52 in the X direction. The element side surface 52E and the element side surface 52F constitute both end surfaces of the element insulating layer 52 in the Y direction. The element side surface 52C constitutes the element side surface closer to the first chip 30 (see FIG. 3) with respect to the element insulating layer 52. The element side surface 52D constitutes the element side surface closer to the second chip 40 (see FIG. 3) with respect to the element insulating layer 52. The element side surface 52E constitutes the element side surface closer to the resin side surface 133 (see FIG. 2) of the sealing resin 130. The element side surface 52F constitutes the element side surface closer to the resin side surface 134 of the sealing resin 130 (see FIG. 2).

[0071] As shown in Fig. 7, the element insulating layer 52 is configured with a laminated structure of a plurality of insulating films. More specifically, as shown in Fig. 8, the element insulating layer 52 includes a plurality of first insulating films 52P and a plurality of second insulating films 52Q. The plurality of first insulating films 52P and the plurality of second insulating films 52Q are laminated alternately one by one in the Z direction.

[0072] The first insulating film 52P is an etching stopper film, and is formed of a material including at least one of, for example, SiN (silicon nitride), SiC, and SiCN (nitrogen-doped silicon carbide). The first insulating film 52P may have a function of preventing the diffusion of, for example, Cu. That is, the first insulating film 52P may be a diffusion prevention film for Cu.

[0073] The second insulating film 52Q is an interlayer insulating film, and is, for example, an oxide film formed of a material containing SiO2 (silicon oxide). The second insulating film 52Q has a thickness greater than that of the first insulating film 52P. The first insulating film 52P has a thickness of, for example, 50 nm or more and less than 1000 nm. The second insulating film 52Q has a thickness of, for example, 500 nm or more and 5000 nm or less. In this embodiment, the first insulating film 52P has a thickness of about 300 nm, and the second insulating film 52Q has a thickness of about 2000 nm. In order to easily understand the drawings, the ratio of the thickness of the first insulating film 52P to the thickness of the second insulating film 52Q in the drawings is different from the actual ratio of the thickness of the first insulating film 52P to the thickness of the second insulating film 52Q.

[0074] The uppermost insulating film of the multiple insulating films in the element insulating layer 52 is formed, for example, by a first insulating film 52P. The lowermost insulating film of the multiple insulating films in the element insulating layer 52 is formed, for example, by a second insulating film 52Q. Therefore, the front surface 52A of the element insulating layer 52 is formed by the first insulating film 52P, and the back surface 52B of the element insulating layer 52 is formed by the second insulating film 52Q.

[0075] As shown in FIGS. 4 to 6, each of the first coil 21 and the second coil 22 of the transformers 15A and 15B is provided on the element insulating layer 52. Each of the first coil 21 and the second coil 22 is made of a material containing one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the first coil 21 may be made of a material containing Cu. In one example, the second coil 22 may be made of a material containing Cu. In other words, the first coil 21 and the second coil 22 may be made of the same material.

[0076] 3, the first coils 21 of the transformers 15A and 15B are disposed closer to the rear surface 52B in the element insulating layer 52. In the example shown in Fig. 5, the first coils 21 of the transformers 15A and 15B are formed on the lowest insulating film among the insulating films of the element insulating layer 52 so as to be in contact with the insulating film.

[0077] The second coils 22 of the transformers 15A and 15B are disposed closer to the surface 52A in the element insulating layer 52. In the example shown in Fig. 6, the second coils 22 of the transformers 15A and 15B are formed directly below the uppermost insulating film among the multiple insulating films of the element insulating layer 52 so as to be in contact with the insulating film. In other words, the second coils 22 are covered by the uppermost insulating film. The second coils 22 of the transformers 15A and 15B face the first coils 21 of the transformers 15A and 15B in the Z direction.

[0078] As shown in Fig. 5, in a plan view, the first coil 21 of the transformer 15A and the first coil 21 of the transformer 15B are arranged at the same position in the X direction and spaced apart from each other in the Y direction. As shown in Fig. 4 and Fig. 6, in a plan view, the second coil 22 of the transformer 15A and the second coil 22 of the transformer 15B are arranged at the same position in the X direction and spaced apart from each other in the Y direction. The first coil 21 of the transformer 15A and the first coil 21 of the transformer 15B, which are arranged to face the second coils 22 of the transformers 15A and 15B in the Z direction, are arranged at the same position as the second coil 22 of the transformer 15A and the second coil 22 of the transformer 15B in a plan view.

[0079] As shown in Figures 5 and 6, the configuration and arrangement of the first coil 21 and the second coil 22 of transformer 15B are the same as those of the first coil 21 and the second coil 22 of transformer 15A, so in the following, the first coil 21 and the second coil 22 of transformer 15A will be described in detail, and a detailed description of the first coil 21 and the second coil 22 of transformer 15B will be omitted.

[0080] As shown in FIG. 5, the first coil 21 of the transformer 15A is formed in an annular shape. In one example, the first coil 21 is formed in a spiral shape by concentrically winding a conductor in a plan view. The first coil 21 includes a first inner peripheral end 21A constituting an end on the inner peripheral side of the first coil 21, and a first outer peripheral end 21B constituting an end on the outer peripheral side of the first coil 21. The first inner peripheral end 21A is an end on the inner peripheral side of both ends in the length direction of the conductor wound to form the first coil 21. The first outer peripheral end 21B is an end on the outer peripheral side of both ends in the length direction of the conductor wound to form the first coil 21. Here, both ends in the length direction of the conductor are the winding start end and the winding end end of the conductor wound to form the first coil 21.

[0081] In one example, the first coil 21 is formed in a ring shape having a long side direction and a short side direction in a plan view. In the example shown in Fig. 5, the first coil 21 is formed in a ring shape (spiral shape) with the X direction being the long side direction and the Y direction being the short side direction in a plan view. In the example shown in Fig. 5, the first coil 21 is in a track shape in a plan view.

[0082] In one example, the X-direction dimension LX1 of the first coil 21 may be two or more times the Y-direction dimension LY1 of the first coil 21. The X-direction dimension LX1 of the first coil 21 may be, for example, larger than 1 / 2 the X-direction dimension LX3 of the element insulating layer 52. The X-direction dimension LX1 of the first coil 21 may be, for example, smaller than 3 / 4 the X-direction dimension LX3 of the element insulating layer 52. In the example shown in FIG. 5, the X-direction dimension LX1 of the first coil 21 is, for example, approximately 2 / 3 the X-direction dimension LX3 of the element insulating layer 52.

[0083] The first coil 21 includes a pair of straight portions 21C, 21D extending along the X direction, and a pair of curved portions 21E, 21F connecting the pair of straight portions 21C, 21D. The pair of straight portions 21C, 21D are arranged apart in the Y direction while being aligned with each other in the X direction. The straight portion 21C is disposed closer to the element side surface 52E than the straight portion 21D. Each of the curved portions 21E, 21F is formed, for example, in a semicircular ring shape in a plan view. The curved portion 21E is connected to the end portion closer to the element side surface 52C among both ends in the X direction of the pair of straight portions 21C, 21D. The curved portion 21F is connected to the end portion closer to the element side surface 52D among both ends in the X direction of the pair of straight portions 21C, 21D.

[0084] As shown in FIG. 6, the second coil 22 of the transformer 15A is formed in an annular shape. In one example, the second coil 22 is formed in a spiral shape by concentrically winding a conductor wire in a plan view. The second coil 22 includes a second inner peripheral end 22A constituting an end on the inner peripheral side of the second coil 22, and a second outer peripheral end 22B constituting an end on the outer peripheral side of the second coil 22. The second inner peripheral end 22A is an end on the inner peripheral side of both ends in the length direction of the conductor wire wound to form the second coil 22. The second outer peripheral end 22B is an end on the outer peripheral side of both ends in the length direction of the conductor wire wound to form the second coil 22. Here, both ends in the length direction of the conductor wire are the winding start end and the winding end end of the conductor wire wound to form the second coil 22.

[0085] In one example, the second coil 22 is formed in a ring shape having a long side direction and a short side direction in a plan view. In the example shown in Fig. 6, the second coil 22 is formed in a ring shape (spiral shape) with the X direction being the long side direction and the Y direction being the short side direction in a plan view. In the example shown in Fig. 6, the second coil 22 is in a track shape in a plan view.

[0086] In one example, the dimension LX2 in the X direction of the second coil 22 is more than twice the dimension LY2 in the Y direction of the second coil 22. The dimension LX2 in the X direction of the second coil 22 is, for example, larger than 1 / 2 of the dimension LX3 in the X direction of the element insulating layer 52. The dimension LX2 in the X direction of the second coil 22 is, for example, larger than 2 / 3 of the dimension LX3 in the X direction of the element insulating layer 52. The dimension LX2 in the X direction of the second coil 22 is, for example, smaller than 4 / 5 of the dimension LX3 in the X direction of the element insulating layer 52. In one example, the dimension LX2 in the X direction of the second coil 22 is, for example, about 3 / 4 of the dimension LX3 in the X direction of the element insulating layer 52.

[0087] In one example, the number of turns of the conductor of the second coil 22 is greater than, for example, the number of turns of the conductor of the first coil 21. Therefore, the dimension LX2 in the X direction of the second coil 22 is greater than the dimension LX1 in the X direction of the first coil 21. The dimension LY2 in the Y direction of the second coil 22 is greater than the dimension LY1 in the Y direction of the first coil 21. The size of the second coil 22 in a plan view can be changed arbitrarily. In one example, the size of the second coil 22 in a plan view may be the same as that of the first coil 21. In other words, the number of turns of the conductor of the second coil 22 may be the same as the number of turns of the conductor of the first coil 21.

[0088] The second coil 22 includes a pair of straight portions 22C, 22D extending in the X direction, and a pair of curved portions 22E, 22F connecting the pair of straight portions 22C, 22D. The pair of straight portions 22C, 22D are arranged apart in the Y direction while being aligned with each other in the X direction. The straight portion 22C is disposed closer to the element side surface 52E than the straight portion 22D. Each of the curved portions 22E, 22F is formed, for example, in a semicircular ring shape in a plan view. The curved portion 22E is connected to the end portion closer to the element side surface 52C among both ends in the X direction of the pair of straight portions 22C, 22D. The curved portion 22F is connected to the end portion closer to the element side surface 52D among both ends in the X direction of the pair of straight portions 22C, 22D.

[0089] As shown in FIG. 4, the element insulating layer 52 includes an inner region 23 that is a region surrounded by the first coil 21 and the second coil 22 in a plan view. The inner region 23 is formed in an elliptical shape having a longitudinal direction and a lateral direction in a plan view. In the example of FIG. 4, the inner region 23 is formed in an elliptical shape with the X direction as the longitudinal direction and the Y direction as the lateral direction. That is, the longitudinal direction of the inner region 23 coincides with the longitudinal direction of the second coil 22 (first coil 21), and the lateral direction of the inner region 23 coincides with the lateral direction of the second coil 22 (first coil 21). The inner region 23 includes a first end 23A and a second end 23B. The first end 23A is an end closer to the curved portion 22E (curved portion 21E) among both ends of the inner region 23 in the X direction (longitudinal direction). The second end 23B is an end closer to the curved portion 22F (curved portion 21F) among both ends of the inner region 23 in the X direction. That is, the second end 23B is an end of the inner region 23 opposite to the first end 23A in the longitudinal direction (X direction) of the second coil 22 (first coil 21).

[0090] 4, the multiple first electrode pads 57 include first inner peripheral pads 57A, 57B formed in the inner region 23 of the transformers 15A, 15B in a plan view, and a first outer peripheral pad 57C formed outward from the first coil 21 and the second coil 22. The first inner peripheral pads 57A, 57B and the first outer peripheral pad 57C are formed on the surface 52A of the element insulating layer 52.

[0091] The first inner peripheral pad 57A is formed in the inner region 23 of the transformer 15A. The first inner peripheral pad 57B is formed in the inner region 23 of the transformer 15B. The first outer peripheral pad 57C is disposed between the first coil 21 (second coil 22) of the transformer 15A and the first coil 21 (second coil 22) of the transformer 15B in the Y direction in a plan view.

[0092] The second electrode pads 58 include second inner peripheral pads 58A, 58B formed in the inner region 23 of the transformers 15A, 15B in a plan view, and a second outer peripheral pad 58C formed outward of the first coil 21 and the second coil 22. The second inner peripheral pads 58A, 58B and the second outer peripheral pad 58C are formed on the surface 52A of the element insulating layer 52.

[0093] The second inner peripheral pad 58A is formed in the inner region 23 of the transformer 15A. The second inner peripheral pad 58B is formed in the inner region 23 of the transformer 15B. The second outer peripheral pad 58C is disposed between the first coil 21 (second coil 22) of the transformer 15A and the first coil 21 (second coil 22) of the transformer 15B in the Y direction in a plan view.

[0094] Thus, in a plan view, the first inner circumferential pad 57A and the second inner circumferential pad 58A are arranged in the inner region 23 of the transformer 15A. In the example of Fig. 4, the first inner circumferential pad 57A and the second inner circumferential pad 58A are arranged at the same position in the Y direction and spaced apart from each other in the X direction. In other words, the first inner circumferential pad 57A and the second inner circumferential pad 58A are arranged at a distance from each other in the longitudinal direction of the second coil 22 (first coil 21) in a plan view.

[0095] The first inner periphery pad 57A is disposed closer to the first end 23A than the center in the X direction of the inner region 23. In one example, the first inner periphery pad 57A is disposed closer to the curved portion 22E than the pair of straight portions 22C, 22D of the second coil 22. In the example of FIG. 4, the first inner periphery pad 57A is disposed at the first end 23A of the inner region 23.

[0096] The second inner pad 58A is disposed closer to the second end 23B than the center in the X direction of the inner region 23. In one example, the second inner pad 58A is disposed closer to the curved portion 22F than the pair of straight portions 22C, 22D of the second coil 22. In the example of FIG. 4, the second inner pad 58A is disposed at the second end 23B of the inner region 23. Therefore, the distance DP between the first inner pad 57A and the second inner pad 58A in the X direction is 1 / 3 or more of the dimension LX2 in the X direction of the second coil 22. In another example, the distance DP is smaller than 1 / 2 of the dimension LX2.

[0097] The arrangement of the first inner circumferential pad 57B and the second inner circumferential pad 58B is similar to the arrangement of the first inner circumferential pad 57A and the second inner circumferential pad 58A, and therefore a detailed description thereof will be omitted.

[0098] The first outer peripheral pad 57C and the second outer peripheral pad 58C are arranged at the same position in the Y direction and spaced apart from each other in the X direction. In one example, the first outer peripheral pad 57C is formed at the same position in the X direction as the first inner peripheral pads 57A and 57B in a plan view. In one example, the second outer peripheral pad 58C is arranged at the same position in the X direction as the second inner peripheral pads 58A and 58B in a plan view. Therefore, in this embodiment, the distance DQ between the first outer peripheral pad 57C and the second outer peripheral pad 58C in the X direction is equal to the distance DP between the first inner peripheral pad 57A and the second inner peripheral pad 58A in the X direction. Here, if the difference between the distance DQ and the distance DP is, for example, within 10% of the distance DQ, it can be said that the distance DQ is equal to the distance DP. Note that the distance DQ and the distance DP can each be changed arbitrarily. In one example, the distance DQ may be greater than the distance DP.

[0099] 8, the transformer chip 50 includes a front-side insulating layer 53 formed on an element insulating layer 52. The front-side insulating layer 53 includes a protective layer 54 and a passivation layer 55. The protective layer 54 is a film that protects the element insulating layer 52. The protective layer 54 is formed on the element insulating layer 52. In one example, the protective layer 54 is formed to be slightly smaller than the element insulating layer 52 in a plan view. The protective layer 54 is in contact with the surface 52A of the element insulating layer 52. The protective layer 54 is formed of a material containing, for example, SiO2. The protective layer 54 is formed of, for example, a laminated structure of a plurality of protective films. In the example shown in FIG. 9, the protective layer 54 includes a first protective film 54A formed on the surface 52A of the element insulating layer 52 and a second protective film 54B laminated on the first protective film 54A. Each of the first inner peripheral pads 57A and 57B, the second inner peripheral pads 58A and 58B, the first outer peripheral pad 57C, and the second outer peripheral pad 58C shown in FIG. 4 is formed on the first protective film 54A.

[0100] The passivation layer 55 is a surface protective film of the transformer chip 50. The passivation layer 55 is formed on the protective layer 54. In one example, the passivation layer 55 is formed over the entire surface of the protective layer 54 in a plan view. The passivation layer 55 is in contact with the surface of the protective layer 54. The passivation layer 55 is formed of a material including at least one of, for example, SiN and SiO2. In one example, the passivation layer 55 is formed of a material including SiN.

[0101] 7, 10, and 12, the front-side insulating layer 53 includes a plurality of first openings 53A, a plurality of second openings 53B, and a plurality of third openings 53C. In this embodiment, two of each of the first to third openings 53A to 53C are formed according to the numbers of the first inner peripheral pads 57A, 57B, the second inner peripheral pads 58A, 58B, the first outer peripheral pads 57C, and the second outer peripheral pads 58C. The first to third openings 53A to 53C are through holes that penetrate both the passivation layer 55 and the second protective film 54B of the protective layer 54 in the thickness direction.

[0102] One of the two first openings 53A is formed so as to expose the first inner peripheral pad 57A corresponding to the transformer 15A. Although not shown, the other of the two first openings 53A is formed so as to expose the first inner peripheral pad 57B corresponding to the transformer 15B.

[0103] One of the two second openings 53B is formed so as to expose the second inner peripheral pad 58A corresponding to the transformer 15A. Although not shown, the other of the two second openings 53B is formed so as to expose the second inner peripheral pad 58B corresponding to the transformer 15B.

[0104] One of the two third openings 53C is formed to expose the first outer peripheral pad 57C. Although not shown, the other of the two third openings 53C is formed to expose the second outer peripheral pad 58C.

[0105] The transformer chip 50 includes a resin layer 56 formed on a passivation layer 55. The resin layer 56 is partially formed on the upper surface of the passivation layer 55. In one example, the resin layer 56 is formed at a position overlapping the second coil 22 in a plan view. Therefore, the resin layer 56 is formed so as to expose most of the inner region 23 in a plan view. More specifically, the resin layer 56 is formed so as to overlap the outer periphery of the inner region 23 in a plan view, while being exposed inward from the outer periphery of the inner region 23. The resin layer 56 is formed of a material including, for example, polyimide (PI).

[0106] As shown in FIG. 4, the transformer chip 50 includes first inner circumferential connecting portions 80A and 80B and second inner circumferential connecting portions 90A and 90B. 7 and 8, the first inner peripheral connection portion 80A electrically connects the first inner peripheral end portion 21A of the first coil 21 of the transformer 15A to the first inner peripheral pad 57A. The first inner peripheral connection portion 80A is provided in the inner region 23 of the transformer 15A in a plan view. The first inner peripheral connection portion 80A is provided in the element insulating layer 52 and the front-side insulating layer 53. That is, the first coil 21 of the transformer 15A and the first inner peripheral pad 57A are electrically connected to each other in the transformer chip 50.

[0107] As shown in FIG. 8, first inner periphery connecting portion 80A includes first inner periphery wiring layer 81 and first inner periphery connecting layer . The first inner circumferential wiring layer 81 is connected to the first inner circumferential end 21A of the first coil 21. The first inner circumferential wiring layer 81 extends in the X direction from the first inner circumferential end 21A. The first inner circumferential wiring layer 81 is formed in the same position as the first coil 21 in the Z direction. In one example, the first inner circumferential wiring layer 81 is formed in the same position as the first coil 21 in the Z direction. The first inner circumferential wiring layer 81 extends to a position overlapping the first inner circumferential pad 57A in a plan view. The first inner circumferential wiring layer 81 is formed in a band shape in which the X direction is the length direction and the Y direction is the width direction in a plan view. Therefore, the length of the first inner circumferential wiring layer 81 in the X direction is longer than the length of the first inner circumferential wiring layer 81 in the Y direction. The first inner circumferential wiring layer 81 is made of a material including one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the first inner circumferential wiring layer 81 may be formed of the same material as the first coil 21.

[0108] The first inner periphery connecting layer 82 electrically connects the first inner periphery wiring layer 81 and the first inner periphery pad 57A. The first inner periphery connecting layer 82 extends in the Z direction. The first inner periphery connecting layer 82 is disposed at a position overlapping both the first inner periphery pad 57A and the first inner periphery wiring layer 81 in a plan view. The first inner periphery connecting layer 82 includes a first via 83, an intermediate wiring layer 84, and a second via 85. The intermediate wiring layer 84 is an example of a "first intermediate wiring layer", the first via 83 is an example of a "first inner periphery via", and the second via 85 is an example of a "second inner periphery via".

[0109] The intermediate wiring layer 84 is formed at the same position as the second coil 22 in the Z direction. The intermediate wiring layer 84 is formed in a rectangular shape that is slightly smaller than the first inner peripheral pad 57A in a plan view. The intermediate wiring layer 84 faces both the first inner peripheral wiring layer 81 and the first inner peripheral pad 57A in the Z direction. The shortest distance DM1 between the first inner peripheral connection portion 80A and the second coil 22 is equal to or greater than the distance DC between the first coil 21 and the second coil 22 in the Z direction. In one example, the shortest distance DM1 may be greater than the distance DC. Here, the shortest distance DM1 is the shortest distance between the intermediate wiring layer 84 and the second coil 22.

[0110] The first via 83 connects the first inner periphery wiring layer 81 and the intermediate wiring layer 84 in the Z direction. The first via 83 penetrates the element insulating layer 52 in the Z direction between the first inner periphery wiring layer 81 and the intermediate wiring layer 84. A plurality of first vias 83 are provided spaced apart from each other in the X and Y directions.

[0111] The second via 85 connects the intermediate wiring layer 84 and the first inner peripheral pad 57A in the Z direction. The second via 85 penetrates the insulating layer interposed between the intermediate wiring layer 84 and the first inner peripheral pad 57A in the Z direction in the Z direction. Specifically, the second via 85 penetrates the uppermost insulating film of the element insulating layer 52 and the first protective film 54A of the protective layer 54 in the Z direction. A plurality of the second vias 85 are provided at a distance from each other in the X direction and the Y direction. The dimensions of each of the second vias 85 in the X direction and the Y direction in a plan view are smaller than the dimensions of each of the first vias 83 in the X direction and the Y direction, respectively. The number of the second vias 85 is greater than the number of the first vias 83. The size and the number of each of the first vias 83 and the second vias 85 can be changed arbitrarily.

[0112] The first via 83, the intermediate wiring layer 84, and the second via 85 are made of a material containing one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the first via 83 may be formed of the same material as the first coil 21. In one example, the intermediate wiring layer 84 may be formed of the same material as the first coil 21. In one example, the second via 85 may be formed of a material different from the first coil 21. The second via 85 may be formed of a material containing, for example, W.

[0113] As shown in FIG. 10, the first inner periphery connection portion 80B electrically connects the first coil 21 of the transformer 15B to the first inner periphery pad 57B. The first inner periphery connection portion 80B is provided in the inner region 23 of the transformer 15B in a plan view. The first inner periphery connection portion 80B is provided in the element insulating layer 52 and the front side insulating layer 53. That is, the first coil 21 of the transformer 15B and the first inner periphery pad 57B are electrically connected in the transformer chip 50. The configuration of the first inner periphery connection portion 80B is the same as the configuration of the first inner periphery connection portion 80A. For this reason, the same reference numerals as the respective components of the first inner periphery connection portion 80B are used, and detailed description thereof will be omitted.

[0114] The second inner peripheral connection portion 90A electrically connects the second inner peripheral end portion 22A of the second coil 22 of the transformer 15A to the second inner peripheral pad 58A. The second inner peripheral connection portion 90A is disposed in the inner region 23 of the transformer 15A in a plan view. As shown in FIG. 4, the second inner peripheral connection portion 90A is disposed closer to the curved portion 22F than the first inner peripheral connection portion 80A in a plan view and spaced apart from the first inner peripheral connection portion 80A in the X direction. The second inner peripheral connection portion 90A is disposed in the element insulating layer 52 and the front side insulating layer 53. That is, the second coil 22 of the transformer 15A and the second inner peripheral pad 58A are electrically connected in the transformer chip 50.

[0115] The second inner periphery connecting portion 90A includes a second inner periphery wiring layer 91 and a second inner periphery connecting layer 92. The second inner periphery wiring layer 91 is connected to the second inner periphery end 22A of the second coil 22. The second inner periphery wiring layer 91 extends in the X direction from the second inner periphery end 22A. As shown in FIG. 9, the second inner periphery wiring layer 91 is formed at the same position as the second coil 22 in the Z direction. That is, the second inner periphery wiring layer 91 is formed at the same position as the intermediate wiring layer 84 in the Z direction. The second inner periphery wiring layer 91 extends to a position overlapping the second inner periphery pad 58A in a plan view. That is, the second inner periphery wiring layer 91 includes a portion facing the second inner periphery pad 58A in the Z direction. Although not shown, the Y direction dimension of the overlapping portion, which is the portion of the second inner periphery wiring layer 91 that overlaps the second inner periphery pad 58A in a plan view, is larger than the Y direction dimension of the portion of the second inner periphery wiring layer 91 other than the overlapping portion. That is, the overlapping portion ensures a space in which the second inner periphery connecting layer 92 is formed in a plan view.

[0116] The second inner periphery connecting layer 92 electrically connects the second inner periphery wiring layer 91 and the second inner periphery pad 58A. The second inner periphery connecting layer 92 is formed at a position overlapping both the second inner periphery wiring layer 91 and the second inner periphery pad 58A in a plan view. The second inner periphery connecting layer 92 penetrates the uppermost insulating film of the element insulating layer 52 and the first protective film 54A of the protective layer 54 in the Z direction. In one example, the second inner periphery connecting layer 92 is a via extending in the Z direction. The second inner periphery connecting layer 92 is provided in a plurality of layers spaced apart from each other in the X direction and the Y direction. In one example, the number of the second inner periphery connecting layers 92 is the same as the number of the second vias 85. The number of the second inner periphery connecting layers 92 can be changed arbitrarily.

[0117] The second inner periphery wiring layer 91 and the second inner periphery connecting layer 92 are made of a material containing one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the second inner periphery wiring layer 91 may be made of the same material as the second coil 22. In one example, the second inner periphery connecting layer 92 may be made of a material different from that of the second coil 22. The second inner periphery connecting layer 92 may be made of a material containing W, for example.

[0118] The second inner circumference connection portion 90B electrically connects the second coil 22 of the transformer 15B to the second inner circumference pad 58B. The second inner circumference connection portion 90B is provided in the inner region 23 of the transformer 15B in a plan view. The second inner circumference connection portion 90B is provided in the X direction away from the first inner circumference connection portion 80B, closer to the curved portion 22F than the first inner circumference connection portion 80B in a plan view. The second inner circumference connection portion 90B is provided in the element insulating layer 52 and the front side insulating layer 53. That is, the second coil 22 of the transformer 15B and the second inner circumference pad 58B are electrically connected in the transformer chip 50. The configuration of the second inner circumference connection portion 90B is the same as the configuration of the second inner circumference connection portion 90A. For this reason, the same reference numerals as the respective components of the second inner circumference connection portion 90B are used, and detailed description thereof will be omitted.

[0119] As shown in FIGS. 10 and 12, the transformer chip 50 includes a first outer periphery connecting portion 100 and a second outer periphery connecting portion 110. As shown in FIG. 10, the first outer peripheral connection portion 100 electrically connects each of the first coils 21 of the transformers 15A and 15B to the first outer peripheral pad 57C. The first outer peripheral connection portion 100 is provided outward from the first coil 21 and the second coil 22 in a plan view.

[0120] As shown in FIG. 11, the first peripheral connecting section 100 includes a first peripheral wiring layer 101 and a first peripheral connecting layer 102. The first outer peripheral wiring layer 101 is formed at the same position as the first coil 21 in the Z direction. The first outer peripheral wiring layer 101 connects the first outer peripheral end 21B of the first coil 21 of the transformer 15A and the first outer peripheral end 21B of the first coil 21 of the transformer 15B. The first outer peripheral wiring layer 101 extends in the Y direction. The first outer peripheral wiring layer 101 includes a portion facing the first outer peripheral pad 57C in the Z direction.

[0121] The first peripheral connecting layer 102 electrically connects the first peripheral wiring layer 101 and the first peripheral pad 57C. The first peripheral connecting layer 102 is formed at a position overlapping both the first peripheral pad 57C and the first peripheral wiring layer 101 in a plan view. The first peripheral connecting layer 102 includes a first via 103, an intermediate wiring layer 104, and a second via 105. Here, the intermediate wiring layer 104 is an example of a "second intermediate wiring layer", the first via 103 is an example of a "first peripheral via", and the second via 105 is an example of a "second peripheral via".

[0122] The intermediate wiring layer 104 is formed at the same position as the second coil 22 in the Z direction. The intermediate wiring layer 104 is formed in a rectangular shape that is slightly smaller than the first outer peripheral pad 57C in a plan view. The intermediate wiring layer 104 faces both the first outer peripheral wiring layer 101 and the first outer peripheral pad 57C in the Z direction. The shortest distance DM2 between the intermediate wiring layer 104 and the second coil 22 is equal to or greater than the distance DC between the first coil 21 and the second coil 22 in the Z direction. In one example, the shortest distance DM2 may be greater than the distance DC.

[0123] The first via 103 connects the first peripheral wiring layer 101 and the intermediate wiring layer 104 in the Z direction. The first via 103 penetrates in the Z direction through the element insulating layer 52 between the first peripheral wiring layer 101 and the intermediate wiring layer 104 in the Z direction. A plurality of first vias 103 are provided spaced apart from each other in the X and Y directions.

[0124] The second via 105 connects the intermediate wiring layer 104 and the first peripheral pad 57C in the Z direction. The second via 105 penetrates in the Z direction an insulating layer interposed between the intermediate wiring layer 104 and the first peripheral pad 57C in the Z direction. Specifically, the second via 105 penetrates in the Z direction an insulating film of the uppermost layer of the element insulating layer 52 and a first protective film 54A of the protective layer 54. A plurality of the second vias 105 are provided at a distance from each other in the X direction and the Y direction. The dimensions of each of the second vias 105 in the X direction and the Y direction in a plan view are smaller than the dimensions of each of the first vias 103 in the X direction and the Y direction, respectively. The number of the second vias 105 is greater than the number of the first vias 103. The size and the number of each of the first vias 103 and the second vias 105 can be changed arbitrarily.

[0125] The element insulating layer 52 is provided with vias 106 that electrically connect the first peripheral connection parts 100 and the substrate 51. The vias 106 are disposed at positions overlapping with the first peripheral pads 57C in a plan view. The vias 106 connect the substrate 51 and the first peripheral wiring layer 101.

[0126] The first via 103, the intermediate wiring layer 104, the second via 105, and the via 106 are made of a material containing one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the first via 103 may be made of the same material as the first coil 21. In one example, the intermediate wiring layer 104 may be made of the same material as the first coil 21. In one example, the second via 105 and the via 106 may be made of a material different from that of the first coil 21. The second via 105 and the via 106 may be made of a material containing, for example, W.

[0127] 12, the second outer peripheral connection portion 110 electrically connects each of the second coils 22 of the transformers 15A and 15B to the second outer peripheral pad 58C. The second outer peripheral connection portion 110 is provided outward from the first coil 21 and the second coil 22 in a plan view.

[0128] As shown in FIG. 13, the second peripheral connecting portion 110 includes a second peripheral wiring layer 111 and a second peripheral connecting layer 112. The second outer peripheral wiring layer 111 is formed at the same position as the second coil 22 in the Z direction. The second outer peripheral wiring layer 111 connects the second outer peripheral end 22B of the second coil 22 of the transformer 15A and the second outer peripheral end 22B of the second coil 22 of the transformer 15B. The second outer peripheral wiring layer 111 extends in the Y direction from the second outer peripheral end 22B. The second outer peripheral wiring layer 111 includes a portion that overlaps with the second outer peripheral pad 58C in a plan view.

[0129] The second peripheral connection layer 112 electrically connects the second peripheral wiring layer 111 and the second peripheral pad 58C. The second peripheral connection layer 112 is formed at a position overlapping both the second peripheral wiring layer 111 and the second peripheral pad 58C in a plan view. The second peripheral connection layer 112 penetrates the uppermost insulating film of the element insulating layer 52 and the first protective film 54A of the protective layer 54 in the Z direction. In one example, the second peripheral connection layer 112 is a via extending in the Z direction. A plurality of second peripheral connection layers 112 are provided at intervals in the X direction and the Y direction. In one example, the number of the second peripheral connection layers 112 is the same as the number of the second vias 105. The number of the second peripheral connection layers 112 can be changed arbitrarily.

[0130] The second outer peripheral wiring layer 111 and the second outer peripheral connecting layer 112 are made of a material containing one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the second outer peripheral wiring layer 111 may be made of the same material as the second coil 22. In one example, the second outer peripheral connecting layer 112 may be made of a material different from that of the second coil 22. The second outer peripheral connecting layer 112 may be made of a material containing W, for example.

[0131] As shown in FIGS. 4 to 13, the transformer chip 50 includes a conductive seal ring 59 provided on the element insulating layer 52. The seal ring 59 is provided on the outer periphery of the element insulating layer 52 in a plan view. The seal ring 59 is formed in a ring shape surrounding the transformers 15A, 15B, the first inner periphery connecting parts 80A, 80B, the second inner periphery connecting parts 90A, 90B, the first outer periphery connecting part 100, the second outer periphery connecting part 110, the plurality of first electrode pads 57, and the plurality of second electrode pads 58 in a plan view. In one example, the seal ring 59 is formed in a rectangular shape with the Y direction being the longitudinal direction and the X direction being the lateral direction in a plan view. The seal ring 59 is configured to prevent foreign matter that has entered the element insulating layer 52 from the outside of the transformer chip 50 from adhering to the transformers 15A, 15B, the first inner peripheral connection parts 80A, 80B, the second inner peripheral connection parts 90A, 90B, the first outer peripheral connection part 100, and the second outer peripheral connection part 110. The seal ring 59 is made of a material including one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the seal ring 59 is made of the same material as the first coil 21 and the second coil 22.

[0132] 8 and 9, the seal ring 59 penetrates the insulating films of the element insulating layer 52 excluding the uppermost insulating film and the lowermost insulating film in the Z direction. For this reason, it can be said that the seal ring 59 is provided at a distance from the substrate 51 in the Z direction. A plurality of vias 59A are provided between the seal ring 59 and the substrate 51 in the Z direction. Each via 59A connects the seal ring 59 and the substrate 51 in the Z direction. This electrically connects the seal ring 59 and the substrate 51.

[0133] [Effect] The operation of the transformer chip 50 of this embodiment will now be described. FIG. 14 is a schematic diagram showing a planar structure of a transformer chip 50X of a comparative example. FIG. 15 is a cross-sectional structure of the transformer chip 50X taken along line F15-F15 in FIG. 14, and shows a cross-sectional structure of a transformer 15A and its periphery. The transformer chip 50X of the comparative example differs from the transformer chip 50 mainly in the position of the first electrode pad 57 and the shapes of the first coil 21 and the second coil 22. In the following description of the transformer chip 50X, components common to the transformer chip 50 are given the same reference numerals, and their description may be omitted.

[0134] 14, in the transformer chip 50X of the comparative example, the second coil 22X is formed in a ring shape in a plan view with the Y direction as the long side and the X direction as the short side. Although not shown, the first coil 21X is formed in the same shape as the second coil 22X in a plan view. Therefore, the inner region 23X is formed in an elliptical shape with the Y direction as the long side and the X direction as the short side.

[0135] One second electrode pad 58 is disposed in the inner region 23X of the transformer 15A in a planar view, and another second electrode pad 58 is disposed in the inner region 23X of the transformer 15B in a planar view. On the other hand, the first electrode pad 57 is disposed closer to the element side surface 52C than the first coil 21X and the second coil 22X in a planar view.

[0136] 15, the first inner periphery connection portion 80AX electrically connecting the first inner periphery end portion 21A of the first coil 21X and the first electrode pad 57 includes a first inner periphery wiring layer 81X, a first inner periphery connection layer 82X, and a first outer periphery connection portion 86X. Note that the first inner periphery connection portion 80BX has the same configuration as the first inner periphery connection portion 80AX.

[0137] Since the first electrode pad 57 is disposed closer to the element side surface 52C than the first coil 21X, the first inner circumferential wiring layer 81X needs to be provided so as to intersect with the first coil 21X in a plan view. Therefore, the first inner circumferential wiring layer 81X needs to be disposed closer to the back surface 52B of the element insulating layer 52 than the first coil 21X. As a result, a dedicated insulating film for the first inner circumferential wiring layer 81X needs to be provided in the element insulating layer 52, and the number of laminated insulating films in the element insulating layer 52 increases.

[0138] In the transformer chip 50 of this embodiment, as shown in FIG. 4, both the first inner peripheral pad 57A as the first electrode pad 57 and the second inner peripheral pad 58A as the second electrode pad 58 are arranged in the inner region 23. Therefore, as shown in FIG. 7, the first inner peripheral wiring layer 81 of the first inner peripheral connection part 80A that electrically connects the first inner peripheral pad 57A and the first inner peripheral end part 21A of the first coil 21 does not need to be arranged so as to intersect with the first coil 21 in a plan view. In addition, the second inner peripheral wiring layer 91 of the second inner peripheral connection part 90A that electrically connects the second inner peripheral pad 58A and the second inner peripheral end part 22A of the second coil 22 does not need to straddle the second coil 22 in a plan view. In other words, the first inner peripheral wiring layer 81 can be arranged at the same position as the first coil 21 in the Z direction, and the second inner peripheral wiring layer 91 can be arranged at the same position as the second coil 22 in the Z direction. Therefore, an increase in the number of laminated insulating films of the element insulating layer 52 can be suppressed.

[0139] [effect] According to the transformer chip 50 of this embodiment, the following effects can be obtained. (1) The transformer chip 50 is composed of a laminated structure of multiple insulating films and includes an element insulating layer 52 including a front surface 52A and a back surface 52B facing opposite each other in the Z direction, a first coil 21 arranged in the element insulating layer 52 toward the back surface 52B, formed in a ring shape, and including a first inner circumferential end 21A, a second coil 22 arranged in the element insulating layer 52 toward the front surface 52A, formed in a ring shape, including a second inner circumferential end 22A, and facing the first coil 21 in the Z direction, a first inner circumferential pad 57A and a second inner circumferential pad 58A formed on the front surface 52A, a first inner circumferential connection portion 80A electrically connecting the first inner circumferential end 21A of the first coil 21 to the first inner circumferential pad 57A, and a second inner circumferential connection portion 90A electrically connecting the second inner circumferential end 22A of the second coil 22 to the second inner circumferential pad 58A. In plan view, the first inner circumferential pad 57A, the second inner circumferential pad 58A, the first inner circumferential connecting portion 80A, and the second inner circumferential connecting portion 90A are arranged in an inner region 23 surrounded by the first coil 21 and the second coil 22.

[0140] According to this configuration, since both the first inner periphery connecting portion 80A and the second inner periphery connecting portion 90A are disposed in the inner region 23 in a plan view, it is not necessary to provide the first inner periphery connecting portion 80A and the second inner periphery connecting portion 90A so as to intersect with the first coil 21 and the second coil 22 in a plan view. This eliminates the need to provide an insulating film dedicated to the first inner periphery connecting portion 80A and the second inner periphery connecting portion 90A in the element insulating layer 52, so that an increase in the number of insulating film layers of the element insulating layer 52 can be suppressed. Therefore, the thickness of the element insulating layer 52 can be reduced while ensuring the necessary withstand voltage between the first coil 21 and the second coil 22.

[0141] (2) The first coil 21 and the second coil 22 are formed in an annular shape having a longitudinal direction and a lateral direction. The first inner circumferential pad 57A and the second inner circumferential pad 58A are arranged to be spaced apart from each other in the longitudinal direction in a plan view.

[0142] This configuration allows the distance between the first inner peripheral pad 57A and the second inner peripheral pad 58A in the longitudinal direction to be large, thereby preventing the breakdown voltage of the transformer chip 50 from decreasing due to the distance between the first inner peripheral pad 57A and the second inner peripheral pad 58A.

[0143] (3) The first inner circumferential pad 57A is disposed at the first end 23A of the inner region 23 in the longitudinal direction. The second inner circumferential pad 58A is disposed at the second end 23B of the inner region 23 in the longitudinal direction.

[0144] This configuration allows the distance between the first inner peripheral pad 57A and the second inner peripheral pad 58A in the longitudinal direction to be further increased, thereby enhancing the effect of suppressing the decrease in withstand voltage of the transformer chip 50 caused by the distance between the first inner peripheral pad 57A and the second inner peripheral pad 58A.

[0145] (4) The transformer chip 50 includes a substrate 51 supporting an element insulating layer 52. The substrate 51 is in contact with a rear surface 52B of the element insulating layer 52. The first coil 21 is formed on the lowermost insulating film constituting the rear surface 52B among the multiple insulating films so as to be in contact with the lowermost insulating film.

[0146] According to this configuration, it is possible to increase the distance in the Z direction between the first coil 21 and the second coil 22 provided in the element insulating layer 52. Therefore, it is possible to improve the withstand voltage of the transformer chip 50.

[0147] (5) The second coil 22 is in contact with the uppermost insulating film that constitutes the surface 52A among the multiple insulating films and is covered by the insulating film. According to this configuration, it is possible to increase the distance in the Z direction between the first coil 21 and the second coil 22 provided in the element insulating layer 52. Therefore, it is possible to improve the withstand voltage of the transformer chip 50.

[0148] (6) The first inner periphery connection portion 80A is provided at the same position as the first coil 21 in the Z direction, and includes a first inner periphery wiring layer 81 extending from the first inner periphery end portion 21A in the longitudinal direction (X direction) of the first coil 21, and a first inner periphery connection layer 82 electrically connecting the first inner periphery wiring layer 81 and the first inner periphery pad 57A in the Z direction.

[0149] According to this configuration, the first inner peripheral end 21A of the first coil 21 and the first inner peripheral pad 57A are electrically connected inside the transformer chip 50. Therefore, compared to a configuration in which the first inner peripheral end 21A of the first coil 21 and the first inner peripheral pad 57A are electrically connected outside the transformer chip 50, the conductive path between the first inner peripheral end 21A of the first coil 21 and the first inner peripheral pad 57A can be made shorter.

[0150] (7) The shortest distance DM1 between the first inner circumference connecting portion 80A and the second coil 22 is equal to or greater than the distance DC between the first coil 21 and the second coil 22 in the Z direction. According to this configuration, a decrease in the withstand voltage of the transformer chip 50 caused by the distance between the first inner circumference connecting portion 80A and the second coil 22 can be suppressed.

[0151] (8) The second inner periphery connection portion 90A is provided at the same position as the second coil 22 in the Z direction, extends from the second inner periphery end portion 22A in the longitudinal direction (X direction) of the second coil 22, and includes a second inner periphery wiring layer 91 including a portion facing the second inner periphery pad 58A in the Z direction, and a second inner periphery connection layer 92 connecting the second inner periphery pad 58A and the second inner periphery wiring layer 91.

[0152] According to this configuration, the second inner peripheral end 22A of the second coil 22 and the second inner peripheral pad 58A are electrically connected inside the transformer chip 50. Therefore, compared to a configuration in which the second inner peripheral end 22A of the second coil 22 and the second inner peripheral pad 58A are electrically connected outside the transformer chip 50, the conductive path between the second inner peripheral end 22A of the second coil 22 and the second inner peripheral pad 58A can be made shorter.

[0153] (10) The transformer chip 50 includes a first outer peripheral pad 57C and a second outer peripheral pad 58C formed on the surface 52A of the element insulating layer 52 outboard of the first coil 21 and the second coil 22, a first outer peripheral connection portion 100 electrically connecting the first outer peripheral end portion 21B of the first coil 21 to the first outer peripheral pad 57C, and a second outer peripheral connection portion 110 electrically connecting the second outer peripheral end portion 22B of the second coil 22 to the second outer peripheral pad 58C. The first outer peripheral connection portion 100 includes a first outer peripheral wiring layer 101 provided at the same position as the first coil 21 in the Z direction, extending from the first outer peripheral end portion 21B in the short direction (Y direction) of the first coil 21, and including a portion facing the first outer peripheral pad 57C in the Z direction, and a first outer peripheral connection layer 102 connecting the first outer peripheral wiring layer 101 to the first outer peripheral pad 57C in the Z direction.

[0154] According to this configuration, the first outer peripheral end 21B of the first coil 21 and the first outer peripheral pad 57C are electrically connected inside the transformer chip 50. Therefore, compared to a configuration in which the first outer peripheral end 21B of the first coil 21 and the first outer peripheral pad 57C are electrically connected outside the transformer chip 50, the conductive path between the first outer peripheral end 21B of the first coil 21 and the first outer peripheral pad 57C can be made shorter.

[0155] (11) The second outer peripheral connection portion 110 is provided at the same position as the second coil 22 in the Z direction, extends from the second outer peripheral end portion 22B of the second coil 22 in the short direction (Y direction) of the second coil 22, and includes a second outer peripheral wiring layer 111 including a portion facing the second outer peripheral pad 58C in the Z direction, and a second outer peripheral connection layer 112 connecting the second outer peripheral wiring layer 111 and the second outer peripheral pad 58C in the Z direction.

[0156] According to this configuration, the second outer peripheral end 22B of the second coil 22 and the second outer peripheral pad 58C are electrically connected inside the transformer chip 50. Therefore, compared to a configuration in which the second outer peripheral end 22B of the second coil 22 and the second outer peripheral pad 58C are electrically connected outside the transformer chip 50, the conductive path between the second outer peripheral end 22B of the second coil 22 and the second outer peripheral pad 58C can be made shorter.

[0157] <Example of change> The above-described embodiments can be modified, for example, as follows. The above-described embodiments and the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, the same reference numerals as those in the above-described embodiments are used for the parts common to the above-described embodiments, and the description thereof will be omitted.

[0158] [Example of transformer tip modification] The numbers of the first inner pads 57A, 57B, the second inner pads 58A, 58B, the first outer pads 57C, and the second outer pads 58C can be changed as desired. In one example, a plurality of first inner pads 57A may be provided. A plurality of first inner pads 57B may be provided. A plurality of second inner pads 58A may be provided. A plurality of second inner pads 58B may be provided. A plurality of first outer pads 57C may be provided. A plurality of second outer pads 58C may be provided.

[0159] The arrangement of the first inner pads 57A, 57B, the second inner pads 58A, 58B, the first outer pads 57C, and the second outer pads 58C can be changed as desired. For example, a first example shown in FIG. 16, a second example shown in FIG. 17, and a third example shown in FIG. 18 can be given.

[0160] As shown in FIG. 16, in the first example, the transformer chip 50 includes a first inner electrode layer 121 that constitutes two first inner pads 57A. The first inner electrode layer 121 is formed in a rectangular flat plate shape with the thickness direction being the Z direction. In a plan view, the first inner electrode layer 121 is formed in a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction. The first inner electrode layer 121 is provided on the element insulating layer 52. The first inner electrode layer 121 is covered with a front-side insulating layer 53. The front-side insulating layer 53 includes two first openings 53A that are provided to expose the first inner electrode layer 121. The two first openings 53A are formed at positions aligned with each other in the Y direction and spaced apart from each other in the X direction. In this way, the portions of the first inner electrode layer 121 exposed from the two first openings 53A each constitute a first inner pad 57A. In other words, the two first inner peripheral pads 57A are formed at positions aligned with each other in the Y direction and spaced apart from each other in the X direction.

[0161] The transformer chip 50 includes a second inner electrode layer 122 that constitutes two second inner pads 58A. The second inner electrode layer 122 is formed in a rectangular flat plate shape with the Z direction as the thickness direction. In a plan view, the second inner electrode layer 122 is formed in a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction. The second inner electrode layer 122 is provided on the element insulating layer 52. The second inner electrode layer 122 is covered with the front side insulating layer 53. The front side insulating layer 53 includes two second openings 53B that are provided to expose the second inner electrode layer 122. The two second openings 53B are formed at positions aligned with each other in the Y direction and spaced apart from each other in the X direction. In this way, the portions of the second inner electrode layer 122 exposed from the two second openings 53B each constitute the second inner pad 58A. In other words, the two second inner peripheral pads 58A are formed at positions aligned with each other in the Y direction and spaced apart from each other in the X direction.

[0162] The transformer chip 50 includes a first peripheral electrode layer 123 that constitutes two first peripheral pads 57C. The first peripheral electrode layer 123 is formed in a rectangular flat plate shape with the Z direction as the thickness direction. In a plan view, the first peripheral electrode layer 123 is formed in a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction. The first peripheral electrode layer 123 is provided on the element insulating layer 52. The first peripheral electrode layer 123 is covered with a front-side insulating layer 53. The front-side insulating layer 53 includes two third openings 53C that are provided so that the first peripheral electrode layer 123 is exposed. The two third openings 53C are formed at positions aligned with each other in the Y direction and spaced apart from each other in the X direction. In this way, the portions of the first peripheral electrode layer 123 exposed from the two third openings 53C each constitute a first peripheral pad 57C. That is, the two first peripheral pads 57C are formed at positions aligned with each other in the Y direction and spaced apart from each other in the X direction.

[0163] The transformer chip 50 includes a second peripheral electrode layer 124 that constitutes two second peripheral pads 58C. The second peripheral electrode layer 124 is formed in a rectangular flat plate shape with the Z direction as the thickness direction. In a plan view, the second peripheral electrode layer 124 is formed in a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction. The second peripheral electrode layer 124 is provided on the element insulating layer 52. The second peripheral electrode layer 124 is covered with a front-side insulating layer 53. The front-side insulating layer 53 includes two third openings 53C that are provided so that the second peripheral electrode layer 124 is exposed. The two third openings 53C are formed at positions aligned with each other in the Y direction and spaced apart from each other in the X direction. In this way, the portions of the second peripheral electrode layer 124 exposed from the two third openings 53C each constitute a second peripheral pad 58C. That is, the two second peripheral pads 58C are formed at positions aligned with each other in the Y direction and spaced apart from each other in the X direction. The configurations of the two first inner circumferential pads 57B and the two second inner circumferential pads 58B are the same as the configurations of the two first inner circumferential pads 57A and the two second inner circumferential pads 58A.

[0164] As shown in FIG. 17, in the second example, the arrangement of the two first inner peripheral pads 57A, the two first inner peripheral pads 57B, the two second inner peripheral pads 58A, the two second inner peripheral pads 58B, the two first outer peripheral pads 57C, and the two second outer peripheral pads 58C is different from that of the first example.

[0165] The two first inner pads 57A are formed at positions aligned with each other in the X direction and spaced apart from each other in the Y direction. The two second inner pads 58A are formed at positions aligned with each other in the X direction and spaced apart from each other in the Y direction. For this reason, the distance DP between the first inner pad 57A and the second inner pad 58A in the X direction is greater than the distance DP in the first example (see FIG. 16).

[0166] The two first inner pads 57B are formed at positions aligned with each other in the X direction and spaced apart from each other in the Y direction. The two second inner pads 58B are formed at positions aligned with each other in the X direction and spaced apart from each other in the Y direction. For this reason, the distance DP between the first inner pad 57B and the second inner pad 58B in the X direction is greater than the distance DP in the first example (see FIG. 16).

[0167] The two first outer peripheral pads 57C are formed at positions aligned with each other in the X direction and spaced apart from each other in the Y direction. The two second outer peripheral pads 58C are formed at positions aligned with each other in the X direction and spaced apart from each other in the Y direction.

[0168] As shown in FIG. 18, in the third example, the arrangement of the two first inner circumferential pads 57A and the two first inner circumferential pads 57B is different from that in the second example. The two first inner peripheral pads 57A are formed at positions aligned with each other in the Y direction and spaced apart from each other in the X direction. The two first inner peripheral pads 57B are formed at positions aligned with each other in the Y direction and spaced apart from each other in the X direction.

[0169] In the third example, the arrangement of the two second inner peripheral pads 58A and the two second inner peripheral pads 58B instead of the two first inner peripheral pads 57A and the two first inner peripheral pads 57B may be different from that of the second example. In this case, the two second inner peripheral pads 58A are formed at positions aligned with each other in the Y direction and spaced apart from each other in the X direction. The two second inner peripheral pads 58B are formed at positions aligned with each other in the Y direction and spaced apart from each other in the X direction. In the first to third examples, the number of first outer peripheral pads 57C may be one. The number of second outer peripheral pads 58C may be one.

[0170] 19, in a plan view, the shortest distance DM3 between the second inner circumferential pad 58A and the second coil 22 may be smaller than the shortest distance between the first inner circumferential pad 57A and the second coil 22. Here, the shortest distance between the first inner circumferential pad 57A and the second coil 22 can be defined by the shortest distance DM1 (see FIG. 8) between the second coil 22 and the intermediate wiring layer 84. In this case, the shortest distance DM3 may be smaller than the distance DC (see FIG. 8) between the first coil 21 and the second coil 22.

[0171] The first coil 21 may be formed in a ring shape with its short side direction being in the X direction and its long side direction being in the Y direction. The second coil 22 may be formed in a ring shape with its short side direction being in the X direction and its long side direction being in the Y direction.

[0172] The shapes of the first coil 21 and the second coil 22 in a plan view can be changed arbitrarily. In one example, the first coil 21 may be formed in a circular ring shape in a plan view. The second coil 22 may be formed in a circular ring shape in a plan view. In another example, the first coil 21 may be formed in a rectangular ring shape in a plan view. The second coil 22 may be formed in a rectangular ring shape in a plan view.

[0173] The position of the second coil 22 in the Z direction can be changed arbitrarily. In one example, the second coil 22 may be provided so as to penetrate the uppermost insulating film among the multiple insulating films of the element insulating layer 52. In this case, the second coil 22 is covered with the front-side insulating layer 53. More specifically, the second coil 22 is covered with the protective layer 54.

[0174] The position of the first coil 21 in the Z direction can be changed as desired. In one example, the first coil 21 may be disposed at a position spaced apart in the Z direction from the lowest insulating film among the multiple insulating films in the element insulating layer 52.

[0175] The position of the first outer peripheral pad 57C in the X direction can be changed as desired. In one example, the first outer peripheral pad 57C may be disposed at a position different from the first inner peripheral pads 57A and 57B in the X direction.

[0176] The position of the second outer peripheral pad 58C in the X direction can be changed as desired. In one example, the second outer peripheral pad 58C may be disposed at a different position in the X direction from the second inner peripheral pads 58A and 58B.

[0177] The distance DQ (see FIG. 4) between the first outer peripheral pad 57C and the second outer peripheral pad 58C in the X direction can be changed as desired. In one example, the distance DQ may be greater than the distance DP between the first inner peripheral pad 57A and the second inner peripheral pad 58A in the X direction. The distance DQ may also be greater than the distance DP between the first inner peripheral pad 57B and the second inner peripheral pad 58B in the X direction.

[0178] Either the protective layer 54 or the passivation layer 55 may be omitted from the front-side insulating layer 53. In one example, when the protective layer 54 is omitted from the front-side insulating layer 53, the passivation layer 55 is formed on the element insulating layer 52 so as to be in contact with the element insulating layer 52. In one example, when the passivation layer 55 is omitted from the front-side insulating layer 53, the resin layer 56 is formed on the protective layer 54 so as to be in contact with the protective layer 54.

[0179] The configuration of the first inner pads 57A, 57B can be changed as desired. In one example, the first inner pads 57A, 57B may be formed to contact the intermediate wiring layer 84 of the first inner connection parts 80A, 80B. In this case, the second vias 85 are omitted from the first inner connection parts 80A, 80B.

[0180] The configuration of the second inner pads 58A, 58B can be changed as desired. In one example, the second inner pads 58A, 58B may be formed to contact the second inner wiring layer 91 of the second inner connecting parts 90A, 90B. In this case, the second inner connecting layer 92 of the second inner connecting parts 90A, 90B is omitted.

[0181] The configuration of the first outer peripheral pad 57C can be changed as desired. In one example, the first outer peripheral pad 57C may be formed so as to contact the intermediate wiring layer 104 of the first outer peripheral connection portion 100. In this case, the second via 105 is omitted from the first outer peripheral connection portion 100.

[0182] The configuration of the second outer peripheral pad 58C can be changed as desired. In one example, the second outer peripheral pad 58C may be formed so as to contact the second outer peripheral wiring layer 111 of the second outer peripheral connection part 110. In this case, the second outer peripheral connection layer 112 is omitted.

[0183] The vias 59A that electrically connect the seal ring 59 and the substrate 51 may be omitted. In this case, the seal ring 59 is, for example, in an electrically floating state. The vias 106 that electrically connect the first outer periphery connecting portion 100 and the substrate 51 may be omitted.

[0184] The front-side insulating layer 53 may be omitted from the transformer chip 50. The resin layer 56 may be omitted from the transformer chip 50. The seal ring 59 may be omitted from the transformer chip 50.

[0185] [Example of modification of signal transmission device] The arrangement of the transformer chip 50 can be changed as desired. In one example, the transformer chip 50 may be arranged on the second die pad 71. In this case, both the transformer chip 50 and the second chip 40 are arranged on the second die pad 71.

[0186] As shown in FIG. 20, the transformer chip 50 may include a primary circuit 13. More specifically, the primary circuit 13 is provided on, for example, a substrate 51. The transformer chip 50 shown in FIG. 20 includes a first circuit connection portion 140 and a second circuit connection portion 150 instead of the first inner peripheral connection portion 80A (see FIG. 7). The first circuit connection portion 140 electrically connects the first inner peripheral pad 57A and the primary circuit 13. The second circuit connection portion 150 electrically connects the first inner peripheral end portion 21A (see FIG. 5) of the first coil 21 of the transformer 15A and the primary circuit 13.

[0187] Although not shown, the transformer chip 50 includes a first circuit connection portion 140 and a second circuit connection portion 150 instead of the first inner peripheral connection portion 80B (see FIG. 4). The first circuit connection portion 140 electrically connects the first inner peripheral pad 57B (see FIG. 4) to the primary side circuit 13. The second circuit connection portion 150 electrically connects the first inner peripheral end portion 21A (see FIG. 5) of the first coil 21 of the transformer 15B to the primary side circuit 13.

[0188] The two first circuit connection parts 140 and the two second circuit connection parts 150 are provided, for example, on the element insulating layer 52. The first circuit connection part 140 and the second circuit connection part 150 corresponding to the transformer 15A are disposed in the inner region 23 of the transformer 15A in a planar view. The first circuit connection part 140 and the second circuit connection part 150 corresponding to the transformer 15B are disposed in the inner region 23 of the transformer 15B in a planar view. Each of the first circuit connection parts 140 and each of the second circuit connection parts 150 includes, for example, a wiring layer and a via. In this case, the multiple first electrode pads 57 are individually electrically connected to the multiple first leads 62 (see FIG. 2) of the first lead frame 60 by multiple wires W5.

[0189] As shown in FIG. 21, the transformer chip 50 may include the secondary circuit 14. More specifically, the secondary circuit 14 is provided on, for example, a substrate 51. The transformer chip 50 shown in FIG. 21 includes a third circuit connection portion 160 and a fourth circuit connection portion 170 instead of the first inner peripheral connection portion 80A (see FIG. 7). The third circuit connection portion 160 electrically connects the first inner peripheral pad 57A and the secondary circuit 14. The fourth circuit connection portion 170 electrically connects the first inner peripheral end portion 21A (see FIG. 5) of the first coil 21 of the transformer 15A and the secondary circuit 14. That is, the transformer chip 50 shown in FIG. 21 is different from the above embodiment in that the second coil 22 of the transformer 15A is electrically connected to the primary circuit 13, and the first coil 21 of the transformer 15A is electrically connected to the secondary circuit 14.

[0190] Although not shown, the transformer chip 50 includes a third circuit connection part 160 and a fourth circuit connection part 170 instead of the first inner peripheral connection part 80B (see FIG. 4). The third circuit connection part 160 electrically connects the first inner peripheral pad 57B (see FIG. 4) to the secondary side circuit 14. The fourth circuit connection part 170 electrically connects the first inner peripheral end part 21A (see FIG. 5) of the first coil 21 of the transformer 15B to the secondary side circuit 14. Therefore, in the transformer chip 50, the second coil 22 of the transformer 15B is electrically connected to the primary side circuit 13, and the first coil 21 of the transformer 15B is electrically connected to the secondary side circuit 14.

[0191] The two third circuit connection parts 160 and the two fourth circuit connection parts 170 are provided, for example, in the element insulating layer 52. The third circuit connection part 160 and the fourth circuit connection part 170 corresponding to the transformer 15A are arranged in the inner region 23 of the transformer 15A in a planar view. The third circuit connection part 160 and the fourth circuit connection part 170 corresponding to the transformer 15B are arranged in the inner region 23 of the transformer 15B in a planar view. In this case, the multiple first electrode pads 57 are individually electrically connected to the multiple second leads 72 (see FIG. 2) of the second lead frame 70 by multiple wires W6. The multiple second electrode pads 58 are individually electrically connected to the multiple second electrode pads 34 of the first chip 30 by multiple wires W2.

[0192] The signal transmission device 10 may include, for example, a plurality of transformer chips. In one example, as shown in FIG. 22, the signal transmission device 10 may include two transformer chips 50. Here, for convenience, the two transformer chips 50 are referred to as a "first transformer chip 50P" and a "second transformer chip 50Q." The first transformer chip 50P is disposed on a first die pad 61 of a first lead frame 60. The second transformer chip 50Q is disposed on a second die pad 71 of a second lead frame 70. In this manner, both the first transformer chip 50P and the first chip 30 are disposed on the first die pad 61, and both the second transformer chip 50Q and the second chip 40 are disposed on the second die pad 71.

[0193] The first transformer chip 50P is disposed closer to the second chip 40 than the first chip 30. The second transformer chip 50Q is disposed closer to the first chip 30 than the second chip 40. Therefore, from the first lead 62 of the first lead frame 60 toward the second lead 72 of the second lead frame 70, the first chip 30, the first transformer chip 50P, the second transformer chip 50Q, and the second chip 40 are disposed in this order.

[0194] The first chip 30 and the first transformer chip 50P are electrically connected by a plurality of wires W2. The second chip 40 and the second transformer chip 50Q are electrically connected by a plurality of wires W3. The connection between the first chip 30 and the first transformer chip 50P by the plurality of wires W2 is the same as the connection between the first chip 30 and the transformer chip 50 by the plurality of wires W2 in the above embodiment. The plurality of wires W3 electrically connect the plurality of first electrode pads 57 of the second transformer chip 50Q and the plurality of first electrode pads 43 of the second chip 40 individually. Therefore, the first coil 21 of the second transformer chip 50Q is electrically connected to the secondary circuit 14 of the second chip 40.

[0195] The first transformer chip 50P and the second transformer chip 50Q are electrically connected by a plurality of wires W7. More specifically, the second electrode pads 58 of the first transformer chip 50P are individually connected to the second electrode pads 58 of the second transformer chip 50Q by a plurality of wires W7. This electrically connects the second coil 22 of the first transformer chip 50P and the second coil 22 of the second transformer chip 50Q.

[0196] According to this configuration, the first chip 30 and the second chip 40 are insulated by a double insulation structure formed by the first transformer chip 50P and the second transformer chip 50Q, thereby improving the dielectric strength of the signal transmission device 10 compared to a configuration in which the first chip 30 and the second chip 40 are insulated by a single transformer chip.

[0197] In addition, since the first transformer chip 50P and the second transformer chip 50Q are provided separately from the first chip 30 and the second chip 40, a common transformer chip can be used for different first chips 30 and second chips 40. This makes it possible to reduce manufacturing costs when manufacturing multiple types of signal transmission devices 10 in which at least one of the first chips 30 and the second chips 40 is different.

[0198] The transformer chip 50 can be applied to devices other than the signal transmission device 10 of each embodiment. In the first example, the transformer chip 50 may be applied to, for example, a primary side circuit module. The primary side circuit module includes a first chip 30, a transformer chip 50, and a sealing resin that seals the chips 30 and 50. The primary side circuit module also includes a first die pad 61 on which both the first chip 30 and the transformer chip 50 are arranged. In this case, the primary side circuit module corresponds to an "insulating module." Note that, as shown in FIG. 20, the transformer chip 50 may include a primary side circuit 13. In this case, the first chip 30 is omitted.

[0199] In the second example, the transformer chip 50 may be applied to, for example, a secondary circuit module. The secondary circuit module includes a second chip 40, a transformer chip 50, and a sealing resin that seals these chips 40, 50. The secondary circuit module also includes a second die pad 71 on which the second chip 40 and the transformer chip 50 are arranged. In this case, the secondary circuit module corresponds to an "insulating module."

[0200] In a third example, the transformer chip 50 may be modularized. That is, the insulating module includes the transformer chip 50 and a sealing resin that seals the transformer chip 50. The insulating module also includes a die pad on which the transformer chip 50 is disposed.

[0201] Based on the above first to third examples, the configuration of the signal transmission device 10 may be modified as follows. In one example, the signal transmission device 10 may include the above-mentioned primary side circuit module and the second chip 40. In this case, the second chip 40 may be disposed on the second die pad 71, and the second die pad 71 and the second chip 40 may be configured as a module sealed with a sealing resin. In other words, this module is provided separately from the primary side circuit module. The signal transmission device 10 includes the primary side circuit module and the above-mentioned module.

[0202] In another example, the signal transmission device 10 may include the secondary circuit module and the first chip 30. In this case, the first chip 30 may be disposed on the first die pad 61, and the first die pad 61 and the first chip 30 may be configured as a module sealed with a sealing resin. In other words, this module is provided separately from the secondary circuit module. The signal transmission device 10 includes the secondary circuit module and the above module.

[0203] In addition, in one example, the signal transmission device 10 may include an insulating module, a first chip 30, and a second chip 40. In this case, the first chip 30 may be disposed on a first die pad 61, and the first die pad 61 and the first chip 30 may be configured as a first module sealed with a sealing resin. The second chip 40 may be disposed on a second die pad 71, and the second die pad 71 and the second chip 40 may be configured as a second module sealed with a sealing resin. In other words, the first module, the second module, and the insulating module are provided separately from each other. The signal transmission device 10 includes a first module, a second module, and an insulating module.

[0204] In each of the above embodiments, the signal transmission device 10 transmits a set signal and a reset signal from the primary side circuit 13 to the secondary side circuit 14, but this is not limited to the above. In one example, the signal transmission device 10 may transmit a signal from the secondary side circuit 14 to the primary side circuit 13. In one example, the signal transmission device 10 may transmit a signal in both directions, such that a signal is transmitted from the primary side circuit 13 to the secondary side circuit 14 and a signal is transmitted from the secondary side circuit 14 to the primary side circuit 13.

[0205] One or more of the various examples described in this specification may be combined to the extent that they are not technically inconsistent. The terms "first", "second", "third", etc. in this disclosure are used merely to distinguish objects and do not rank the objects.

[0206] In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B." The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" is intended to mean that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0207] The Z direction used in this disclosure does not necessarily have to be a vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this specification being "up" and "down" of the vertical direction. For example, the X direction may be a vertical direction, or the Y direction may be a vertical direction.

[0208] <Additional Notes> The technical ideas that can be understood from this disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference numbers of the corresponding components in the above embodiment. The reference numbers are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numbers.

[0209] [Appendix 1] an insulating layer (52) having a laminated structure of a plurality of insulating films (52P, 52Q) and including a front surface (52A) and a back surface (52B) facing opposite sides in a thickness direction (Z direction); a first coil (21) disposed in the insulating layer (52) toward the back surface (52B), formed in an annular shape, and including a first inner peripheral end portion (21A); a second coil (22) disposed in the insulating layer (52) toward the surface (52A), formed in an annular shape, including a second inner peripheral end portion (22A), and facing the first coil (21) in the thickness direction (Z direction); a first inner peripheral pad (57A) and a second inner peripheral pad (58A) formed on the surface (52A); a first inner peripheral connection portion (80A) that electrically connects the first inner peripheral end portion (21A) of the first coil (21) and the first inner peripheral pad (57A); a second inner peripheral connection portion (90A) that electrically connects the second inner peripheral end portion (22A) of the second coil (22) and the second inner peripheral pad (58A); Equipped with When viewed from the thickness direction (Z direction), the first inner peripheral pad (57A), the second inner peripheral pad (58A), the first inner peripheral connecting portion (80A), and the second inner peripheral connecting portion (90A) are disposed in an inner region (23) surrounded by the first coil (21) and the second coil (22). Transformer chip(50).

[0210] [Appendix 2] a substrate (51) in contact with the back surface (52B) of the insulating layer (52) and supporting the insulating layer (52); The first coil (21) is formed on a lowest insulating film (52Q) constituting the rear surface (52B) among the plurality of insulating films (52P, 52Q) so as to be in contact with the lowest insulating film (52Q). The transformer chip described in appendix 1.

[0211] [Appendix 3] The second coil (22) is covered by the insulating film (52P) in a state of contact with the uppermost insulating film (52P) constituting the surface (52A) among the plurality of insulating films (52P, 52Q). The transformer chip described in appendix 2.

[0212] [Appendix 4] The first coil (21) and the second coil (22) are formed in an annular shape having a longitudinal direction (X direction) and a lateral direction (Y direction), The first inner peripheral pad (57A) and the second inner peripheral pad (58A) are arranged apart from each other in the longitudinal direction (X direction) when viewed from the thickness direction (Z direction). 4. The transformer chip according to any one of claims 1 to 3.

[0213] [Appendix 5] the first inner peripheral pad (57A) is disposed at a first end (23A) of the inner region (23) in the longitudinal direction (X direction); The second inner peripheral pad (58A) is disposed at a second end (23B) of the inner region (23) opposite to the first end (23A) in the longitudinal direction (X direction). The transformer chip described in appendix 4.

[0214] [Appendix 6] The first inner circumferential connecting portion (80A) is a first inner circumferential wiring layer (81) provided at the same position as the first coil (21) in the thickness direction (Z direction) and extending from the first inner circumferential end portion (21A) in the longitudinal direction (X direction); a first inner circumferential connection layer (82) that electrically connects the first inner circumferential wiring layer (81) and the first inner circumferential pad (57A); 6. The transformer chip of claim 4 or 5, comprising:

[0215] [Appendix 7] The first inner circumferential connecting layer (82) is a first intermediate wiring layer (84) that is provided at the same position as the second coil (22) in the thickness direction (Z direction) and faces both the first inner peripheral wiring layer (81) and the first inner peripheral pad (57A) in the thickness direction (Z direction); a first inner peripheral via (83) connecting the first inner peripheral wiring layer (81) and the first intermediate wiring layer (84) in the thickness direction (Z direction); a second inner peripheral via (85) that connects the first intermediate wiring layer (84) and the first inner peripheral pad (57A) in the thickness direction (Z direction); 7. The transformer chip of claim 6, comprising:

[0216] [Appendix 8] The shortest distance (DM1) between the first inner peripheral connection portion (80A) and the second coil (22) is equal to or greater than the distance (DC) between the first coil (21) and the second coil (22) in the thickness direction (Z direction). 8. The transformer chip according to claim 6 or 7.

[0217] [Appendix 9] The second inner circumferential connection portion (90A) is a second inner circumferential wiring layer (91) provided at the same position as the second coil (22) in the thickness direction (Z direction), extending from the second inner circumferential end portion (22A) in the longitudinal direction (X direction), and including a portion facing the second inner circumferential pad (58A) in the thickness direction (Z direction); a second inner peripheral connection layer (92) that electrically connects the second inner peripheral pad (58A) and the second inner peripheral wiring layer (91); The transformer chip according to any one of claims 4 to 8, comprising:

[0218] [Appendix 10] a first outer circumferential pad (57C) and a second outer circumferential pad (58C) formed on the surface (52A) outwardly of the first coil (21) and the second coil (22); a first outer periphery connection portion (100) that electrically connects a first outer periphery end portion (21B) of the first coil (21) and the first outer periphery pad (57C); a second outer periphery connection portion (110) that electrically connects a second outer periphery end portion (22B) of the second coil (22) and the second outer periphery pad (58C); The transformer chip according to any one of claims 1 to 9, comprising:

[0219] [Appendix 11] The first coil (21) and the second coil (22) are formed in an annular shape having a longitudinal direction (X direction) and a lateral direction (Y direction), The first outer peripheral pad (57C) is disposed at the same position as the first inner peripheral pad (57A) in the longitudinal direction (X direction) when viewed from the thickness direction (Z direction), The second outer peripheral pad (58C) is disposed at the same position as the second inner peripheral pad (58A) in the longitudinal direction (X direction) when viewed from the thickness direction (Z direction). 11. The transformer chip of claim 10.

[0220] [Appendix 12] The first coil (21) and the second coil (22) are formed in an annular shape having a longitudinal direction (X direction) and a lateral direction (Y direction), A distance (DQ) between the first outer peripheral pad (57C) and the second outer peripheral pad (58C) in the longitudinal direction (X direction) is equal to or greater than a distance (DP) between the first inner peripheral pad (57A) and the second inner peripheral pad (58A) in the longitudinal direction (X direction). 11. The transformer chip of claim 10.

[0221] [Appendix 13] The first outer periphery connecting portion (100) is a first outer peripheral wiring layer (101) provided at the same position as the first coil (21) in the thickness direction (Z direction), extending from the first outer peripheral end portion (21B) in the short-side direction (Y direction), and including a portion facing the first outer peripheral pad (57C) in the thickness direction (Z direction); a first outer peripheral connection layer (102) that electrically connects the first outer peripheral wiring layer (101) and the first outer peripheral pad (57C); 13. The transformer chip of claim 11 or 12, comprising:

[0222] [Appendix 14] The first peripheral connecting layer (102) is a second intermediate wiring layer (104) that is provided at the same position as the second coil (22) in the thickness direction (Z direction) and faces both the first peripheral wiring layer (101) and the first peripheral pad (57C) in the thickness direction (Z direction); a first peripheral via (103) that connects the first peripheral wiring layer (101) and the second intermediate wiring layer (104) in the thickness direction (Z direction); a second peripheral via (105) that connects the second intermediate wiring layer (104) and the first peripheral pad (57C) in the thickness direction (Z direction); 14. The transformer chip of claim 13, comprising:

[0223] [Appendix 15] The second outer periphery connecting portion (110) is a second outer peripheral wiring layer (111) provided at the same position as the second coil (22) in the thickness direction (Z direction), extending from the second outer peripheral end portion (22B) in the short direction (Y direction), and including a portion facing the second outer peripheral pad (58C) in the thickness direction (Z direction); a second peripheral connection layer (112) that electrically connects the second peripheral wiring layer (111) and the second peripheral pad (58C) in the thickness direction (Z direction); 15. The transformer chip according to any one of claims 11 to 14, comprising:

[0224] [Appendix 16] The first inner peripheral pad (57A) and the second inner peripheral pad (58A) are each provided in plurality, the first inner peripheral pads (57A) are arranged in the longitudinal direction (X direction) of the first coil (21) and the second coil (22) when viewed from the thickness direction (Z direction); The second inner peripheral pads (58A) are arranged in the longitudinal direction (X direction) of the first coil (21) and the second coil (22) when viewed from the thickness direction (Z direction). The transformer chip according to any one of claims 4 to 9.

[0225] [Appendix 17] The first inner peripheral pad (57A) and the second inner peripheral pad (58A) are each provided in plurality, the first inner peripheral pads (57A) are arranged in the short-side direction (Y direction) of the first coil (21) and the second coil (22) when viewed from the thickness direction (Z direction); The second inner peripheral pads (58A) are arranged in the short-side direction (Y direction) of the first coil (21) and the second coil (22) when viewed from the thickness direction (Z direction). The transformer chip according to any one of claims 4 to 9.

[0226] [Appendix 18] A transformer chip (50) according to any one of appendixes 1 to 17; A first circuit (13); a second circuit (14) connected to the first circuit (13) via the transformer chip (50); Equipped with The first circuit (13) and the second circuit (14) are configured to transmit signals via the transformer chip (50). Signal transmission device (10).

[0227] [Appendix 19] a first chip (30) including the first circuit (13); a second chip (40) including the second circuit (14); 19. The signal transmission device (10) of claim 18, comprising:

[0228] [Appendix 20] The transformer chip (50) includes a first transformer chip (50A) and a second transformer chip (50B), The second coil (22) of the first transformer chip (50A) is electrically connected to the first coil (21) of the second transformer chip (50B). 19. The signal transmission device of claim 18.

[0229] [Appendix 21] a first chip (30) including the first circuit (13); a second chip (40) including the second circuit (14); a first die pad (61) on which both the first chip (30) and the first transformer chip (50A) are arranged; a second die pad (71) on which both the second chip (40) and the second transformer chip (50B) are arranged; 21. The signal transmission device of claim 20, comprising:

[0230] [Appendix 22] Transformer chip (50) and A first circuit (13); a second circuit (14) connected to the first circuit (13) via the transformer chip (50); Equipped with the first circuit (13) and the second circuit (14) are configured to transmit signals via the transformer chip (50); The transformer chip (50) includes the first circuit (13), The second circuit (14) is provided separately from the transformer chip (50), The transformer chip (50) is an insulating layer (52) having a laminated structure of a plurality of insulating films (52P, 52Q) and including a front surface (52A) and a back surface (52B) facing opposite sides in a thickness direction (Z direction); a first coil (21) disposed in the insulating layer (52) toward the back surface (52B), formed in an annular shape, and including a first inner peripheral end portion (21A); a second coil (22) disposed in the insulating layer (52) toward the surface (52A), formed in an annular shape, including a second inner peripheral end portion (22A), and facing the first coil (21) in the thickness direction (Z direction); a first inner peripheral pad (57A) and a second inner peripheral pad (58A) formed on the surface (52A); a first circuit connection portion (140) that electrically connects the first circuit (13) and the first inner peripheral pad (57A); a second inner peripheral connection portion (90A) that electrically connects the second inner peripheral end portion (22A) of the second coil (22) and the second inner peripheral pad (58A); Equipped with When viewed from the thickness direction (Z direction), the first inner peripheral pad (57A), the second inner peripheral pad (58A), the first circuit connection portion (140), and the second inner peripheral connection portion (90A) are disposed in an inner region (23) surrounded by the first coil (21) and the second coil (22). Signal transmission device (10).

[0231] [Appendix 23] the transformer chip (50) includes a second circuit connection portion (150) that electrically connects the first inner peripheral end portion (21A) of the first coil (21) and the first circuit (13); When viewed from the thickness direction (Z direction), the second circuit connection portion (150) is disposed in the inner region (23). 23. A signal transmission device as described in claim 22.

[0232] [Appendix 24] Transformer chip (50) and A first circuit (13); a second circuit (14) connected to the first circuit (13) via the transformer chip (50); Equipped with the first circuit (13) and the second circuit (14) are configured to transmit signals via the transformer chip (50); The transformer chip (50) includes the second circuit (14), the first circuit (13) is provided separately from the transformer chip (50); The transformer chip (50) is an insulating layer (52) having a laminated structure of a plurality of insulating films (52P, 52Q) and including a front surface (52A) and a back surface (52B) facing opposite sides in a thickness direction (Z direction); a first coil (21) disposed in the insulating layer (52) toward the back surface (52B), formed in an annular shape, and including a first inner peripheral end portion (21A); a second coil (22) disposed in the insulating layer (52) toward the surface (52A), formed in an annular shape, including a second inner peripheral end portion (22A), and facing the first coil (21) in the thickness direction (Z direction); a first inner peripheral pad (57A) and a second inner peripheral pad (58A) formed on the surface (52A); a third circuit connection portion (160) that electrically connects the second circuit (14) and the first inner peripheral pad (57A); a second inner peripheral connection portion (90A) that electrically connects the second inner peripheral end portion (22A) of the second coil (22) and the second inner peripheral pad (58A); Equipped with When viewed from the thickness direction (Z direction), the first inner peripheral pad (57A), the second inner peripheral pad (58A), the second inner peripheral connection portion (90A), and the third circuit connection portion (160) are disposed in an inner region (23) surrounded by the first coil (21) and the second coil (22). Signal transmission device (10).

[0233] [Appendix 25] the transformer chip (50) includes a fourth circuit connection portion (170) that electrically connects the first inner circumferential end portion (21A) of the first coil (21) and the second circuit (14), When viewed from the thickness direction (Z direction), the fourth circuit connection portion (170) is disposed in the inner region (23). 26. A signal transmission device as described in claim 25.

[0234] The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and alterations that fall within the scope of the present disclosure, including the scope of the claims. [Explanation of symbols]

[0235] 10. Signal transmission device 10A…Signal transmission circuit 11…Primary side terminal 12…Secondary side terminal 13…Primary side circuit (1st circuit) 14…Secondary circuit (second circuit) 15, 15A, 15B...Transformer 16A,16B…Primary side signal line 17A,17B…Secondary side signal line 21…First coil 21A…First inner peripheral end 21B...First outer peripheral end 21C, 21D…Straight section 21E, 21F…Bend 22…Second coil 22A…Second inner peripheral end 22B…Second outer peripheral end 22C,22D…Straight section 22E, 22F…Bend 23…Inner area 23A…First end 23B…Second end 30…First tip 31…Chip surface 32…Chip backside 33…First electrode pad 34…Second electrode pad 35…Third electrode pad 36... Circuit board 37...Wiring layer 40…Second chip 41…Chip surface 42…Chip backside 43…First electrode pad 44…Second electrode pad 45…Third electrode pad 46…Substrate 47...Wiring layer 50...Trans chip 50A…Chip surface 50B…Chip backside 50P…First transformer chip 50Q…Second transformer chip 51... Circuit board 51A…Substrate surface 51B…Back side of board 52... Element insulating layer 52A…Surface 52B…Back 52C~52F: Side of element 52P…First insulating film 52Q…Second insulating film 53... Surface insulating layer 53A…1st opening 53B…Second opening 53C…Third opening 54...Protective layer 54A…1st protective film 54B…Second protective film 55…passivation layer 56…Resin layer 57…First electrode pad 57A, 57B…First inner pad 57C…First outer pad 58…Second electrode pad 58A, 58B…Second inner pad 58C…Second outer pad 59…Seal ring 59A…Via 60…First lead frame 61…First die pad 62…1st lead 70…2nd lead frame 71…Second die pad 72…2nd lead 80A, 80B…First inner connection part 81...First inner wiring layer 82…First inner connecting layer 83…First via 84...Intermediate wiring layer 85…Second via 90A, 90B…Second inner circumference connection part 91...Second inner wiring layer 92…Second inner connection layer 100…First outer periphery connection part 101...First outer wiring layer 102...First outer peripheral connection layer 103…First via 104...Intermediate wiring layer 105…Second via 106…Beer 110...Second outer periphery connection part 111…Second outer wiring layer 112...Second outer peripheral connection layer 121...First inner electrode layer 122...Second inner electrode layer 123...First outer electrode layer 124…Second outer electrode layer 130...Sealing resin 131~134…Resin side 140...First circuit connection part 150…Second circuit connection part 160…Third circuit connection part 170…4th circuit connection part W1~W7…Wire SD: Conductive adhesive LX1: X-direction dimension of the first coil LY1: Y-direction dimension of the first coil LX2: X-direction dimension of second coil LY2: Y-direction dimension of second coil LX3: Dimension of element insulating layer in the X direction DC: Distance between the first and second coils DM1, DM2: Shortest distance between the second coil and the middle wiring layer DM3: Shortest distance between the second inner pad and the second coil DP: Distance between the first inner pad and the second inner pad in the X direction DQ: Distance between the first and second outer pads in the X direction

Claims

1. an insulating layer having a laminated structure of a plurality of insulating films and including a front surface and a back surface facing opposite sides in a thickness direction; a first coil disposed in the insulating layer toward the rear surface, the first coil being formed in an annular shape and including a first inner peripheral end portion; a second coil disposed in the insulating layer toward the surface, formed in an annular shape, including a second inner peripheral end portion, and facing the first coil in the thickness direction; a first inner peripheral pad and a second inner peripheral pad formed on the surface; a first inner peripheral connection portion that electrically connects the first inner peripheral end portion of the first coil and the first inner peripheral pad; a second inner peripheral connection portion that electrically connects the second inner peripheral end portion of the second coil and the second inner peripheral pad; Equipped with When viewed from the thickness direction, the first inner peripheral pad, the second inner peripheral pad, the first inner peripheral connecting portion, and the second inner peripheral connecting portion are disposed in an inner region surrounded by the first coil and the second coil. Transformer chip.

2. a substrate in contact with the back surface of the insulating layer and supporting the insulating layer; The first coil is formed on a lowest insulating film constituting the rear surface among the plurality of insulating films so as to be in contact with the lowest insulating film. The transformer chip according to claim 1 .

3. The second coil is covered by an insulating film in a state of contact with the uppermost insulating film constituting the surface among the plurality of insulating films. The transformer chip according to claim 2.

4. The first coil and the second coil are formed in an annular shape having a longitudinal direction and a lateral direction, The first inner peripheral pad and the second inner peripheral pad are arranged apart from each other in the longitudinal direction when viewed from the thickness direction. The transformer chip according to claim 1 .

5. The first inner peripheral pad is disposed at a first end of the inner region in the longitudinal direction, The second inner peripheral pad is disposed at a second end portion of the inner region opposite to the first end portion in the longitudinal direction. The transformer chip according to claim 4.

6. The first inner circumferential connecting portion is a first inner circumferential wiring layer provided at the same position as the first coil in the thickness direction and extending in the longitudinal direction from the first inner circumferential end portion; a first inner periphery connection layer electrically connecting the first inner periphery wiring layer and the first inner periphery pad; Includes The transformer chip according to claim 4.

7. The first inner circumferential connecting layer is a first intermediate wiring layer provided at the same position as the second coil in the thickness direction and facing both the first inner peripheral wiring layer and the first inner peripheral pad in the thickness direction; a first inner via that connects the first inner wiring layer and the first intermediate wiring layer in the thickness direction; a second inner peripheral via that connects the first intermediate wiring layer and the first inner peripheral pad in the thickness direction; Includes The transformer chip according to claim 6.

8. The shortest distance between the first inner circumferential connection portion and the second coil is equal to or greater than the distance between the first coil and the second coil in the thickness direction. The transformer chip according to claim 6.

9. The second inner circumferential connecting portion is a second inner wiring layer provided at the same position as the second coil in the thickness direction, extending in the longitudinal direction from the second inner end portion, and including a portion facing the second inner pad in the thickness direction; a second inner connection layer electrically connecting the second inner pad and the second inner wiring layer; Includes The transformer chip according to claim 4.

10. a first outer pad and a second outer pad formed on the front surface outwardly of the first coil and the second coil; a first outer connection portion that electrically connects a first outer end portion of the first coil and the first outer pad; a second outer connection portion that electrically connects a second outer end portion of the second coil and the second outer pad; Equipped The transformer chip according to claim 1 .

11. The first coil and the second coil are formed in an annular shape having a longitudinal direction and a lateral direction, the first outer peripheral pad is disposed at the same position as the first inner peripheral pad in the longitudinal direction when viewed from the thickness direction, The second outer peripheral pad is disposed at the same position as the second inner peripheral pad in the longitudinal direction when viewed from the thickness direction. The transformer chip according to claim 10.

12. The first coil and the second coil are formed in an annular shape having a longitudinal direction and a lateral direction, The distance between the first outer peripheral pad and the second outer peripheral pad in the longitudinal direction is equal to or greater than the distance between the first inner peripheral pad and the second inner peripheral pad in the longitudinal direction. The transformer chip according to claim 10.

13. The first outer circumferential connection portion is a first outer wiring layer provided at the same position as the first coil in the thickness direction, extending in the short direction from the first outer end, and including a portion facing the first outer pad in the thickness direction; a first outer connection layer electrically connecting the first outer wiring layer and the first outer pad; Includes The transformer chip according to claim 11.

14. The first peripheral connection layer is a second intermediate wiring layer that is provided at the same position as the second coil in the thickness direction and faces both the first outer wiring layer and the first outer pad in the thickness direction; a first peripheral via that connects the first peripheral wiring layer and the second intermediate wiring layer in the thickness direction; a second outer peripheral via that connects the second intermediate wiring layer and the first outer peripheral pad in the thickness direction; Includes The transformer chip according to claim 13.

15. The second outer circumferential connection portion is a second outer wiring layer provided at the same position as the second coil in the thickness direction, extending in the short direction from the second outer end, and including a portion facing the second outer pad in the thickness direction; a second outer connection layer electrically connecting the second outer wiring layer and the second outer pad; Includes The transformer chip according to claim 11.

16. The first inner peripheral pad and the second inner peripheral pad are each provided in plurality, the first inner peripheral pads are arranged in the longitudinal direction of the first coil and the second coil when viewed from the thickness direction, The second inner peripheral pads are arranged in the longitudinal direction of the first coil and the second coil when viewed from the thickness direction. The transformer chip according to claim 4.

17. The first inner peripheral pad and the second inner peripheral pad are each provided in plurality, The first inner peripheral pads are arranged in the short side direction of the first coil and the second coil when viewed from the thickness direction, The second inner peripheral pads are arranged in the short direction of the first coil and the second coil when viewed from the thickness direction. The transformer chip according to claim 4.

18. A transformer chip according to any one of claims 1 to 17, A first circuit; a second circuit connected to the first circuit via the transformer chip; Equipped with The first circuit and the second circuit are configured to transmit a signal through the transformer chip. Signal transmission device.

19. a first chip including the first circuit; a second chip including the second circuit; Includes 20. The signal transmission device according to claim 18.

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