Apriori application with dynamic digital correction (DDC) function

Abstract

To provide an apriori application with a dynamic digital correction (ddc) function.SOLUTION: In one embodiment of the present disclosure, a method includes measuring a location of a die pad of a die placed on a substrate, and determining a die pad shift between an expected location of the die pad and the measured location of the die pad. The method also includes using the determined die pad shift and an expected via location to generate a shifted via location for a via electrically connecting to the die pad. The method further includes patterning the via at the shifted via location with a maskless lithography tool, and utilizing a physical mask with a mask-based lithography tool to pattern a redistribution layer (RDL) pad electrically connected to the via patterned at the shifted via location with the maskless lithography tool.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to lithography systems and, more particularly, to lithography systems, software applications, and methods for semiconductor packaging. [Background technology]

[0002] Electronic packaging and assembly is generally used to couple small dimension integrated circuits (ICs) to interconnection substrates, such as printed circuit boards (PCBs) or interposers. PCBs usually contain several passive components and ICs to build microelectronic devices, and interposers are connection boards embedded with packaged chips, on which are multiple chiplet ICs. The semiconductor industry is experiencing rapid growth due to the continuous improvement of integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In general, the improvement of integration density comes from the repeated reduction of minimum feature size, which allows more components to be integrated in a given area. As the demand for shrinking electronic devices increases, the need for smaller and more ingenious packaging techniques for semiconductor dies becomes evident.

[0003] For the foregoing reasons, there is a need for lithography systems, software applications, and methods for semiconductor packaging. Summary of the Invention

[0004] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to lithography systems and, more particularly, to lithography systems, software applications, and methods for semiconductor packaging.

[0005] In one embodiment, a method is disclosed. The method includes measuring a location of a die pad of a die placed on a substrate, and determining a die pad shift between an expected location of the die pad and the measured location of the die pad. The method further includes generating a shifted via location for a via electrically connecting to the die pad using the determined die pad shift and the expected via location. The method further includes patterning a via at the shifted via location using a maskless lithography tool, and utilizing a physical mask in a mask-based lithography tool to pattern a redistribution layer (RDL) pad electrically connecting to the via patterned with the maskless lithography tool at the shifted via location.

[0006] In another embodiment, a layer structure is disclosed. The layer structure includes one or more die pads, each of the one or more die pads including a die pad center point. The layer structure further includes one or more vias disposed on the one or more die pads, each of the one or more vias including a via center point. The layer structure further includes one or more redistribution metal layer (RDL) pads disposed on the one or more vias, each of the one or more RDL pads including an RDL pad center point, the die pad center point, the via center point, and the RDL pad center point are not aligned, and the via center point is disposed between the RDL pad center point and the die pad center point.

[0007] In yet another embodiment, a non-transitory computer-readable medium is disclosed. The non-transitory computer-readable medium stores instructions that, when executed by a processor, cause a computer system to perform a step of calculating a correction factor, the calculation including a via radius, a redistribution metal layer (RDL) pad radius, and a die pad radius. The step further includes a step of determining one or more shifted die pad coordinates, and a step of shifting one or more via coordinates utilizing the correction factor, where each via coordinate is moved to a shifted via coordinate between a theoretical die pad coordinate and a shifted die pad coordinate with respect to the one or more shifted die pad coordinates.

[0008] So that the above-described features of the present disclosure can be understood in detail, a more particular description of the above briefly summarized disclosure can be made with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that since the present disclosure can admit of other equally effective embodiments, the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered as limiting its scope.

[0009] This disclosure contains at least one drawing executed in color. Copies of this disclosure with color drawing(s) will be provided by the U.S. Patent and Trademark Office upon request and payment of the necessary fee. Color drawings will be submitted electronically via EFS Web so only one set of drawings need be submitted. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic diagram of a lithography system in accordance with one or more embodiments of the present disclosure. [Figure 2A] FIG. 1 is a perspective view of a maskless lithography tool that can benefit from the embodiments described herein. [Figure 2B] 1 is a schematic cross-sectional view of a lithography tool in accordance with one or more embodiments of the present disclosure. [Figure 3A] 1 is a schematic diagram of a portion of a mask pattern according to one or more embodiments of the present disclosure. [Figure 3B] FIG. 2 is a cross-sectional view of a layer structure with theoretical die pad locations in accordance with one or more embodiments of the present disclosure. [Figure 4] FIG. 1 is a schematic diagram of an interface according to one or more embodiments of the present disclosure. [Diagram 5] 1 is a schematic top view of a packaging substrate prior to a first operation of the digital dynamic connection method described herein. FIG. [Figure 6] 1 is a flow diagram of a digital dynamic connection method according to one or more embodiments of the present disclosure. [Figure 7A] 1 is a schematic top view of a layer structure after correcting via positions to partially shifted via positions in accordance with one or more embodiments of the present disclosure. [Figure 7B] 1 is a schematic cross-sectional view of a layer structure according to one or more embodiments of the present disclosure. [Figure 8A] FIG. 13 is a schematic top view of a layer structure without RDL positions after correcting the via positions to shifted via positions according to one embodiment of the present disclosure. [Figure 8B] FIG. 13 is a schematic top view of a layer structure without RDL positions after correcting the via positions to partially shifted via positions according to one embodiment of the present disclosure. [Figure 9A] FIG. 13 is a schematic top view of a layer structure after correcting via positions to shifted via positions according to one embodiment of the present disclosure. [Figure 9B] FIG. 13 is a schematic top view of a layer structure after correcting via positions to partially shifted via positions according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] For ease of understanding, wherever possible, identical reference numbers have been used to designate identical elements that are common to the figures. It is intended that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0012] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to lithography systems and, more particularly, to lithography systems, software applications, and methods for semiconductor packaging.

[0013] In advanced packaging industry, the die pad position of a semiconductor package has unexpected drift due to die pick and placement. For proper electrical connection, the top and bottom areas of the via are between the die pad and the redistribution metal layer (RDL). In some methods suitable for conventional litho tools to correct the die pad position drift, the die pad size and other inherent feature dimensions of the die pad are enlarged to cover the variations caused by the die position drift. However, enlarging the feature dimensions will reduce the I / O density, increase the power consumption, and reduce the chip performance. In other methods to adjust the die pad position drift, the inherent feature dimensions of the die pad remain unadjusted, but the RDL pad and via positions are moved by a maskless lithography tool to compensate for the die pad shift. However, the movement of the RDL pad and via positions requires a direct-write lithography tool (or a maskless lithography tool). Due to the movement of the RDL pad positions, conventional litho tools using a physical mask cannot properly pattern the RDL pad positions.

[0014] 1 is a schematic diagram of a lithography system 100 in accordance with one or more embodiments of the present disclosure. As shown, the lithography system 100 includes, but is not limited to, a pattern generator 102, a metrology device 104, a maskless lithography tool 108, a controller 110, and a number of communication links 101. The lithography system 100 may further include a transport system 103. The maskless lithography tool 108 and the metrology device 104 may be connected by the transport system 103. The transport system 103 is operable to transport substrates from the metrology device 104 to and from the maskless lithography tool 108. In some embodiments, the transport system 103 may also be operable to transport substrates to and from the maskless lithography tool 108 to a lithography tool 200, i.e., a mask-based lithography tool.

[0015] Each of the lithography system devices (pattern generator 102, metrology device 104, and maskless lithography tool 108) is operatively connected to a controller 110 via a communication link 101. The lithography system 100 can be located in the same area or manufacturing facility, or each of the lithography system devices can be located in different areas.

[0016] Each of the pattern generator 102, the metrology device 104, the maskless lithography tool 108, and the controller 110 includes an on-board processor and memory configured to store instructions corresponding to any portion of the digital dynamic connection method 600 described below. The communication link 101 may include at least one of a wired connection, a wireless connection, a satellite connection, and the like. The communication link 101 facilitates sending and receiving files for storing data according to embodiments described further herein. The transfer of data along the communication link 101 may include temporarily or permanently storing the file or data in a cloud before transferring or copying the file or data to the lithography environment device.

[0017] The controller 110 includes a central processing unit (CPU) 112, support circuits 114, and memory 116. The CPU 112 can be one of any form of computer processor that can be used in an industrial environment to control lithography system devices. The memory 116 is coupled to the CPU 112. The memory 116 can be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits 114 are coupled to the CPU 112 to support the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input / output circuits, subsystems, and the like. The controller 110 can include the CPU 112 coupled to the support circuits 114 and input / output (I / O) devices found in the memory 116. The controller 110 is operable to serve design files and transfer the design files to the maskless lithography tool 108 via the communication link 101.

[0018] The memory 116 may include one or more software applications, such as a control software program. The memory 116 may further include stored media data used by the CPU 112 to execute the digital dynamic connection method 600 described herein. The CPU 112 may be a hardware unit or combination of hardware units capable of executing software applications and processing data. In some configurations, the CPU 112 includes a central processing unit (CPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), and / or a combination of such units. The CPU 112 is generally configured to execute one or more software applications and process stored media data, each of which may be included in the memory 116. The controller 110 controls the transfer of data and files to and from various lithography system devices. The memory 116 is configured to store instructions corresponding to any operation of the digital dynamic connection method 600 according to the embodiments described herein.

[0019] The pattern generator 102 may include software and hardware for creating a graphic data system (GDS) design, a virtual mask software application (such as vMASC software), performing data transfers, and generating an output file of the mask pattern 300 (as shown in FIG. 3A). The pattern generator 102 may be utilized to create the mask pattern 300 prior to operation 610 of the digital dynamic connection method 600. The mask pattern 300 generated by the pattern generator 102 may be sent to the controller 110 via the communication link 101.

[0020] The metrology device 104 may include software and hardware for printing on a substrate, measuring the die shift and / or rotation, converting the die shift and rotation data into a format, and transferring the data to the controller 110. The metrology data generated from the metrology device 104 may be sent to the controller 110 via the communication link 101. The controller 110 may update the mask pattern 300 with the metrology data generated via the metrology device 104 to generate a compensated pattern having partially shifted via locations 302′ (as shown in FIGS. 8B and 9B ).

[0021] The compensated pattern with the partially shifted via locations 302' is sent from the controller 110 to the maskless lithography tool 108 via the communication link 101. The maskless lithography tool 108 may include software and / or hardware for loading the substrate, leveling the substrate, homing the laser, finding the edge of the substrate, pre-focusing the laser, aligning the laser on the substrate, and performing the laser printing. In some embodiments, the maskless lithography tool 108 may not be utilized to pattern the RDL pad locations 304 (shown in FIG. 7A). The lithography tool 200 may be utilized to pattern the RDL pad locations 304.

[0022] 2A is a perspective view of an exemplary maskless lithography tool 108, such as a maskless lithography system, that may benefit from embodiments described herein. The maskless lithography tool 108 includes a stage 202 and a processing unit 204. A chuck 214 on the stage 202 is supported by a track motor 216. A packaging substrate 220 is supported by the chuck 214. The chuck 214 is operable to move along the track motor 216 to move the substrate 220 to a particular position. A position sensor 218 is coupled to the stage 202 to provide information of the position of the chuck 214 to a lithography controller 222.

[0023] The lithography controller 222 is designed to facilitate control and automation of the processing techniques described herein. The lithography controller 222 can be coupled to or communicate with the processing units 204, the stage 202, and the position sensor 218. The processing units 204 and the position sensor 218 can provide information regarding substrate processing and substrate alignment to the lithography controller 222. For example, the processing units 204 provide information to the lithography controller 222 to inform the lithography controller 222 that substrate processing is complete. The lithography controller 222 facilitates control and automation of the maskless lithography process based on a design file provided by the interface 230. The design file (or computer instructions), sometimes referred to as an imaging design file, readable by the lithography controller 222 determines which tasks should be performed on the substrate. The design file (e.g., design file 420 of FIG. 4) includes mask pattern data. The mask pattern data includes the mask pattern 300 and code for monitoring and controlling processing time and substrate position. Mask pattern 300 corresponds to a pattern that can be written using electromagnetic radiation.

[0024] The packaging substrate 220 is made of any suitable material, for example glass. In other embodiments that can be combined with other embodiments described herein, the packaging substrate 220 is made of other materials that can be used as part of a flat panel display or advanced packaging. The packaging substrate 220 has a film layer formed thereon that is to be patterned, such as by pattern etching, and a photoresist layer 250 formed on the film layer to be patterned that is sensitive to electromagnetic radiation, for example UV, deep UV "light". A positive photoresist includes portions of the photoresist that are respectively soluble in a photoresist developer applied to the photoresist when exposed to radiation after a pattern is written into the photoresist using electromagnetic radiation. After exposure of the photoresist to electromagnetic radiation, the resist is developed to leave the patterned photoresist on the underlying film layer. Then, using the patterned photoresist, the underlying thin film is pattern etched through the openings in the photoresist to form a portion of the packaging circuit.

[0025] The processing unit 204 is supported by a support 208 such that the processing unit 204 straddles one of the track motors 216. The support 208 includes an opening 212 for the track motor 216 and the chuck 214 to pass under the processing unit 204. The processing unit 204 is a pattern generator configured to receive mask pattern data from the interface 230 and expose photoresist in a maskless lithography process using one or more image projection systems 206 operable to project a writing beam of electromagnetic radiation onto the packaging substrate 220. The pattern generated by the processing unit 204 is projected by the image projection system 206 to expose the photoresist of the packaging substrate 220 to the mask pattern, and the mask pattern is written into the photoresist. In one embodiment, which can be combined with other embodiments described herein, each image projection system 206 includes a spatial light modulator for modulating incident light to create a desired image. Each spatial light modulator includes a plurality of electrically addressable elements that can be individually controlled. Each electrically addressable element can be in an "on" or "off" position based on the mask pattern data and the corrections provided by the position correction model created by the digital dynamic connection method 600 described herein. When light reaches the spatial light modulator, the electrically addressable elements in the "on" position project multiple writing beams to a projection lens (not shown). The projection lens then projects the writing beams to the packaging substrate 220. The electrically addressable elements include, but are not limited to, digital micromirrors, liquid crystal displays (LCDs), liquid crystal over silicon (LCoS) devices, ferroelectric liquid crystal on silicon (FLCoS) devices, microshutters, micro LEDs, VCSELs, liquid crystal displays (LCDs), or any solid-state emitter of electromagnetic radiation.

[0026] 2B is a schematic cross-sectional view of a lithography tool according to one or more embodiments of the present disclosure. The lithography tool 200 can be utilized for photolithography or electron beam (e-beam) lithography. The lithography tool 200 includes a source 201 and a stage 202. A packaging substrate 220 is disposed on the stage 202. The stage 202 includes an actuator operable to rotate the packaging substrate 220 to scan the packaging substrate 220 in the X and Y directions.

[0027] Mask 203 is a physical mask and includes one or more apertures 255 that correspond to a mask pattern. Beam 210 is projected by source 201 through the one or more apertures 255 to form a mask pattern in a resist layer 250 disposed over packaging substrate 220. Mask 203 is coupled to an actuator (not shown) for scanning in the X and Y directions to pattern the entire packaging substrate 220. In an embodiment utilizing photolithography, source 201 is a light source and beam 210 is a beam of light.

[0028] 3A is a schematic diagram of a portion of a mask pattern 300 according to one or more embodiments of the present disclosure. FIG. 3B is a cross-sectional view of a layer structure 301 with theoretical die pad locations 306, i.e., expected locations of die pads on a die (not shown), according to one or more embodiments of the present disclosure. The mask pattern 300 can be written into photoresist using the processing unit 204. The mask pattern data includes a via mask pattern 307, a redistribution metal layer (RDL) mask pattern 303, and a die pad mask pattern 305. The via mask pattern 307 includes one or more via locations 302, i.e., expected via locations. The RDL mask pattern 303 includes one or more RDL locations 304. The die pad mask pattern 305 includes one or more theoretical die pad locations 306. Each of the via locations 302 has a center x and y coordinate (x,y) 302Each of the RDL locations 304 has a center x and y coordinate (x,y) 304 Each of the theoretical die pad locations 306 has a center x and y coordinate (x,y) 306 so that the metrology device 104 can perform recipe-based measurements at defined locations before the packaging substrate 220 is processed through the maskless lithography tool 108.

[0029] In layer structure 301, as shown in FIG. 3B, via location 302 is centered over theoretical die pad location 306. RDL location 304 is centered over via location 302. In FIG. 3B, the central x and y coordinates (x,y) of via location 302 are: 302 , and the center x and y coordinates (x,y) of the RDL position 304 304 are the x and y coordinates (x, y) of the theoretical center of the die pad 306 306 is aligned with.

[0030] 4 is a schematic diagram of an interface 230 according to one or more embodiments of the present disclosure. The interface 230 includes a computing device 410 and an input / output (I / O) device 430. The interface 230 can be utilized to at least one of optimize, verify, or update a design file (e.g., design file 420). The interface 230 can be utilized to at least one of optimize, verify, or update the design file 420 per instructions and readable data of a universal metrology file (UMF) provided from one of the pattern generator 102, the metrology device 104, and the controller 110. The optimization, verification, and update of the design file 420 are further described in the operation of the digital dynamic connection method 600.

[0031] The computing device 410 may include a controller 412, a network interface 414, and a memory 416. The controller 412 retrieves and executes programming data stored in the memory 416 and coordinates the operation of other system components. Similarly, the controller 412 stores and retrieves application data residing in the memory 416. The controller 412 may be one or more central processing units (CPUs).

[0032] The memory 416 may store instructions and logic to be executed by the controller 412. Furthermore, the memory 416 may be one or more of a random access memory (RAM) and a non-volatile memory (NVM). The NVM may be a hard disk, a network attached storage (NAS), and a removable storage device, among others. Furthermore, the memory 416 may include a design application 418 and a design file 420.

[0033] The design application 418 at least one of optimizes, verifies, and updates the design data of the design file 420. The design application 418 may be controlled by the controller 412 to optimize and / or update the design data of the design file 420.

[0034] The design file 420 may be stored in the memory 416 and is accessible by the controller 412 and the design application 418. The design file 420 includes mask pattern data that is interpreted by the lithography controller 222 to pattern the photoresist disposed on the packaging substrate 220. The design file 420 may be provided in different formats. For example, the format of the design file 420 may be one of a GDS format and an OASIS format, among others. The mask pattern data of the design file 420 includes the via mask pattern 307, the RDL mask pattern 303, and the die PAD mask pattern 306. Other data included in the design file include exposure dose data, exposure focus data, and inter-image projection system (IPS) calibration data. The exposure dose data corresponds to the dose of the writing beam to be projected on the photoresist. The exposure focus data corresponds to the focus of each of the image projection systems 206. The inter-IPS calibration data corresponds to the stitching of the image projection systems 206 such that the entire mask pattern 300 is projected. The design file 420 may be in the form of a bitmap or similar file.

[0035] The I / O device 430 may include one or more of a keyboard, a display device, a mouse, an audio device, and a touch screen, among others. The I / O device 430 may be utilized to input information to and / or output data from the pattern generator 102. For example, a user may use a keyboard and a pointing device to create and / or adjust elements of the design file 420. In another embodiment, which may be combined with other embodiments described herein, the I / O device 430 is coupled to the controller 110 via a network interface 414 that communicates with the communication link 101. The pattern generator 102 coupled to the controller provides a computer-based computer integrated manufacturing (CIM) procedure to control the overall operation of the digital dynamic connection method 600 described herein.

[0036] 5 is a schematic top view of the packaging substrate 220 prior to a first operation of the digital dynamic connection method 600 described herein. During processing, the theoretical die pad location 306 may be shifted or rotated to a shifted die pad location 306', i.e., the measurement location of the die pad. This shift or rotation may be caused by pick, place, and form. For example, the die pad 306 may be located at the theoretical die pad coordinates (x,y) 306 The x and y coordinates (x,y) shifted from 306’ 5, the theoretical die pad position 306 may shift on the x-axis, on the y-axis, or at any angle in the xy plane to a shifted die pad position 306'.

[0037] 6 is a flow diagram of a digital dynamic connection method 600 according to one or more embodiments of the present disclosure. FIG. 7A is a schematic top view of layer structure 301 after correcting via location 302 to a partially shifted via location 302', i.e., a shifted via location, according to one or more embodiments of the present disclosure. FIG. 7B is a schematic cross-sectional view of layer structure 301 according to one or more embodiments of the present disclosure. In FIG. 7A-7B, die pad 306 is aligned at shifted x and y coordinates (x,y). 306’ The RDL pad location 304 remains the same without shifting. The via 302 is at a shifted die pad location 306' with shifted x and y coordinates (x,y). 302’ 3 to a shifted via position 302' having a

[0038] Operation 610 includes determining the shifted die pad location 306'. In operation 620, a correction factor is calculated. The amount that the via location 302 needs to be shifted is calculated by measuring the amount of correction needed to match the shifted die pad 306' and scaling those corrections down by the correction factor ξ. In some embodiments, the correction factor ξ is greater than 0 and less than 1. The correction factor ξ is calculated according to the following formula:

[0039]

number

[0040] Top overlap OL top is the radius r of the RDL pad 304 and the via radius r 302 In embodiments where the via 302 is tapered, the top surface of the via has a top surface overlap OL top For the calculation of via radius r 302 It is defined as the bottom overlap OL. bot is the die pad radius r 304 and the via radius r 302In embodiments where the via 302 is tapered, the bottom surface of the via is defined as the difference between the bottom overlap OL bot For the calculation of via radius r 302 The available correction range OL is defined as total is the theoretical die pad coordinate (x,y) 306 and the shifted die pad coordinates (x, y) 306’ In one embodiment, the RDL pad radius r 304 is 10 μm, and the via radius r 302 is 5 μm, and the die pad radius r 306 is 15μm. Top overlap OL top is 15μm-5μm=10μm. Bottom overlap OL bot is 20 μm−5 μm=15 μm. The correction coefficient ξ is 10 μm / (10 μm+15 μm)=40%. Therefore, in this embodiment, the variation range of the via pad position 302 is 40%×15 μm=6 μm.

[0041] FIG. 8A is a schematic top view of layer structure 301 without RDL position 304 after correcting via position 302 to fully shifted via position 302″, in accordance with one embodiment of the present disclosure. FIG. 8B is a schematic top view of layer structure 301 without RDL position 304 after correcting via position 302 to partially shifted via position 302′, in accordance with one embodiment of the present disclosure.

[0042] Operation 630 includes correcting the via location 302 and printing the via location 302 to electrically connect the via 302 to the die pad 306. The via location 302 is corrected based on the correction factor ξ and the shifted die pad location 306′. As shown in FIG. 8A , the fully shifted via location 302″ is expressed as the shifted die pad coordinates (x,y) 306’ Coordinates (x,y) to align with 302” As shown in FIG. 8B, the partially shifted via location 302′ has theoretical die pad coordinates (x,y) 306 and the shifted die pad coordinates (x,y) 306’Coordinates (x,y) that lie partially between the coordinates of 302’ In some embodiments, the via locations may be corrected via the maskless lithography tool 108.

[0043] FIG. 9A is a schematic top view of layer structure 301 after correcting via position 302 to a fully shifted via position 302″, according to one embodiment of the present disclosure. FIG. 9B is a schematic top view of layer structure 301 after correcting via position 302 to a partially shifted via position 302′, according to one embodiment of the present disclosure.

[0044] As shown in FIG. 9A, the fully shifted via location 302″ does not overlap the RDL location 304. As shown in FIG. 9B, the partially shifted via location 302′ completely overlaps the RDL location 304. Operation 640 includes developing the substrate for the via layer. Operation 645 includes transferring the substrate 220 from the maskless lithography tool 108 to the lithography tool 200. Operation 650 includes patterning the RDL pad 304 utilizing the mask pattern 300. Since the RDL pad location 304 remains intact, the mask pattern 300 can be utilized to pattern the RDL pad 304. In some embodiments, the lithography tool 200 can be utilized to pattern the RDL pad location 304.

[0045] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope of the disclosure, which scope is determined by the following claims. [Explanation of symbols]

[0046] 100 Lithography System 101 Communication Links 102 Pattern Generator 103 Transport System 104 Measuring Devices 108 Maskless Lithography Tools 110 Controller 112 CPU 114 Support Circuit 116 Memory 200 Lithography Tools 201 Source 202 Stage 203 Mask 204 Processing Unit 206 Image Projection System 208 Support 210 Beam 212 Opening 214 Chuck 216 Truck Motor 218 Position Sensor 220 Packaging Substrate 222 Lithography Controller 230 Interface 250 photoresist layers 255 Open hole 300 Mask Patterns 301 layer structure 302 Via position, via 302' Partially shifted via position 302” fully shifted via position 303 Redistribution metal layer (RDL) mask pattern 304 RDL pad position 305 Die pad mask pattern 306 Theoretical Die Pad Position 306' Shifted die pad position 307 Via Mask Pattern 410 Computing Devices 412 Controller 414 Network Interface 416 Memory 418 Design Applications 420 Design Files 430 Input / Output (I / O) Devices 600 Digital Dynamic Connection Method r302 via radius r304 RDL pad radius r306 Die pad radius

Claims

1. Measuring a location of a die pad of a die disposed on a substrate; determining a die pad shift between an expected location of the die pad and the measured location of the die pad; generating a shifted via location for a via electrically connecting to the die pad using the determined die pad shift and an expected via location; patterning a via at the shifted via location with a maskless lithography tool; utilizing a physical mask in a mask-based lithography tool to pattern a redistribution layer (RDL) pad at the shifted via location, the redistribution layer (RDL) pad being electrically connected to the via patterned using the maskless lithography tool; A method comprising:

2. The method of claim 1 , wherein the shifted via location is calculated using a correction factor.

3. The correction coefficient is expressed by the formula [0010] where OL top is the difference between the radius of the RDL pad and the top radius of the via, and OL bot The method of claim 2 , wherein: is the difference between the die pad radius and the bottom radius of the via.

4. The method of claim 3 , wherein ξ is greater than 0 and less than 1.

5. 2. The method of claim 1, wherein the shifted via location has a top surface area disposed below a surface area of ​​the RDL pad.

6. The method of claim 1 , wherein a bottom area of ​​the shifted via location is disposed above a surface area of ​​the die pad.

7. The method of claim 1 , further comprising transferring the substrate from the maskless lithography tool to a lithography tool.

8. The method of claim 1 , further comprising: updating a design file containing the predicted via locations with the shifted via locations.

9. The method of claim 8 , further comprising transferring the design file to the maskless lithography tool.

10. one or more die pads, each of the one or more die pads including a die pad center point; one or more vias disposed on the one or more die pads, the one or more vias each including a via center point; one or more redistribution metal layer (RDL) pads disposed over the one or more vias, the one or more RDL pads each including an RDL pad center point, the die pad center point, the via center point, and the RDL pad center point are not aligned, and the via center point is disposed between the RDL pad center point and the die pad center point; A layer structure comprising:

11. When executed by the processor, the computer system: Calculating a correction factor, said calculation comprising: Via radius, Redistribution metal layer (RDL) pad radius, and Die Pad Radius a calculating step including: determining one or more shifted die pad coordinates; Shifting one or more via coordinates utilizing the correction factor, each via coordinate being shifted to a shifted via coordinate between a theoretical die pad coordinate and a shifted die pad coordinate of the one or more shifted die pad coordinates; A non-transitory computer-readable medium storing instructions for causing a computer to execute a program.

12. The via radius is the top radius of the via, and the correction factor is expressed by the formula [0025] where OL top is the difference between the radius of the RDL pad and the top radius of the via, and OL bot 12. The non-transitory computer-readable medium of claim 11, wherein: is a difference between the die pad radius and the via bottom radius.

13. 12. The non-transitory computer-readable medium of claim 11, wherein the one or more shifted die pad coordinates are determined using a maskless lithography tool.

14. 12. The non-transitory computer readable medium of claim 11, further comprising transferring a substrate from a maskless lithography tool to a mask-based lithography tool, wherein the vias, the RDL pads, and the die pads are on the substrate.

15. The non-transitory computer-readable medium of claim 13 , further comprising updating a design file with the shifted via coordinates.

16. The non-transitory computer-readable medium of claim 15 , further comprising transferring the design file to the maskless lithography tool.

17. The non-transitory computer-readable medium of claim 11 , wherein the one or more via coordinates are moved using a maskless lithography tool.

18. 12. The non-transitory computer-readable medium of claim 11, further comprising patterning a redistribution layer (RDL) pad electrically connected to the via.

19. 20. The non-transitory computer readable medium of claim 18, wherein the RDL pad is patterned using a mask-based lithography tool.

20. 12. The non-transitory computer-readable medium of claim 11, wherein the shifted via location at the shifted via coordinates has a top surface area disposed below a surface area of ​​the RDL pad.

Images