Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device having a structure that can demonstrate high reliability even when a wafer size is increased, etc., and a method for manufacturing the same.SOLUTION: A semiconductor device comprises: a semiconductor substrate; a semiconductor layer located on the semiconductor substrate and having a drain region, a source region, a drift region, and a channel region; an insulating film in contact with the semiconductor layer and located above the channel region; an interlayer dielectric film covering the insulating film; and a field plate located on the interlayer dielectric film, overlapping the drain region and electrically connected to the drain region.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor layer, a first electrode, a second electrode, a lateral element, and a LOCOS oxide resistive field plate. The first electrode is formed on the surface of the semiconductor layer. The second electrode is formed on the surface of the semiconductor layer at a distance from the first electrode. The lateral element is formed in a region between the first electrode and the second electrode in a surface layer portion of the surface of the semiconductor layer, and is electrically connected to the first electrode and the second electrode. The LOCOS oxide separates each part constituting the lateral element on the surface of the semiconductor layer. The resistive field plate is formed on the LOCOS oxide. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2013 / 0075877 Summary of the Invention [Problem to be solved by the invention]

[0004] In manufacturing semiconductor devices, increasing the wafer size, miniaturizing elements and wiring, etc. are considered from the viewpoints of efficiency and performance improvement, etc. If increasing the wafer size and miniaturizing elements and wiring are implemented while keeping the structure shown in the above Patent Document 1, there is a concern that the reliability of the semiconductor device will decrease due to structural problems.

[0005] An object according to one aspect of the present disclosure is to provide a semiconductor device having a structure that can exhibit high reliability even when the wafer size is increased, and a manufacturing method thereof. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate, a semiconductor layer located on the semiconductor substrate and having a drain region, a source region, a drift region, and a channel region, an insulating film in contact with the semiconductor layer and located on the channel region, an interlayer insulating film covering the insulating film, and a field plate located on the interlayer insulating film, overlapping the drift region, and electrically connected to the drain region.

[0007] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes the steps of forming a semiconductor layer on a semiconductor substrate, the semiconductor layer having a drain region, a source region, a drift region, and a channel region, forming an insulating film in contact with the semiconductor layer and located on the channel region, forming an interlayer insulating film covering the insulating film, forming a field plate located on the interlayer insulating film and overlapping the drift region, forming a second interlayer insulating film covering the field plate, forming a first opening in the interlayer insulating film and the second interlayer insulating film, forming a second opening in the second interlayer insulating film exposing the field plate, and forming a first contact filled in the first opening and a second contact filled in the second opening.

[0008] A method for manufacturing a semiconductor device according to yet another aspect of the present disclosure includes the steps of forming a semiconductor layer on a semiconductor substrate, the semiconductor layer having a drain region, a source region, a drift region, and a channel region; forming an insulating film in contact with the semiconductor layer and located on the channel region; forming an interlayer insulating film covering the insulating film; forming a first opening in the interlayer insulating film; forming a contact filled in the first opening and a conductive layer located on the interlayer insulating film; forming a resistive layer covering the interlayer insulating film, the contact, and the conductive layer and including chromium silicide; and patterning the resistive layer to form a field plate having a covering portion covering the conductive layer.

[0009] The semiconductor device and the manufacturing method thereof can exhibit high reliability even when the wafer size is increased. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing a chip of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is an enlarged plan view of region II shown in FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view of region III shown in FIG. [Figure 4] FIG. 4 is a circuit diagram showing the electrical structure within the transistor region. [Figure 5A] FIG. 5A is a view for explaining a method for manufacturing a main part of the semiconductor device according to the first embodiment. [Figure 5B] FIG. 5B is a view for explaining a method for manufacturing a main part of the semiconductor device according to the first embodiment. [Figure 5C] FIG. 5C is a view for explaining a method for manufacturing a main part of the semiconductor device according to the first embodiment. [Figure 5D] FIG. 5D is a view for explaining a method for manufacturing a main part of the semiconductor device according to the first embodiment. [Figure 5E] FIG. 5E is a view for explaining a method for manufacturing a main part of the semiconductor device according to the first embodiment. [Figure 5F] FIG. 5F is a view for explaining a method for manufacturing a main part of the semiconductor device according to the first embodiment. [Figure 5G] FIG. 5G is a view for explaining a method for manufacturing a main part of the semiconductor device according to the first embodiment. [Figure 5H] FIG. 5H is a view for explaining a method for manufacturing a main part of the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view of a main part of a semiconductor device according to a modified example of the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view of a main part of a semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view of region VIII shown in FIG. [Figure 9A]FIG. 9A is a view for explaining a method for manufacturing a main part of a semiconductor device according to the second embodiment. [Figure 9B] FIG. 9B is a view for explaining a method for manufacturing a main part of the semiconductor device according to the second embodiment. [Figure 9C] FIG. 9C is a view for explaining a method for manufacturing a main part of the semiconductor device according to the second embodiment. [Figure 9D] FIG. 9D is a view for explaining a method for manufacturing a main part of the semiconductor device according to the second embodiment. [Figure 9E] FIG. 9E is a view for explaining a method for manufacturing a main part of the semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view of a main part of a semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, the same elements or elements having the same functions will be designated by the same reference numerals, and duplicated descriptions will be omitted. In this specification, the term "same" and similar words are not limited to "completely same". In addition, since the drawings are intended to conceptually explain the embodiments, the dimensions and ratios of each component shown may differ from the actual ones.

[0012] (First embodiment) FIG 1 is a plan view showing a chip of a semiconductor device according to a first embodiment. FIG 2 is an enlarged view of region II shown in FIG 1. FIG 3 is a schematic cross-sectional view of region III shown in FIG 2. As shown in FIG 1, a semiconductor device 1A includes a silicon chip 2 (semiconductor chip) having a rectangular parallelepiped shape. The chip 2 is one of a number of devices formed on a silicon wafer having a diameter of, for example, 300 mm (about 12 inches).

[0013] The chip 2 has a pair of main surfaces, a first main surface 3 and a second main surface 4, and a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D that connect the first main surface 3 and the second main surface 4. In the following, the extension direction of the first side surface 5A and the second side surface 5B in a plan view is defined as a first direction X, the extension direction of the third side surface 5C and the fourth side surface 5D in a plan view is defined as a second direction Y, and the normal direction of the first main surface 3 and the second main surface 4 is defined as a third direction Z. The second direction Y is a direction that intersects with the first direction X in a plan view, and the third direction Z corresponds to the thickness direction of the chip 2.

[0014] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed from the third direction Z, but are not limited to this. In the first embodiment, the first main surface 3 is the top surface, and the second main surface 4 is the bottom surface. For this reason, a configuration located near the first main surface 3 in the third direction Z corresponds to a configuration located on the top surface side (upper side) of the semiconductor device 1A, and a configuration located near the second main surface 4 in the third direction Z corresponds to a configuration located on the bottom surface side (lower side) of the semiconductor device 1A.

[0015] The semiconductor device 1A includes a first semiconductor region 6 located in an upper region in the chip 2. The first semiconductor region 6 is a region having a first conductivity type and has a layer shape extending along the first main surface 3. For this reason, the first semiconductor region 6 is sometimes also called a semiconductor layer. The first semiconductor region 6 is at least a part of an epitaxial semiconductor layer. The first semiconductor region 6 is exposed from the first main surface 3 and the first side surface 5A, the second side surface 5B, the third side surface 5C, and the fourth side surface 5D. The thickness of the first semiconductor region 6 is, for example, 5 μm or more and 20 μm or less. In the first embodiment, the first conductivity type is n-type.

[0016] The semiconductor device 1A includes a second semiconductor region 7 located in a lower region within the chip 2. The second semiconductor region 7 is a region having a second conductivity type and fixed to a predetermined potential, and has a layer shape extending along the second main surface 4. The second semiconductor region 7 is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In the first embodiment, the second semiconductor region 7 is fixed to a back gate potential. The back gate potential may be a reference potential that serves as a reference for circuit operation, or may be a ground potential. In the first embodiment, the second conductivity type is p-type.

[0017] The second semiconductor region 7 is connected to the first semiconductor region 6. The thickness of the second semiconductor region 7 may be 50 μm or more and 400 μm or less. The second semiconductor region 7 is at least a part of a p-type semiconductor substrate. That is, the chip 2 has the first semiconductor region 6 included in an epitaxial semiconductor layer, and the second semiconductor region 7 included in a semiconductor substrate. In other words, the chip 2 has a layered structure including a semiconductor substrate and an epitaxial semiconductor layer located on the semiconductor substrate.

[0018] The semiconductor device 1A includes a plurality of device regions 8 defined on the first main surface 3. In the semiconductor device 1A, the number and arrangement of the plurality of device regions 8 are determined appropriately. Each of the plurality of device regions 8 includes a functional device formed by utilizing regions inside and outside the chip 2. The functional device includes, for example, at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional device may include a circuit network in which at least two of the semiconductor switching device, the semiconductor rectifying device, and the passive device are combined.

[0019] The semiconductor switching device may include at least one of a metal insulator semiconductor field effect transistor (MISFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a JFET. The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse.

[0020] The multiple device regions 8 include at least one transistor region 9. The transistor region 9 includes a FET structure 10. In the first embodiment, the FET structure 10 has a so-called LDMISFET (Lateral Double Diffused MISFET) structure. The FET structure 10 is, for example, a high-voltage device to which a drain voltage of 800 V or more can be applied in an off state. The structure of the transistor region 9 will be described below.

[0021] 2 and 3, the semiconductor device 1A includes a p-type separation region 11, which is an example of a region separation structure. The separation region 11 is a region that defines the transistor region 9 on the first main surface 3. The separation region 11 has a ring shape that surrounds a part of the first main surface 3 in a plan view, and defines the transistor region 9. The separation region 11 electrically isolates the transistor region 9 from other regions (device region 8).

[0022] In the first embodiment, the separation region 11 has a substantially rectangular ring shape in a plan view. In a plan view, the transistor region 9 is located inside the separation region 11. As shown in FIG. 3, the separation region 11 extends in the third direction Z from the first main surface 3 to the second semiconductor region 7 via the first semiconductor region 6. In other words, the separation region 11 is provided in both the first semiconductor region 6 and the second semiconductor region 7. Therefore, the separation region 11 is electrically connected to the second semiconductor region 7. The separation region 11 is fixed to the potential of the second semiconductor region 7 (e.g., the back gate potential).

[0023] The isolation region 11 includes a first isolation region 12, a second isolation region 13, and a third isolation region 14. The first isolation region 12 is provided in both the first semiconductor region 6 and the second semiconductor region 7. Therefore, a part of the first isolation region 12 is provided in the boundary between the first semiconductor region 6 and the second semiconductor region 7. The first isolation region 12 is spaced apart from both the first main surface 3 and the second main surface 4, and is electrically connected to the second semiconductor region 7. The p-type impurity concentration of the first isolation region 12 is higher than the p-type impurity concentration of the second semiconductor region 7. The second isolation region 13 is a region provided in the first semiconductor region 6 between the first main surface 3 and the first isolation region 12, and is electrically connected to the first isolation region 12. The p-type impurity concentration of the second isolation region 13 is, for example, lower than the p-type impurity concentration of the first isolation region 12. The third isolation region 14 is a region that constitutes a part of the first main surface 3, and is surrounded by the second isolation region 13 in a plan view. The third isolation region 14 is in contact with the second isolation region 13. Therefore, the third isolation region 14 is electrically connected to the first isolation region 12 via the second isolation region 13. The p-type impurity concentration of the third isolation region 14 is higher than the p-type impurity concentration of the second isolation region 13, for example.

[0024] The transistor region 9 includes an n-type impurity region 15 located in the first semiconductor region 6, an n-type well region 16, and an n-type drain region 17.

[0025] In the first embodiment, the impurity region 15 is a part of the portion of the first semiconductor region 6 that is partitioned by the separation region 11. The n-type impurity concentration of the impurity region 15 is equal to the n-type impurity concentration of the first semiconductor region 6, for example.

[0026] The well region 16 and the drain region 17 are provided above the first semiconductor region 6. The well region 16 surrounds the drain region 17 in a plan view and is in contact with at least a bottom portion of the drain region 17. Therefore, the potential of the well region 16 and the potential of the drain region 17 are fixed to an equal potential (drain potential). In a plan view, the drain region 17 is spaced apart from the periphery of the well region 16. In other words, in a plan view, the drain region 17 is located inside the periphery of the well region 16. The drain region 17 constitutes a part of the first main surface 3. The n-type impurity concentration of the well region 16 is higher than the n-type impurity concentration of the impurity region 15. Also, the n-type impurity concentration of the drain region 17 is higher than the n-type impurity concentration of the well region 16.

[0027] In the first embodiment, the well region 16 has an elliptical shape extending along the impurity region 15 in a plan view, but is not limited to this. The well region 16 may have a circular, elliptical, or polygonal shape (e.g., a rectangular shape) in a plan view. In the first embodiment, the drain region 17 has an elliptical shape in a plan view similar to the well region 16, but is not limited to this. The drain region 17 may have a circular, elliptical, or polygonal shape (e.g., a rectangular shape) in a plan view.

[0028] The semiconductor device 1A includes an n-type buried region 18 located inside the chip 2. The buried region 18 is provided in both the first semiconductor region 6 and the second semiconductor region 7. Therefore, a part of the buried region 18 is provided at the boundary between the first semiconductor region 6 and the second semiconductor region 7. The n-type impurity concentration of the buried region 18 is higher than the n-type impurity concentration of the impurity region 15. The n-type impurity concentration of the buried region 18 may be higher than the n-type impurity concentration of the well region 16. The buried region 18 is provided at a position separated from the well region 16. Therefore, a part of the impurity region 15 is located between the buried region 18 and the well region 16 in the third direction Z. In a plan view, the buried region 18 is provided, for example, inside the periphery of the well region 16. In this case, the buried region 18 does not need to overlap the periphery of the well region 16 in a plan view. The area of ​​the buried region 18 in a plan view may be smaller than the area of ​​the well region 16.

[0029] The semiconductor device 1A includes a p-type body region 19 located between the isolation region 11 and the well region 16 in a plan view. Like the isolation region 11, the body region 19 extends in the third direction Z from the first main surface 3 to the second semiconductor region 7 via the first semiconductor region 6. In other words, the body region 19 is provided in both the first semiconductor region 6 and the second semiconductor region 7. For this reason, the body region 19 is electrically connected to the second semiconductor region 7 and is fixed to the potential of the second semiconductor region 7 (for example, the back gate potential). In the first embodiment, the body region 19 includes a first body region 20 and a second body region 21.

[0030] The first body region 20 is provided in both the first semiconductor region 6 (impurity region 15) and the second semiconductor region 7. Therefore, a part of the first body region 20 is provided in the boundary between the first semiconductor region 6 and the second semiconductor region 7. The first body region 20 is separated from both the first main surface 3 and the second main surface 4, and is electrically connected to the second semiconductor region 7. The p-type impurity concentration of the first body region 20 is higher than the p-type impurity concentration of the second semiconductor region 7. The second body region 21 is a region provided in the first semiconductor region 6, in a region between the first main surface 3 and the first body region 20, and is electrically connected to the first body region 20. The p-type impurity concentration of the second body region 21 is, for example, lower than the p-type impurity concentration of the first body region 20.

[0031] In the first embodiment, the body region 19 is located inside the isolation region 11 in a plan view and has an oval ring shape surrounding the well region 16 and the drain region 17. In a plan view, the body region 19 is partitioned into a first region 19A, a second region 19B, a third region 19C, and a fourth region 19D. The first region 19A, the second region 19B, the third region 19C, and the fourth region 19D are formed by a first body region 20 and a second body region 21, respectively.

[0032] The first region 19A and the second region 19B are each a strip-shaped portion extending along the second direction Y in a plan view and extend parallel to each other. The first region 19A and the second region 19B are provided such that the drain region 17 is located between the first region 19A and the second region 19B in the first direction X in a plan view. In the second direction Y, the length of the first region 19A and the length of the second region 19B may each be equal to or shorter than the length of the drain region 17.

[0033] The third region 19C is a band-shaped portion connecting one end of the first region 19A in the second direction Y and one end of the second region 19B in the second direction Y. In the first embodiment, the third region 19C extends in an arc-shaped band shape between one end of the first region 19A and one end of the second region 19B in a plan view, but is not limited to this. The third region 19C may extend along the first direction X.

[0034] The fourth region 19D is a band-shaped portion connecting the other end of the first region 19A in the second direction Y and the other end of the second region 19B in the second direction Y. In the first embodiment, the fourth region 19D extends in an arc band shape between the other end of the first region 19A and the other end of the second region 19B in a plan view, but is not limited to this. The fourth region 19D may extend along the first direction X.

[0035] The semiconductor device 1A includes a source region 22 provided in the body region 19. In the first embodiment, the semiconductor device 1A includes a plurality of source regions 22, but is not limited thereto. Each of the plurality of source regions 22 is an n-type region and is fixed to a source potential. Specifically, a source potential is applied to each of the plurality of source regions 22 from the outside of the chip 2. Therefore, the source potential is applied to each of the plurality of source regions 22 independently of the back gate potential. The source potential may be a reference potential, a ground potential, or a potential other than these. The n-type impurity concentration of the source region 22 is higher than the n-type impurity concentration of the well region 16. The n-type impurity concentration of the source region 22 may be equal to the n-type impurity concentration of the drain region 17.

[0036] Each of the source regions 22 has a band shape in a plan view and is located in the body region 19 and inside the periphery of the body region 19. Each of the source regions 22 constitutes a part of the first main surface 3, that is, a part of the surface layer of the body region 19. A part of the source regions 22 is located in the first region 19A. Each end of the part in the second direction Y is located inside the each end of the first region 19A in the second direction Y, but is not limited to this. The other part of the source regions 22 is located in the second region 19B. Each end of the other part in the second direction Y is located inside the each end of the second region 19B in the second direction Y, but is not limited to this. In the first embodiment, none of the source regions 22 is located in the third region 19C or the fourth region 19D, but is not limited to this. In the second direction Y, the length of each source region 22 is, for example, equal to or less than the length of the drain region 17.

[0037] When one source region 22 is located in the body region 19, the source region 22 is located in at least one of the first region 19A, the second region 19B, the third region 19C, and the fourth region 19D of the body region 19. When the one source region 22 is located in all of the first region 19A, the second region 19B, the third region 19C, and the fourth region 19D, the source region 22 may have, for example, an oval ring shape surrounding the impurity region 15.

[0038] The semiconductor device 1A includes an n-type drift region 23 located between the drain region 17 and the source region 22 and in a surface layer portion of the impurity region 15. The drift region 23 is located in a region between the drain region 17 and the body region 19, and forms a current path connecting the drain region 17 and the source region 22. The drift region 23 has, for example, an oval ring shape surrounding the drain region 17 in a plan view. In the first embodiment, the drift region 23 has a first portion (straight portion) extending in the second direction Y so as to be parallel to the first region 19A and the second region 19B, and a second portion (arc portion) extending in an arc shape so as to be parallel to the third region 19C and the fourth region 19D. The drift region 23 forms a current path in a portion along the first region 19A and the second region 19B, but does not form a current path in a portion along the third region 19C and the fourth region 19D.

[0039] The width of the drift region 23 is, for example, not less than 50 μm and not more than 200 μm. The width of the drift region 23 corresponds to the distance between the drain region 17 and the body region 19, and is, for example, approximately constant along the elliptical ring shape. The width of the arc portion of the drift region 23 may increase from the straight portion toward the center of the arc. On the other hand, the width of the straight portion of the drift region 23 may be approximately constant.

[0040] The semiconductor device 1A includes a p-type channel region 24 located between the drain region 17 and the source region 22 and in a surface layer portion of the impurity region 15. The channel region 24 is located between the drift region 23 and the source region 22. Therefore, the drift region 23 is located closer to the drain region 17 than the channel region 24, and the channel region 24 is located closer to the source region 22 than the drift region 23. The channel region 24 controls the conduction and non-conduction of the current path between the drain region 17 and the source region 22.

[0041] The semiconductor device 1A includes a back-gate region 25 located in a surface layer portion of the first main surface 3. In the first embodiment, the semiconductor device 1A includes a plurality of back-gate regions 25, but is not limited thereto. Each of the plurality of back-gate regions 25 is a p-type region and is fixed to a back-gate potential. That is, the back-gate potential is applied to the plurality of back-gate regions 25 independently of the source potential. In the first embodiment, each of the plurality of back-gate regions 25 is specifically located in a region different from the source region 22 in the surface layer portion of the body region 19. The p-type impurity concentration of the back-gate region 25 is higher than the p-type impurity concentration of the body region 19.

[0042] In the first embodiment, each of the back gate regions 25 has a band shape in a plan view and is located in the body region 19 and inside the periphery of the body region 19. Each of the back gate regions 25 constitutes a part of the first main surface 3, that is, a part of the surface layer of the body region 19. Each of the back gate regions 25 is located between the corresponding source region 22 and the periphery of the body region 19 in a plan view. Each of the back gate regions 25 is separated from the periphery of the body region 19, but is not limited to this. A part of the back gate regions 25 is located in the first region 19A. Each end of the part in the second direction Y is located inside each end of the first region 19A in the second direction Y, but is not limited to this. The other part of the back gate regions 25 is located in the second region 19B. Each end of the other part in the second direction Y is located inside each end of the second region 19B in the second direction Y, but is not limited to this. In the first embodiment, none of the back gate regions 25 is located in the third region 19C or the fourth region 19D, but this is not limited to this. In the second direction Y, the length of each back gate region 25 is, for example, equal to or less than the length of the drain region 17.

[0043] Each of the back gate regions 25 is located between the corresponding source region 22 and the periphery of the body region 19 in a plan view. Each of the back gate regions 25 is adjacent to the corresponding source region 22 in a plan view. Therefore, in the surface layer portion of the body region 19, the source region 22 fixed to the source potential and the back gate region 25 fixed to the back gate potential coexist.

[0044] When one back-gate region 25 is located in the body region 19, the back-gate region 25 is located in at least one of the first region 19A, the second region 19B, the third region 19C, and the fourth region 19D of the body region 19. When the one back-gate region 25 is located in all of the first region 19A, the second region 19B, the third region 19C, and the fourth region 19D, the back-gate region 25 may have, for example, an oval ring shape surrounding the impurity region 15.

[0045] The semiconductor device 1A includes an insulating film 30 that selectively covers the first main surface 3 in the transistor region 9. The insulating film 30 includes silicon oxide. The insulating film 30 is a LOCOS film (Local oxidation of silicon film) formed by selective oxidation of the first main surface 3, a buried oxide film (STI: Shallow Trench Isolation) that fills a shallow trench provided in the first main surface 3, or the like. From the viewpoint of preventing warping of the semiconductor device 1A, the insulating film 30 has a thickness of, for example, 100 nm or more and 300 nm or less. The insulating film 30 selectively covers the first main surface 3 so as to expose the isolation region 11, the drain region 17, the source region 22, and the backgate region 25. In a plan view, the insulating film 30 covers the drift region 23, but does not cover at least a part of the channel region 24, at least a part of the isolation region 11, at least a part of the source region 22, or at least a part of the backgate region 25. Therefore, at least a part of the channel region 24, at least a part of the isolation region 11, at least a part of the source region 22, and at least a part of the back gate region 25 are exposed from the insulating film 30. Moreover, the insulating film 30 covers the region outside the transistor region 9.

[0046] The insulating film 30 has a portion covering the region between the drain region 17 and the source region 22 on the first main surface 3. This portion is located, for example, on the drift region 23 in the impurity region 15 and has an oval ring shape surrounding the drain region 17 in a plan view. In addition, the insulating film 30 has a portion covering the region between the isolation region 11 and the source region 22 on the first main surface 3. This portion is located in the region between the isolation region 11 and the body region 19 and has a ring shape surrounding the body region 19.

[0047] The semiconductor device 1A includes a gate insulating film 36 that is in contact with the first semiconductor region 6 and located on the channel region 24. A portion of the gate insulating film 36 overlaps the insulating film 30. The thickness of the gate insulating film 36 is less than that of the insulating film 30, and is, for example, 10 nm or more and 200 nm or less. The gate insulating film 36 has a single-layer structure or a multilayer structure, and includes, for example, a silicon oxide film. In the first embodiment, the gate insulating film 36 has an oval ring shape surrounding the insulating film 30 in a plan view. The gate insulating film 36 covers a portion of the drift region 23 and a portion of the body region 19. In the first embodiment, the gate insulating film 36 covers a portion of the second body region 21 and a portion of the source region 22.

[0048] The semiconductor device 1A includes a gate electrode 37 located on a gate insulating film 36. The gate electrode 37 includes, for example, a metal film, an alloy film, conductive polysilicon, etc. When the gate electrode 37 includes conductive polysilicon, the conductive polysilicon includes at least one of an n-type region and a p-type region. The gate electrode 37 overlaps not only the channel region 24 but also the drift region 23 in the third direction Z. The gate electrode 37 has an oval ring shape extending along the channel region 24 in a plan view, but is not limited to this. The gate electrode 37 has an extraction portion 38 that is extracted from the gate insulating film 36 onto the insulating film 30. The extraction portion 38 has an oval ring shape surrounding a field electrode 31 described later in a plan view. Moreover, the entire gate electrode 37 is located outside the field electrode 31 described later in a plan view.

[0049] The gate electrode 37 includes an inner edge portion 37a and an outer edge portion 37b. The inner edge portion 37a is formed by an extension portion 38. The outer edge portion 37b is located in a region overlapping the body region 19 in a plan view. In the first embodiment, the width of the gate electrode 37 is non-uniform along the circumferential direction, but is not limited to this. Specifically, the gate electrode 37 has a gate extension portion 37c that extends toward the drain region 17 at the outer edge portion 37b (extension portion 38). The gate extension portion 37c is a portion that is provided according to the shape of the field electrode 31 described later. By providing the gate extension portion 37c, the distance between the gate electrode 37 and the field electrode 31 is maintained approximately constant in a plan view.

[0050] The semiconductor device 1A includes an insulating layer 40 covering a plurality of device regions 8 on the first main surface 3. The insulating layer 40 has a laminated structure including a plurality of interlayer insulating films 41 stacked on top of each other. The number of stacked interlayer insulating films 41 is arbitrary and is not limited to a specific value. The insulating layer 40 may include three or more interlayer insulating films 41. FIG. 3 shows a first interlayer insulating film 41A, a second interlayer insulating film 41B, and a third interlayer insulating film 41C among the plurality of interlayer insulating films 41.

[0051] The first interlayer insulating film 41A, the second interlayer insulating film 41B, and the third interlayer insulating film 41C are stacked in order in the third direction Z. The first interlayer insulating film 41A covers the first main surface 3, the insulating film 30, the gate insulating film 36, and the gate electrode 37. The thickness of the first interlayer insulating film 41A is determined according to the function required of the field electrode 31 described later and the thickness of the insulating film 30. In the first embodiment, the thickness of the first interlayer insulating film 41A is 200 nm or more and 800 nm or less. The second interlayer insulating film 41B covers the first interlayer insulating film 41A, and the third interlayer insulating film 41C covers the second interlayer insulating film 41B. Each of the first interlayer insulating film 41A, the second interlayer insulating film 41B, and the third interlayer insulating film 41C includes at least one of a silicon oxide film and a silicon nitride film. Therefore, each of first interlayer insulating film 41A, second interlayer insulating film 41B, and third interlayer insulating film 41C may have a single-layer structure or a multilayer structure.

[0052] As shown in FIG. 3, the semiconductor device 1A includes a field electrode 31 (field plate) located on the first interlayer insulating film 41A in the transistor region 9. The field electrode 31 has a function of suppressing disturbance of the electric field in the first semiconductor region 6 and the like, a function of suppressing local electric field concentration, a function of monitoring a high drain-gate voltage Vdg, and the like, and is a high-resistance film connected to the drain region 17 and the backgate region 25. The field electrode 31 overlaps the drift region 23 and a portion of the insulating film 30 located on the drift region 23 in the third direction Z. In the first embodiment, the field electrode 31 does not overlap the channel region 24 in the third direction Z. The field electrode 31 includes, for example, polysilicon. The field electrode 31 is not electrically connected to the source region 22. The field electrode 31 forms a potential gradient from the drain region 17 toward the backgate region 25. By providing such a field electrode 31, bias in the electric field distribution in the drift region 23 is suppressed. The thickness of the field electrode 31 is, for example, not less than 50 nm and not more than 100 nm.

[0053] The field electrode 31 is routed in a line shape on the first interlayer insulating film 41A. When a straight line is defined connecting the drain region 17 and the back gate region 25 in a plan view, the field electrode 31 extends so as to cross the straight line multiple times. For example, the field electrode 31 surrounds the drain region 17 multiple times in a concentric manner in a plan view. In the first embodiment, the field electrode 31 has a spiral shape surrounding the drain region 17 in a plan view.

[0054] The field electrode 31 has a first end 32 located near the drain region 17, a second end 33 located near the body region 19, and a spiral portion 34 extending between the first end 32 and the second end 33. The location of the first end 32 and the second end 33 is arbitrary.

[0055] The first end 32 is a connection part electrically connected to the drain region 17, and is the part (innermost periphery) located on the innermost side of the field electrode 31. The potential applied to the first end 32 is the drain potential or a potential in the vicinity thereof. The first end 32 overlaps the well region 16 in the third direction Z, but is not limited to this. The second end 33 is a connection part electrically connected to the back gate region 25, and is the part (outermost periphery) located on the outermost side of the field electrode 31. The potential applied to the second end 33 is the back gate potential or a potential in the vicinity thereof. The second end 33 overlaps the drift region 23 in the third direction Z, but is not limited to this. The spiral part 34 is a part (connection part) that connects the first end 32 and the second end 33, and is wound in an elliptical spiral shape from the first end 32 to the second end 33 so as to surround the drain region 17 in a plan view. The spiral part 34 overlaps the drift region 23 in the third direction Z. A portion of the spiral portion 34 may overlap the well region 16 .

[0056] The field electrode 31 forms a potential gradient in the spiral direction from the first end 32 to the second end 33. The field electrode 31 also forms a potential gradient in a direction perpendicular to the spiral direction that gradually decreases according to the winding pitch of the spiral portion 34 from the drain region 17 to the backgate region 25. The field electrode 31 thins out the electric field in the drift region 23, suppressing bias in the electric field distribution in the drift region 23.

[0057] The field electrode 31 may have a line width of 1 μm or more and 5 μm or less. The line width is defined by the width in a direction perpendicular to the extension direction (i.e., the spiral direction) of the field electrode 31. The field electrode 31 may have a resistance value of 10 MΩ or more and 100 MΩ or less. The field electrode 31 may be formed with a substantially constant line width in the straight portion and the arc portion. In addition, when the width of the drift region 23 gradually increases toward the center of the arc, the line width of the field electrode 31 may gradually increase from the straight portion toward the center of the arc.

[0058] The pitch of the field electrode 31 may be 1 μm or more and 10 μm or less. The pitch of the field electrode 31 is defined by the distance between adjacent line portions (i.e., the winding pitch of the spiral portion 34). The number of turns of the field electrode 31 may be 5 to 100, or 25 to 75.

[0059] The semiconductor device 1A includes an inner field electrode 35 located on the first interlayer insulating film 41A and connected to the field electrode 31. The inner field electrode 35 is located closer to the drain region 17 than the field electrode 31 in a plan view. In the first embodiment, the inner field electrode 35 is located in a region surrounded by the field electrode 31 in a plan view. The potential of the inner field electrode 35 is fixed to the drain potential. The inner field electrode 35 may be a part of the field electrode 31. In this case, the inner field electrode 35 functions as the innermost part of the field electrode 31. The inner field electrode 35 includes, for example, the same material as the field electrode 31 (i.e., conductive polysilicon).

[0060] The inner field electrode 35 is disposed at a position spaced apart from the drain region 17 in a plan view. In the first embodiment, the inner field electrode 35 has an oval ring shape surrounding the drain region 17. The inner field electrode 35 overlaps the well region 16 in the third direction Z. The inner field electrode 35 includes an inner edge portion 35a and an outer edge portion 35b. The inner edge portion 35a is provided, for example, at a position spaced apart from the drain region 17 in a plan view. The outer edge portion 35b is provided, for example, at a position spaced apart from the spiral portion 34 of the field electrode 31. The distance between the inner field electrode 35 and the spiral portion 34 is, for example, equal to the pitch of the field electrode 31.

[0061] In the first embodiment, the width of the innerfield electrode 35 is non-uniform along the circumferential direction. The innerfield electrode 35 has a protruding portion 35c at the outer edge portion 35b. The protruding portion 35c protrudes toward the field electrode 31 so as to contact the first end 32 of the field electrode 31. From the viewpoint of suppressing the bias of the electric field caused by the first end 32 of the field electrode 31, the protruding portion 35c keeps the distance between the innerfield electrode 35 and the field electrode 31 substantially constant. The protruding portion 35c is connected to the first end 32, but is not limited thereto. In other words, the innerfield electrode 35 does not need to be connected to the first end 32 as long as it is fixed to the same potential as the first end 32. Therefore, the protruding portion 35c may face the tip of the first end 32 in the spiral direction. The presence or absence of the innerfield electrode 35 is optional. Therefore, the innerfield electrode 35 may not be provided as necessary.

[0062] The width of the innerfield electrode 35 is, for example, 1 μm or more and 15 μm or less. The innerfield electrode 35 may be formed wider than the field electrode 31. In this case, the width of the innerfield electrode 35 is, for example, 1.5 times or more and 5 times or less the width of the field electrode 31. The width of the innerfield electrode 35 may be equal to or less than the line width of the field electrode 31.

[0063] The semiconductor device 1A includes a drain wiring 42 electrically connected to the drain region 17 and the first end 32 of the field electrode 31. The drain wiring 42 is selectively routed within the insulating layer 40. The drain wiring 42 applies a drain potential to the drain region 17 and the first end 32 of the field electrode 31. The drain wiring 42 forms a multi-layer wiring within the insulating layer 40, for example.

[0064] In the first embodiment, the drain wiring 42 includes a first drain wiring 43, a second drain wiring 44, first drain via electrodes 45A and 45B, and a second drain via electrode 46. The first drain wiring 43 overlaps the drain region 17, the first end 32 of the field electrode 31, and the inner field electrode 35 in the third direction Z, and is located on the second interlayer insulating film 41B. The first drain wiring 43 may overlap the entire drain region 17, the entire first end 32, and the entire inner field electrode 35 in the third direction Z. The first drain wiring 43 includes a first portion 43A that overlaps the drain region 17 in the third direction Z, and a second portion 43B that overlaps the first end 32 of the field electrode 31 in the third direction Z. The first portion 43A and the second portion 43B may be separated from each other as long as they are fixed to the same potential.

[0065] The second drain wiring 44 overlaps the first drain wiring 43 in the third direction Z, and is located on the third interlayer insulating film 41C. In the third direction Z, the second drain wiring 44 may overlap the inner field electrode 35, or the first end 32 of the field electrode 31, or the second drain wiring 44 may overlap the spiral portion 34 of the field electrode 31. The thickness of the second drain wiring 44 may be greater than the thickness of the first drain wiring 43.

[0066] The first drain via electrode 45A is located between the drain region 17 and the first drain wiring 43 in the third direction Z, and connects the drain region 17 and the first drain wiring 43. The first drain via electrode 45A is embedded in an opening provided in the second interlayer insulating film 41B. The first drain via electrode 45B is located between the first end 32 of the field electrode 31 and the first drain wiring 43 in the third direction Z, and connects the first end 32 and the first drain wiring 43. The first drain via electrode 45B is embedded in an opening provided in the first interlayer insulating film 41A and the second interlayer insulating film 41B. The first drain via electrode 45A may be located between the inner field electrode 35 and the first drain wiring 43 in the third direction Z, and electrically connect the inner field electrode 35 to the first drain wiring 43. The second drain via electrode 46 is located between the first drain wiring 43 and the second drain wiring 44 in the third direction Z, and connects the first drain wiring 43 and the second drain wiring 44 to each other.

[0067] The semiconductor device 1A includes a source wiring 47 electrically connected to the source region 22. The source wiring 47 is selectively routed within the insulating layer 40. The source wiring 47 is electrically insulated from the drain wiring 42 and the back gate region 25. The source wiring 47 applies a source potential to the source region 22. The source wiring 47 forms a multi-layer wiring within the insulating layer 40.

[0068] The source wiring 47 includes a first source wiring 48, a second source wiring 49, a first source via electrode 50, and a second source via electrode 51. The first source wiring 48 overlaps the source region 22 in the third direction Z and is located on the second interlayer insulating film 41B. The first source wiring 48 may overlap the entire source region 22 in the third direction Z. The first source wiring 48 does not have to overlap the back gate region 25 in the third direction Z.

[0069] The second source wiring 49 is disposed on the second interlayer insulating film 41B so as to face the first source wiring 48 in the third direction Z. The second source wiring 49 may overlap the entire area of ​​the source region 22 in the third direction Z. The second source wiring 49 may overlap the gate electrode 37 and the second end 33 of the inner field electrode 35 in the third direction Z. The second source wiring 49 may overlap a part of the spiral portion 34 of the inner field electrode 35 in the third direction Z. The thickness of the second source wiring 49 may be equal to or greater than the thickness of the first source wiring 48.

[0070] The first source via electrode 50 is located between the source region 22 and the first source wiring 48 in the third direction Z, and is connected to the source region 22 and the first source wiring 48. The second source via electrode 51 is located between the first source wiring 48 and the second source wiring 49 in the third direction Z, and is connected to the first source wiring 48 and the second source wiring 49.

[0071] The semiconductor device 1A includes a back gate wiring 52 electrically connected to the back gate region 25 and the second end 33 of the field electrode 31. The back gate wiring 52 is selectively routed within the insulating layer 40. The back gate wiring 52 is electrically insulated from the source wiring 47. In the first embodiment, the back gate wiring 52 is also electrically connected to the isolation region 11. The back gate wiring 52 forms a multi-layer wiring within the insulating layer 40.

[0072] The back gate wiring 52 includes a first back gate wiring 53, a second back gate wiring 54, first back gate via electrodes 55A to 55C, and a second back gate via electrode 56. The first back gate wiring 53 integrally includes a first portion 53A overlapping the back gate region 25 in the third direction Z, a second portion 53B overlapping the second end 33 in the third direction Z, and a third portion 53C overlapping the separation region 11 in the third direction Z. The first portion 53A, the second portion 53B, and the third portion 53C may be separated from each other as long as they are fixed to the same potential.

[0073] The first back gate wiring 53 is spaced apart from the source region 22 and is located on the second interlayer insulating film 41B. The first back gate wiring 53 overlaps the back gate region 25, the second end 33 of the field electrode 31, and the separation region 11 in the third direction Z. The first back gate wiring 53 may overlap the entire back gate region 25 in the third direction Z. The first back gate wiring 53 may overlap a part of the spiral portion 34 of the field electrode 31. The first back gate wiring 53 may be drawn out to a region outside the transistor region 9 in a planar view.

[0074] In the first embodiment, the second back gate wiring 54 is located on the second interlayer insulating film 41B. The second back gate wiring 54 overlaps the first back gate wiring 53 in a region outside the transistor region 9. The second back gate wiring 54 may overlap the first back gate wiring 53 in the transistor region 9. The thickness of the second back gate wiring 54 may be equal to or greater than the thickness of the first back gate wiring 53.

[0075] The first backgate via electrode 55A is located between the backgate region 25 and the first backgate wiring 53 in the third direction Z, and is connected to the backgate region 25 and the first backgate wiring 53. The first backgate via electrode 55B is located between the second end 33 of the field electrode 31 and the first backgate wiring 53 in the third direction Z, and is connected to the second end 33 and the first backgate wiring 53. The first backgate via electrode 55C is located between the isolation region 11 and the first backgate wiring 53 in the third direction Z, and is connected to the isolation region 11 and the first backgate wiring 53. Each of the first backgate via electrodes 55A and 55C is embedded in an opening provided in the first interlayer insulating film 41A and the second interlayer insulating film 41B. The first backgate via electrode 55B is embedded in an opening provided in the second interlayer insulating film 41B.

[0076] The second back gate via electrode 56 is located between the first back gate wiring 53 and the second back gate wiring 54 in the third direction Z, and is connected to the first back gate wiring 53 and the second back gate wiring 54. The second back gate via electrode 56 is embedded in an opening provided in the third interlayer insulating film 41C.

[0077] The semiconductor device 1A includes a gate wiring 57 selectively routed in the insulating layer 40 so as to be electrically connected to the gate electrode 37. The gate wiring 57 applies a gate potential to the gate electrode 37. The gate wiring 57 is spaced apart from the drain wiring 42, the source wiring 47, and the back gate wiring 52. The gate wiring 57 forms a multi-layer wiring in the insulating layer 40.

[0078] The gate wiring 57 includes a first gate wiring 58, a second gate wiring (not shown), a first gate via electrode 59, and a second gate via electrode (not shown). The first gate wiring 58 overlaps the gate electrode 37 in the third direction Z, and is located on the second interlayer insulating film 41B. The first gate wiring 58 is drawn out to a region outside the transistor region 9 in a plan view. In the first embodiment, the second gate wiring (not shown) is located on the second interlayer insulating film 41B, and overlaps with the first gate wiring 58 in a region outside the transistor region 9 in the third direction Z. The thickness of the second gate wiring may be equal to or greater than the thickness of the first gate wiring 58.

[0079] The first gate via electrode 59 is located between the gate electrode 37 and the first gate wiring 58 in the third direction Z, and is connected to the gate electrode 37 and the first gate wiring 58. The second gate via electrode (not shown) is located between the first gate wiring 58 and the second gate wiring in the third direction Z, and is connected to the first gate wiring 58 and the second gate wiring.

[0080] Fig. 4 is a circuit diagram showing an electrical structure (specifically, a FET structure 10 and a field electrode 31) in a transistor region 9. As shown in Fig. 4, a semiconductor device 1A includes a FET structure 10 and a resistor R in a transistor region 9. Fig. 4 shows a drain D corresponding to the drain region 17, a source S corresponding to the source region 22, a back gate BG corresponding to the back gate region 25, and a gate G corresponding to a gate insulating film 36 and a gate electrode 37.

[0081] The resistor R corresponds to the field electrode 31 and is electrically connected to the drain D and the back gate BG. On the other hand, the resistor R is not connected to the gate G and the source S. In the first embodiment, only the FET structure 10 and the resistor R are formed in the transistor region 9. That is, in the transistor region 9, no other functional device is formed that is connected between the drain D and the source S. In addition, in the transistor region 9, no other functional device is formed that is connected between the drain D and the gate G. In addition, in the transistor region 9, no other functional device is formed that is connected between the source S and the gate G.

[0082] In the FET structure 10, for example, a drain potential, a source potential, a backgate potential, and a gate potential are applied to the drain D, the source S, the backgate BG, and the gate G, respectively, from a region outside the transistor region 9 (including a region outside the semiconductor device 1A). That is, the FET structure 10 is configured so that a source potential is individually applied to the source S, and a backgate potential is individually applied to the backgate BG.

[0083] The drain potential may be a power supply potential. The source potential is equal to or lower than the drain potential. The source potential may be a reference potential, a ground potential, or other potentials. The backgate potential is equal to or lower than the drain potential. The backgate potential may be a reference potential, a ground potential, or other potentials. The backgate potential is not prevented from being the same potential as the source potential. That is, while the backgate region 25 is electrically isolated from the source region 22 inside the chip 2, the backgate region 25 may be fixed to the same potential as the source region 22 by external potential control.

[0084] Next, a method for manufacturing a main part of the semiconductor device 1A according to the first embodiment will be described with reference to Figures 5A to 5H. Each of Figures 5A to 5H is a diagram for explaining a method for manufacturing a main part of the semiconductor device according to the first embodiment. The main part is a field electrode 31 located on a first semiconductor region 6.

[0085] 5A, a gate electrode 37 including an extension portion 38 is formed on the insulating film 30 and the gate insulating film 36 provided on the first semiconductor region 6. The gate electrode 37 is provided, for example, by patterning polysilicon formed on the first semiconductor region 6. The polysilicon may be patterned after being silicided.

[0086] Before the gate electrode 37 shown in FIG. 5A is formed, a first semiconductor region 6 (semiconductor layer) having an isolation region 11, a drain region 17, a source region 22, a drift region 23, and a channel region 24 is formed on a second semiconductor region 7 included in the semiconductor substrate (i.e., on the semiconductor substrate) by a known method. At this time, a first isolation region 12, a buried region 18, and a first body region 20 are also formed in the first semiconductor region 6 and the second semiconductor region 7. Then, an insulating film 30 in contact with the first semiconductor region 6 and a gate insulating film 36 are formed in this order. The insulating film 30 is formed, for example, by forming a groove in a part of the first semiconductor region 6 and then filling the groove with an insulating material. A part of the insulating film 30 is formed on the drift region 23 in the first semiconductor region 6 (see FIG. 3). The gate insulating film 36 is formed, for example, by patterning an insulating film formed on the first semiconductor region 6 and the insulating film 30. The gate insulating film 36 is formed on the channel region 24 in the first semiconductor region 6 (see FIG. 3).

[0087] 5B, an insulating layer 60 is formed to cover the gate electrode 37. The insulating layer 60 covers not only the gate electrode 37 but also the first semiconductor region 6, the insulating film 30, the gate insulating film 36, and the like. For example, the insulating layer 60 is formed by a physical vapor deposition method (PVD method) such as a vacuum deposition method or a sputtering method, or a chemical vapor deposition method (CVD method).

[0088] 5C, the insulating layer 60 is thinned to form a planarized first interlayer insulating film 41A. For example, the insulating layer 60 is thinned by chemical mechanical polishing (CMP) to form the first interlayer insulating film 41A. Like the insulating layer 60, the first interlayer insulating film 41A covers the gate electrode 37, the first semiconductor region 6, the insulating film 30, the gate insulating film 36, and the like.

[0089] 5D, a field electrode 31 is formed on the first interlayer insulating film 41A. For example, a polysilicon film formed on the first interlayer insulating film 41A is patterned using a mask to form the field electrode 31 overlapping the drift region 23. Although not shown, an inner field electrode 35 is also formed from the polysilicon film at the same time as the field electrode 31.

[0090] 5E, a second interlayer insulating film 41B that covers the field electrode 31 is formed on the first interlayer insulating film 41A. For example, the second interlayer insulating film 41B in which the field electrode 31 is embedded is formed by a PVD method or a CVD method.

[0091] Next, as shown in FIG. 5F, a first opening O1 (contact hole) exposing the gate electrode 37 is formed in the first interlayer insulating film 41A and the second interlayer insulating film 41B. For example, a mask is used to selectively etch a part of the first interlayer insulating film 41A and a part of the second interlayer insulating film 41B. The etching is, for example, anisotropic etching using dry etching. Although not shown, in the first embodiment, an opening in which the first drain via electrode 45A will be provided later, an opening in which the first source via electrode 50 will be provided later, an opening in which the first back gate via electrode 55A will be provided, an opening in which the first back gate via electrode 55C will be provided, and the like are formed in the first interlayer insulating film 41A and the second interlayer insulating film 41B at the same time as the formation of the first opening O1. As a result, simultaneously with the formation of the first opening O1, an opening exposing the drain region 17, an opening exposing the source region 22, an opening exposing the backgate region 25, an opening exposing the isolation region 11, etc. are formed in the first interlayer insulating film 41A and the second interlayer insulating film 41B.

[0092] Next, as shown in FIG. 5G, a second opening O2 exposing the field electrode 31 is formed in the second interlayer insulating film 41B. For example, another part of the second interlayer insulating film 41B is selectively etched by performing anisotropic etching using a mask. As a result, the second opening O2 is formed on the second end 33 of the field electrode 31. Although not shown, in the first embodiment, an opening that overlaps with the first end 32 of the field electrode 31 and in which the first drain via electrode 45B will be provided later is formed in the second interlayer insulating film 41B at the same time as the second opening O2 is formed. As a result, an opening exposing the first end 32 is formed in the second interlayer insulating film 41B at the same time as the second opening O2 is formed.

[0093] Next, as shown in FIG. 5H, a first gate via electrode 59 (first contact) is filled in the first opening O1, and a first back gate via electrode 55B (second contact) is filled in the second opening O2. For example, the first gate via electrode 59 and the first back gate via electrode 55B are formed by patterning a conductive deposit formed by a PVD method. The conductive deposit is not only filled in the first opening O1 and the second opening O2, but also filled in other openings. For this reason, although not shown, in the first embodiment, the first drain via electrode 45A, the first drain via electrode 45B, the first source via electrode 50, the first back gate via electrode 55A, the first back gate via electrode 55C, and the like are formed at the same time as the first gate via electrode 59 and the first back gate via electrode 55B are formed. In addition, the conductive deposit is also deposited on the second interlayer insulating film 41B. For this reason, although not shown, the first drain wiring 43, the first source wiring 48, the first back gate wiring 53, the first gate wiring 58, and the like are also formed simultaneously with the first gate via electrode 59 and the first back gate via electrode 55B. As a result, the drain region 17 and the first end 32 of the field electrode 31 are electrically connected, and the second end 33 of the field electrode 31, the separation region 11, and the back gate region 25 are electrically connected.

[0094] Although not shown, after the formation of the first gate via electrode 59 and the like, the third interlayer insulating film 41C is formed. Then, an opening is formed in a part of the third interlayer insulating film 41C, and the opening is filled to form a conductive deposit. The conductive deposit is also deposited on the third interlayer insulating film 41C. Then, the conductive deposit is patterned to form the second drain via electrode 46, the second drain wiring 44, the second source wiring 49, the second source via electrode 51, the second back gate wiring 54, the second back gate via electrode 56, the second gate wiring, the second gate via electrode, and the like. In this manner, the FET structure 10 included in the semiconductor device 1A is formed.

[0095] The effects of the semiconductor device 1A according to the first embodiment described above will be described.

[0096] For example, when a semiconductor device is formed from a 200 mm (approximately 8 inch) silicon wafer, the thickness of the insulating film (e.g., buried insulating film, LOCOS film, etc.) that contacts the semiconductor layer and overlaps the field electrode is set to 500 nm or more (e.g., approximately 700 nm) from the viewpoint of resistance to electric field strength. In this case, for example, when a drain voltage of 800 V is applied to the FET structure, a maximum potential difference of approximately 100 V occurs between the field electrode and the surface of the semiconductor region directly below the insulating film. As a result, the electric field strength in the insulating film is approximately 1.4×10 6 V / cm (=approximately 100V / 700nm).

[0097] Here, when a semiconductor device is formed from a 300 mm (about 12 inches) silicon wafer as in the first embodiment described above, if the thickness of the buried insulating film is set to 500 nm, there is a concern that the silicon wafer may warp. In addition, with the increase in performance of semiconductor devices, miniaturization of wiring, elements, etc. (for example, minimum active dimension: 160 nm) is also implemented. In this case, the formation of a buried insulating film having a thickness of 500 nm results in an aspect ratio exceeding 3, which is technically difficult. Therefore, from the viewpoints of preventing the above-mentioned warpage and the feasibility of the semiconductor device manufacturing process, the thickness of the insulating film formed on the silicon wafer is set to about 250 nm at most. When a field electrode is formed directly on an insulating film of such a thickness, the electric field strength in the insulating film is about 3.92×10 6 V / cm, which raises the concern that dielectric breakdown may occur in the insulating film.

[0098] In contrast, in the semiconductor device 1A manufactured by the manufacturing method according to the first embodiment, the field electrode 31 is located on the first interlayer insulating film 41A. As a result, the first interlayer insulating film 41A, in addition to the insulating film 30, is located between the surface of the first semiconductor region 6 and the field electrode 31. Therefore, the presence of the first interlayer insulating film 41A can reduce the electric field strength in the insulating film 30. Therefore, in the semiconductor device 1A, even if the insulating film 30 is thinned due to the increase in size of the silicon wafer and the miniaturization of wiring, elements, etc., the occurrence of dielectric breakdown between the first semiconductor region 6 and the field electrode 31 can be effectively suppressed. Therefore, according to the first embodiment, a semiconductor device that can exhibit high reliability even when the wafer size is increased can be provided.

[0099] In the first embodiment, the first semiconductor region 6 has a back gate region 25 electrically connected to the field electrode 31. This makes it possible to satisfactorily adjust the electric field distribution between the drain region 17 and the back gate region 25.

[0100] In the first embodiment, the field electrode 31 has a first end 32 electrically connected to the drain region 17, a second end 33 electrically connected to the back gate region 25, and a spiral portion 34 connecting the first end 32 and the second end 33. This allows a good potential gradient to be formed from the first end 32 to the second end 33.

[0101] FIG. 6 is a schematic cross-sectional view showing a semiconductor device according to a modified example of the first embodiment. As shown in FIG. 6, the semiconductor device 1B is different from the first embodiment in that the insulating film 30 is not formed, but an insulating film 36A is formed instead. In other words, in this modified example, no groove is provided in the first semiconductor region 6. In this modified example, not only the insulating film 36A but also the first interlayer insulating film 41A is located between the field electrode 31 and the first semiconductor region 6 (i.e., the first main surface 3). Therefore, the modified example also achieves the same effects as the first embodiment.

[0102] In the above modification, the insulating film 36A is located between the field electrode 31 and the first semiconductor region 6, but this is not limited to the above. For example, only the first interlayer insulating film 41A may be located between the field electrode 31 and the first semiconductor region 6. Even in this case, the same effects as those of the first embodiment can be achieved by thickening the first interlayer insulating film 41A.

[0103] Second embodiment The second embodiment will be described below with reference to Figures 7, 8, and 9A to 9E. In the description of the second embodiment, descriptions that overlap with the first embodiment described above will be omitted, and only differences will be described. In other words, the descriptions of the first embodiment may be used appropriately for the second embodiment to the extent technically possible.

[0104] Fig. 7 is a schematic cross-sectional view of a main part of a semiconductor device according to a second embodiment. Fig. 8 is a schematic cross-sectional view of a region VIII shown in Fig. 7. As shown in Fig. 7, a semiconductor device 1C according to the second embodiment is different from the semiconductor device 1A according to the first embodiment in that a field electrode 31A is provided. In addition, in the semiconductor device 1C according to the second embodiment, a first gate wiring 58A is located on a first interlayer insulating film 41A.

[0105] As shown in FIG. 8, the field electrode 31A is formed of a thin-film resistor TR. The thin-film resistor TR is a high-resistance film containing, for example, chromium silicide, and is significantly thinner than the polysilicon in the first embodiment. In the second embodiment, the thickness of the thin-film resistor TR is 1 nm or more and 30 nm or less. The thin-film resistor TR includes a main portion TR1 forming the spiral portion 34A and a covering portion TR2 described below. The chromium silicide includes, for example, at least one of CrSi, CrSi2, CrSiN, and CrSiO. CrSiN is also a chromium nitride. CrSiO is also a chromium oxide. In the second embodiment, the chromium silicide is CrSi.

[0106] A conductive layer C (first conductive layer) is provided on the second end 33A included in the field electrode 31A. The conductive layer C is a conductor formed simultaneously with the gate wiring 57A and the like. At least a part of the conductive layer C is covered by the covering portion TR2 included in the thin-film resistor TR and contacts the thin-film resistor TR. Therefore, the conductive layer C is electrically connected to the thin-film resistor TR. In addition, the conductive layer C contacts the first backgate via electrode 55B (second conductive layer). Therefore, the backgate wiring 52 is electrically connected to the field electrode 31A via the conductive layer C. Although not shown, a conductive layer covered by the thin-film resistor TR is provided on the first end included in the field electrode 31A as in the second end 33A.

[0107] Next, a method for manufacturing a main part of the semiconductor device 1C according to the second embodiment will be described with reference to Figures 9A to 9E. Each of Figures 9A to 9E is a diagram for explaining a method for manufacturing a main part of the semiconductor device according to the second embodiment. The main part is a field electrode 31A.

[0108] 9A, a gate wiring 57A including a first gate via electrode 59A filling a first opening O1A provided in a first interlayer insulating film 41A is formed. At the same time as the formation of the gate wiring 57A, a conductive layer C is formed in a portion where a second end 33A of the field electrode 31A will be provided later. Also, another conductive layer is formed in a portion where a first end of the field electrode 31A will be provided later.

[0109] 9A, the first semiconductor region 6 (semiconductor layer), insulating film 30, gate insulating film 36, gate electrode 37, and first interlayer insulating film 41A are formed on the second semiconductor region 7 (on the semiconductor substrate) in a manner similar to that of the first embodiment. Note that the second embodiment differs from the first embodiment in that the first opening O1A, gate wiring 57A, conductive layer C, and the like are formed before the field electrode 31A is formed.

[0110] 9B, a thin-film resistance layer TRL is formed to cover first interlayer insulating film 41A, conductive layer C, gate wiring 57A, etc. For example, a thin-film resistance layer TRL containing chromium silicide is formed by a PVD method.

[0111] 9C, a patterned resist mask RM is formed on the thin-film resistance layer TRL. For example, the resist mask RM is formed by photolithography. The resist mask RM may be a negative resist or a positive resist.

[0112] Next, as shown in FIG. 9D, a portion of the thin-film resistive layer TRL that is not covered by the resist mask RM is etched. For example, a portion of the thin-film resistive layer TRL is etched by wet etching or dry etching. Then, the resist mask RM is removed. For example, the resist mask RM is removed by wet etching. As a result, the field electrode 31A is formed on the first interlayer insulating film 41A. Also, the gate wiring 57A and the like are exposed from the thin-film resistive layer TRL.

[0113] Next, as shown in FIG. 9E, a second interlayer insulating film 41B is formed to cover the first interlayer insulating film 41A, the gate wiring 57A, the field electrode 31A, and the like. Then, a second opening O2 is formed in the second interlayer insulating film 41B by etching a part of the second interlayer insulating film 41B. In the second embodiment, when the second opening O2 is formed, a part of the covered part TR2 of the thin-film resistor TR (a part of the covered part TR2 that overlaps with the second opening O2) is also etched. As a result, a part of the top surface of the conductive layer C that overlaps with the second opening O2 is exposed from the second interlayer insulating film 41B. Although not shown, when the second opening O2 is formed, a part of the thin-film resistor TR that is exposed from the second interlayer insulating film 41B (for example, a part included in the first end) is also removed. Then, a backgate wiring 52 is formed including a first backgate via electrode 55B (a second contact or a second conductive layer) that is filled in the second opening O2. As in the first embodiment, a via electrode (first drain via electrode) is formed in the opening formed in the second interlayer insulating film 41B. Then, the third interlayer insulating film 41C and the like are formed in the same manner as in the first embodiment, thereby manufacturing the semiconductor device 1C.

[0114] The second embodiment described above also has the same effects as the first embodiment. In addition, since the field electrode 31A includes the thin-film resistor TR, the semiconductor device 1C can have a higher breakdown voltage and the field electrode 31A can have a higher precision in resistance. Furthermore, since the number of masks can be reduced compared to the first embodiment, the cost can be reduced and the yield can be improved.

[0115] As described above, in the second embodiment, when the second opening O2 is formed, a part of the covered portion TR2 of the thin-film resistor TR is also etched. This allows the conductive layer C to directly contact the first back gate via electrode 55B, thereby reducing the contact resistance. Note that when the second opening O2 is formed, the covered portion TR2 of the thin-film resistor TR does not have to be etched. In this case, the covered portion TR2 can function as an etch stopper.

[0116] The second embodiment may be modified from the first embodiment. For example, the insulating film 30 may not be formed in the semiconductor device 1C. In this case, the insulating film 36A may be formed as in the modified first embodiment, or only the first interlayer insulating film 41A may be located between the field electrode 31A and the first semiconductor region 6.

[0117] Third embodiment The third embodiment will be described below with reference to Fig. 10. In the description of the third embodiment, descriptions that overlap with the first and second embodiments will be omitted, and only differences will be described. In other words, the descriptions of the first and second embodiments may be used appropriately in the third embodiment to the extent technically possible.

[0118] Fig. 10 is a schematic cross-sectional view of a main part of a semiconductor device according to embodiment 3. As shown in Fig. 10, a FET structure 10A included in a semiconductor device 1D has a so-called JFET (Junction FET) structure, and includes a p-type semiconductor substrate 102 and an n-type semiconductor layer 103 located on the semiconductor substrate 102.

[0119] The semiconductor substrate 102 is a high-resistance silicon substrate. The semiconductor layer 103 is an epitaxial semiconductor layer formed on the semiconductor substrate 102. A drain region 104 having a second conductivity type is located in the semiconductor layer 103. The drain region 104 is a region that functions as a drain of the FET structure 10A, and has an oval ring shape in a plan view. An n-type drain side well region 105 that contacts the drain region 104 is formed below the drain region 104 in the semiconductor layer 103. The drain side well region 105 is a region that covers the bottom and sides of the drain region 104, and has an oval ring shape that surrounds the drain region 104 in a plan view. An n-type drain buffer region 106 is formed below the drain side well region 105. The drain buffer region 106 is a region that forms a pn junction with the semiconductor substrate 102, and is located in the semiconductor substrate 102 and the semiconductor layer 103. The drain buffer region 106 and the semiconductor substrate 102 form a pn junction, thereby increasing the breakdown voltage of the semiconductor device 1D. The drain buffer region 106 has an elliptical shape in a plan view. The periphery of the drain buffer region 106 is located outside the outer periphery of the drain region 104 in a plan view.

[0120] In the semiconductor layer 103, source / gate regions 109 are formed. Although not shown, in the source / gate regions 109, n-type source regions (not shown) and p-type gate regions 108 are electrically connected to each other and are alternately arranged at intervals in a plan view. In the third embodiment, the source / gate regions 109 have an oval ring shape spaced apart from the drain region 104 and positioned around the drain region 104 in a plan view. The source regions are electrically floating and have a rectangular shape in a plan view. The gate regions 108 are electrically connected to ground (GND) and have a rectangular shape in a plan view.

[0121] The source / gate region 109 includes an n-type source-side well region (not shown) and a p-type gate-side well region 111. The source-side well region is located in the semiconductor layer 103 below the source region. The gate-side well region 111 is located in the semiconductor substrate 102 and in the semiconductor layer 103 below the gate region 108. The source-side well region is a region that contacts the source region and covers the bottom and sides of the source region. The gate-side well region 111 is a region that contacts the gate region 108 and covers the bottom and sides of the gate region 108. The contact between the gate-side well region 111 and the source-side well region forms a pn junction. The gate-side well region 111 includes a region located between two adjacent source-side well regions, and the like.

[0122] The current flowing between the drain region 104 and the source region through the semiconductor layer 103 is controlled by applying a predetermined control voltage to the source / gate region 109. More specifically, when a predetermined control voltage is applied to the source region, a depletion layer spreads from the pn junction formed by the source-side well region and the gate-side well region 111. This causes the source region and the source-side well region to be depleted. This closes the current path between the drain region 104 and the source region, so that no current flows between the drain region 104 and the source region. On the other hand, when the application of the control voltage to the source region is released, the depletion of the source region and the source-side well region is released. This opens the current path between the drain region 104 and the source region, so that a current flows between the drain region 104 and the source region. In this way, the current flowing between the drain region 104 and the source region is controlled in the FET structure 10A.

[0123] A LOCOS film 112, which is an example of an insulating layer that selectively exposes the drain region 104 and the source / gate region 109, is located on the semiconductor layer 103. The LOCOS film 112 is located between the drain region 104 and the source / gate region 109 in a plan view. The LOCOS film 112 has a thickness of, for example, 5000 Å or more and 15000 Å or less. The LOCOS film 112 has an inner LOCOS film 113 that has an elliptical shape in a plan view and covers the region surrounded by the drain region 104, and an outer LOCOS film 114 that has an elliptical ring shape in a plan view and covers the region between the drain region 104 and the source / gate region 109.

[0124] In the semiconductor layer 103, a region overlapping with the outer LOCOS film 114 corresponds to the drift region 115. The length of the drift region 115 is, for example, not less than 80 μm and not more than 200 μm. The length of the drift region 115 corresponds to the channel length of the FET structure 10A. Therefore, in the third embodiment, it can be said that the drift region 115 also includes a channel region. A p-type RESURF layer 116 is formed in a portion of the semiconductor layer 103 that contacts the outer LOCOS film 114. The RESURF layer 116 forms a pn junction with the drift region 115 of the semiconductor layer 103. In a plan view, the RESURF layer 116 has an oval ring shape that follows the planar shape of the outer LOCOS film 114.

[0125] A plurality of interlayer insulating films 133 are provided on the semiconductor layer 103. In the third embodiment, the plurality of interlayer insulating films 133 include a first interlayer insulating film 133A located directly on the LOCOS film 112 and a second interlayer insulating film 133B located on the first interlayer insulating film 133A. The first interlayer insulating film 133A has, for example, the same function and configuration as the first interlayer insulating film 41A of the first embodiment. Each of the first interlayer insulating film 133A and the second interlayer insulating film 133B may have a single layer structure or a multilayer structure.

[0126] A resistive field electrode 120 is located on the first interlayer insulating film 133A. Therefore, the LOCOS film 112 and the first interlayer insulating film 133A are located between the semiconductor layer 103 and the field electrode 120. The field electrode 120 has, for example, the same function and configuration as the field electrode 31 of the first embodiment. The field electrode 120 is disposed between the drain region 104 and the source / gate region 109 in a plan view. The field electrode 120 has an innermost periphery 201, an outermost periphery 202, and an intermediate portion 203.

[0127] The innermost periphery 201 is a portion electrically connected to the drain region 104, and is the closest to the drain region 104 in the field electrode 120. Therefore, in a plan view, the field electrode 120 does not exist inside the innermost periphery 201 of the field electrode 120. The outermost periphery 202 is a portion electrically connected to the source / gate region 109 and ground, and is the closest to the source / gate region 109 in the field electrode 120. Therefore, the field electrode 120 does not exist outside the outermost periphery 202 of the field electrode 120. The intermediate portion 203 is a main portion of the field electrode 120, and is a connecting portion that connects the innermost periphery 201 and the outermost periphery 202. The intermediate portion 203 has a band shape extending spirally in a plan view.

[0128] On the semiconductor layer 103, a drain metal 130 electrically connected to the drain region 104 and a gate metal 131 electrically connected to the gate region 108 are disposed. Although not shown, a source metal electrically connected to the source region is also disposed on the semiconductor layer 103. At least a part of the drain metal 130, at least a part of the gate metal 131, and at least a part of the source metal are selectively formed in the interlayer insulating film 133. The drain metal 130 is electrically connected to the drain region 104 and the innermost periphery 201 of the field electrode 120. The gate metal 131 is electrically connected to the gate region 108 and the outermost periphery 202 of the field electrode 120. Although not shown, the source metal is electrically connected to the source region.

[0129] The third embodiment described above also provides the same advantageous effects as the first embodiment, that is, even if the structure of the FET is changed, a semiconductor device 1D exhibiting high reliability can be obtained.

[0130] The third embodiment may be applied to the modified example of the first embodiment. For example, the LOCOS film 112 may not be formed in the semiconductor device 1D. In this case, for example, the insulating film 36A may be formed as in the modified example of the first embodiment. Alternatively, the third embodiment may be applied to the modified example of the second embodiment.

[0131] Although the embodiment and modified examples of the present disclosure have been described above, the present disclosure can be embodied in further other forms.

[0132] In the above embodiment and modified examples, the conductivity types of various semiconductor regions may be inverted, that is, p-type portions may be made n-type, and n-type portions may be made p-type.

[0133] In the above embodiment and the above modified example, the semiconductor device can be applied to a power module used in an inverter circuit that drives an electric motor used as a power source for, for example, automobiles (including electric automobiles), trains, industrial robots, air conditioners, air compressors, electric fans, vacuum cleaners, dryers, refrigerators, etc. The semiconductor device can also be applied to a power module used in an inverter circuit for solar cells, wind power generators, and other power generation devices, etc. Alternatively, the semiconductor device can be applied to a circuit module that constitutes an analog control power supply, a digital control power supply, etc.

[0134] Although the embodiments and variants relating to one aspect of the present disclosure have been described in detail above, these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be interpreted as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims.

[0135] Below, examples of features extracted from the description of this specification and the drawings are presented.

[0136] [A1] A semiconductor substrate; a semiconductor layer located on the semiconductor substrate and having a drain region, a source region, a drift region and a channel region; an insulating film in contact with the semiconductor layer and located on the channel region; an interlayer insulating film covering the insulating film; a field plate located on the interlayer insulating film, overlapping the drift region, and electrically connected to the drain region; A semiconductor device comprising:

[0137] [A2] Further comprising a gate electrode located on the insulating film, The semiconductor device according to [A1], wherein the gate electrode is covered with the interlayer insulating film.

[0138] [A3] The semiconductor device according to [A2], wherein each of the gate electrode and the field plate includes polysilicon.

[0139] [A4] The semiconductor device according to any one of [A1] to [A3], wherein the semiconductor layer further has a back gate region electrically connected to the field plate.

[0140] [A5] The semiconductor device described in [A4], wherein the field plate has an innermost portion electrically connected to the drain region, an outermost portion electrically connected to the backgate region, and a connection portion connecting the innermost portion and the outermost portion.

[0141] [A6] Further comprising a LOCOS film in contact with the semiconductor layer, The semiconductor device according to any one of [A1] to [A5], wherein the field plate overlaps the LOCOS film and the interlayer insulating film.

[0142] [A7] The semiconductor device according to [A1], wherein the semiconductor layer further has a source / gate region in which the source region and a gate region electrically connected to the source region are provided, the source / gate region being spaced apart from the drain region and positioned around the drain region.

[0143] [A8] The semiconductor device according to [A7], wherein the field plate has an innermost portion electrically connected to the drain region, an outermost portion electrically connected to ground, and a connection portion connecting the innermost portion and the outermost portion.

[0144] [A9] The semiconductor device according to any one of [A1] to [A8], wherein the insulating film is a LOCOS film.

[0145] [A10] The semiconductor device according to any one of [A1] to [A9], wherein the field plate includes polysilicon.

[0146] [A11] The semiconductor device according to any one of [A1] to [A10], wherein the field plate includes chromium silicide.

[0147] [A12] The semiconductor device according to [A11], wherein the field plate has a thickness of 1 nm or more and 30 nm or less.

[0148] [A13] a first conductive layer located on the interlayer insulating film and electrically connected to the field plate; a second interlayer insulating film covering the first conductive layer and the field plate; a second conductive layer that is filled in an opening provided in the second interlayer insulating film and is electrically connected to the field plate; the first conductive layer has an exposed portion exposed from the field plate; The semiconductor device according to [A11] or [A12], wherein the second conductive layer is in contact with the exposed portion.

[0149] [B1] forming a semiconductor layer having a drain region, a source region, a drift region and a channel region on a semiconductor substrate; forming an insulating film in contact with the semiconductor layer and located on the channel region; forming an interlayer insulating film covering the insulating film; forming a field plate located on the interlayer insulating film and overlapping the drift region; forming a second interlayer insulating film covering the field plate; forming a first opening in the interlayer insulating film and the second interlayer insulating film; forming a second opening in the second interlayer insulating film to expose the field plate; forming a first contact filled in the first opening and a second contact filled in the second opening; A method for manufacturing a semiconductor device comprising the steps of:

[0150] [B2] The method for manufacturing a semiconductor device according to [B1], wherein the field plate includes polysilicon.

[0151] [C1] forming a semiconductor layer having a drain region, a source region, a drift region and a channel region on a semiconductor substrate; forming an insulating film in contact with the semiconductor layer and located on the channel region; forming an interlayer insulating film covering the insulating film; forming a first opening in the interlayer insulating film; forming a contact filled in the first opening and a conductive layer located on the interlayer insulating film; forming a resistive layer covering the interlayer insulating film, the contacts and the conductive layer and including chromium silicide; patterning the resistive layer to form a field plate having a covering portion overlying the conductive layer; A method for manufacturing a semiconductor device comprising the steps of:

[0152] [C2] The method for manufacturing a semiconductor device according to [C1], wherein the field plate has a thickness of 1 nm or more and 30 nm or less.

[0153] [C3] forming a second interlayer insulating film covering the field plate; forming a second opening in the second interlayer insulating film by etching the second interlayer insulating film and a portion of the covering portion of the field plate, the second opening exposing the conductive layer; The method for manufacturing a semiconductor device according to [C1] or [C2], further comprising: forming a second contact that fills the second opening.

[0154] [C4] The method for manufacturing a semiconductor device according to any one of [B1], [B2], [C1], [C2] and [C3], further comprising a step of forming a gate electrode on the insulating film before forming the interlayer insulating film. [Explanation of symbols]

[0155] Reference Signs List 1A, 1B, 1C, 1D...semiconductor device, 2...chip, 3...first main surface, 4...second main surface, 6...first semiconductor region (semiconductor layer), 7...second semiconductor region (semiconductor substrate), 8...device region, 9...transistor region, 10, 10A...FET structure (transistor structure), 11...isolation region, 22...source region, 17, 104...drain region, 23, 115...drift region, 24...channel region, 25...backgate region, 30, 36A...insulating film, 31, 31A, 120...field electrode (field plate), 32...first end, 33, 33A...second end, 34, 34A...spiral portion, 36...gate insulating film, 37...gate electrode, 41, 133...interlayer insulating film, 41A, 133 A...first interlayer insulating film, 41B, 133B...second interlayer insulating film, 41C...third interlayer insulating film, 42...drain wiring, 47...source wiring, 52...back gate wiring, 55B...first back gate via electrode (second contact or second conductive layer), 57, 57A...gate wiring, 59...first gate via electrode (first contact), 102...semiconductor substrate, 103...semiconductor layer, 108...gate region, 109...source / gate region, 112...LOCOS film, 130...drain metal, 131...gate metal, 201...innermost portion, 202...outermost portion, C...conductive layer (first conductive layer), O1...first opening (contact hole), O1A...first opening, O2...second opening, TR2...covered portion.

Claims

1. A semiconductor substrate; a semiconductor layer located on the semiconductor substrate and having a drain region, a source region, a drift region and a channel region; an insulating film in contact with the semiconductor layer and located on the channel region; an interlayer insulating film covering the insulating film; a field plate located on the interlayer insulating film, overlapping the drift region, and electrically connected to the drain region; A semiconductor device comprising:

2. A gate electrode is further provided on the insulating film. The semiconductor device according to claim 1 , wherein said gate electrode is covered with said interlayer insulating film.

3. The semiconductor device according to claim 2 , wherein each of said gate electrode and said field plate includes polysilicon.

4. 4. The semiconductor device according to claim 1, wherein the semiconductor layer further includes a back gate region electrically connected to the field plate.

5. 5. The semiconductor device according to claim 4, wherein the field plate has an innermost portion electrically connected to the drain region, an outermost portion electrically connected to the backgate region, and a connection portion connecting the innermost portion and the outermost portion.

6. Further comprising a LOCOS film in contact with the semiconductor layer, 4. The semiconductor device according to claim 1, wherein said field plate overlaps said LOCOS film and said interlayer insulating film.

7. 2. The semiconductor device according to claim 1, wherein the semiconductor layer further includes a source / gate region in which the source region and a gate region electrically connected to the source region are provided, the source / gate region being spaced apart from the drain region and positioned around the drain region.

8. 8. The semiconductor device according to claim 7, wherein the field plate has an innermost portion electrically connected to the drain region, an outermost portion electrically connected to ground, and a connection portion connecting the innermost portion and the outermost portion.

9. 9. The semiconductor device according to claim 1, wherein the insulating film is a LOCOS film.

10. 9. The semiconductor device according to claim 1, wherein the field plate includes polysilicon.

11. 9. The semiconductor device according to claim 1, wherein the field plate includes chromium silicide.

12. The semiconductor device according to claim 11 , wherein the field plate has a thickness of not less than 1 nm and not more than 30 nm.

13. a first conductive layer located on the interlayer insulating film and electrically connected to the field plate; a second interlayer insulating film covering the first conductive layer and the field plate; a second conductive layer that is filled in an opening provided in the second interlayer insulating film and is electrically connected to the field plate; the first conductive layer has an exposed portion exposed from the field plate; The semiconductor device according to claim 11 , wherein the second conductive layer is in contact with the exposed portion.

14. forming a semiconductor layer on a semiconductor substrate, the semiconductor layer having a drain region, a source region, a drift region and a channel region; forming an insulating film in contact with the semiconductor layer and located on the channel region; forming an interlayer insulating film covering the insulating film; forming a field plate located on the interlayer insulating film and overlapping the drift region; forming a second interlayer insulating film covering the field plate; forming a first opening in the interlayer insulating film and the second interlayer insulating film; forming a second opening in the second interlayer insulating film to expose the field plate; forming a first contact filled in the first opening and a second contact filled in the second opening; A method for manufacturing a semiconductor device comprising the steps of:

15. The method for manufacturing a semiconductor device according to claim 14 , wherein the field plate includes polysilicon.

16. forming a semiconductor layer on a semiconductor substrate, the semiconductor layer having a drain region, a source region, a drift region and a channel region; forming an insulating film in contact with the semiconductor layer and located on the channel region; forming an interlayer insulating film covering the insulating film; forming a first opening in the interlayer insulating film; forming a contact filled in the first opening and a conductive layer located on the interlayer insulating film; forming a resistive layer covering the interlayer insulating film, the contacts and the conductive layer and including chromium silicide; patterning the resistive layer to form a field plate having a covering portion overlying the conductive layer; A method for manufacturing a semiconductor device comprising the steps of:

17. The method for manufacturing a semiconductor device according to claim 16, wherein the field plate has a thickness of 1 nm or more and 30 nm or less.

18. forming a second interlayer insulating film covering the field plate; forming a second opening in the second interlayer insulating film by etching the second interlayer insulating film and a portion of the covering portion of the field plate, the second opening exposing the conductive layer; 18. The method for manufacturing a semiconductor device according to claim 16, further comprising the step of: forming a second contact that fills the second opening.

19. 18. The method for manufacturing a semiconductor device according to claim 14, further comprising the step of forming a gate electrode on the insulating film before forming the interlayer insulating film.

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