On-die shared bus speedup for multi-channel communication

Abstract

A shared bus for inter-channel communication includes two or more channels, each having a signal processing element configured to receive and process a received channel-specific signal. A sequence generator is configured to generate a test sequence suitable for testing the signal processing elements of the channels. An error checker is configured to check for errors in the received channel-specific signal. The shared bus connects to the two or more channels for transmitting the received channel-specific signal to the error checker and transmitting the test sequence to the signal processing elements of the channels. One or more pull-up and / or termination resistors connect to the shared bus. The bus includes a clock signal path and a data signal path. The test sequence is a pseudo-random bit sequence. The bus interface includes open-collector current mode logic drivers in a cascode arrangement.

Description

[Technical field]

[0001] This invention relates to communication between channels, and in particular to a shared bus for use during error checking and test signal generation. [Background technology]

[0002] Functionality and complexity are continually being added to semiconductors. To increase test efficiency, end users are demanding built-in diagnostic capabilities to quickly debug their systems without deploying or connecting complex and expensive test equipment. In the data center, this means being able to turn off a poorly performing link, inject a known data pattern such as a Pseudo Random Bit Sequence (PRBS) generator, and check for bit errors at various locations to properly debug the link. Summary of the Invention [Problem to be solved by the invention]

[0003] FIG. 1 shows a representative prior art multi-channel communication system co-integrated with diagnostic elements. This embodiment is an example of an optical communication system having channels 104A, 104B, 104C, and 104D shown in FIG. 1. Each channel may include a transmitter and a receiver for transmitting and receiving data transmissions. The electrical elements of the receiver are provided with electrical signals, such as electrical signals from a photodetector and a transimpedance amplifier (not shown) at input 108, to an analog front end (AFE) 112 that processes the analog signal and converts it to a digital signal. The digital signal is provided to a clock data recovery (CDR) circuit 116 that recovers the clock and data. Both the clock and data are provided to a driver 120 that is configured to amplify the signal for downstream components.

[0004] The diagnostic elements are represented by a sequence generator 124 and an error checker 128, each connected to the driver 120 with two paths 132, 136. These paths 132, 136 are high speed paths and must be dimensioned to handle high speed operation. A sequence generator 124 and an error checker 128 are associated with each channel. Thus, the system of FIG. 1 has four sequence generators 124 and four error checkers 128. While this system would be acceptable as a prior art system given a channel pitch of 750 μm, the combined size of the signal paths and diagnostic elements makes this physical arrangement impossible when the available area is low. For example, the diagnostic system would take up approximately two-thirds of the available area.

[0005] Meanwhile, the die size and especially the channel pitch are not expected to increase. These factors must be accommodated with industry standard parts (optical side channel pitch is only 250 μm). Even the current generation of datacom chips, integrating the CDR function that converts electrical to optical (E to O) and vice versa (O to E), have more stretched die sizes (2:1 ratio) and no room for the diagnostic block. The diagnostic block is an elaborate subsystem and hence large, which is often overlooked but deserves more attention. As shown below with respect to Figure 2, the diagnostic elements must be moved to the side. This creates a new problem of transmitting high speed data back and forth.

[0006] FIG. 2 shows an alternative prior art design when the allocated channel width per channel is 250 μm. In this layout, the diagnostic elements 204, 208 are moved out of the channel, thereby requiring two communication paths per channel, resulting in a total of 16 pairs of controlled impedance traces (two for NRZ streams) that must be sized to allow high speed communication to reach each channel 104A, 104B, 104C, and 104D. These signal trace paths must travel a distance of millimeters requiring impedance controlled transmission lines. Each channel has two different pairs connected to a diagnostic element 204, 208 dedicated to each channel. Thus, each channel is provided with an associated diagnostic element 204, 208. In a four channel system, four sets of diagnostic elements 204, 208 are provided such that each channel 104A, 104B, 104C, 104D has an associated diagnostic element 204, 208. This arrangement consumes space, power resources and space budget given the narrow channel width, and may not even fit on the die.

[0007] This is exacerbated by the move to new multi-level modulation formats (NRZ to PAM-4), which are known to include built-in diagnostic features, but which significantly increase complexity. On a chip, this requires multiple parallel high speed paths that require a significant amount of space. For example, at 30 Gb / s, each path would be 30 μm wide to avoid unnecessary signal quality impairments. This path size would be replicated eight times, resulting in the total path width consuming unwanted area and would not fit within the 250 μm channel width allocation. [Means for solving the problem]

[0008] To overcome the shortcomings of the prior art and provide additional benefits, a shared bus for inter-channel communication is disclosed.

[0009] In one embodiment, a shared bus for inter-channel communication includes two or more channels having signal processing elements. Each channel is configured to receive and process a received channel-specific signal. A sequence generator is configured to generate an appropriate test sequence for testing the signal processing elements of the channel. An error checker is provided and configured to error check the received channel-specific signal. The shared bus connects to the two or more channels for communicating the received channel-specific signal to the error checker and communicating the test sequence to the signal processing elements of the channel. Portions of this embodiment also include one or more loads connected to the shared bus. The loads may be one or more resistors, one or more resistors and peaking inductors, or other types of loads.

[0010] In one embodiment, the bus is formed by a clock signal path and a data signal path. The test sequence may be a pseudo-random bit sequence. The size, location, and number of loads (such as pull-up resistors) are selected to optimize reflections and jitter. In one embodiment, the error checker is configured to compare the received channel-specific signal to a known channel-specific signal generated by a sequence generator to detect errors. In one embodiment, each channel has a bus interface including open-collector current-mode logic drivers in a cascode arrangement.

[0011] Also disclosed is a method for inter-channel communication over a shared bus. An embodiment of the method includes initializing an error checking mode for a selected channel. An embodiment of the method includes enabling the selected channel to transmit or receive data over the shared bus and disabling the unselected channels to transmit or receive data over the shared bus. An embodiment of the method includes generating sequence data with a sequence generator and communicating the sequence data from the sequence generator to the selected channel over the shared bus. An embodiment of the method includes thereafter processing the sequence data with the selected data to generate processed sequence data and checking errors in the processed sequence data by comparing the processed sequence data to the sequence data.

[0012] In one embodiment, the bus is comprised of a clock signal path and a data signal path. The test sequence may be a pseudorandom bit sequence. The size, location and number of loads are selected to optimize reflections and jitter. The method of claim 7, wherein the error checker is configured to compare the received channel specific signal to a known channel specific signal generated by a sequence generator to detect errors. In one configuration, each channel has a bus interface including an open collector current mode logic driver in a cascode arrangement.

[0013] Also disclosed is an inter-channel communication system including two or more data communication channels, each data communication channel having a data processing unit. A bus driver is associated with each channel such that the bus driver is configured to occupy or release the bus and to transmit or receive data via the shared bus. The shared bus connects to the bus driver associated with each channel such that the shared bus also connects to at least one error checker and a sequence generator configured to generate sequence data.

[0014] As discussed below, the shared bus is a two-conductor bus comprised of a clock signal path and a data signal path. The sequence generator may be configured to generate a pseudo-random bit sequence, and transmission over the shared bus may occur using a bus driver associated with the sequence generator. The system may further include two or more pull-up resistors coupled to the shared bus. In one configuration, the error checker is configured to process the sequence data generated by the sequence generator after processing by the data processing unit to detect errors. The system may include one or more termination resistors coupled to the shared bus to reduce reflections and jitter.

[0015] Other systems, methods, features, and advantages of the invention will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.

[0016] The features depicted in the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.Like reference characters in the drawings indicate corresponding parts in the different views. [Brief description of the drawings]

[0017] [Figure 1]FIG. 1 illustrates a representative prior art multi-channel communication system co-integrated with diagnostic elements. [Diagram 2] FIG. 2 shows an alternative prior art design when the allocated channel width per channel is 250 μm. [Diagram 3] FIG. 1 is a diagram illustrating an example of a typical usage environment. [Figure 4] FIG. 1 illustrates an example of a layout for high speed communication between diagnostic elements and multiple communication channels. [Diagram 5] FIG. 5 illustrates the exemplary high-speed communication system of FIG. [Figure 6A] FIG. 1 illustrates a typical driver circuit. [Figure 6B] FIG. 1 illustrates a representative end-to-end driver circuit with an interconnect bus. [Figure 7] FIG. 2 illustrates the bus layout geometry of a die with multiple optical modules. [Figure 8] FIG. 1 illustrates a representative signal plot resulting from high speed communication over a diagnostic signal bus. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] 3 shows an example of a typical usage environment. In this embodiment, a first host 304 generates or receives data to be transmitted to a remote location, such as a second host 328. The first host 304 processes the data and prepares it for transmission before providing the data to a first optical module 312. Data from the first host 304 travels to the first optical module 312 as an electrical signal via an electrical channel 308.

[0019] The first optical module 312 converts electrical signals indicative of the data into optical signals that are transmitted over an optical channel 316, such as a fiber optic cable, to a second optical module 320. In the second optical module, the optical signals are converted into electrical signals that are provided over an electrical channel 324 to a second host 328. The second host 328 regenerates and repairs the data after travel from the remote first host 304 and provides the data for use by subsequent processing elements. In this processing path, the processing is performed in reverse for data transmitted from the second host 328 to the first host 304. Although illustrated in the context of an optical communications system, it is contemplated that the innovations disclosed below may be utilized in electrical or wireless communications environments.

[0020] FIG. 4 shows an example of a layout for high-speed communication between diagnostic elements and multiple communication channels. Other configurations other than this one example are possible without departing from the scope of the claims. In this example, only 250 μm is allocated as the width of each channel, and the layout shown in this way solves the reasons revealed in the background section. Within this width, there are AFEs 430, CDRs 432, and drivers 436 that consume die area, and there is no room for a large pattern generator 412 and error detection module 408. Therefore, the pattern generator 412 and error detection module 408 are shared among multiple channels 404. A two-path shared bus 424 with a data path 416 and a clock path 420 connects each channel 404A, 404B, 404C, 404D to the pattern generator 412 and error detection module 408. Within each channel 404A, 404B, 404C, 404D, the pattern generator 412 and the error detection module 408 are drivers that send and receive data and are synchronized by a clock.

[0021] This embodiment has several advantages over the prior art shown in Figures 1 and 2. Area savings are realized by reducing the number of systems from four sequence generators and four error checkers in Figure 1 until each channel shares a pattern generator 412 and an error detection module 408. This is a significant reduction in area requirements. It allows the system to fit on a die when the allocated channel width is reduced to 250 μm. Compared to the system in Figure 2, only two conductive paths 416, 420 are required instead of eight large paths (two for each channel to the diagnostic element). This reduces layout complexity, signal combinations and size requirements (two paths vs. eight paths in Figure 2).

[0022] FIG. 5 illustrates the exemplary high speed communication system of FIG. 4. With reference to FIG. 4, channel 0 404A, channel 1 404B, channel 2 404C, and channel 3 404D are shown. Associated with each channel are channel drivers 508A, 508B, 508C, and 508D that connect to a shared bus 424. Although shown as a single line, the bus 424 includes two conductive paths. Also connected to the bus 424 is a diagnostic system driver 512 that connects to the sequence generator 412 and the error checker 408. The diagnostic system driver 512 interfaces the sequence generator 412 and the error checker 408 to the bus 424. Drivers 520 and 508 function to provide signals through the channels. The sequence generator 412 and the error checker 408 share the driver 520, although it is contemplated that the generator and checker each have their own driver.

[0023] At each end of the bus 424, an adjustable termination element 504 is provided. The termination element 504 includes some type of resistance or impedance configured to match the impedance of the bus 424. The impedance of the termination element 504 and its match to the bus 424 may be selected to minimize reflections, minimize power loss, or mitigate jitter. Thus, in some embodiments, the resistance or impedance of the termination element 504 does not exactly match the resistance or impedance of the bus 424. The termination element 504 may be adjustable or may be comprised of a resistor, a MOS switch, or other element or elements. Also shown in FIG. 5 are one or more loads 530, such as, for example, multiple pull-up resistors configured to reduce reflections and jitter. These loads 530 are selectively and strategically placed and sized based on testing to accommodate high frequency operation, such as operation at 30 Gb / s. A number of loads 530 may be placed at several locations along the bus 424. An optimized algorithm is used to derive the location, number and value of the loads 530 .

[0024] In operation, the signal generator 412, the error checker 408, or both may be enabled. In an error detection mode, received data is provided to a particular channel, for example, channel 1 404B. To determine if the received data has errors, the data is sent to the error checker 408 via bus 424 using the channel 1 driver 508B, which checks the received data for errors. If the sequence generator 412 is active, it generates a sequence that is sent to the bus 424 using the diagnostic system driver 520. From the bus 424, the sequence is sent to the required channel 404. Either channel may be selected via resistor settings and local switches. On a common channel, the sequence generator and error checker cannot both be active at the same time, nor may they be requested by the application.

[0025] FIG. 6A shows a representative driver circuit. This is just one possible configuration for the driver circuit. In this embodiment, the driver circuit is an open collector current mode logic (CML) driver in a cascode configuration using bipolar technology. Other technologies such as CMOS, BiCMOS or HBT may be used without departing from the scope of the invention. The driver die 604 includes the circuit as shown. A resistor 612 is connected between the voltage node 608 and the driver, connected by a bus 616. The driver includes a first transistor 624 and a second transistor 628 arranged in a cascode configuration. Transistor 624 has a base connected to voltage node 620 and a collector connected to the opposite terminal of resistor 612. The emitter terminal is also connected to a capacitor 636A, which has an opposite terminal connected to a reference ground. The size of capacitor 636A is smaller than that of capacitor 636B. A smaller capacitor 636A provides the benefit of reducing or eliminating discontinuities, but can be a source of unwanted reflections. The emitter of transistor 624 connects to the collector terminal of transistor 628 as shown. The base of transistor 628 connects to voltage node 620, while the emitter terminal connects to ground through resistor 632. This configuration isolates the sensitive node (bus node 616) from node 640.

[0026] FIG. 6B illustrates an exemplary inter-die communication system with associated drivers. This embodiment illustrates a bus 616 interconnecting a first die 640 and a second die 644. The die may include channel processing elements or may be part of an error checker or sequence generator. A pull-up resistor 612 is also illustrated connected to the bus 616 and a voltage node 608. The second die 644 is configured to use a transmit enable subcircuit 648 and a transmit disable subcircuit 652 in a transmit mode. A signal 654 to be transmitted to the bus 616 is provided to the input 668 to enable a current source 660. During the transmit disable mode, the current source 662 is shut off and the input 664 is tied to ground.

[0027] During the receive activation mode, the first die 640 receives a signal 670 over the bus 616 and provides it to an output 672. During the receive activation mode, a current source 674 is activated. During the receive deactivation mode, a current source 680 is turned off. Figure 6B shows one representative circuit of the driver and bus system, and it is contemplated that other circuit configurations may be produced that deviate from this exact circuit but do not depart from the claims.

[0028] FIG. 7 illustrates a bus layout geometry for a die using multiple optical subsystems. This is just one possible bus layout, and other embodiments are possible without departing from the scope of the following claims. Elements described above or known in the prior art will not be described in detail, but instead will focus on new aspects. The illustrated die 704 is configured with four channels, referenced as channel 0, channel 1, channel 2, and channel 3. The system may be configured as a transmitter or receiver, although this is generally defined. Optical fibers 716A, 716B, 716C, and 716D connect to or provide signals to the die 704 and route optical signals to portions of the optical subsystems 704A, 704B, 704C, and 704D of each channel. The optical subsystems 704A, 704B, 704C, and 704D convert the optical signals to electrical signals that are provided to electrical subsystems 708A, 708B, 708C, and 708D when the system is configured as a receiver. An example of such an optical subsystem is a photodetector coupled with a transimpedance amplifier (TIA). The electrical subsystems 708A, 708B, 708C, and 708D process signals to recover clock and data signals that are provided to downstream components at outputs 740A, 740B, 740C, and 740D. If configured as a transmitter, the electrical subsystem 708 prepares data for transmission and provides the data to the optical subsystem 704, which transmits the data through the optical fiber 716. Examples of such optical subsystems include, but are not limited to, a modulator driver using silicon photonics components or a laser driver using a laser. Other implementations are possible.

[0029] A shared diagnostic subsystem 712 is shown associated with each channel. A novel method of bus routing is shown such that a data path 730 utilized by the shared diagnostic subsystem 712 is provided under either the main power pad ring 720 or the ground pad ring 724. Similarly, a clock path 734 utilized by the shared diagnostic subsystem 712 is provided under either the main power pad ring 720 or the ground pad ring 724. As shown, the data path 730 and clock path 734 connect to each channel as shown.

[0030] Placing the data path 730 and clock path 734 under the ground pad ring 724 and power pad ring 720 provides several advantages. The data path 730 and clock path 734 are high speed communication paths that, as such, require controlled impedance traces and occupy a large amount of space due to the wavelength of the signals traveling along these paths. One such advantage is that the space is currently unused and the ground pad ring 724 and power pad ring 720 are low impedance, ideal for use as a reference for transmission lines. Additionally, this area generally has enough space for the size of the data path 730 and clock path 734 without the signals being disturbed.

[0031] FIG. 8 shows representative signal plots resulting from high speed communication over the diagnostic signal bus. These plots show eye diagrams of the recovered data sent to the error checker or transmitted sequence signals sent over the bus utilized by the diagnostic system communicating with each channel. Plot 800 is shown by ATLC electromagnetic analysis modeling software. As can be seen from these plots, the data signals, generated sequence signals, and clock signals are properly recovered after being sent over the bus.

[0032] As various embodiments of the invention are described, it will be apparent to one of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of the invention. In addition, various features, elements and embodiments described below may be claimed or combined in any combination or arrangement.

Claims

1. A shared bus for inter-channel communication, two or more channels having signal processing elements; Each channel is configured to receive and process a receive channel specific signal; The shared bus for inter-channel communication includes: a sequence generator configured to generate appropriate test sequences for testing the signal processing elements of a channel; an error checker configured to perform an error check on the received channel specific signal; a shared bus connected to the two or more channels; The shared bus is transmitting the receiving channel identification signal to the error checker; communicating said test sequence to said signal processing elements of a channel; The shared bus for inter-channel communication includes: The shared bus for inter-channel communication further comprising one or more electrical load circuits connected to the shared bus.

2. 2. The shared bus for inter-channel communication according to claim 1, wherein said bus is formed by a clock signal path and a data signal path.

3. 2. The shared bus for inter-channel communication of claim 1, wherein the test sequence is a pseudo-random bit sequence.

4. the electrical load circuit being selected to optimize reflections and jitter; 2. The shared bus for inter-channel communication of claim 1, wherein the electrical load circuit comprises an active load including one or more resistors, a combination of one or more peaking inductors and resistors, or one or more active devices including but not limited to bipolar or HBT CMOS transistors.

5. 2. The shared bus for inter-channel communication of claim 1, wherein the error checker is configured to compare the received channel-specific signal with a known channel-specific signal generated by the sequence generator to detect errors.

6. 2. The shared bus for inter-channel communication of claim 1, wherein each channel has a bus interface including open-collector current-mode logic drivers in a cascode arrangement.

7. A method for communication between channels over a shared bus, comprising: initializing an error checking mode for a selected channel; enabling selected channels to transmit or receive data over the shared bus; disabling non-selected channels from transmitting or receiving data over the shared bus; generating sequence data using a sequence generator; transmitting the sequence data from the sequence generator to the selected channel via the shared bus; processing the sequence data with the selected data to generate processed sequence data; and checking the processed sequence data for errors by comparing the processed sequence data with the sequence data.

8. 8. The method of claim 7, wherein the bus is formed by a clock signal path and a data signal path.

9. The method of claim 7, wherein the sequence data is a pseudo-random bit sequence.

10. 8. The method of claim 7, wherein the size, location and number of pull-up resistors are selected to optimize reflections and jitter.

11. 8. The method of claim 7, wherein the error checker is configured to compare a received channel-specific signal with a known channel-specific signal generated by the sequence generator to detect errors.

12. 8. The method of claim 7, wherein each channel has a bus interface including an open-collector current-mode logic driver in a cascode arrangement.

13. A channel-to-channel communication system, comprising: two or more data communication channels, each having a data processing section; a bus driver associated with each channel; The bus driver: Connect or disconnect from the bus, configured to transmit or receive data over the shared bus; a shared bus connecting said bus drivers associated with each channel; The shared bus also connects to at least one of an error checker and a sequence generator configured to generate sequence data.

14. 14. The communication system of claim 13, wherein the shared bus is a dual conductive bus consisting of a clock signal path and a data signal path.

15. 14. The communications system of claim 13, wherein the sequence generator is configured to generate a pseudo-random bit sequence and to transmit the pseudo-random bit sequence over the shared bus using a bus driver associated with the sequence generator.

16. The communication system of claim 13 , further comprising two or more pull-up resistors connected to the shared bus.

17. 14. The communication system of claim 13, wherein the error checker is configured to process the sequence data generated by the sequence generator after processing by the data processing unit to detect errors.

18. 14. The communication system of claim 13, wherein the bus driver comprises an open-collector current-mode logic driver in a cascode arrangement.

19. 14. The communication system of claim 13, wherein the communication system includes one or more termination resistors connected to the shared bus to reduce reflections and jitter.

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