Power Converter Control

Abstract

In some examples, the circuit includes a state machine. The state machine is configured to operate in a first state (202) where the state machine gates a pulse width modulated (PWM) signal provided for control of the power converter according to a first signal provided by a voltage control loop. The state machine is configured to operate in a second state (204) where the state machine gates the PWM signal according to a second signal provided by a current limit comparator. The state machine is configured to transition from the first state to the second state in response to the second signal being asserted after the first signal is asserted in a switching cycle of the power converter. The state machine is configured to transition from a current state to the first state in response to the first signal being asserted after the second signal in a switching cycle of the power converter.

Description

[Technical field]

[0001] A switched mode power supply (SMPS) transfers power from an input power source to a load by switching one or more power transistors or other switching elements coupled to an energy storage element (such as an inductor, a transformer inductance, and / or a capacitor) that can be coupled to the load via a switch node / terminal. The power transistors can be included in a power converter that includes the energy storage element or can be coupled to the energy storage element. The SMPS can include a SMPS controller for providing one or more gate drive signals for switching the power transistors. The switching of the power transistors can be controlled based on the current through the power converter. Summary of the Invention

[0002] In some examples, the circuit includes a state machine. The state machine is configured to operate in a first state where the state machine gates a pulse width modulated (PWM) signal provided for control of the power converter according to a first signal provided by a voltage control loop. The state machine is configured to operate in a second state where the state machine gates the PWM signal according to a second signal provided by a current limit comparator. The state machine is configured to transition from the first state to the second state in response to the second signal being asserted after the first signal is asserted in a switching cycle of the power converter. The state machine is configured to transition from a current state to the first state in response to the first signal being asserted after the second signal in a switching cycle of the power converter.

[0003] In some examples, the circuit includes a first comparator, a current sensing element, a second comparator, and a state machine. The first comparator has a first output, a first input, and a second input, the first input adapted to be coupled to an output of the power converter and the second input configured to receive a voltage ramp signal. The current sensing element has a current sensing input and a current sensing output, the current sensing input adapted to be coupled to the power converter. The second comparator has a second output, a third input, a fourth input, and a blanking input, the third input coupled to the current sensing output, the fourth input configured to receive a current limit threshold signal, and the blanking input configured to receive a blanking signal. The state machine is coupled to the first output and the second output and configured to provide a PWM signal for controlling the power converter based on the signal at the first output and the signal at the second output.

[0004] In some examples, a system includes a load and a switching mode power supply (SMPS). The SMPS includes a power converter coupled to the load and configured to switch power to the load based on control exerted by the SMPS. The SMPS is configured to implement a state machine, where the state machine is configured to operate in a first state to gate a PWM signal provided for control of the power converter according to a first signal. The state machine is configured to operate in a second state to gate the PWM signal according to a second signal. The state machine is configured to transition from the first state to the second state in response to the second signal being asserted after the first signal is asserted in a switching cycle of the power converter. The state machine is configured to transition from a current state to the first state in response to the first signal being asserted after the second signal in a switching cycle of the power converter. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram of an example system.

[0006] [Diagram 2] FIG. 2 is an example state diagram of a state machine.

[0007] [Diagram 3] 2 is an example signal diagram of signals that may be provided in a SMPS.

[0008] [Figure 4] 2 is an example signal diagram of signals that may be provided in a SMPS. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In some device architectures, a switched mode power supply (SMPS) may include or be coupled to an output capacitor in parallel with a load. An SMPS controller switches power transistors to form a circuit configuration with an energy storage element to provide a load current to the load and / or the output capacitor to maintain a regulated output voltage. Alternatively, although not shown herein, at least some of the power transistors may be implemented as passive switches, such as diodes. The power transistors may be coupled to an energy storage inductor via a switch node / terminal during charging and / or discharging switching states of the power converter. In at least some examples, the energy storage inductor is switched by the SMPS controller between a charging switching state and a discharging switching state to provide an inductor current (e.g., a current through the energy storage inductor) to the load and the output capacitor to maintain a regulated output voltage. As mentioned above, in at least some examples, one or more of the power transistors are replaced by a passive switch that reacts based on characteristics of a received input signal and is not switched by the SMPS controller. In some examples, the SMPS may be configured to operate as a constant current source with an energy storage element but no output capacitor. A power converter periodically cycles through a sequence of switching states (such as "on" and "off" states). A single on / off cycle is sometimes referred to as a switching cycle.

[0010] The power transistors may be implemented as field effect transistors (FETs), such as metal oxide field effect transistors (MOSFETs), or any other suitable solid-state transistor devices (e.g., bipolar junction transistors (BJTs), etc.). The power converters may be of various architectures, each having a particular function, such as buck-boost and buck-boost, among others. Depending on the application in which the buck-boost converter is used, the input voltage (VIN) and / or output voltage (VOUT) of the power converter may vary. To address this, the SMPS controller controls the buck-boost converter to operate in different operating modes. For example, based on VIN being greater than VOUT, the SMPS controller operates the power converter in a buck mode of operation. Based on VIN being less than VOUT, the SMPS controller operates the power converter in a boost mode of operation. Based on VIN approximately equal to VOUT, the SMPS controller operates the power converter in a buck-boost mode of operation, or in alternating cycles of buck and boost mode operation. The above examples are non-exclusive and generally apply to power converters with a buck-boost topology or architecture. However, at least some of the above examples also apply to power converters of other topologies or architectures, such as buck or boost, operating under specific control modes.

[0011] To control the operating mode of the power converter, the SMPS controller provides gate control signals to one or more power transistors of the power converter. The gate control signals received by the power transistors control whether the power transistors are in a conducting state (e.g., turned on) or a non-conducting state (e.g., turned off). Each state of the power converter includes a particular combination of conducting and non-conducting transistors. To change the operating mode of the power converter, the SMPS controller alters the sequence of switching states that it instructs the transistors to assume. In at least some examples, the SMPS controller implements a state machine or other logic such that the value of the gate control signal is determined based on or for the operating mode of the power converter. Also, while remaining in the operating mode of the power converter, the SMPS controller may alter the value of one or more of the gate control signals to alternately turn on and off one or more power transistors.

[0012] In some instances, the energy storage element may saturate. For example, if the energy storage element is an inductor, the energy storage element may saturate such that the magnetic flux of the inductor does not increase incrementally as the current through the inductor increases. This inductor saturation can result in an uncontrolled increase in inductor current. The uncontrolled increase in inductor current can then damage or otherwise adversely affect a load receiving VOUT from the SMPS. Repeated inductor saturation can also change the operating characteristics of the inductor (such as its saturation point) and damage or adversely affect the inductor. To protect against saturation of the energy storage element, a current limit may be implemented in the SMPS. For example, the SMPS may implement a valley or peak sense current limit of the energy storage element. However, control based on a sensed current limit may have certain drawbacks, such as at low duty cycle operation or while operating at high switching frequencies. For example, in each operating condition, the delay between sensing the current and making a control decision based on the sensed current may be greater than the time period available for the SMPS controller to provide a pulse-width modulated (PWM) signal that causes the current in the energy storage element to overshoot the programmed current limit.

[0013] Various examples of control schemes for controlling a power converter are described herein. In some examples, the power converter may be a component of an SMPS. The control schemes may be implemented in a controller, which may be a component of an SMPS or may be adapted to be coupled to an SMPS. For example, the controller may implement a state machine, such as a digital finite state machine, to control the power converter in accordance with the described control schemes. In at least some examples of the described control schemes, two operating modes are defined. The first operating mode is a normal operating mode and the second operating mode is a current-limited operating mode. In at least some examples, the state machine may receive an input signal from a PWM comparator that compares a signal having a value based on the output voltage of the power converter to a reference signal, such as a voltage ramp signal (Vramp). The state machine may also receive an input signal from a current-limit comparator that compares a sensed current in an energy storage element of the power converter to a programmed current-limit threshold. The PWM comparator may provide a signal LOOP, and the current-limit comparator may provide a signal CURRENT, each of which is an active low signal for purposes of this description.

[0014] The current limit comparator may be gated by a blanking signal (BLANK), which is also an active low signal for purposes of this description. For example, while BLANK is asserted, the current limit comparator may be prevented from providing CURRENT to have an asserted value, regardless of the value of the sensed current of the energy storage element of the power converter or the current limit threshold. By varying the amount of time BLANK is asserted, the current limit comparator may be blocked for a programmed time of BLANK, regardless of the minimum on-time of the power converter. The programmed time may be based on the switching frequency of the power converter, thereby increasing the accuracy of the current limit control of the power converter, such as by increasing the noise immunity of the control of the power converter. In some examples, the assertion of BLANK may further take into account other circuit conditions. For example, whether to assert BLANK may be determined at least in part according to a sensor output, a signal, various programmed circuit protections or operating schemes, etc. For example, a microcontroller or other processing component such as a digital logic device may receive signals and provide a BLANK having a value determined based on those received signals and the particular use case for which the BLANK is used.

[0015] In at least some examples, the state machine may be configured to provide a PWM signal having an asserted value in response to a second one of LOOP and CURRENT being asserted during a switching cycle of the power converter. During the normal operating mode described above, the PWM signal provided by the state machine to pulse the power converter is gated by LOOP. For example, CURRENT may be asserted, then LOOP is asserted. In at least some examples, CURRENT may be asserted only while BLANK is also asserted. In the normal operating mode, the PWM signal provided by the state machine may be asserted based on LOOP being asserted. Also, while operating in the normal operating mode, BLANK may be asserted on a falling edge (e.g., deasserted) of the PWM signal provided by the state machine, and may be deasserted in response to CURRENT being deasserted. When CURRENT is asserted after LOOP is asserted, the PWM signal provided by the state machine may be asserted based on the assertion of OCP_RAW, and the state machine may transition to a current-limit mode of operation. In a current-limit mode of operation, the PWM signal provided by the state machine may be asserted based on CURRENT being asserted. Also, while operating in a current-limit mode of operation, the amount of time that BLANK is asserted may be programmable to prevent OCP_BLANK from being asserted for a programmed amount of time. When LOOP is asserted after CURRENT is asserted, the PWM signal provided by the state machine may be asserted again based on the assertion of LOOP, and the state machine may transition back to a normal mode of operation. In at least some examples, the programmability of BLANK facilitates operation of the power converter over a variety of switching frequencies, providing precise control based on CURRENT while limiting adverse effects on the power converter's transient performance.

[0016] FIG. 1 illustrates a block diagram of an example system 100. In at least one example, the system 100 includes an SMPS 102 including a controller 104 and a power converter 106. The SMPS 102 switches power provided to the SMPS 102 as VIN to a load 108 via the power converter 106. In some examples, the SMPS is adapted to be coupled to the load 108 at an output terminal of the SMPS 102. In some examples, the power converter 106 is a buck power converter. In other examples, the power converter 106 is a buck-boost power converter that may operate according to a buck mode of operation, a boost mode of operation, and / or a buck-boost mode of operation. In other examples, the power converter 106 is a boost power converter. A buck power converter implementation is assumed for purposes of the description herein. In at least one example, the controller 104 is adapted to include or be coupled to a PWM comparator 111, a current limit comparator 112, and a state machine 114. In some examples, the power converter 106 is also adapted to be coupled to the capacitor 115. The controller 104 may further include or be adapted to be coupled to a driver 116 and a current sensing element 118. In other examples, the current sensing element 118 is a component of the power converter 106. The power converter 106 includes a power transistor 120 and a power transistor 122 and is adapted to be coupled to an inductor 124. The SMPS 102 herein is shown and described as implementing valley-mode constant on-time control for the power converter 106. However, other control methods are possible, such as peak current mode control, average current mode control, voltage mode control, or any other suitable form of control implemented in a fixed frequency method, a variable frequency method, a constant time method (e.g., constant Ton or constant Toff), etc.

[0017] At least one example of the SMPS 102 includes at least some aspects of the controller 104 and the power converter 106 on the same semiconductor die and / or in the same component package (or encapsulation), while in other examples the controller 104 and the power converter 106 may be fabricated separately and adapted to be coupled together. For example, at least some aspects of the controller 104 may be fabricated separately and coupled together. Thus, while shown as including the driver 116, in at least one example the controller 104 does not include the driver 116, but rather is adapted to be coupled to the driver 116. Similarly, other components shown as included in the controller 104 may be adapted to be coupled in whole or in part to the controller 104 and not included on the same semiconductor die and / or in the same component package as the controller 104. Similarly, components shown or described herein as being included in the power converter 106 (such as an inductor) may be adapted to be coupled in whole or in part to the power converter 106 and may not be included on the same semiconductor die and / or in the same component package as the power converter 106.

[0018] In at least one example architecture of the system 100, the PWM comparator 111 has a first input terminal (e.g., a positive or non-inverting input terminal), a second input terminal (e.g., a negative or inverting input terminal), and an output terminal. The first input terminal of the PWM comparator Ill is coupled to a node 125 to which VOUT is provided, the second input terminal of the PWM comparator 111 is configured to receive Vramp, and the output terminal of the PWM comparator Ill is coupled to the state machine 114. In at least some examples, the node 125 is an output terminal of the SMPS 102. In at least some examples, one or more components or circuits are coupled between the first input terminal of the PWM comparator 111 and the node 125, such as a loop compensation circuit or component, a slope compensation circuit or component, etc. The current limit comparator 112 has a first input terminal (e.g., a positive or non-inverting input terminal), a second input terminal (e.g., a negative or inverting input terminal), and an output terminal. A first input terminal of the current limit comparator 112 is coupled to the current sensing element 118, a second input terminal of the current limit comparator 112 is configured to receive a current limit threshold signal (shown in FIG. 1 as CURRENT_LIMIT), and an output terminal of the current limit comparator 112 is coupled to the state machine 114. The current limit comparator 112 further has a control input configured to receive BLANK. The state machine 114 has an output terminal adapted to be coupled to an input terminal of a driver 116, which has an output terminal adapted to be coupled to a node 125. The capacitor 115 is adapted to be coupled between the node 125 and ground. The power transistor 120 has a gate terminal configured to be coupled to the node 125, a drain terminal configured to receive VIN, and a source terminal coupled to a node 126. The power transistor 122 has a gate terminal configured to be coupled to the node 125, a drain terminal configured to be coupled to ground, and a source terminal coupled to the node 126. The inductor 124 is adapted to be coupled between a node 126 and a node 125 .Current sensing element 118 is coupled to inductor 124 or otherwise adapted to sense the current in inductor 124. In at least some examples, controller 104, or any one or more components of controller 104, and / or current sensing element 118, may be collectively referred to as a voltage control loop, such that the voltage provided at node 125 (or the PWM on which the voltage provided at node 125 is based) is controlled by the voltage control loop.

[0019] In an example of operation of system 100, state machine 114 provides PWM based on a decision made by state machine 114 based at least in part on LOOP and CURRENT. Based on PWM, driver 116 is configured to drive power transistor 120 and power transistor 122. For example, in response to assertion of PWM, driver 116 is configured to drive power transistor 120 to cause power transistor 120 to conduct and conduct current from the power source from which VIN is received to node 126 to energize inductor 124. While PWM is asserted, driver 116 is also configured to drive power transistor 122 to cause power transistor 122 to be non-conductive between node 126 and ground. In response to de-assertion of PWM, driver 116 is configured to drive power transistor 120 to cause power transistor 120 to be non-conductive between the power source from which VIN is received and node 126. Additionally, while PWM is de-asserted, driver 116 is configured to drive power transistor 122 to cause power transistor 122 to conduct between node 126 and ground and to de-energize inductor 124.

[0020] The PWM comparator 111 receives a signal representative of VOUT (or in some examples receives VOUT) at a first input terminal of the PWM comparator 111. The PWM comparator 111 compares the signal representative of VOUT to Vramp. In response to the signal representative of VOUT having a value that does not exceed the value of Vramp, the PWM comparator 111 provides the loop with an asserted value. In response to the signal representative of VOUT having a value that exceeds the value of Vramp, the PWM comparator 111 provides the loop with a deasserted value. The current limit comparator 112 receives a signal, shown in FIG. 1 as IL, representative of the inductor current of the inductor 124 from the current sensing element 118 at a first input terminal of the current limit comparator 112. The current limit comparator 112 compares IL to CURRENT_LIMIT. In response to IL having a value that does not exceed CURRENT_LIMIT, current limit comparator 112 provides CURRENT having an asserted value while BLANK has an asserted value. In response to IL having a value that exceeds CURRENT_LIMIT, current limit comparator 112 provides CURRENT having a deasserted value while BLANK has an asserted value. In response to BLANK having a deasserted value, current limit comparator 112 provides CURRENT having a deasserted value.

[0021] In at least some examples, state machine 114 is configured to provide a PWM having an asserted value in response to the second of LOOP and CURRENT having an asserted value. Operation of state machine 114 is further described below with respect to FIG.

[0022] 2 illustrates an example state diagram 200 of the state machine 114. The state diagram 200 represents, in at least some examples, the states and state transitions of at least one implementation of the state machine 114 of FIG. 1. At least some examples of the state machine 114 are configured to implement a normal state 202 and a current-limited state 204.

[0023] While operating in the normal state 202, the state machine 114 is configured to control the power converter 106 to operate in a normal operating mode in which the state machine 114 gates the PWM according to LOOP. For example, while operating in the normal state 202, in a given switching cycle of the power converter 106, the state machine 114 may receive LOOP having an asserted value after already receiving CURRENT having an asserted value in the same switching cycle. Based on receiving LOOP as the second of LOOP and CURRENT to be asserted, the state machine 114 provides the PWM having an asserted value. In some examples of operation in the normal state 202, the state machine 114 receives CURRENT as the second of LOOP and CURRENT to be asserted. In response to receiving CURRENT as the second of LOOP and CURRENT to be asserted, the state machine 114 transitions from the normal state 202 to the current-limit state 204.

[0024] While operating in the current-limit state 204, the state machine 114 is configured to control the power converter 106 to operate in a current-limit mode of operation in which the state machine 114 gates the PWM according to CURRENT. For example, while operating in the current-limit state 204, in a given switching cycle of the power converter 106, the state machine 114 may receive CURRENT with an asserted value after already receiving LOOP with an asserted value in the same switching cycle. Based on receiving CURRENT as the second of LOOP and CURRENT to be asserted, the state machine 114 provides the PWM with an asserted value. In response to the state machine 114 receiving LOOP as the second of LOOP and CURRENT to be asserted, the state machine 114 transitions from the current-limit state 204 back to the normal state 202.

[0025] 3 illustrates an example signal diagram 300 of signals that may be provided in the SMPS 102. The signal diagram 300 illustrates, in at least some examples, PWM, BLANK, CURRENT, LOOP, IL, and CURRENT_LIMIT, each of which are described above. The signal diagram 300 corresponds, in at least some examples, to the operation of the state machine 114 beginning in the normal state 202 and transitioning to the current limit state 204.

[0026] As shown by signal diagram 300, in normal state 202, state machine 114 provides PWM for a pulsed period based on the assertion of LOOP. While operating in normal state 202, BLANK is configured to be asserted in response to a deassertion (e.g., falling edge) of PWM. While BLANK is asserted, CURRENT is permitted to be asserted by current limit comparator 112. For example, while BLANK is asserted, CURRENT may be asserted for a pulsed period in response to IL being less than or equal to CURRENT_LIMIT. While BLANK is not asserted, current limit comparator 112 is inhibited or blocked from providing CURRENT with an asserted value.

[0027] As further illustrated by signal diagram 300, in response to the assertion of CURRENT being delayed to cause the second of LOOP and CURRENT to be asserted, the state machine 114 provides PWM based on the assertion of CURRENT. For example, in response to the current drawn by the load 108 increasing, IL also increases. As IL increases, the assertion of CURRENT begins to be delayed. Similarly, if the current drawn by the load 108 is greater than CURRENT_LIMIT, the frequency of assertion of LOOP may increase to provide greater amounts of energy to the load 108. In response to the state machine 114 providing PWM based on the assertion of CURRENT, the state machine 114 transitions from the normal state 202 to the current-limit state 204, as illustrated by signal diagram 300. While operating in the current-limit state 204, the time period during which BLANK is not asserted, thereby blocking the assertion of CURRENT, is altered according to a programmed value. The programmed value may be determined based on any suitable factors, such as the switching frequency of the power converter 106, the duty cycle of the PWM, and board noise of a circuit board that includes at least some of the components of the SMPS 102.

[0028] In at least some examples, modifying the time period during which BLANK is not asserted provides a degree of noise immunity to the SMPS 102. For example, in a system that does not include BLANK, CURRENT may be asserted in response to IL momentarily crossing the CURRENT_LIMIT threshold due to signal noise or other external influences. In some examples, when an inductor, such as the inductor 124 in a power converter, has a high inductance, the inductor may conduct and de-conduct with a current that has a small slope. Such examples may be susceptible to inaccurate assertion of CURRENT in the absence of BLANK, as described herein. These assertions of CURRENT resulting from signal noise may increase IL beyond the value for which the SMPS 102 is configured, potentially damaging components of the SMPS 102 and / or the load 108. Also, by preventing the assertion of CURRENT for a programmable amount of time, the state machine 114 is prevented from providing a PWM with an asserted value. In at least some instances, this is advantageous in low duty cycle or high switching frequency applications of the SMPS 102. For example, in low duty cycle or high switching frequency applications, there may be a delay between the change in current in the inductor 124 and the rendering of a decision by the current limit comparator 112 based on IL and CURRENT_LIMIT (provided as a value of CURRENT). This delay may mean that by the time the current limit comparator 112 makes its decision, the state machine 114 has already provided another asserted PWM pulse. However, the state machine 114 may then receive a delayed assertion of CURRENT after PWM has been deasserted, causing the state machine 114 to provide yet another asserted pulse of PWM just (or just after) the minimum off-time for the power converter 106 in response to LOOP being asserted. This can cause the current in the power converter 106 to overshoot the programmed value set based on the CURRENT_LIMIT, sometimes by a large amount, potentially damaging the SMPS 102 and / or the load 108.You can prevent this overshoot by preventing the assertion of CURRENT for a programmed amount of time, according to BLANK.

[0029] 4 illustrates an example signal diagram 400 of signals that may be provided in the SMPS 102. The signal diagram 400 illustrates, in at least some examples, PWM, BLANK, CURRENT, LOOP, IL, and CURRENT_LIMIT, each of which are described above. The signal diagram 400 corresponds, in at least some examples, to the operation of the state machine 114 beginning in the current limit state 204 and transitioning to the normal state 202.

[0030] As illustrated by signal diagram 400, in current-limit state 204, state machine 114 provides PWM for a pulsed time period based on the assertion of CURRENT. While operating in current-limit state 204, BLANK is configured to be asserted for a programmed time period after deassertion, which occurs substantially simultaneously with the deassertion of CURRENT. While BLANK is asserted, CURRENT is permitted to be asserted by current-limit comparator 112. For example, CURRENT may be asserted for a pulsed period while BLANK is asserted and in response to IL being less than or equal to CURRENT_LIMIT. While BLANK is not asserted, current-limit comparator 112 is inhibited or blocked from providing CURRENT with an asserted value. In at least some examples, such blocking prevents current-limit comparator 112 from inaccurately providing multiple assertions of CURRENT substantially in quick succession. Such multiple incorrectly provided assertions of CURRENT may result from an accurate decision (and assertion of CURRENT) of the current limit comparator 112, which may be followed by one or more incorrect decisions (and assertions of CURRENT) of the current limit comparator 112, such as due to noisy IL.

[0031] As further shown by signal diagram 400, in response to the assertion of LOOP being delayed so that it becomes the second of CURRENT and LOOP to be asserted, the state machine 114 provides a PWM based on the assertion of LOOP. In response to the state machine 114 providing a PWM based on the assertion of LOOP, the state machine 114 transitions from the current-limit state 204 back to the normal state 202, as shown by signal diagram 400. While operating in the normal state 202, BLANK may become asserted in response to a deassertion (e.g., a falling edge) of PWM and may become deasserted in response to a deassertion of CURRENT.

[0032] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, then (A) in a first example, device A is directly coupled to device B, or (B) in a second example, device A is indirectly coupled to device B via an intervening component C, where intervening component C does not substantially change the functional relationship between device A and device B, and thus device B is controlled by device A via a control signal provided by device A.

[0033] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by a manufacturer to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the hardware components, through the interconnections of the device, or through a combination thereof.

[0034] A circuit or device described herein as including certain components may be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure either during manufacture or after manufacture, for example, by an end user and / or a third party.

[0035] Although certain components may be described herein as being of a particular process technology, these components may be replaced with components of other process technologies. The circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to that available prior to the component replacement. A component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown, unless otherwise noted. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series or parallel between the same two nodes as a single resistor or capacitor.

[0036] Use of the phrase "ground voltage potential" in this description includes chassis ground, ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of this description. Unless otherwise specified, "about," "approximately," or "substantially" preceding a value means ±10% of the stated value.

[0037] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. 1. A circuit comprising:

1. A state machine comprising: operating in a first state to gate a pulse width modulated (PWM) signal provided for control of the power converter according to a first signal provided by a voltage control loop; operating in a second state to gate the PWM signal according to a second signal provided by a current limit comparator configured to be gated by a blanking signal having an assertion time based on a switching frequency of the power converter; transitioning from the first state to the second state in response to the second signal being asserted after the first signal is asserted during a switching cycle of the power converter; transitioning from the second state to the first state in response to the first signal being asserted after the second signal in a switching cycle of the power converter. A circuit comprising the state machine, configured as follows:

2. 2. The circuit of claim 1, The circuit, wherein the voltage control loop is configured to compare an output voltage of the power converter to a voltage ramp to determine an output to provide as the first signal.

3. 2. The circuit of claim 1, The circuitry is configured to compare a value of a signal representative of current flowing through the power converter to a current limit threshold to determine an output to provide as the second signal.

4. 2. The circuit of claim 1, A circuit wherein, in the first state, the blanking signal is asserted in response to a deassertion of the PWM signal, and is deasserted a programmed amount of time after assertion.

5. 2. The circuit of claim 1, The circuit wherein, in the second state, the blanking signal is deasserted in response to a deassertion of the second signal, and is asserted a programmed amount of time after assertion.

6. 2. The circuit of claim 1, A circuit configured such that the current limit comparator is prevented from providing the second signal having an asserted value while the blanking signal has an asserted value.

7. 1. A circuit comprising: a first comparator having a first output, a first input adapted to be coupled to the output of the power converter, and a second input configured to receive a voltage ramp signal; a current sense element having a current sense input adapted to be coupled to the power converter and a current sense output; a second comparator having a second output, a third input coupled to the current sense output, a fourth input configured to receive a current limit threshold signal, and a blanking input configured to receive a blanking signal; a state machine coupled to a first output and a second output, the state machine configured to provide a pulse width modulated (PWM) signal for controlling the power converter based on a signal at the first output and a signal at the second output; The circuit includes:

8. 8. The circuit of claim 7, The circuitry, wherein the second comparator is configured to be prevented from asserting the signal at the second output in response to the blanking signal being asserted.

9. 8. The circuit of claim 7, The circuit, wherein the state machine is further configured to operate in a first state in response to the PWM signal being provided based on the signal at the first output.

10. 10. The circuit of claim 9, The circuit wherein, while the state machine is operating in the first state, the blanking signal is asserted for a pulsed period in response to deassertion of the PWM signal.

11. 8. The circuit of claim 7, The circuit, wherein the state machine is further configured to operate in a second state in response to the PWM signal being provided based on the signal at the second output.

12. 12. The circuit of claim 11, a blanking signal that is deasserted in response to a deassertion of the signal at the second output, and is asserted a programmed amount of time after deassertion, while the state machine is operating in the second state.

13. 1. A system comprising: Load and a switched mode power supply (SMPS) coupled to the load, the power converter configured to switch power to the load based on control exercised by the SMPS; operating in a first state to gate a pulse width modulated (PWM) signal provided for control of the power converter according to a first signal provided by a voltage control loop; operating in a second state to gate the PWM signal according to a second signal provided by a current limit comparator configured to be gated by a blanking signal having an assertion time based on a switching frequency of the power converter; transitioning from the first state to the second state in response to the second signal being asserted after the first signal is asserted in a switching cycle of the power converter; transitioning from a current state to a first state in response to the first signal being asserted after the second signal in a switching cycle of the power converter; the SMPS configured to implement the state machine configured to: Including, the system.

14. 14. The system of claim 13, The system, wherein the voltage control loop is configured to compare an output voltage of the power converter to a voltage ramp to determine an output to provide as the first signal.

15. 14. The system of claim 13, The system, wherein the current limit comparator is configured to compare a value of a signal representative of current flowing through the power converter to a current limit threshold to determine an output to provide as the second signal.

16. 14. The system of claim 13, The system, wherein in the first state, the blanking signal is asserted in response to a deassertion of the PWM signal and is deasserted a programmed amount of time after assertion.

17. 14. The system of claim 13, The system, wherein in the second state, the blanking signal is deasserted in response to a deassertion of the second signal and is asserted a programmed amount of time after assertion.

18. 14. The system of claim 13, The system, wherein the current limit comparator is configured to be prevented from providing the second signal having an asserted value while the blanking signal has an asserted value.

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