P-type field effect transistor (PFET) on silicon germanium (Ge) buffer layer and method of fabrication for increasing germanium (Ge) in PFET source and drain to increase compression of the PFET channel

Abstract

An exemplary high performance P-type field effect transistor (PFET) is disclosed that has a SiGe source (211S) and drain (211D) fabricated on a silicon (Si) germanium (Ge) (SiGe) buffer layer and has a Ge percentage higher than the threshold that causes dislocations at the Si substrate interface. The source and drain with a Ge percentage above 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. By forming the PFET (200) on a SiGe buffer layer (214) rather than directly on a Si substrate (216), dislocations are avoided in the source and drain lattices, and the SiGe buffer layer has a smaller Ge percentage than the Ge percentage in the source and drain. In one example, the lattice of the buffer layer is relaxed by injecting dislocations at the interface of the buffer layer and the Si substrate and annealing the buffer layer.

Description

[Technical field]

[0001] Priority Application

[0001] This application claims priority to U.S. patent application Ser. No. 17 / 180,219, entitled "P-TYPE FIELD EFFECT TRANSISTOR (PFET) ON A SILICON GERMANIUM (GE) BUFFER LAYER TO INCREASE GE IN THE PFET SOURCE AND DRAIN TO INCREASE COMPRESSION OF THE PFET CHANNEL AND METHOD OF FABRICATION," filed on February 19, 2021, the entire contents of which are incorporated by reference into this specification.

[0002] FIELD OF THE DISCLOSURE

[0002] The field of the disclosure relates generally to semiconductor devices, and more particularly, to fabricating high performance transistors on silicon substrates. [Background technology]

[0003]

[0003] A transistor is an electrical device that can switch and amplify electrical signals. A transistor is constructed from a semiconductor material and has three or four terminals. A voltage or current applied to one terminal can change the current flow between the other terminals. A field effect transistor (FET) is a type of transistor that consists of a source and a drain disposed on either side of a channel, and an insulated gate disposed over the channel to apply an electric field that changes the conductivity between the source and drain. The semiconductor materials of the source, drain, and channel are generally intrinsic semiconductor materials doped with impurities that have a different number of valence electrons per atom than the semiconductor. The impurities are selected to increase the concentration of either electrons or holes in the composite lattice structure to increase the electrical conductivity. The source and drain have a first type of doping, and the channel is doped with the opposite type.

[0004]

[0004] The addition of impurities can also increase or decrease the size of the semiconductor lattice structure. This size difference can be employed in a transistor to induce a tensile stress or compressive strain on the channel. Tensile stress in the semiconductor lattice stretches the atoms and increases the spacing between the valence electrons and the nucleus, which increases the mobility of electrons in the lattice structure. Alternatively, compressive strain on the lattice structure increases the hole mobility. These effects can be used in N-type FETs (NFETs) and P-type FETs (PFETs), respectively. However, extreme stress or strain can create defects in the lattice structure, which can become a path for current leakage in the transistor. Summary of the Invention

[0005]

[0005] Aspects disclosed herein include a P-type field-effect transistor (PFET) on a silicon (Si:silicon) germanium (Ge:germanium) (SiGe) buffer layer for increasing germanium (Ge) in the PFET source and drain to increase compression of the PFET channel. A method of fabricating a PFET on a SiGe buffer layer is also disclosed. The PFET includes a P-type source and drain and an N-type channel in which holes are the majority carriers. A compressive strain applied to the molecular lattice of the N-type channel increases the hole mobility in the N-type channel, which increases the current flow in the channel. The compressive strain is applied from both ends of the channel by a source and drain formed from a SiGe lattice with a lattice constant larger than the Si lattice of the N-type channel. The lattice constant of the SiGe lattice is increased by adding Ge to Si, and is larger as the Ge fraction increases. When the Ge fraction in the SiGe lattice of the source and drain reaches a threshold level, such that the SiGe lattice constant is much larger than that of the Si substrate lattice constant, the SiGe lattice grown on the Si substrate develops dislocations at the lattice interfaces. Dislocations are defects in the lattice that provide paths for current leakage through the source and drain, which prevents current flow through the PFET from being completely blocked.

[0006]

[0006] An exemplary high performance PFET with a SiGe source and drain having a Ge percentage higher than the threshold that causes dislocations at the Si substrate interface is fabricated on a SiGe buffer layer. The source and drain with a Ge percentage above 45% threshold provides increased compressive strain in the channel for higher performance of the PFET. Dislocations in the source and drain lattice are avoided by forming the PFET on a SiGe buffer layer rather than directly on a Si substrate, and the SiGe buffer layer has a smaller Ge percentage than the Ge percentage in the source and drain. In one example, the lattice of the buffer layer is relaxed by implantation to form dislocations at the interface between the buffer layer and the Si substrate and annealing the buffer layer. After the buffer layer lattice is relaxed, the mismatch in lattice size at the Si substrate interface does not create stress at the top surface of the buffer layer. The size difference between the SiGe lattice of the buffer layer and the SiGe lattice of the source and drain does not cause dislocations to occur. Thus, dislocation-induced leakage current is avoided even when the percentage of Ge in the source and drain epitaxial layers is at least 46 percent (%), and PFETs formed on relaxed SiGe buffer layers achieve higher performance.

[0007] In an exemplary embodiment, a semiconductor device is disclosed that includes a silicon substrate, a buffer layer, and a transistor. The buffer layer is disposed on the silicon substrate and includes a first percentage of Ge. The transistor is disposed on the buffer layer and includes a channel region, a gate, a source, and a drain. The channel region includes a semiconductor material. The gate is disposed on the channel region. The source is disposed on a first side of the channel region, and the drain is disposed on a second side of the channel region. The source and drain each include a SiGe compound that includes a second percentage of Ge that is greater than the first percentage, and the second percentage of Ge is at least 46 percent (%).

[0008]

[0008] In another exemplary aspect, a method of fabricating a semiconductor device is disclosed. The method includes forming a buffer layer on a silicon substrate, the buffer layer comprising silicon and a first percentage of Ge. The method further includes relaxing strain in the buffer layer and forming a semiconductor layer on the buffer layer. The method includes forming a first gate on the semiconductor layer. The method includes forming a first recess on a first side of the first gate and forming a second recess on a second side of the first gate, the first recess and the second recess each extending through the semiconductor layer to the buffer layer. The method includes forming a first composite of Si and Ge in the first recess and in the second recess, the first composite comprising a second percentage of Ge higher than the first percentage of germanium, the second percentage of Ge being at least 46 percent (%). [Brief description of the drawings]

[0009] [Figure 1]

[0009] A three-dimensional perspective view of a complementary metal-oxide-semiconductor (MOS) (CMOS) device including a P-type field effect transistor (FET) (PFET) and an N-type FET (NFET) formed on a silicon substrate. [Diagram 2]

[0010] FIG. 1 is a cross-sectional side view of a CMOS device including a PFET and an NFET formed on a silicon (Si) germanium (Ge) (SiGe) composite buffer layer and including greater than 45% Ge in the SiGe composite in the PFET source and drain for increased performance. [Diagram 3]

[0011] 3 is a flow chart of a method for fabricating the PFET and NFET of the CMOS device formed on the buffer layer shown in FIG. 2 . [Figure 4A]

[0012] 4 is a diagram of the fabrication steps in the method of fabricating the PFETs and NFETs in the CMOS device of FIG. 2, as shown in the flow chart in FIG. 3. [Figure 4B] 4 is a diagram of the fabrication steps in the method of fabricating the PFETs and NFETs in the CMOS device of FIG. 2, as shown in the flow chart in FIG. 3. [Figure 4C] 4 is a diagram of the fabrication steps in the method of fabricating the PFETs and NFETs in the CMOS device of FIG. 2, as shown in the flow chart in FIG. 3. [Figure 4D] 4 is a diagram of the fabrication steps in the method of fabricating the PFETs and NFETs in the CMOS device of FIG. 2, as shown in the flow chart in FIG. 3. [Figure 4E] 4 is a diagram of the fabrication steps in the method of fabricating the PFETs and NFETs in the CMOS device of FIG. 2, as shown in the flow chart in FIG. 3. [Figure 4F] 4 is a diagram of the fabrication steps in the method of fabricating the PFETs and NFETs in the CMOS device of FIG. 2, as shown in the flow chart in FIG. 3. [Figure 4G] 4 is a diagram of the fabrication steps in the method of fabricating the PFETs and NFETs in the CMOS device of FIG. 2, as shown in the flow chart in FIG. 3. [Figure 4H] 4 is a diagram of the fabrication steps in the method of fabricating the PFETs and NFETs in the CMOS device of FIG. 2, as shown in the flow chart in FIG. 3. [Figure 4I]4 is a diagram of the fabrication steps in the method of fabricating the PFETs and NFETs in the CMOS device of FIG. 2, as shown in the flow chart in FIG. 3. [Diagram 5]

[0013] FIG. 4I is a block diagram of an exemplary wireless communication device including a radio-frequency (RF) module that includes a CMOS device including the PFETs and NFETs shown in FIGS. 2 and 4I. [Figure 6]

[0014] FIG. 4I is a block diagram of an exemplary IC package including a CMOS device including a PFET and an NFET formed on a SiGe buffer layer and including greater than 45% Ge in the PFET source and drain for increased performance in accordance with any of the embodiments shown in FIG. 2 and FIG. 4I and disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010]

[0015] Several exemplary aspects of the present disclosure are now described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0011]

[0016] Embodiments disclosed herein include a P-type field effect transistor (PFET) on a silicon (Si) germanium (Ge) (SiGe) buffer layer for increasing germanium (Ge) in the PFET source and drain to increase compression of the PFET channel. A method for fabricating a PFET on a SiGe buffer layer is also disclosed. The PFET includes a P-type source and drain and an N-type channel in which holes are the majority carriers. A compressive strain applied to the molecular lattice of the N-type channel increases the hole mobility in the N-type channel, which increases the current flow in the channel. The compressive strain is applied from both ends of the channel by a source and drain formed from a SiGe lattice with a larger lattice constant than the Si lattice of the N-type channel. The lattice constant of the SiGe lattice is increased by adding Ge to Si, and is larger as the Ge fraction increases. When the fraction of Ge in the SiGe lattice of the source and drain reaches a threshold level, such that the SiGe lattice constant is much larger than that of the Si substrate lattice constant, the SiGe lattice grown on the Si substrate develops dislocations at the lattice interfaces. Dislocations are defects in the lattice that provide paths for current leakage through the source and drain, which prevents current flow through the PFET from being completely blocked.

[0012]

[0017] An exemplary high performance PFET with a SiGe source and drain having a Ge percentage higher than the threshold that causes dislocations at the Si substrate interface is fabricated on the SiGe buffer layer. The source and drain with a Ge percentage above 45% threshold provides increased compressive strain in the channel for higher performance of the PFET. By forming the PFET on the SiGe buffer layer rather than directly on the Si substrate, dislocations in the source and drain lattice are avoided, and the SiGe buffer layer has a smaller Ge percentage than the Ge percentage in the source and drain. In one example, the strain in the SiGe buffer layer is relaxed by intentional implantation to generate dislocations in the SiGe buffer layer, followed by a high temperature anneal to recrystallize the SiGe buffer layer. As a result of these processing steps, the dislocations generated in the SiGe buffer layer are trapped at the interface between the SiGe buffer layer and the Si substrate. After the buffer layer lattice is relaxed, the mismatch in lattice size at the Si substrate interface does not create stress at the top surface of the buffer layer. The size difference between the SiGe lattice of the buffer layer and the SiGe lattice of the source and drain does not cause dislocations to occur, so that the leakage current caused by dislocations is avoided even when the percentage of Ge in the source and drain epitaxial layers is at least 46 percent (%), and the PFET formed on the relaxed SiGe buffer layer achieves higher performance.

[0013]

[0018] Before describing an exemplary P-type field effect transistor (FET) (PFET) 200 in a complementary metal-oxide semiconductor (MOS) (CMOS) device 202 in FIG. 2, an example of a conventional CMOS device 100 will be described with reference to FIG. 1. FIG. 1 is a three-dimensional perspective view of a CMOS device 100 including a PFET 102P and an N-type FET (NFET) 102N formed on a silicon (Si) substrate 104. A CMOS device such as CMOS device 100 may be configured such that PFET 102P provides a binary "1" (e.g., a "2" at a power supply voltage V DD) and NFET 102N is better able to pass a "0" (e.g., ground voltage V SS ), it is often employed in two-valued logic.

[0014]

[0019] Structurally, PFET 102P includes a P-type source 106S and a P-type drain 106D on either side of an N-type well 108. An insulated gate 110 is disposed on the N-type well 108. NFET 102N includes an N-type source 112S and an N-type drain 112D on either side of a P-type well 114. An insulated gate 116 is disposed on a P-type well 114 formed in a Si substrate 104. Insulated gate 116 can be metal or highly conductive polysilicon. N-type well 108 is formed in an N-well 118 disposed in the Si substrate 104.

[0015]

[0020] The P-type source 106S and drain 106D of the PFET 102P are fabricated by etching out trenches 120 in the N-well 118 on either side of the insulated gate 110 and growing a P-type semiconductor compound 122 in the trenches 120. The P-type semiconductor compound 122 is formed as a SiGe (SiGe) lattice 124. One of the best ways to improve the performance of a PFET is to increase the hole mobility in the P-channel 125, which is induced at the top surface of the N-well 108. Since the P-channel 125 is formed in the N-well 108, the N-well 108 is also referred to herein as the channel region 108. The increase in hole mobility can be achieved by employing the SiGe lattice 124 in the P-type source 106S and P-type drain 106N to provide a compressive force on the N-well 108.

[0016]

[0021] The SiGe lattice structure is a combination of smaller Si atoms with larger Ge atoms, which results in a lattice that is larger than intrinsic Si. The SiGe lattice 124 has a lattice constant A 126 Lattice constant A is larger than 124The SiGe lattice 124 of the P-type semiconductor compound 122 is grown by epitaxy in the trench 120 to form the P-type source 106S and the P-type drain 106D, creating a compressive strain on either side of the N-type well 108. The compressive strain increases the hole mobility in the P-channel 125, which is induced in the N-type well 108. However, as the proportion of Ge in the P-type semiconductor compound 122 increases to a threshold value, the lattice constant A 124 is the lattice constant A 126 , dislocations form at the interface 128 of the SiGe lattice 124 and the Si lattice 126 of the Si substrate 104. The Ge fractions described herein are atomic percents based on the atomic ratio of Ge atoms to total atoms. In practice, the threshold is a Ge fraction of 45%. The compressive strain provided by the P-type source 106S and P-type drain 106D in the CMOS device 100 is limited by this Ge fraction threshold.

[0017]

[0022] FIG. 2 is a cross-sectional side view of an exemplary CMOS device 202 including a PFET 200 and an NFET 204, including a buffer layer 206 on a Si substrate 208. The performance of the PFET 200 is improved over the PFET 102P in FIG. 1 because the greater compression of the N-well 210 by the source 211S and drain 211D increases the hole mobility therein. The N-well 210 is formed from a semiconductor layer 212 disposed on the buffer layer 206. The semiconductor layer 212 is doped with a pentavalent impurity to become an N-type material from which the N-well 210 is formed. The N-well 210 is also referred to herein as a channel region 210 because a P-channel (not shown) is formed in the N-well 210 during operation of the PFET 200. The semiconductor layer 212 is removed from both sides of the N-well 210, and the source 211S and drain 211D are formed on either side of the N-well 210 from which the semiconductor layer 212 was removed. The source 211S and drain 211D are formed from epitaxial SiGe with a higher percentage of Ge than in the P-type source 106S and drain 106D in Figure 1 without creating dislocations. The higher percentage of Ge can be employed successfully because the source 211S and drain 211D are formed on a buffer layer 206 formed from SiGe with a lower percentage of Ge, rather than directly on the semiconductor layer 212.

[0018]

[0023] 1, dislocations are created at the interface 128 of the SiGe lattice 124 and the Si substrate 104 when the percentage of Ge in the SiGe lattice 124 reaches a Ge threshold (e.g., 45% Ge). This threshold indicates the point at which the difference between the size of the SiGe lattice 124 (e.g., of the P-type source 106S) and the size of the Si lattice 126 of the Si substrate 104 causes a mismatch that cannot be accommodated by compression or expansion of the respective lattices. When the difference in the lattice constants of the interfacing lattices becomes too large, dislocations occur at the interface. Thus, in FIG. 1, the lattice constant A of the SiGe lattice 124 is 45% Ge. 124 is the lattice constant A of the Si lattice 126. 126When the axial displacement becomes much larger than 0, the mismatch cannot be accommodated and dislocations form.

[0019]

[0024] To overcome the Ge fraction threshold in PFET 200, source 211S and drain 211D are formed on buffer layer 206. Source 211S and drain 211D have a lattice constant A 213 The buffer layer 206 includes an S / D lattice 213 having a lattice constant A 214 and has a lattice constant A 214 is the lattice constant A of the Si lattice 216 of the Si substrate 208 216 The lattice constant A of the S / D lattice 213 is larger than 213 With the BL lattice 214 between the Si lattice 216 and the S / D lattice 213, the dislocations are avoided as follows: The lattice constant A 214 and the lattice constant A of S / D lattice 213 213 The difference between the lattice constant A of the BL lattice 214 is not large enough to induce dislocations at the upper interface 217 where the buffer layer 206 intersects with the source 211S and drain 211D. 214 and the lattice constant A of Si lattice 216 216 is not large enough to cause dislocations at the lower interface 218 between the Si substrate 208 and the buffer layer 206.

[0020]

[0025] More specifically, the BL lattice 214 is composed of SiGe with a first percentage of Ge that is less than a second percentage of Ge in the source 211S and drain 211D. In one example, the first percentage is in the range of 12 to 18 percent (e.g., atomic percent) Ge. In one example, the BL lattice 214 is 15% Ge. The lattice constant A 214 The BL lattice 214 has a lattice constant A because Ge atoms are larger than Si atoms. 216 The BL grating 214 is disposed on the Si substrate 208 and has a thickness T of at least 1 micron. 214 This is achieved by using a thickness T of the Si substrate 208 of about 100 microns. 208Much smaller than the thickness T 214 Much thicker than thickness T 208 The Si lattice 216 has a thickness T 214 It is much less flexible than the BL lattice 214 of the 214 and A 216 The difference between the thickness T forces the more flexible BL lattice 214 to compress at the bottom interface 218 to conform to the Si lattice 216. The compressive stress or force 220 on the BL lattice 214 at the bottom interface 218 is 214 2 to the top surface 222 at the top interface 217 with the S / D lattice 213. The compressive force 220 transferred to the top surface 222 of the BL lattice 214 will affect the accommodation of the BL lattice 214 with the larger S / D lattice 213 at the top interface 217. The effect of such compressive force 220 is avoided by intentionally creating defects 224 by damaging the BL lattice 214 at the bottom interface 218 to reduce the compressive force exerted on the BL lattice 214 caused by the mismatch with the Si lattice 216. The BL lattice 214 is fully relaxed (i.e., has minimal compressive or expansive stress) at the top surface 222 as the BL lattice accommodates the defects 224 during epitaxy. The BL lattice 214 being fully relaxed at the top surface 222 can better accommodate the larger S / D lattice 213 due to the higher percentage of Ge. In one alternative to inserting defects, the compressive stress can be relieved by a superlattice structure (not shown) that includes alternating layers of Si and SiGe. The compressive stress 220 at the bottom interface 218 does not continue through the interfaces between the layers of the superlattice structure and is therefore not present at the top interface 217.

[0021]

[0026] In this regard, the buffer layer 206 buffers (e.g., isolates) the S / D lattice 213 from the Si substrate 208, allowing the second Ge fraction of the S / D lattice 213 to exceed 45%. A limit on the second Ge fraction in the S / D lattice 213 is the lattice constant A 213 and the lattice constant A of BL lattice 214 214In some examples, the second percentage of Ge in the S / D lattice 213 is greater than 46%. In some examples, the second percentage of Ge in the S / D lattice 213 is greater than 60%. In some examples, the second percentage of Ge in the S / D lattice can be up to 100% (i.e., completely Ge). Increasing the second percentage of Ge makes the S / D lattice 213 larger, which increases the compression of the N-well 210. The increased compression increases the conductivity C through the N-well 210. 210 , which increases the performance of PFET 200. Increasing the Ge fraction in S / D lattice 213 by 10% can increase the performance of PFET 200 by 5%.

[0022]

[0027] In addition to providing increased performance for the PFET 200, the buffer layer 206 also provides benefits to the performance of the NFET 204. The NFET 204 includes a source 228S and a drain 228D on either side of a P-type well 226. The P-type well 226 is also referred to herein as a "channel region 226" because an N-channel (not shown) is formed therein during operation of the NFET 204. The P-type well 226 is formed from a semiconductor layer 212 doped with a trivalent impurity. The semiconductor layer 212 is removed from either side of the P-type well 226, and a source 228S and a drain 228D are formed on either side of the P-type well 226 from which the semiconductor layer 212 was removed. The electron mobility of the P-type well 226 (channel region 226) increases with tensile (pulling) stress. To provide tensile stress to the P-well 226 from each side, the source 228S and drain 228D of the NFET 204 are formed from a compound 230 of Si and another element 232. In one example, the other element 232 in the compound 230 can be phosphorous (P). The compound 230 includes a silicon phosphorous (SiP) lattice 234. The element 232 is selected from the lattice constant A of the SiP lattice 234 in the source 228S and drain 228D. 234 is the lattice constant A of the P-well lattice 236 in the P-well 226.236 Therefore, the SiP lattice 234 of the source 228S and drain 228D is tensioned on each side of the P-well 226.

[0023]

[0028] The P-well lattice 236 of the P-well 226 has a lattice constant A 216 Lattice constant A close to the range 236 The P-type well 226 is disposed on the buffer layer 206 and has a thickness T 226 The 15% Ge in the BL lattice 214 reduces the lattice constant A 214 is the lattice constant A of the P-well lattice 236 236 The BL lattice 214 has a larger size than the P-well lattice 236 and a larger thickness T 214 By having the buffer layer 206, the P-well lattice 236 is subjected to additional tensile stress which forces the P-well lattice 236 to expand to accommodate the BL lattice 214. The additional tensile stress exerted by the buffer layer 206 further increases the electron mobility in the P-well 226, thereby increasing the performance of the NFET 204. Thus, the performance of both the PFET 200 and the NFET 204 is improved by incorporating the buffer layer 206 in the CMOS device 202.

[0024]

[0029] 3 is a flow chart illustrating a method 300 of fabricating a CMOS device 202 including a PFET 200 and an NFET 204 on a buffer layer 206 for increased performance. The method 300 is described with reference to fabrication stages 400A-400I in FIGS. 4A-4I. Features in FIGS. 4A-4I that correspond to the CMOS device 202 in FIG. 2 are labeled as in FIG. 2. The first fabrication stage 400A shown in FIG. 4A includes a Si substrate 208 shown in FIG. 2. The Si substrate 208 in this example has a thickness T of about 100 microns. 208 , but may be thinner or thicker.

[0025]

[0030] 4B, the method 300 includes forming a buffer layer 206 on a Si substrate 208, the buffer layer 206 comprising Si and a first percentage of Ge (block 302). The buffer layer 206 has a thickness T of at least 1 micron. 214 In some instances, the thickness T 214 can be in the range of 0.9 microns to 1.5 microns or greater. Due to the lattice mismatch between the Si lattice 216 of the Si substrate 208 and the BL lattice 214 of the buffer layer 206, the Si lattice 216 induces a compressive strain on the BL lattice 214 at the lower interface 218. Thus, the method 300 includes relaxing the strain in the buffer layer 206 (block 304). In one example, relaxing the strain in the buffer layer 206 includes creating defects 224 in the BL lattice 214 of the buffer layer 206 at the lower interface 218 between the buffer layer 206 and the Si substrate 208 and annealing (i.e., heat treating) the buffer layer 206.

[0026]

[0031] The method 300 further includes forming a semiconductor layer 212 on the buffer layer 206 (block 306). In one example, forming the semiconductor layer 212 includes forming the semiconductor layer 212 to a thickness T of 100 angstroms (A) to 500 A. 212 In another example, forming the semiconductor layer 212 may further include doping the semiconductor layer 212. For example, in an area 402P of the semiconductor layer 212 where the PFET 200 (not shown) is to be formed, the semiconductor layer 212 may be doped to be an N-type material by adding a pentavalent impurity (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.). In an area 402N of the semiconductor layer 212 where the NFET 204 (not shown) is to be formed, the semiconductor layer 212 may be doped to be a P-type semiconductor by adding a trivalent impurity (e.g., boron (B), gallium (G), indium (In), etc.).

[0027]

[0032] As shown in the diagram of the third fabrication stage 400C in FIG. 4C, the method 300 includes forming a gate 403 on the semiconductor layer 212 (block 308). In one example, the gate 403 is disposed in an area 402P of the semiconductor layer 212. Forming the gate 403 may include forming sidewalls 404, forming a dielectric layer 406, and forming a conductive gate 408. As shown in the diagram of the third fabrication stage 400C, in one example, the method may further include forming a gate 409 on the semiconductor layer 212 in an area 402N for the NFET 204. The method 300 may further include forming an isolation trench 410 between the gate 403 and the gate 409, and filling the isolation trench 410 with a shallow trench isolation (STI) material, such as an insulator (e.g., silicon oxide), where the isolation trench 410 extends through the semiconductor layer 212 to the buffer layer 206. The isolation trench 410 is formed to have a thickness T 214 Extends through a portion of the

[0028]

[0033] As shown in the diagram in FIG. 4D of a fourth fabrication stage 400D, the method 300 includes forming a first recess 412S on a first side of the gate 403 and forming a second recess 412D on a second side of the gate 403, the first recess 412S and the second recess 412D each extending through the semiconductor layer 212 to the buffer layer 206 (block 310). In one example, the portion 414 of the semiconductor layer 212 under the gate 403 is the N-type well 210 in FIG. 2. The first recess 412S and the second recess 412D can be removed, for example, by wet and / or dry etching. Forming the first recess 412S and the second recess 412D exposes the top surface 222 of the buffer layer 206.

[0029]

[0034] The diagram in FIG. 4E of the fifth fabrication stage 400E shows that the method 300 further includes forming a Si and Ge composite 416 in the first recess 412S and the second recess 412D, the composite 416 comprising a second percentage of Ge greater than the first percentage of Ge, where the second percentage is at least 46% Ge (block 312). In one example, the composite 416 is an S / D lattice 213 in the first recess 412S on the first side and the second recess 412D on the second side of the N-well 210. In one example, the composite 416 is in direct contact with the N-well 210. In one example, the composite 416 is epitaxied to at least a thickness T of the semiconductor layer 212. 212 It can be grown to.

[0030]

[0035] 4F of a sixth fabrication stage 400F, the method 300 may further include forming a third recess 418S in the semiconductor layer 212 on a first side of the gate 409 and forming a fourth recess 418D in the semiconductor layer 212 on a second side of the gate 409, the third recess 418S and the fourth recess 418D each extending into but not through the semiconductor layer 212. In other words, the third recess 418S and the fourth recess 418D are formed at a depth equal to or greater than the thickness T of the semiconductor layer 212. 212 2. In one example, the portion 420 of the semiconductor layer 212 under the gate 409 is the P-well 226 in FIG. 2. The third recess 418S and the fourth recess 418D may be removed, for example, by wet and / or dry etching. After forming the third recess 418S and the fourth recess 418D, the thickness T 422 remains on the top surface 222 of the buffer layer 206 .

[0031]

[0036] The diagram in FIG. 4G of a seventh fabrication stage 400G indicates that the method 300 may further include forming a compound 230 of Si and another element 232 in the third recess 418S and the fourth recess 418D, the compound 230 being a compound having a lattice constant A of the semiconductor layer 212. 2122. In one example, the other element is phosphorus, and the compound 230 is a compound of Si and P. The compound 230 is formed on a first side and a second side of the P-well 226. In one example, the compound 230 is in direct contact with the P-well 226. The compound 230 of Si and the other element 232 ... 422 2. The buffer layer 206 is spaced apart by a distance of 100 nm.

[0032]

[0037] 4H is an illustration of an eighth fabrication stage 400H of the method 300 of fabricating the CMOS device 202. In this regard, the method includes forming a dielectric layer 438 over the areas 402P and 402N, and forming vertical contacts 440 through the dielectric layer 438. The vertical contacts 440 provide electrical connections to each of the source 211S, the gate 403, the drain 200D, the drain 228D, the gate 409, and the source 228S.

[0033]

[0038] FIG. 4I shows a ninth fabrication stage 400I of the method for fabricating the CMOS device 202, which includes forming a second dielectric layer 442 and forming metal routing 444 in the second dielectric layer 442 to interconnect vertical contacts 440 of the PFET 200 and NFET 204 to a circuit (not shown).

[0034]

[0039] FIG. 5 illustrates an exemplary wireless communication device 500 including radio frequency (RF) components formed from one or more integrated circuits (ICs) 502, where any of the ICs 502 may include an exemplary CMOS device including a PFET and an NFET formed on a SiGe compound buffer layer and including greater than 45% Ge in the SiGe compound at the PFET source and drain for increased performance, according to any of the embodiments illustrated in FIG. 2 and 4A-4I and disclosed herein. The wireless communication device 500 may include or be provided in any of the above devices, as examples. As illustrated in FIG. 5, the wireless communication device 500 includes a transceiver 504 and a data processor 506. The data processor 506 may include a memory for storing data and program code. The transceiver 504 includes a transmitter 508 and a receiver 510 supporting bidirectional communication. In general, the wireless communication device 500 may include any number of transmitters 508 and / or receivers 510 for any number of communication systems and frequency bands. All or a portion of the transceiver 504 may be implemented on one or more analog ICs, RFICs, mixed-signal ICs, etc.

[0035]

[0040] The transmitter 508 or receiver 510 may be implemented using a super-heterodyne architecture or a direct conversion architecture. In a super-heterodyne architecture, a signal is frequency converted between RF and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne architecture and the direct conversion architecture may use different circuit blocks and / or have different requirements. In the wireless communication device 500 in FIG. 5, the transmitter 508 and receiver 510 are implemented using a direct conversion architecture.

[0036]

[0041] In the transmit path, the data processor 506 processes data to be transmitted and provides I and Q analog output signals to a transmitter 508. In the exemplary wireless communication device 500, the data processor 506 includes digital-to-analog converters (DACs) 512(1), 512(2) to convert digital signals generated by the data processor 506 to I and Q analog output signals, e.g., I and Q output currents, for further processing.

[0037]

[0042] Within the transmitter 508, lowpass filters 514(1), 514(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 516(1), 516(2) amplify the signals from the lowpass filters 514(1), 514(2), respectively, and provide I and Q baseband signals. An upconverter 518 upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator 522 through mixers 520(1), 520(2) to provide an upconverted signal 524. A filter 526 filters the upconverted signal 524 to remove undesired signals caused by frequency upconversion as well as noise in the receive frequency band. A power amplifier (PA) 528 amplifies the upconverted signal 524 from filter 526 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 530 and transmitted via an antenna 532.

[0038]

[0043] In the receive path, an antenna 532 receives a signal transmitted by a base station and provides a receive RF signal, which is routed through a duplexer or switch 530 and provided to a low noise amplifier (LNA) 534. The duplexer or switch 530 is designed to operate with a specific RX-TX duplexer frequency separation such that the receive (RX) signal is separated from the TX signal. The receive RF signal is amplified by the LNA 534 and filtered by a filter 536 to obtain a desired RF input signal. Downconversion mixers 538(1), 538(2) mix the output of the filter 536 with I and Q RX LO signals (i.e., LO_I and LO_Q) from a RX LO signal generator 540 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 542(1), 542(2) and further filtered by low pass filters 544(1), 544(2) to obtain I and Q analog input signals, which are provided to data processor 506. In this example, data processor 506 includes analog-to-digital converters (ADCs) 546(1), 546(2) to convert the analog input signals to digital signals to be further processed by data processor 506.

[0039]

[0044] In the wireless communication device 500 of FIG. 5, the TX LO signal generator 522 generates I and Q TX LO signals used for frequency up-conversion, and the RX LO signal generator 540 generates I and Q RX LO signals used for frequency down-conversion. Each LO signal is a periodic signal having a particular fundamental frequency. The TX phase-locked loop (PLL) circuit 548 receives timing information from the data processor 506 and generates control signals used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 522. Similarly, the RX PLL circuit 550 receives timing information from the data processor 506 and generates control signals used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 540.

[0040]

[0045] A wireless communication device 500 including exemplary CMOS devices including a PFET and an NFET each formed on a SiGe composite buffer layer and including greater than 45% Ge in the SiGe composite in the PFET source and drain for increased performance according to any of the embodiments shown in FIGS. 2 and 4A-4I and disclosed herein may be provided in or incorporated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0041]

[0046] In this regard, Figure 6 illustrates an example of a processor-based system 600 including an exemplary CMOS device including a PFET and an NFET formed on a SiGe composite buffer layer and including greater than 45% Ge in the SiGe composite at the PFET source and drain for increased performance according to any embodiment shown in Figures 2 and 4A-4I and disclosed herein. In this example, the processor-based system 600 includes one or more central processor units (CPUs) 602, sometimes referred to as CPUs or processor cores, each including one or more processors 604. The CPU(s) 602 may have a cache memory 606 coupled to the processor(s) 604 for fast access to temporarily stored data. As an example, the processor(s) 604 may include an exemplary CMOS device including a PFET and an NFET formed on a SiGe compound buffer layer and including greater than 45% Ge in the SiGe compound at the PFET source and drain for increased performance, according to any of the embodiments shown in FIG. 2 and 4A-4I and disclosed herein. The CPU(s) 602 may be coupled to a system bus 608 to interconnect master and slave devices included in the processor-based system 600. As is well known, the CPU(s) 602 communicate with these other devices by exchanging address, control, and data information via the system bus 608. For example, the CPU(s) 602 may communicate bus transaction requests to a memory controller 610, as an example of a slave device. Although not shown in FIG. 6, multiple system buses 608 may be provided, where each system bus 608 constitutes a different fabric.

[0042]

[0047] Other master and slave devices may be connected to the system bus 608. As shown in FIG. 6, these devices may include, by way of example, a memory system 612 including a memory controller 610 and one or more memory arrays 614, one or more input devices 616, one or more output devices 618, one or more network interface devices 620, and one or more display controllers 622. Each of the memory system 612, the one or more input devices 616, the one or more output devices 618, the one or more network interface devices 620, and the one or more display controllers 622 may include exemplary CMOS devices including PFETs and NFETs formed on a SiGe composite buffer layer and including greater than 45% Ge in the SiGe composite in the PFET source and drain for increased performance, as shown in FIG. 2 and in FIG. 4A-4I, and according to any of the embodiments disclosed herein. The input device(s) 616 may include any type of input device, including, but not limited to, input keys, switches, audio processors, and the like. The output device(s) 618 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s) 620 may be any device configured to enable the exchange of data to and from a network 624. The network 624 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH network, and the Internet. The network interface device(s) 620 may be configured to support any type of communication protocol desired.

[0043]

[0048] The CPU(s) 602 may also be configured to access display controller(s) 622 via the system bus 608 to control information sent to one or more displays 626. The display controller(s) 622 send information to be displayed to the display(s) 626 via one or more video processors 628, which process the information to be displayed into a format suitable for the display(s) 626. The display(s) 626 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc. The display controller(s) 622, the display(s) 626, and / or the video processor(s) 628 may include an exemplary CIM bit cell array circuit including CIM bit cell circuitry arranged in an orientation of the CIM bit cell circuit physical layout including read word line circuitry to increase uniformity for improved performance and reliability, as shown in any of FIGS. 4, 8, and 9, and in accordance with any of the aspects disclosed herein.

[0044]

[0049] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithms described with respect to the aspects disclosed herein may be implemented as electronic hardware, as instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or as a combination of both. The master and slave devices described herein may be employed in any circuit, hardware component, IC, or IC chip, as examples. The memories disclosed herein may be of any type and size and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0045]

[0050] The various example logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0046]

[0051] Aspects disclosed herein may be implemented in hardware and with instructions stored in the hardware, which may be present, for example, in a random access memory (RAM), a flash memory, a read only memory (ROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from the storage medium and write information to the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, a base station, or a server.

[0047]

[0052] It should also be noted that the operational steps described in any of the exemplary aspects herein have been described to provide examples and explanations. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operational step may in fact be performed in several different steps. Furthermore, one or more operational steps described in the exemplary aspects may be combined. It should be understood that the operational steps shown in the flow chart diagrams may be subject to many different modifications, as will be readily apparent to those skilled in the art. Those skilled in the art will also appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0048]

[0053] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0049]

[0054] Example implementations are described in the following numbered clauses. 1. A silicon substrate; a buffer layer disposed on a silicon substrate, the buffer layer comprising a first percentage of germanium; a transistor disposed on the buffer layer; A semiconductor device comprising: a channel region comprising a semiconductor material; a gate disposed over the channel region; a source disposed on a first side of the channel region; a drain disposed on a second side of the channel region; Equipped with Here, the source and drain each comprise a silicon germanium (SiGe) compound having a second percentage of germanium, the second percentage being greater than the first percentage; Semiconductor device. 2. The semiconductor device of claim 1, wherein the second percentage of germanium is at least 46 percent. 3. The semiconductor device of clause 1 or 2, wherein the second proportion of germanium is greater than 60 percent. 4. A semiconductor device according to any one of clauses 1 to 3, wherein the source and drain are doped with trivalent impurities. 5. The semiconductor device of any one of clauses 1 to 4, wherein the first proportion of germanium is 15 percent. 6. A semiconductor device according to any one of clauses 1 to 5, wherein the buffer layer has a thickness of at least 1 micron. 7. The semiconductor material of the channel region has a thickness of 100 to 500 angstroms; the source and drain each having a thickness equal to or greater than a thickness of the semiconductor material of the channel region; 7. A semiconductor device according to any one of clauses 1 to 6. 8. A semiconductor device according to any one of clauses 1 to 7, wherein the channel region, the source and the drain are directly above the buffer layer. 9. Further comprising a second transistor on the buffer layer, the second transistor comprising: a silicon layer on the buffer layer; a second gate disposed over the second channel region of the silicon layer; a second source disposed on one side of the second gate and embedded in the silicon layer on one side of the second gate; a second drain disposed on another side of the second gate and embedded in the silicon layer on the other side of the second gate; 9. The semiconductor device of any one of clauses 1 to 8, comprising: 10. The transistor comprises a P-type field effect transistor (FET) (PFET); the second transistor comprises an N-type FET (NFET); 10. A semiconductor device as claimed in claim 9. 11. The second source and the second drain of the second transistor comprise silicon and phosphorus; 11. A semiconductor device according to clause 9 or 10. 12. A semiconductor device according to any one of clauses 1 to 11, incorporated in a radio frequency (RF) front end module. 13. The semiconductor device of any one of clauses 1 to 12 incorporated into a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a Global Positioning System (GPS) device, a mobile phone, a cellular phone, a smartphone, a Session Initiation Protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter. 14. A method of making a semiconductor device, the method comprising: forming a buffer layer on a silicon substrate, the buffer layer comprising silicon and a first proportion of germanium; Relieving strain in the buffer layer; forming a semiconductor layer on the buffer layer; forming a first gate on the semiconductor layer; forming a first recess on a first side of the first gate and a second recess on a second side of the first gate, the first recess and the second recess each extending through the semiconductor layer into the buffer layer; forming a first compound of silicon and germanium in the first recess and in the second recess, the first compound comprising a second percentage of germanium higher than the first percentage of germanium; A method comprising: 15. The method of claim 14, wherein the second proportion of germanium is at least 46 percent. 16. Relieving strain is creating defects in the buffer layer at an interface between the buffer layer and a silicon substrate; Annealing the buffer layer. 16. The method of claim 14 or 15, further comprising: 17. The method of any one of clauses 14 to 16, wherein forming the semiconductor layer further comprises forming the semiconductor layer to a thickness of between 100 angstroms and 500 angstroms. 18. The method of any one of clauses 14 to 17, wherein forming the buffer layer further comprises forming the buffer layer to a thickness of 1 micron. 19. Forming a second gate on the semiconductor layer; forming a third recess in the semiconductor layer on one side of the second gate; forming a fourth recess in the semiconductor layer on another side of the second gate; forming a second composite of silicon and another element in the third recess and in the fourth recess, the second composite having a lattice constant smaller than a lattice constant of the semiconductor layer under the second gate; 19. The method of any one of clauses 14 to 18, further comprising: 20. A second compound of silicon and another element is separated from the buffer layer by a portion of the semiconductor layer; The method described in clause 19. 21. Forming an isolation trench between the first gate and the second gate, the isolation trench extending through the semiconductor layer to the buffer layer; 21. The method of claim 19 or 20, further comprising:

Claims

1. A semiconductor device, comprising: A silicon substrate; a buffer layer disposed on the silicon substrate, the buffer layer comprising a first proportion of germanium; a transistor disposed on the buffer layer, the transistor comprising: a channel region comprising a semiconductor material; a gate disposed over the channel region; a source disposed on a first side of the channel region; a drain disposed on a second side of the channel region; Source contact; and a drain contact, wherein: the source and the drain each comprise a silicon germanium (SiGe) compound comprising a second percentage of germanium; the second ratio is greater than the first ratio; the SiGe compound of the source is in contact with the source contact and directly overlies the buffer layer; the SiGe composite of the drain is in contact with the drain contact and directly overlies the buffer layer; the semiconductor material of the channel region is directly above the buffer layer and extends to the gate layer; a second transistor on the buffer layer; and the second transistor, a silicon layer on the buffer layer; a second gate disposed over the second channel region of the silicon layer; a second source disposed on one side of the second gate and embedded in the silicon layer on the one side of the second gate; a second drain disposed on another side of the second gate and embedded in the silicon layer on the other side of the second gate, wherein a portion of the silicon layer is between the second source and the buffer layer and between the second drain and the buffer layer. A semiconductor device comprising:

2. 2. The semiconductor device of claim 1, wherein said second percentage of germanium is at least 46 percent.

3. 2. The semiconductor device of claim 1, wherein said second percentage of germanium is greater than 60 percent.

4. The semiconductor device of claim 1 , wherein said source and said drain are doped with a trivalent impurity.

5. 2. The semiconductor device of claim 1, wherein said first percentage of germanium is 15 percent.

6. The semiconductor device of claim 1 , wherein the buffer layer comprises a thickness of at least 1 micron.

7. the semiconductor material of the channel region having a thickness of between 100 and 500 angstroms; the source and the drain each have a thickness equal to or greater than the thickness of the semiconductor material of the channel region; The semiconductor device of claim 1 .

8. the transistor comprises a P-type field effect transistor (FET) (PFET); the second transistor comprises an N-type FET (NFET); The semiconductor device of claim 1 .

9. the second source and the second drain of the second transistor comprise silicon and phosphorus; The semiconductor device of claim 1 .

10. The semiconductor device of claim 1 , incorporated into a radio frequency (RF) front-end module.

11. 10. The semiconductor device of claim 1 , wherein the semiconductor device is incorporated into a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter.

Images