Polymer coatings for semiconductor processing chamber components

Abstract

A component within a semiconductor processing chamber is provided. The conductive semiconductor or metal body has a thickness of 10.0×10 -6 / K. An intermediate layer is disposed over at least one surface of the body, the intermediate layer comprising a fluoropolymer. A perfluoroalkoxyalkane (PFA) layer is disposed over the intermediate layer to form a component.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to U.S. Patent Application No. 63 / 158,115, filed March 8, 2021, which is incorporated herein by reference for all purposes.

[0002] The present disclosure relates generally to semiconductor device manufacturing. More specifically, the present disclosure relates to chamber components used in the manufacturing of semiconductor devices.

[0003] During semiconductor wafer processing, plasma processing chambers are used to process the semiconductor devices. The plasma processing chambers are exposed to halogen plasma and / or oxygen plasma, which can degrade components within the plasma processing chamber.

[0004] The description of the background art provided herein is intended to provide a general background to the present disclosure, and the work of the inventors named herein, to the extent described in this background art, together with aspects of the description that would not ordinarily be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art to the present disclosure. Summary of the Invention

[0005] To achieve the above, and in accordance with the objectives of the present disclosure, a component within a semiconductor processing chamber is provided. The conductive semiconductor or metal body has a diameter of 10.0×10 -6 / K. An intermediate layer is disposed over at least one surface of the body, the intermediate layer comprising a fluoropolymer. A perfluoroalkoxyalkane (PFA) layer is disposed over the intermediate layer to form a component.

[0006] In another aspect, an edge ring for use in a plasma processing chamber is provided. An elemental silicon edge ring body is provided. A fluoropolymer is on at least one surface of the elemental silicon edge ring body. A perfluoroalkoxyalkane (PFA) coating is on the fluorinated ethylene propylene or polyethersulfane coating.

[0007] In another aspect, a method is provided for forming a component for use in a semiconductor processing chamber. A conductive semiconductor or metal body is provided, the body having a thickness of 10.0×10 -6 / K. An intermediate layer is formed on at least one surface of the body, the intermediate layer comprising a fluoropolymer. A perfluoroalkoxyalkane (PFA) layer is formed on the intermediate layer to form a component.

[0008] These and other features of the present disclosure are set forth in the detailed description that follows, taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0009] The present disclosure is illustrated by way of example, and not by way of limitation, in the accompanying drawings, in which like elements are numbered like elements and in which:

[0010] [Figure 1] 1 is a schematic flow chart of one embodiment.

[0011] 2A-2E illustrate one embodiment of a method for fabricating an edge ring component for use in a plasma processing chamber. [Figure 2A] FIG. 2 is a top view showing a component substrate in the form of an edge ring. [Figure 2B] 2B is a cross-sectional view of the component substrate of FIG. 2A. [Figure 2C] FIG. 2B is a detailed cross-sectional view of the surface of the substrate of FIG. 2A. [Figure 2D] FIG. 2B is a detailed cross-sectional view of an intermediate fluoropolymer layer coated on the substrate of FIG. 2A. [Figure 2E] FIG. 2E is a detailed cross-sectional view showing the structure of FIG. 2D after a perfluoroalkoxyalkane (PFA) layer has been applied to the fluoropolymer interlayer to form a component for a plasma processing chamber.

[0012] [Diagram 3] 1 is a cross-sectional view of a portion of a plasma processing chamber.

[0013] [Figure 4] 1 is a schematic diagram illustrating a plasma processing chamber that can be used in one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The present disclosure will be described in detail below with reference to some preferred embodiments illustrated in the accompanying drawings. In the following description, numerous specific details are set forth to facilitate a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without some or all of these specific details. Additionally, detailed descriptions of well-known process steps and / or structures are omitted to avoid unnecessarily obscuring the present disclosure.

[0015] Various embodiments described herein provide semiconductor processing chamber components that are resistant to arcing and / or corrosion damage resulting from processes such as plasma etching, thus reducing or minimizing wear on components that may result from plasma and etching processes present in semiconductor processing systems, such as plasma processing chambers.

[0016] To aid in understanding, Figure 1 is a schematic flow chart illustrating a first embodiment process for manufacturing and utilizing a component for a semiconductor processing chamber (such as a plasma processing chamber). A component body is provided (step 104). The component body has a low coefficient of thermal expansion (CTE) (e.g., 10.0 x 10 -6 / K~5.0x10 -61 / K). As described in more detail below, the electrical conductivity and low CTE of the component body are particularly beneficial attributes for use in components of semiconductor processing chambers, such as plasma processing chambers.

[0017] 2A-2C, a substrate body 204 is provided that may be formed in the shape of a component utilized in a plasma processing chamber, such as an edge ring having a central hole 208 or inner diameter surface that at least partially surrounds an electrostatic chuck (ESC). FIG. 2A is a top view of the substrate body, and FIG. 2B is a cross-sectional view of the substrate body. FIG. 2C is an enlarged view of cross section AA of the substrate body surface 212. It is understood that the drawings shown in FIGS. 2A-4 are for illustrative purposes only and may vary in scale, form, and features. The substrate body 204 may be formed by many different processing processes (e.g., machining, casting, sintering, polishing, chemical etching, etc.).

[0018] According to one embodiment, the substrate body 204 has a low coefficient of thermal expansion (CTE) (e.g., 10.0×10 -6 / K, and in a further embodiment, less than 5.0×10 -6 / K). In a further embodiment, the substrate body 204 comprises a conductive semiconductor, in particular a conductive polycrystalline (multi-crystalline) doped silicon or silicon carbide semiconductor material. In another embodiment, the substrate body 204 comprises elemental silicon. In alternative embodiments, the substrate body may comprise other conductive semiconductors (e.g., germanium) or low CTE metals (e.g., titanium, etc.). In various embodiments, the semiconductor may be poly-crystalline. Polycrystalline (multi-crystalline) silicon has grains that are larger on average than those of polycrystalline (polycrystalline) silicon. Polycrystalline (multi-crystalline) silicon has an average grain size larger than 1 mm. A lower coefficient of thermal expansion generally provides lower stress, wear, and better fit between components. In particular, during chamber processing, the edge ring and other adjacent parts (e.g., the ESC base plate) are at different temperatures. Due to the heating induced by the plasma, the edge ring generally runs much hotter (in the range of 150°C to 250°C) than the ESC base plate, whose temperature is actively controlled (in the range of -40°C to 50°C). Selecting an edge ring material with a low coefficient of thermal expansion effectively reduces the variation in the gap size between the edge ring and the adjacent component (ESC), resulting in a more consistent capacitance between the two conductors. As a result, electrically more consistent performance is realized.

[0019] In one embodiment, the component body is formed by molding the shape of a particular component (e.g., by pouring or injecting the molten semiconductor into a mold) where the molten semiconductor cools to a hardened form within the mold to form a polycrystalline (multi-crystalline) structure with large grain size. In another embodiment, the semiconductor is solidified into a cylindrical shape and then machined into its final shape by abrasive grinding or other machining techniques.

[0020] 1 and 2D, after the substrate body 204 is provided, an intermediate fluoropolymer layer 216 (FIG. 2D) is formed on one or more surfaces 212 of the substrate body 204 (step 108). The intermediate fluoropolymer layer 216 aids in the adhesion of subsequent layers (e.g., PFA layer 224 in FIG. 2D) to the substrate body 204. In one embodiment, the intermediate fluoropolymer layer 216 includes a fluoropolymer (e.g., fluorinated ethylene propylene (FEP)) having a high cure temperature (e.g., 350° C.-400° C.) and a composition that aids in bonding of the subsequent PFA layer 224. In another embodiment, the intermediate fluoropolymer layer 216 includes a resin (e.g., polyethersulfane (PES)) to aid in bonding to the substrate surface 212. Additionally, the intermediate fluoropolymer layer 216 has little to no color (i.e., is transparent) to minimize contamination in the processing chamber. To aid in deposition (e.g., liquid spray deposition techniques), the intermediate fluoropolymer layer 216 comprises a solvent-based or water-based composition. In one embodiment, the intermediate fluoropolymer layer 216 is comprised of Xylan® 8840 dry film lubricant manufactured by PPG Industries Ohio, Inc., Cleveland, Ohio. However, it is understood that any resin-bonded or resin-based, FEP-based coating, particularly those that are solvent-based or water-based, may be used.

[0021] According to some embodiments, the intermediate fluoropolymer layer 216 is deposited using a spray deposition method that provides a substantially uniform layer to act as a primer for the coating of subsequent layers with suitable adhesion to the underlying substrate body 204. Convenient for spray deposition, the intermediate fluoropolymer layer 216 is water-based or solvent-based. In alternative embodiments, deposition methods (such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), electrodeposition (electrodeposition coating, also known as Elecoat Nicelon™ by Shimizu Corporation (shimizu-corp.co.jp)), or similar deposition methods) may be used. In one embodiment, prior to application of any coating layer, the substrate body 204 is pretreated to remove or substantially remove any oxides (e.g., silicon oxide) and surface damage to or loosely attached microstructures on the substrate surface 212 that may have occurred during processing. For example, when priming a silicon substrate, a deionized (DI) water rinse may be performed on the substrate body 204, followed by a mixed acid etch to remove any surface defects and increase the surface roughness, for example to 20 microns or more.

[0022] The thickness of the intermediate fluoropolymer layer 216 may vary depending on one or more factors such as component type, component location, component geometry, substrate material properties, cost, etc. According to one embodiment, the thickness of the intermediate fluoropolymer layer 216 is between about 1 micrometer (μm) and 30 μm.

[0023] 1 and 2E, after the intermediate fluoropolymer layer 216 is formed, a final coating or layer is applied to the surface 220 of the intermediate fluoropolymer layer 216, the final coating layer also being a fluoropolymer (e.g., perfluoroalkoxyalkane (PFA)) with good resistance to hot acid, hereafter referred to as PFA layer 224. Other fluoropolymers may be considered. For example, polytetrafluoroethylene (PTFE) may be used, but is generally more porous. FIG. 2E is a cross-sectional view of one embodiment of a portion of the substrate body 204 after application of the PFA layer 224. As shown in FIG. 2E, the PFA layer 224 is added onto the original surface 220 of the intermediate fluoropolymer layer 216, thus increasing the overall thickness of the part. In some embodiments, the PFA layer 224 is at least 20 μm thick, and may be 150 μm or thicker. Since PFA generally has poor adhesion characteristics to metals and semiconductors (such as silicon), the intermediate fluoropolymer layer 216 acts as a primer to the substrate body 204. The PFA bonds well to the intermediate fluoropolymer layer 216 with good overall adhesion to the semiconductor substrate body 204 so that the resulting PFA layer 224 coating is securely attached to the substrate body 204 to minimize delamination or separation. According to some embodiments, the PFA layer 224 is applied to the intermediate fluoropolymer layer 216 using an electrostatic spray deposition process that provides a substantially uniform layer across the surface of the substrate body 204.

[0024] As detailed above, the resulting PFA coated substrate body processed according to steps 104-112 of the process of FIG. 1 has minimal contaminants and is highly resistant to the chemicals and corrosive processes inherent in semiconductor processing chambers.

[0025] After component 200 has been appropriately processed per steps 104-112 of Figure 1, it is then placed (step 116, Figure 1) into a semiconductor processing chamber, such as a plasma processing chamber. The processing illustrated in Figure 1 is particularly useful for fabricating plasma processing chamber components using substrate materials that are typically consumed very quickly by oxygen / halogen reactants common in plasma processing chambers.

[0026] In the following embodiments, the component 200 formed from the processes illustrated in Figures 1 and 2A-2E is directed to a particular application as an edge ring or similar component in an electrostatic chuck (ESC) assembly or system (e.g., ESC assembly 300 of Figure 3) for use in a plasma processing chamber (e.g., plasma processing chamber 404 shown in Figure 4). However, it is understood that the component 200 formed from the processes illustrated in Figures 1 and 2A-2E may be implemented as any number of components in the ESC assembly 300 or plasma processing chamber 404 (such as Pinnacle® and electrostatic chuck (ESC), in addition to high flow liners, gas distribution plates, etc., among other parts) so long as the properties of high corrosion resistance, good electrical conductivity, and low thermal expansion coefficient are desired.

[0027] FIG. 3 is a cross-sectional view of a portion of an ESC assembly 300 with a movable edge ring configuration for use in a plasma processing system (defined by cross section BB shown in FIG. 4). The ESC assembly 300 includes an upper edge ring 324 configured to surround an electrostatic chuck (ESC) 304. The ESC 304 may also be referred to as a substrate support that serves as a support for a processing wafer 466 during processing. The upper edge ring 324 has an annular lower recess 326 supported by a movable edge ring 308. The movable edge ring 308 is arranged to vertically articulate within a cavity defined by a radially inner side including the ESC 304, a heating plate 352, and a central inner edge ring 328, and a radially outer side including a stationary edge ring 316, an outer edge ring 312, and a cover edge ring 320. The cover edge ring 320 has a radially inner protrusion 322 that partially covers the upper edge ring 324.

[0028] As the upper edge ring 324 is exposed to corrosive plasma and etchants during processing of the process wafer 466, it constantly wears away, and its thickness decreases in height with increasing exposure. Thus, the movable edge ring 308 is used to lift the edge ring 324 to restore the height relationship between the upper surface of the upper edge ring 324 and the process wafer / substrate 466. To affect such height adjustment, one or more lift pins 340 are actuated vertically (through openings 348 in the ESCs 304 and openings 318 in the stationary edge ring 316) to lift the movable edge ring 308, thus adjusting the vertical position of the upper edge ring 324. A sleeve 344 is disposed around the periphery of the lift pins 340 to seal the openings 348 in the ESCs 304.

[0029] In one embodiment, the component 200 is processed according to the process of Figures 1 and 2A-2E to form a stationary edge ring 316 that attaches to the ESC assembly 300. The stationary edge ring 316 benefits greatly from the corrosion resistance of the intermediate fluoropolymer / PFA coating 216 / 224 of the component 200 due to its location in the chamber and its proximity / exposure to plasma during processing of the process wafer 466 (i.e., having one or more "plasma-facing surfaces"). In one example, plasma can pass between the top edge ring 324 and the outer edge ring 312 and cover edge ring 320 to the outer surface of the movable edge ring 308 and the inner surface of the stationary edge ring 316 (e.g., inner diameter surface or central hole 208 in Figure 2B). The amount of plasma passed depends on the location of the top edge ring 324. 3 , the top edge ring 324 can prevent plasma from passing between the top edge ring 324 and the central inner edge ring 328 and / or outer edge ring 312 to reach the inner or outer surface of the movable edge ring 308. When the movable edge ring 308 lifts the top edge ring 324, a gap is created between the top edge ring 324 and the central inner edge ring 328 and / or outer edge ring 312, allowing plasma to reach the surfaces of the movable edge ring 308 and the stationary edge ring 316.

[0030] In one embodiment, the entire outer surface of the stationary edge ring 316 may be treated to include the intermediate fluoropolymer / PFA coating 216 / 224 as provided in the component 200. However, it is understood that only a portion of the component's outer surface need be treated. For example, the outer or outer diameter surface of the stationary edge ring 316 may be excluded (e.g., by a mask or similar process) from the PFA layer 224 such that only the plasma-facing surface (e.g., inner diameter surface 208, see FIG. 2B) includes the intermediate fluoropolymer / PFA coating 216 / 224. Such a partial coating process may require masking portions that are not to be coated. The plasma-facing surface is the surface that is exposed to plasma during plasma processing or exposed to reactive halogen species at high temperature and low pressure. The reactive halogen species may be formed from remote plasma or thermally reactive fluorine. In some embodiments, multiple points on the movable edge ring 308 are not coated because they may be utilized to connect with an electrode during an electroplating process.

[0031] Additionally, the movable edge ring 308, together with the stationary edge ring 316, benefits from the conductive properties of the substrate body 204 of the component 200 to provide an RF conductive (AC) path to the ESCs 304 to achieve a more uniform plasma during chamber processing and improve wafer processing uniformity near the edge. Thus, the movable edge ring 308 and the upper edge ring 324, among other components in the ESC assembly 300 and plasma processing chamber system 400, may also be formed with the intermediate fluoropolymer / PFA coating 216 / 224 of the component 200 using the processes illustrated in Figures 1 and 2A-2E.

[0032] Returning to the process disclosed in Figure 1, component 200 is utilized in a plasma processing chamber (step 120) to facilitate semiconductor processing on a process wafer 466. The plasma processing may be one or more of the following processes: etching, deposition, passivation, or another plasma process. Plasma processing may also be performed in combination with non-plasma processes.

[0033] For ease of understanding, FIG. 4 shows a schematic diagram of an example of a plasma processing chamber system 400 that can be used in an embodiment. The plasma processing chamber system 400 includes a plasma reactor 402 having a plasma processing chamber 404 therein. A plasma power supply 406 is tuned by a power matching network 408 and supplies power to a transformer-coupled plasma (TCP) coil 410 disposed near a dielectric-induced power window 412 to generate a plasma 414 in the plasma processing chamber 404 by supplying inductively coupled power. A pinnacle 472 extends from a chamber wall 476 of the plasma processing chamber 404 to the dielectric-induced power window 412 to form a pinnacle ring. The pinnacle 472 is angled with respect to the chamber wall 476 and the dielectric-induced power window 412. For example, the interior angle between the pinnacle 472 and the chamber wall 476 and the interior angle between the pinnacle 472 and the dielectric-induced power window 412 may each be greater than 90° and less than 180°. The pinnacle 472 provides a slanted ring near the top of the plasma processing chamber 404 as shown. The TCP coil (upper power source) 410 may be configured to produce a uniform diffusion profile in the plasma processing chamber 404. For example, the TCP coil 410 may be configured to generate a toroidal power distribution in the plasma 414. The dielectric induction power window 412 is provided to allow energy to pass from the TCP coil 410 to the plasma processing chamber 404 while isolating the TCP coil 410 from the plasma processing chamber 404. A wafer bias voltage power supply 416 tuned by a bias matching network 418 provides power to the ESC assembly 300 to set a bias voltage when a process wafer 466 is placed on the ESC assembly 300. A controller 424 controls the plasma power supply 406 and the wafer bias voltage power supply 416.

[0034] The plasma power source 406 and the wafer bias voltage power source 416 may be configured to operate at a particular high frequency (e.g., 13.56 megahertz (MHz), 27 MHz, 1 MHz, 2 MHz, 60 MHz, 400 kilohertz (kHz), 2.54 gigahertz (GHz), or a combination thereof). The plasma power source 406 and the wafer bias voltage power source 416 may be appropriately sized to provide a range of power to achieve a desired processing performance. For example, in one embodiment, the plasma power source 406 may provide a power in the range of 50-5000 watts, and the wafer bias voltage power source 416 may provide a bias voltage of 20-3000 volts (V). Furthermore, the TCP coil 410 and / or the ESC assembly 300 may be configured with two or more sub-coils or sub-electrodes. The sub-coils and sub-electrodes may be powered by a single power source or by multiple power sources.

[0035] As shown in FIG. 4, the plasma processing chamber system 400 further comprises a gas source / gas delivery mechanism 430. The gas source 430 is in fluid communication with the plasma processing chamber 404 through a gas inlet (such as a gas injector 440). The gas injector 440 has at least one borehole 441 to allow gas to pass through the gas injector 440 into the plasma processing chamber 404. The gas injector 440 may be located at any advantageous location in the plasma processing chamber 404 and may take any form to inject gas. However, preferably, the gas inlet may be configured to create a “tunable” gas injection profile. The tunable gas injection profile allows for independent adjustment of the respective flow rates to multiple compartments in the plasma processing chamber 404. More preferably, the gas injector is mounted to the dielectric induction power window 412. The gas injector may be mounted on, in, or form part of the power window. Process gases and by-products are removed from the plasma processing chamber 404 via a pressure control valve 442 and a pump 444. The pressure control valve 442 and the pump 444 also function to maintain a particular pressure within the plasma processing chamber 404. The pressure control valve 442 can maintain a pressure of less than 1 Torr during processing. One or more edge rings may be disposed around the top of the ESC assembly 300. The gas source / gas delivery mechanism 430 is controlled by a controller 424. A Kiyo®, Strata®, or Vector® gas purifier manufactured by Lam Research, Fremont, Calif., may be used to implement one embodiment.

[0036] A process wafer 466 is placed in the plasma processing chamber 404, specifically on or in the ESC assembly 300, as shown in FIG. 3. A plasma treatment is applied to the process wafer 466 (e.g., step 120 of FIG. 1). In this example, the plasma treatment of the process wafer 466 is used to provide etching of a portion of the stack on the process wafer 466, such as to etch a tungsten-containing layer in the stack. In this embodiment, the plasma treatment heats the process wafer 466 to a temperature greater than 550° C. Additionally, the plasma treatment deposits residues inside the plasma processing chamber 404. After the plasma treatment of the process wafer 466, the process wafer 466 is removed from the plasma processing chamber 404. The plasma processing chamber 404 is cleaned to remove the deposited residues. In this embodiment, reactive fluorine from a remote fluorine plasma is used to clean the interior of the plasma processing chamber 404. A pressure in the range of 1 milliTorr (mTorr) to 10 Torr is provided. The ESC assembly 300 does not cool sufficiently and remains at a temperature above 500° C. After cleaning is completed, a new process wafer 466 may be placed in the plasma processing chamber 404 to begin a new cycle. In another example, plasma processing is used to provide etching including carbon layers, polysilicon layers, or oxide / nitride layers. In such an example, the wafer temperature is controlled in the range of 0° C. to 150° C., and the chamber is cleaned after wafer processing with in-situ oxygen (O2) and nitrogen trifluoride (NF3) plasma.

[0037] In various embodiments, the intermediate fluoropolymer / PFA coating 216 / 224 and features of the component 200 may be implemented on various parts of the plasma processing chamber 404, such as a confinement ring, edge ring, electrostatic chuck, ground ring, chamber liner, door liner, pinnacle, showerhead, dielectric power window, gas injector, edge ring, ceramic transfer arm, or other components. For example, the intermediate fluoropolymer / PFA coating 216 / 224 may be formed on the upper edge ring 324. Although the component 200 and ESC assembly 300 are shown in the embodiment of FIG. 4 for use in an inductively coupled plasma (ICP) reactor for the plasma processing chamber system 400, it is understood that other components and / or types of plasma processing chambers may be used. Examples of other types of plasma processing chambers in which the component 200 may be used are capacitively coupled plasma processing chambers (CCP), bevel plasma processing chambers, and similar processing chambers. In another example, the plasma processing chamber may be a dielectric processing chamber or a conductive processing chamber. One example of such a plasma processing chamber is the Exelan Flex® Etch System manufactured by Lam Research®, Fremont, California.

[0038] Although the present disclosure has been described with reference to certain preferred embodiments, there are alternatives, permutations, variations, and various substitute equivalents, which are within the scope of the present disclosure. It should also be noted that there are many alternative ways of implementing the method and apparatus of the present disclosure. Therefore, the appended claims are intended to be construed as including all such alternatives, permutations, and various substitute equivalents that fall within the true spirit and scope of the present disclosure.

Claims

1. A component within a semiconductor processing chamber, comprising: A conductive semiconductor or metal body, The body is 10.0×10 －６ a body having a CTE less than 0.1 / K; an intermediate layer disposed on at least one surface of the body, the intermediate layer comprising a fluoropolymer; a perfluoroalkoxyalkane (PFA) layer disposed on the intermediate layer to form the component; A component comprising:

2. A component according to claim 1, The body is a semiconductor body comprising silicon or silicon carbide.

3. A component according to claim 2, The semiconductor body comprises elemental silicon.

4. A component according to claim 1, The body is 5.0×10 －６ Component having a CTE less than 1 / K.

5. A component according to claim 1, The intermediate layer is polyethersulfone (PES) resin based to aid in bonding to the at least one surface of the body.

6. A component according to claim 1, The intermediate layer is water-based or solvent-based to enable application of the intermediate layer to the at least one surface of the body by spray deposition.

7. A component according to claim 1, A component, wherein the PFA layer is applied to the intermediate layer by spray deposition for bonding to the intermediate layer.

8. A component according to claim 1, the component is configured to be installed in a semiconductor processing chamber; The component forms a ring around an electrostatic chuck in the semiconductor processing chamber, the electrostatic chuck supporting a wafer for processing.

9. A component according to claim 1, the semiconductor processing chamber comprises a plasma processing chamber; The component is exposed to a corrosive process in the plasma processing chamber, and the PFA layer is resistant to damage or corrosion from the corrosive process.

10. A component according to claim 1, The intermediate layer is fluorinated ethylene propylene resin based to aid in bonding to the at least one surface of the body.

11. A component according to claim 1, The fluoropolymer is at least one of fluorinated ethylene propylene (FEP) and polyethersulfone (PES).

12. 1. A method for forming a component for use in a semiconductor processing chamber, comprising: Providing a conductive semiconducting or metallic body, The body is 10.0×10 －６ / K; forming an intermediate layer on at least one surface of the body, the intermediate layer comprising a fluoropolymer; forming a perfluoroalkoxyalkane (PFA) layer over the intermediate layer to form the component; A method comprising:

13. 13. The method of claim 12, The method of claim 1, wherein the body is a semiconductor body comprising silicon or silicon carbide.

14. 14. The method of claim 13, The method of claim 1, wherein the semiconductor body comprises elemental silicon.

15. 13. The method of claim 12, The body is 5.0×10 －６ 3. The method of claim 2, wherein the CTE is less than 1 / K.

16. 13. The method of claim 12, The method, wherein the intermediate layer is resin-based to aid in bonding to the at least one surface of the body.

17. 17. The method of claim 16, The method of claim 1, wherein the resin comprises polyethersulfone (PES).

18. 13. The method of claim 12, The method, wherein the intermediate layer is water-based or solvent-based, and forming the intermediate layer comprises applying the intermediate layer to the at least one surface of the body by spray deposition.

19. 13. The method of claim 12, The method wherein the PFA layer is applied to the intermediate layer by spray deposition for bonding to the intermediate layer.

20. 13. The method of claim 12 further comprising: placing the component in a semiconductor processing chamber; The method, wherein the components form a ring around an electrostatic chuck in the semiconductor processing chamber, the electrostatic chuck supporting a wafer for processing.

21. 21. The method of claim 20, the semiconductor processing chamber comprises a plasma processing chamber; The method, wherein the component is exposed to a corrosive treatment in the plasma processing chamber, and the PFA layer is resistant to damage or corrosion from the corrosive treatment.

22. 13. The method of claim 12, The method of claim 1, wherein the intermediate layer comprises at least one of fluorinated ethylene propylene and polyethersulfone (PES).

23. 1. An edge ring for use in a plasma processing chamber, comprising: An elemental silicon edge ring body; a fluoropolymer coating on at least one surface of said elemental silicon edge ring body; a perfluoroalkoxyalkane (PFA) coating on said fluoropolymer coating; An edge ring.

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