Calibration Schemes for Nonlinear ADCs

Abstract

In the illustrated example, an analog-to-digital converter (ADC) (100) having an input operable to receive an analog signal (110) and an output (130) operable to output a digital representation of the analog signal includes a voltage delay (VD) block (106). The VD block (106) is coupled to the input of the ADC (100) and generates a delay signal in response to a calibration signal. A back-end ADC (124) is coupled to the VD block (106) and receives the delay signal. The back-end ADC (124) has multiple stages including a first stage. A calibration engine (102) is coupled to the multiple stages and to the VD block (106). The calibration engine (102) measures an error number of the first stage and stores a delay value of the first stage with the smallest error number.

Description

[Technical field]

[0001] This description relates generally to analog-to-digital converters (ADCs), and more particularly to using lookup tables in ADCs. [Background technology]

[0002] In many electronic devices, analog input signals are converted to digital output signals using an analog-to-digital converter (ADC). ADCs used to digitize signals in radio frequency (RF) sampling receivers may need to operate at high speeds. Such speeds may be on the order of giga samples per second (GSPS). However, nonlinearities in high speed ADCs must be corrected. Summary of the Invention

[0003] In the described example, an analog-to-digital converter (ADC) having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal includes a voltage delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal in response to a calibration signal. A back-end ADC is coupled to the VD block and receives the delay signal. The back-end ADC has a number of stages including a first stage. A calibration engine is coupled to the number of stages and to the VD block. The calibration engine measures an error count for the first stage and selects a delay value for the first stage with the smallest error count. Remember.

[0004] The description also relates to a method of operating an analog-to-digital converter (ADC), the method including generating a delay signal in response to a calibration signal, providing the delay signal to a back-end ADC, the back-end ADC having a first stage of a plurality of stages, measuring an error number of the first stage with a calibration engine, the error number being an absolute difference in the number of ones and zeros generated by the first stage, and storing in the calibration engine the delay value of the first stage with the smallest error number.

[0005] The present description also relates to a device including a processor, a memory coupled to the processor, and an analog-to-digital converter (ADC). The ADC is coupled to the processor and the memory. The analog-to-digital converter (ADC) has an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, and includes a voltage delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal in response to a calibration signal. A back-end ADC is coupled to the VD block and receives the delay signal. The back-end ADC has a number of stages including a first stage. A calibration engine is coupled to the number of stages and the VD block. The calibration engine measures an error number of the first stage and stores a delay value of the first stage with the smallest error number. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram of a circuit, in accordance with an example.

[0007] [Diagram 2] 2 is a block diagram of a portion of the circuitry shown in FIG. 1, in accordance with an example.

[0008] [Diagram 3] 2 is a block diagram of a portion of the circuitry shown in FIG. 1, in accordance with an example.

[0009] [Figure 4] 1 is a flow chart of a method of operation of a circuit, in accordance with certain examples.

[0010] [Diagram 5] 1 is a flow chart of a method of operation of a circuit, in accordance with certain examples.

[0011] [Figure 6] 1 is a graph illustrating an AND gate delay and a comparator delay generated by an AND gate and a delay comparator, respectively, in a stage of a back-end ADC, in accordance with an example.

[0012] [Figure 7] 1 is a graph illustrating the output signal delay of a stage of a back-end ADC as a function of the input signal delay of the stage, in accordance with an example.

[0013] [Figure 8A] 1 is a graph illustrating output signal delays of different stages as a function of input signal delays of a back-end ADC, in accordance with an example. [Figure 8B] 1 is a graph illustrating output signal delays of different stages as a function of input signal delays of a back-end ADC, in accordance with an example.

[0014] [Figure 9] 9 is a block diagram of an example device 900 in which some aspects of the examples can be implemented.

[0015] The same reference numerals or other reference designators are used to refer to identical or similar (structural and / or functional) features. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] 1 is a block diagram of a circuit 100 in accordance with an example. The circuit 100 includes a calibration engine 102, a digital-to-analog converter (DAC) 104, a multiplexer M112, a voltage delay (VD) block 106, a back-end analog-to-digital converter (ADC) 124, and a storage circuit 108. The DAC 104 is coupled between the calibration engine 102 and the multiplexer M112. The multiplexer M112 is also coupled to the calibration engine 102. In one version, the multiplexer M112 is controlled by the calibration engine 102. The multiplexer M112 receives an input voltage Vin 110. The VD block 106 is coupled to the multiplexer M112 and the calibration engine 102. The back-end ADC 124 is coupled to the VD block 106 and the calibration engine 102. The storage circuitry 108 is coupled to the back-end ADC 124 and the calibration engine 102. The storage circuitry 108 may be comprised of digital memory circuits, registers, flip-flops, RAM, ROM, temporary memory, a portion of a conventional storage circuit, and / or a portion of a digital processor system.

[0017] The VD block 106 includes a preamp array 116 and a delay multiplexer DM120. The preamp array 116 is coupled to the multiplexer M112 and includes one or more preamps. The delay multiplexer DM120 is coupled to the preamp array 116. The back-end ADC 124 is coupled to the delay multiplexer DM120. The back-end ADC 124 may include multiple stages, such as a first stage and a second stage illustrated in FIG. 3. Each stage includes a delay block, an AND gate, and a delay comparator. The calibration engine 102 is coupled to multiple stages in the back-end ADC 124. The calibration engine 102, in one example, includes an accumulator. The accumulator is coupled to multiple stages in the back-end ADC 124. The calibration engine 102, in one example, is or is part of a processing unit, a digital signal processor (DSP), a processor, and / or a programmable logic device. The calibration engine 102 may include memory, logic, and / or software.

[0018] In some examples, each component of the VD block 106 can communicate individually with the calibration engine 102 and with other components of the circuit 100. Each block or component of the circuit 100 can also be coupled to other blocks in FIG. 1. These connections are not described herein. The circuit 100 can include one or more conventional components not described herein for simplicity of description.

[0019] In one example, the circuit 100 is an analog-to-digital converter where the VD block performs a voltage delay function and the back-end ADC 124 performs a delay digital function. The circuit 100 operates in a delay calibration mode, a memory calibration mode, and a mission mode. The mission mode is also referred to as the normal operation mode. The delay calibration mode and the memory calibration mode will now be described in that order.

[0020] The calibration engine 102 generates a plurality of input codes, which in some examples correspond to a range of known analog signals. In one example, the plurality of input codes range from a minimum input code to a maximum input code. In one example, the plurality of input codes are uniformly distributed in terms of both frequency and step size. In one version, the step size is the difference between two consecutive input codes. The DAC 104 generates a calibration signal in response to each of the plurality of input codes. For example, the DAC 104 generates a first calibration signal (e.g., a first analog calibration signal) in response to a first input code of the plurality of input codes. The first calibration signal is received by the VD block 106.

[0021] The multiplexer M112 provides the first calibration signal to the preamp array 116 in both the delay calibration mode and the memory calibration mode. In one example, the multiplexer M112 is controlled by the calibration engine 102. Each preamp in the VD block 106 has a different threshold voltage. As shown in FIG. 2, each preamp in the preamp array 116 includes a first input connected to the output of the multiplexer M112 (for receiving the input signal Vin 110 or a calibration signal from the DAC 104) and a second input coupled to the threshold voltage. Each preamp in the preamp array 116 compares the first calibration signal to a threshold voltage (e.g., a threshold voltage associated with each preamp in the preamp array 116) in both the delay calibration mode and the memory calibration mode. The delay multiplexer DM120 generates a delay signal based on the output of one of the preamps.

[0022] A first stage in the back-end ADC 124 generates digital bits in response to the delayed signals from the delay multiplexer DM 120. Thus, the calibration engine 102 generates a plurality of input codes, the DAC 104 generates a plurality of calibration signals in response to the plurality of input codes, the VD block 106 generates a plurality of delayed signals in response to the plurality of calibration signals, and the first stage in the back-end ADC 124 generates a plurality of digital bits in response to the plurality of delayed signals. These plurality of digital bits generated by the first stage represent digital codes generated by the first stage in response to the plurality of input codes generated by the calibration engine 102.

[0023] In one example, the delay calibration mode includes multiple cycles. In one cycle, the calibration engine 102 modifies the delay value of the first delay block in the first stage. The calibration engine 102 generates multiple input codes. The first stage in the back-end ADC 124 generates a digital code in response to the multiple input codes. An accumulator in the calibration engine 102 measures an error number of the first stage. The error number is an absolute difference in the number of 1s and 0s in the digital code. Based on the error number, the calibration engine 102 modifies the delay value of the first delay block in a subsequent cycle. The calibration engine 102 measures the error number generated by the first stage in multiple such cycles. The calibration engine 102 stores the delay value of the first stage with the smallest first stage error number. This delay value is the delay value (or calibrated delay value) of the first delay block in the first stage. In one example, the circuit 100 uses a binary search or other known techniques to find the delay value that minimizes the error number. Nonlinearity in the output of a stage of the back-end ADC 124 is due to the nonlinear transfer function of that stage. The delay calibration mode calibrates the stage to define the optimal gain of that stage over a range defined by multiple input codes.

[0024] The calibration engine 102 then calibrates the delay value of the second delay block in the second stage, which also includes multiple cycles. In one cycle, the calibration engine 102 modifies the delay value of the second delay block in the second stage. The calibration engine 102 generates multiple input codes. The second stage generates a digital code in response to the multiple input codes. An accumulator in the calibration engine 102 measures an error number of the second stage. The error number is an absolute difference in the number of 1s and 0s in the digital code. Based on the error number, the calibration engine 102 modifies the delay value of the second delay block in a subsequent cycle. The calibration engine 102 measures the error number generated by the second stage in multiple such cycles. The calibration engine 102 stores the delay value of the second stage for which the error number of the second stage is the smallest. This delay value is the delay value (or calibrated delay value) of the second delay block in the second stage.

[0025] In a similar manner, the calibration engine 102 measures the error number of each of the stages in the back-end ADC 124 over multiple cycles and also stores the delay value of each stage of the back-end ADC 124. The delay value (or calibrated delay value) for each of the stages in the back-end ADC 124 is then used during other operating modes of the circuit 100. In one example, the delay value is used to correct for any nonlinearity introduced in the back-end ADC 124. The delay calibration mode is described in more detail in connection with the circuit 300 shown in FIG.

[0026] In the memory calibration mode, the calibration engine 102 generates a plurality of input codes. In some examples, the plurality of input codes correspond to a range of known analog signals. The DAC 104 generates a calibration signal in response to an input code of the plurality of input codes. The VD block 106 generates a delayed signal in response to the calibration signal. The back-end ADC 124 generates an output code in response to the delayed signal. The storage circuit 108 stores the input codes at an address associated with the corresponding output code. For example, the storage circuit 108 stores a first input code at an address corresponding to a first output code, and the storage circuit 108 stores a second input code at an address corresponding to a second output code. In one example, the storage circuit 108 maintains a lookup table to store an input code at an address corresponding to an associated output code for all input codes. For example, in one version, when an output code 100 is generated corresponding to an input code 010, the input code 010 is stored at address 100 in the lookup table. Thus, a look-up table in memory circuit 108 is entered with the input codes at the addresses of each of the output codes in the memory calibration mode.

[0027] In the mission mode, the multiplexer M112 provides the input voltage Vin110 to the VD block 106. In one example, the multiplexer M112 is controlled by the calibration engine 102. The VD block 106 generates a delayed signal in response to the input voltage Vin110. The back-end ADC 124 generates a raw code in response to the delayed signal. An input code stored at an address corresponding to the raw code is generated as the final output 130 by the circuit 100. For each value of the input voltage Vin110, the raw code is matched to an address of an output code, and the input code stored at the address is provided as the final output 130. Thus, the mission mode represents, in one version, a normal operation of the circuit 100, in which an analog signal (such as a radio frequency analog signal) is received as Vin110 and converted to a digital (binary) representation via the VD block 106, the back-end ADC 1224, and the storage circuit 108. Thus, the final output 130 is a digital representation of the analog signal Vin 110.

[0028] The multiplexer M112, the VD block 106, the back-end ADC 124, and the storage circuit 108 form one channel in the circuit 100. The circuit 100 can be implemented with two or more channels. In one example, each channel can be implemented in parallel with the other channel. A second channel can include a second multiplexer, a second VD block, a second back-end ADC, and a second storage circuit. The second back-end ADC in the second channel can be similar to the back-end ADC 124, but is calibrated separately because both may have different transfer functions due to manufacturing variations. Multiple channels allow the flexibility of putting one channel into a calibration mode (delay calibration mode or memory calibration mode) and operating the other channel in a mission mode. Multiple channels also allow the flexibility of having one or more channels in delay calibration mode, one or more channels in memory calibration mode, and other channels in mission mode. Thus, when one or more channels are being calibrated, the remaining channels are used in mission mode for analog-to-digital conversion. In one example, all channels are calibrated using DACs 104, and all channels are controlled by the calibration engine 102. In some examples, the back-end ADCs in each channel are individually calibrated, so no matching is required between channels. This also reduces the need for background prediction and calibration algorithms.

[0029] The combination of the preamp array 116, the delay multiplexer DM 120, and the back-end ADC 124 acts as a nonlinear ADC or delay-based ADC in one example. Although this combination is highly nonlinear, the circuit 100 is highly linear and operates at high speed with relaxed area and power requirements. The circuit 100 scales well to technology nodes. The circuit 100 facilitates high linearity requirements for the DAC 104. This is advantageous because it is relatively less difficult to design and implement analog circuits to operate at low speeds with linearity and accuracy. In accordance with the present description, the back-end ADC 124 can be designed to run at high speeds by compromising linearity. However, when the back-end ADC 124 operates in combination with a look-up table in the storage circuit 108, the circuit 100 behaves like a linear analog-to-digital converter (ADC). Similarly, the storage circuit 108 may be implemented in digital circuitry and configured for high speeds.

[0030] Interacting external analog signals with fast digital processing cores generally requires ADCs. Higher speeds in data transmission may require ADCs to operate very fast and with good signal-to-noise ratios. Without the benefit of some examples, such constraints may result in high power dissipation and large area requirements for supporting integrated circuits. These issues may be particularly pronounced at high sampling rates (e.g., sampling rates in the gigasamples / second range) due to analog non-idealities that may limit performance. The example circuit 100 provides a back-end ADC 124 with a look-up table approach that can be calibrated to provide the advantageous performance of highly linear ADCs while opening up a wide architecture with one or more nonlinear ADCs.

[0031] In the delay calibration mode, a certain delay value of each delay block in the back-end ADC 124 is calibrated and fixed, which ensures that the circuit 100 has a minimum gain over the multiple input codes (which correspond to a range of known analog signals) generated by the calibration engine 102. The gain of the circuit 100 is affected by the delay value of each stage in the back-end ADC 124, and the delay calibration mode ensures that the delay value of each stage is optimally calibrated for the circuit 100 to operate as a linear high-speed ADC. The delay calibration mode allows the circuit 100 to act as a linear ADC while the delay of each stage in the back-end ADC 124 is calibrated to obtain an optimal gain over a range defined by multiple input codes.

[0032] Therefore, the circuit 100 does not require any complex algorithms or hardware for digital conversion of the input voltage Vin 110. This reduces the area and power requirements of the circuit 100. Thus, the circuit 100 can be used in RF sampling receivers operating at GSPS speeds. The circuit 100 can be well scaled to technology nodes to support high GSPS transmission rates in future technology nodes.

[0033] FIG. 2 is a block diagram of a portion of the circuit 100 illustrated in FIG. 1 according to an example. The preamp array 116 includes a plurality of preamplifiers, 1 through n, where n is an integer, e.g., preamp 216a, preamp 216b through preamp 216n. In one example, one or more preamplifiers are integrated threshold preamplifiers (preamplifiers with fixed thresholds). The delay multiplexer DM120 is coupled to the plurality of preamplifiers in the preamp array 116. The back-end ADC 124 is coupled to the output of the delay multiplexer DM120. The calibration engine 102 is coupled to each preamplifier in the preamp array 116 via an input line 240, the delay multiplexer DM120, and the back-end ADC 124. In one example, the calibration engine 102 resets the preamplifiers through the input line 240.

[0034] In operation, the preamplifier array 116 receives the input voltage Vin110 from the multiplexer M112 in mission mode. Similar to amplifiers 54-60 of U.S. Patent No. 10,673,456 (which is hereby incorporated by reference in its entirety), each preamplifier receives a different threshold voltage. For example, preamplifier 216a receives the threshold voltage Vt1, preamplifier 216b receives the threshold voltage Vt2, and preamplifier 216n receives the threshold voltage Vtn. In one example, Vt1 < Vt2 < Vtn. The threshold voltages Vt1, Vt2 - Vtn are generated using a voltage divider 230 in one example. In one version, preamplifier 216n is coupled to a voltage source, either directly or via a resistor. Each preamplifier generates first and second output signals (differential output signals) based on the difference between the input voltage Vin110 and the threshold voltage. For example, preamplifier 216a generates a differential signal (first output signal OUT_M1, second output signal OUT_P1). Similarly, preamplifier 216n generates a differential signal (first output signal OUT_Mn and second output signal OUT_Pn). [Patent Document 1] U.S. Patent No. 10,673,456

[0035] Similar to the operation of the multiplexer 211 in U.S. Pat. No. 10,673,452 (incorporated herein by reference in its entirety), the delay multiplexer DM120 receives a first and a second output signal (differential output signal) from each preamplifier of the multiple preamplifiers. The delay multiplexer DM120 generates a delayed signal 202 based on an output of one of the multiple preamplifiers. The delayed signal 202 includes a first delayed signal OUT_M and a second delayed signal OUT_P, and corresponds to the output signal of the preamplifier whose threshold voltage is closest to the input voltage Vin110. For example, when the magnitude of the input voltage Vin110 is closest to the threshold voltage Vt1 of the preamplifier 216a, the first delayed signal OUT_M1 and the second delayed signal OUT_P1 correspond to the first output signal OUT_M1 and the second output signal OUT_P1 of the preamplifier 216a. On the other hand, when the magnitude of the input voltage Vin110 is closest to the threshold voltage Vt2 of the preamplifier 216b, the first delayed signal OUT_M and the second delayed signal OUT_P correspond to the first output signal OUT_M2 and the second output signal OUT_P2 of the preamplifier 216b. In one example, the calibration engine 102 controls the delay multiplexer DM120 to select the output signal of the preamplifier whose threshold voltage is closest to the input voltage Vin110. In another example, in the calibration mode (both the delay calibration mode and the memory calibration mode), the calibration engine 102 controls the delay multiplexer DM120, and in the mission mode, the high-speed logic controls the delay multiplexer DM120. In some examples, the high-speed logic includes a processor, a memory, digital logic, and / or a state machine. [Patent Document 2] U.S. Patent No. 10,673,452

[0036] In some examples, the VD block 106 (the combination of the preamp array 116 and the delay multiplexer DM 120) converts the input voltage Vin 110 to the delayed signals 202 (OUT_P and OUT_M) such that the timing of the delayed signals 202 (OUT_P and OUT_M) represents the input voltage Vin 110. The VD block 106 that may be used to generate the delayed signals 202 (OUT_P and OUT_M) based on the input voltage Vin 110 may be configured and operated as described, for example, in U.S. Patent No. 10,673,456 (based on U.S. Patent Application Serial No. 16 / 410,698). The VD block 106 may include, for example, a conversion and folding circuit as described in U.S. Patent No. 10,673,456, which includes a number of preamplifiers for converting voltage signals into delayed signals, and a folding block including a number of logic gates for selecting the earlier arriving and later arriving of the first delayed signal OUT_M and the second delayed signal OUT_P.

[0037] An example of a voltage delay device that may be incorporated within the VD block 106 and used to generate the delay signals 202 (OUT_P and OUT_M) based on the input voltage Vin110 is illustrated in U.S. Patent Application No. 17 / 131,981, filed December 23, 2020. A voltage delay device configured in accordance with U.S. Patent Application No. 17 / 131,981 may, for example, have first and second comparators connected to first and second lines carrying complementary voltages representative of the input voltage Vin110, generating first and second output signals during an active phase when the complementary voltages reach suitable threshold voltages, such that the delay between the output signals represents the input voltage Vin110. However, this description is not limited to the devices and processes described in detail herein. Other suitable devices may perform suitable voltage delay functions within the VD block 106. As noted above, U.S. Patent No. 10,673,456 and U.S. Patent Application No. 17 / 131,981 are incorporated herein by reference. [Patent Document 3] U.S. Patent Application No. 17 / 131,981

[0038] The preamps (preamp 216a, preamp 216b, preamp 216n) in the preamp array 116 have varying gain (e.g., as used herein, "gain" can mean voltage gain, current gain, or delay; as described in more detail below, the amplifiers / comparators have different delays based on the input signal) as a result of various factors, which can include design, process, input voltage Vin 110, and / or temperature. In one example, the gain and range of the preamps 216a, preamp 216b, preamp 216n can be adjusted and preferably matched across the preamp array 116. The preamp array 116 and back-end ADC 124 enable the circuit 100 to operate as a high-speed, high-performance analog-to-digital converter (ADC).

[0039] 3 is a block diagram of a portion of the circuit 100 shown in FIG. 1 according to an example. The back-end ADC 124 includes a number of stages, shown as a first stage 310a, a second stage 310b, through an nth stage 31, where n is an integer equal to or greater than 1 and is not necessarily equal to the value of n used in FIG. 2. Each stage includes a delay block, an AND gate, and a delay comparator. For example, the first stage 310a includes a delay block 304a, an AND gate 306a, and a delay comparator 308a. Similarly, the second stage 310b includes a delay block 304b, an AND gate 306b, and a delay comparator 308b. The illustrated AND gates are merely exemplary of logic gates that may be employed in accordance with the present description. If desired, these examples may be implemented with or without AND gates and / or with or without gates other than AND gates. Furthermore, in the illustrated configuration, the AND gates 306a, 306b-306n may be essentially identical to one another, and the delay comparators 308a, 308b-308n may be essentially identical.

[0040] The calibration engine 102 is coupled to a number of stages in the back-end ADC 124. The calibration engine 102 includes a first multiplexer MUX1 314 and an accumulator 316. The accumulator 316 includes a second multiplexer MUX2 322, an adder 324, and a register 326. A delay block in each stage of the back-end ADC 124 is coupled to the calibration engine 102. For example, delay block 304a, delay block 304b, delay block 304n, delay block 304n are coupled to the calibration engine 102. A delay comparator in each stage of the back-end ADC 124 is coupled to the first multiplexer MUX1 314 in the calibration engine 102. For example, delay comparator 308a, delay comparator 308b, delay comparator 308n are coupled to the first multiplexer MUX1 314 in the calibration engine 102.

[0041] The accumulator 316 is coupled to the first multiplexer MUX1 314. The second multiplexer MUX2 322 is coupled to the first multiplexer MUX1 314. The adder 324 is coupled to the second multiplexer MUX2 322 and to the register 326. The calibration engine 102 may include multiple other components not shown herein for brevity. The calibration engine 102 may include one or more conventional components not described herein for brevity. Multiple components of the back-end ADC 124 may be coupled to and in communication with the calibration engine 102. However, these connections are not shown in FIG. 3 for brevity.

[0042] In operation, signals AN and BN (N=1, 2, ... n for the first stage 310a, the third stage 310b to the nth stage 310n, respectively) are received by respective AND gates 306a, 306b to 306n. The AND gates 306a, 306b to 306(n-1) generate a corresponding signal AN'. For example, AND gate 306a receives signals A1 and B1 and generates A1'. For each one of the AND gates, the timing of the rising edge of signal AN' tracks the timing of the rising edges of the later arriving signals AN and BN.

[0043] The circuit 100 operates in a delay calibration mode, a memory calibration mode, and a mission mode. The delay calibration mode and the memory calibration mode will now be described in that order. The calibration engine 102 generates a plurality of input codes. In some examples, the plurality of input codes corresponds to a range of known analog signals. In one example, the plurality of input codes ranges from a minimum input code to a maximum input code. In one example, the plurality of input codes are uniformly distributed in terms of both frequency and step size. In one version, the step size is the difference between two consecutive input codes. The DAC 104 generates a calibration signal in response to each of the plurality of input codes. For example, the DAC 104 generates a first calibration signal (e.g., a first analog calibration signal) in response to a first input code of the plurality of input codes. The first calibration signal is received by the VD block 106.

[0044] The multiplexer M112 provides the first calibration signal to the preamplifier array 116 in both the delay calibration mode and the memory calibration mode. In one example, the multiplexer M112 is controlled by the calibration engine 102. Each preamplifier in the VD block 106 has a different threshold voltage. As described in connection with FIG. 2, the delay multiplexer DM120 outputs a delay signal 302 based on an output of one of the preamplifiers. The delay signal 302 includes a differential signal (the first delayed signal OUT_M and the second delayed signal OUT_P) and corresponds to the output signal of the preamplifier whose threshold voltage is closest to the calibration signal. In one example, the calibration engine 102 enables the delay multiplexer DM120 in the calibration mode (both the delay calibration mode and the memory calibration mode), and the high-speed logic enables the delay multiplexer DM120 in the mission mode. In some examples, the high-speed logic includes a processor, a memory, digital logic, and / or a state machine.

[0045] The back-end ADC 124 receives the delayed signals 302 (OUT_P and OUT_M) from the VD block 106. The timing of the first delayed signal OUT_M and the second delayed signal OUT_P has a delay that represents the input voltage Vin 110. The first stage 310a in the back-end ADC 124 generates digital bits in response to the delayed signal 302 from the delay multiplexer DM 120. Thus, the calibration engine 102 generates a plurality of input codes, the VD block 106 generates a plurality of delayed signals in response to the plurality of input codes, and the first stage 310a in the back-end ADC 124 generates a plurality of digital bits in response to the plurality of delayed signals. These plurality of digital bits generated by the first stage 310a represent the digital code generated by the first stage in response to the plurality of input codes generated by the calibration engine 102. Thus, the digital code includes a plurality of digital bits, and the digital bits correspond to the input codes.

[0046] The delay calibration mode may be implemented over multiple cycles. For example, referring to the delay calibration of the first stage 310a, in one cycle, the calibration engine 102 modifies the delay value D1 312a of the delay block 304a in the first stage 310a. The calibration engine 102 generates multiple input codes. The first stage 310a in the back-end ADC 124 generates digital codes in response to the multiple input codes. The digital codes from the first stage 310a are provided to an accumulator 316 in the calibration engine 102 through a first multiplexer MUX1 314. The accumulator 316 in the calibration engine 102 measures an error number of the first stage 310a. The error number is the absolute difference in the number of ones and zeros in the digital code.

[0047] In operation, the accumulator 316, in one version, serially processes the digital bits in the digital code. The accumulator 316 includes a second multiplexer MUX2 322 that receives the digital bits from the first multiplexer MUX1 314. Based on the digital bits, the second multiplexer MUX2 322 generates one of the inputs, +1 or -1. The adder 324 adds the previous value of the error number, stored in a register 326, to the input received from the second multiplexer MUX2 322 to generate a new value of the error number. This new value of the error number is stored in the register 326.

[0048] Based on the error number stored in the register 326, the calibration engine 102 modifies the delay value D1 312a of the delay block 304a in a subsequent cycle (e.g., the next cycle). The calibration engine 102 measures the error number generated by the first stage 310a in multiple such cycles. The calibration engine 102 stores the delay value of the first stage 310a that has the smallest error number of the first stage 310a. This delay value is the delay value D1 312a of the delay block 304a in the first stage 310a. The delay value D1 312a of the first stage 310a is stored in a memory location (not shown in FIG. 3) specific to the first stage 310a. Thus, the calibration engine 102 provides multiple input codes over multiple cycles, and the delay value of a stage (e.g., the first stage 310a) is repeatedly modified until the delay calibration mode of that stage is completed. Nonlinearity in a given output of a given stage of the back-end ADC 124 is due to the nonlinear transfer function of that stage. The delay calibration mode calibrates the stage to define an optimal gain for that stage over a range defined by multiple input codes. For example, the stored delay value D1 312a of the first stage 310a is used to compensate for any nonlinearity due to the nonlinear transfer function of the first stage 310a. Thus, the delay calibration mode calibrates the first stage 310a to obtain an optimal gain for the first stage 310a over a range defined by multiple input codes.

[0049] Once the first stage 310a is calibrated, the calibration engine 102 calibrates the delay value D2 312b of the delay block 304b in the second stage 310b. This also includes multiple cycles. In one cycle, the calibration engine 102 modifies the delay value D2 312b of the delay block 304b in the second stage 310b. The calibration engine 102 generates multiple input codes. The second stage 310b generates a digital code in response to the multiple input codes. The accumulator 316 in the calibration engine 102 measures an error number of the first stage 310b. The error number is the absolute difference in the number of 1s and 0s in the digital code. Based on the error number stored in the register 326, the calibration engine 102 modifies the delay value D1 312b of the delay block 304b in a subsequent cycle. The calibration engine 102 measures the error number produced by the second stage 310b over a number of such cycles. The calibration engine 102 stores the delay value of the second stage 310b that results in the smallest error number for the second stage 310b. This delay value is the delay value D2 312b of the delay block 304b in the second stage 310b. The delay value D2 312b may be stored in a memory location specific to the second stage 310b (not shown in FIG. 3), in the same memory as the stored delay value D1 312a, or in a separate memory.

[0050] In a similar manner, the calibration engine 102 measures the error number of each of the multiple stages in the back-end ADC 124 over multiple cycles and also stores the delay value of each stage of the back-end ADC 124. Based on the error number of each stage, each stage is modified by the calibration engine 102 to obtain an optimal uniform gain up to that stage. Thus, the delay calibration mode can be performed repeatedly, whereby the delay value of a stage is calibrated over one or more cycles, and then the delay value of the next stage is calibrated. During the calibration mode, each stage (310a, 310b-310n) is repeatedly calibrated, and the corresponding delay value (D1, D2-Dn) is generated and stored as described above. The delay value (or calibrated delay value) for each of the multiple stages in the back-end ADC 124 is then used during other operating modes of the circuit 100. Thus, the circuit 100 uses a single accumulator 316 to calibrate all stages in the back-end ADC 124.

[0051] In the memory calibration mode, the calibration engine 102 generates a plurality of input codes. In some examples, the plurality of input codes correspond to a range of known analog signals. The DAC 104 generates a calibration signal in response to an input code of the plurality of input codes. The VD block 106 generates a delay signal in response to the calibration signal. The back-end ADC 124 generates an output code in response to the delay signal. The delay values ​​of the stages in the back-end ADC 124 stored during the delay calibration mode are used in the memory calibration mode to generate an output code. The storage circuit 108 stores the input codes at addresses associated with the corresponding output codes. For example, the storage circuit 108 stores a first input code at an address corresponding to a first output code, and the storage circuit 108 stores a second input code at an address corresponding to a second output code. In one example, the storage circuit 108 maintains a look-up table to store an input code at an address corresponding to an associated output code for all input codes. For example, in one version, when an output code of 100 is generated in response to an input code of 010, the input code of 010 is stored in the lookup table at address 100. Thus, the lookup table in storage circuit 108 is populated with the input codes at the addresses of each of the output codes in the memory calibration mode.

[0052] In the mission mode, the multiplexer M112 provides the input voltage Vin110 to the VD block 106. In one example, the multiplexer M112 is controlled by the calibration engine 102. The VD block 106 generates a delayed signal in response to the input voltage Vin110. The back-end ADC 124 generates a low code in response to the delayed signal. An input code stored at an address corresponding to the low code is generated as the final output 130 by the circuit 100. For each value of the input voltage Vin110, the low code is matched to an address of an output code, and the input code stored at the address is provided as the final output 130. Thus, when the input voltage Vin110 is received by the circuit 100, a digital code corresponding to the input voltage Vin110 is generated by the circuit 100, and the look-up table in the storage circuit 108 is used by the circuit 100 in converting the input voltage Vin110 to a digital code.

[0053] In the delay calibration mode, a certain delay value of each delay block in the back-end ADC 124 is calibrated and fixed, which ensures that the circuit 100 has a minimum gain over the multiple codes (which correspond to the range of known analog signals) generated by the calibration engine 102. The gain of the circuit 100 is affected by the delay value of each stage in the back-end ADC 124, and the delay calibration mode ensures that the delay value of each stage is optimally calibrated for the circuit 100 to operate as a linear high-speed ADC. The delay calibration mode allows the circuit 100 to act as a linear ADC to obtain an optimal gain over the range defined by the multiple input codes, when the delay of each stage in the back-end ADC 124 is calibrated.

[0054] Therefore, the circuit 100 does not require any complex algorithms or hardware for digital conversion of the input voltage Vin 110. This reduces the area and power requirements of the circuit 100. Thus, the circuit 100 can be used in RF sampling receivers operating at GSPS speeds. The circuit 100 can be well scaled to technology nodes to support high GSPS transmission rates in future technology nodes.

[0055] FIG. 4 is a flowchart 400 of a method of operation of a circuit according to an example. The flowchart 400 is described in relation to the circuit 100 of FIG. 1 and / or components thereof illustrated in FIG. 2 and FIG. 3. The flowchart 400 illustrates a method for operating a circuit in a delay calibration mode. In step 402, a delay signal is generated in response to a calibration signal. In the circuit 100, the calibration engine 102 generates a plurality of input codes. In some examples, the plurality of input codes corresponds to a range of known analog signals. In one example, the plurality of input codes ranges from a minimum input code to a maximum input code. In one example, the plurality of input codes are uniformly distributed in terms of both frequency and step size. In one version, the step size is the difference between two consecutive input codes. The DAC 104 generates a calibration signal in response to each of the plurality of input codes. For example, the DAC 104 generates a first calibration signal (e.g., a first analog calibration signal) in response to a first input code of the multiple input codes. The VD block 106 receives the calibration signal and generates a delayed signal. The VD block 106 includes a preamp array 116 and a delay multiplexer DM120. The multiplexer M112 provides the first calibration signal to the preamp array 116. In one example, the multiplexer M112 is controlled by the calibration engine 102. Each preamp in the VD block 106 has a different threshold voltage. In both the delay calibration mode and the memory calibration mode, each preamp in the preamp array 116 compares the first calibration signal with a threshold voltage (e.g., a threshold voltage associated with each preamp in the preamp array 116). The delay multiplexer DM120 generates a delayed signal based on an output of one preamp in the multiple preamps. As described in connection with FIG. 3, the delayed signals 302 include a first delayed signal OUT_M and a second delayed signal OUT_P, which correspond to the output signal of the preamplifier whose threshold voltage is closest to the calibration signal.

[0056] In step 404, the delayed signal is provided to a back-end ADC. The back-end ADC includes a first stage of a plurality of stages. An error number of the first stage is measured by a calibration engine in step 406. The error number is the absolute difference in the number of ones and zeros generated by the first stage. The back-end ADC 124 includes a plurality of stages, as shown in FIG. 3, as first stage 310a, second stage 310b through nth stage 310n. Each stage includes a delay block, an AND gate, and a delay comparator.

[0057] A first stage 310a in the back-end ADC 124 generates digital bits in response to the delayed signal 302 from the delay multiplexer DM 120. The calibration engine 102 generates a plurality of input codes, the VD block 106 generates a plurality of delayed signals in response to the plurality of input codes, and the first stage 310a in the back-end ADC 124 generates a plurality of digital bits in response to the plurality of delayed signals. The plurality of digital bits generated by the first stage 310a represent digital codes generated by the first stage in response to the plurality of input codes generated by the calibration engine 102.

[0058] A first stage 310a in the back-end ADC 124 generates a digital code in response to a plurality of input codes. The digital code from the first stage 310a is provided to an accumulator 316 in the calibration engine 102 through a first multiplexer MUX1 314. The accumulator 316 in the calibration engine 102 measures an error number of the first stage 310a. The error number is the absolute difference in the number of 1s and 0s in the digital code.

[0059] In step 408, the delay value of the first stage with the smallest error number is stored in the calibration engine. In the circuit 100, the calibration engine 102 stores the delay value of the first stage 310a with the smallest error number for the first stage 310a. This delay value is the delay value D1 312a of the delay block 304a in the first stage 310a.

[0060] The circuit 100 operates in a delay calibration mode that may be implemented over multiple cycles. For example, referring to the delay calibration of the first stage 310a, in one cycle, the calibration engine 102 modifies the delay value D1 312a of the delay block 304a in the first stage 310a. The calibration engine 102 generates multiple input codes. The first stage 310a in the back-end ADC 124 generates digital codes in response to the multiple input codes. The digital codes from the first stage 310a are provided to an accumulator 316 in the calibration engine 102 through a first multiplexer MUX1 314. The accumulator 316 in the calibration engine 102 measures an error number of the first stage 310a. The error number is the absolute difference in the number of ones and zeros in the digital code.

[0061] Based on the error number, the calibration engine 102 modifies the delay value D1 312a of the delay block 304a in a subsequent cycle (e.g., the next cycle). The calibration engine 102 measures the error number generated by the first stage 310a in multiple such cycles. The calibration engine 102 stores the delay value of the first stage 310a that has the smallest error number of the first stage 310a. This delay value is the delay value D1 312a (or calibrated delay value) of the delay block 304a in the first stage 310a. The delay value D1 312a of the first stage 310a is stored in a memory location (not shown in FIG. 3) specific to the first stage 310a. Thus, the calibration engine 102 provides multiple input codes over multiple cycles, and the delay value of a stage (e.g., the first stage 310a) is repeatedly modified until the delay calibration mode of that stage is completed. Nonlinearity in a given output of a given stage of the back-end ADC 124 is due to the nonlinear transfer function of that stage. The delay calibration mode calibrates the stage to define the optimal gain of that stage over a range defined by multiple input codes. For example, the stored delay value D1 312a of the first stage 310a is used to compensate for any nonlinearity due to the nonlinear transfer function of the first stage 310a. Thus, the delay calibration mode calibrates the first stage 310a to obtain the optimal gain of the first stage 310a over a range defined by multiple input codes.

[0062] Once the first stage 310a is calibrated, the calibration engine 102 calibrates the delay value D2 312b of the delay block 304b in the second stage 310b. This also includes multiple cycles. In one cycle, the calibration engine 102 modifies the delay value D2 312b of the delay block 304b in the second stage 310b. The calibration engine 102 generates multiple input codes. The second stage 310b generates a digital code in response to the multiple input codes. An accumulator 316 in the calibration engine 102 measures an error number of the first stage 310b. The error number is the absolute difference in the number of 1s and 0s in the digital code. Based on the error number, the calibration engine 102 modifies the delay value D2 312b of the delay block 304b in a subsequent cycle. The calibration engine 102 measures the error number produced by the second stage 310b over a number of such cycles. The calibration engine 102 stores the delay value of the second stage 310b that has the smallest error number for the second stage 310b. This delay value is the delay value D2 312b (or calibrated delay value) of the delay block 304b in the second stage 310b. The delay value D2 312b may be stored in a memory location specific to the second stage 310b (not shown in FIG. 3), in the same memory as the stored delay value D1 312a, or in a separate memory.

[0063] In a similar manner, the calibration engine 102 measures the error number of each of the multiple stages in the back-end ADC 124 over multiple cycles, and stores the delay value (or calibrated delay value) of each stage of the back-end ADC 124. Based on the error number of each stage, the calibration engine 102 modifies each stage to compensate for the nonlinearity of each stage. Thus, the delay calibration may be performed iteratively, where the delay value of a stage is calibrated over one or more cycles, and then the delay value of the next stage is calibrated. The delay values ​​for each of the multiple stages in the back-end ADC 124 are then used during other operating modes of the circuit 100.

[0064] This method allows the circuit 100 to calibrate and fix the delay value of each delay block in the back-end ADC 124 in the delay calibration mode, thereby ensuring that the circuit 100 has a minimum gain across multiple codes generated by the calibration engine 102. The gain of the circuit 100 is affected by the delay value of each stage of the back-end ADC 124 (which is subject to irregularities and nonlinearities based on, for example, semiconductor manufacturing variations and temperature dependent factors), and the method via the delay calibration mode ensures that the delay value of each stage is optimally calibrated for the circuit 100 to operate as a high-speed ADC. The delay calibration mode allows the circuit 100 to act as a linear ADC when the delay of each stage in the back-end ADC 124 is calibrated to obtain an optimal gain across a range defined by multiple input codes.

[0065] Thus, this method provides that the circuit 100 does not require any complex algorithms or hardware for digital conversion of the input voltage Vin 110. Thus, some example methods ensure that the circuit 100 can be used in RF sampling receivers operating at GSPS speeds. The circuit 100 can be well scaled to technology nodes and support high GSPS transmission rates in future technology nodes.

[0066] FIG. 5 is a flowchart 500 of a method of operation of a circuit, according to an example. The flowchart 500 is described in conjunction with the circuit 100 of FIG. 1 and / or components thereof illustrated in FIGS. 2 and 3. The flowchart 500 illustrates calibrating a plurality of stages 310a, 310b, 310n, for example, using a delay calibration mode including a plurality of cycles. In step 502, a delay value of a stage k is set. In the circuit 100, for example, the back-end ADC 124 includes a plurality of stages illustrated in FIG. 3 as the first stage 310a, the second stage 310b, 310n ...

[0067] In step 504, the calibration engine generates a number of input codes. For example, in circuit 100, calibration engine 102 generates a number of input codes. A first stage 310a (or stage k) in back-end ADC 124 generates a digital code in response to the number of input codes. The digital code from first stage 310a (or stage k) is provided to an accumulator 316 in calibration engine 102. In step 506, the number of 1s (c1) and 0s (c0) in the output of stage k is counted. An absolute error number (E) is measured from the difference between the 1s (c1) and 0s (c0). E = |c1-c0| (1) An accumulator 316 in the calibration engine 102 measures the error number of the first stage 310a (or stage k). The error number is the absolute difference in the numbers in the digital code generated by the first stage 310a (or stage k). In step 508, it is determined whether the search (calibration of stage k) is complete. The search (or calibration of stage k) is considered complete when an error number at the output of stage k has been obtained for all input codes. In one version, the search is considered complete when there is a change in the sign of the error number (E) for stage k. In another example, the search is considered complete when the minimum absolute value of the error number (E) has been obtained. If the search (calibration of stage k) is complete, the method proceeds to step 520; otherwise, the method proceeds to step 512.

[0068] In step 512, the delay value of stage k is modified. The delay value is modified based on the error number (E) (or the relative number of ones and zeros) of that stage. If the error number (E) is greater than zero, the delay value of stage k is incremented, and when the error number (E) is less than zero, the delay value of stage k is decremented. In circuit 100, for example, based on the error number (or the number of ones and zeros), calibration engine 102 modifies delay value D1 312a of delay block 304a in the first stage 310a. In one version, if the error number is greater than a threshold, the delay value of delay block 304a is incremented, and if the error number is less than the threshold, the delay value of delay block 304a is decremented.

[0069] Steps 504-512 are repeated until the search (or delay calibration) is completed for stage k. In one version, steps 504-512 are repeated until there is a change in the sign of the error number (E) for stage k. In another example, steps 504-512 are repeated until the minimum absolute value of the error number (E) is obtained. In circuit 100, the delay calibration mode may also include multiple cycles. In one example, delay calibration begins with the first stage 310a (k=1) at step 502. In each cycle of steps 504-512, calibration engine 102 iteratively modifies delay value D1 312a of delay block 304a. Calibration engine 102 measures the error number generated by first stage 310a in multiple such cycles.

[0070] In step 520, the delay of stage k where the minimum absolute value of the error number (E) is obtained is fixed. In the circuit 100, the calibration engine 102 stores the delay value of the first stage 310a where the absolute value of the error number of the first stage 310a is the minimum. This delay value is the delay value D1 312a of the delay block 304a in the first stage 310a. In step 524, in a system having n stages, where n is the last stage, the method compares whether k is equal to n. In step 526, if the method has not reached the last stage, in one example, k is incremented by 1. In another example, k is incremented by an integer greater than 1. Then, all steps illustrated in the flowchart 500 are repeated for stage k+1.

[0071] In step 528, if the method has reached the final stage (n), the system is reset and the steps illustrated in flowchart 500 are repeated from the first stage to the nth stage. Similarly, in circuit 100, calibration engine 102 measures the error number of each of the stages in back-end ADC 124 over multiple cycles and also stores the delay value of each of the stages in back-end ADC 124. The delay value for each of the stages in back-end ADC 124 is then used during other operating modes of circuit 100. In some examples, step 528 is optional.

[0072] The method illustrated in flow chart 500 allows circuit 100 to calibrate and compensate for the delay value of each delay block in back-end ADC 124 in a delay calibration mode, thereby ensuring that circuit 100 has a minimum gain across multiple codes generated by calibration engine 102. The gain of circuit 100 is affected by the delay value of each stage in back-end ADC 124, and the method through delay calibration mode ensures that the delay value of each stage is optimally calibrated for circuit 100 to operate as a linear high-speed ADC. The method allows circuit 100 to act as a linear ADC when the delay of each stage in back-end ADC 124 is calibrated to obtain optimal gain across a range defined by multiple input codes.

[0073] Thus, the method provides that the circuit 100 does not require any complex algorithms or hardware for digital conversion of the input voltage Vin 110. This reduces the area and power requirements of the circuit 100. Thus, the method ensures that the circuit 100 can be used in RF sampling receivers operating at GSPS speeds. The circuit 100 can be well scaled to technology nodes and support high GSPS transmission rates in future technology nodes.

[0074] 6 is a graph illustrating the AND gate delay and the comparator delay generated by the AND gate and the delay comparator, respectively, in a stage of the back-end ADC, according to an example. The graph is described with reference to the back-end ADC 124 illustrated in FIG. 3. The graph includes an X-axis (T_IN) and a Y-axis (output delay). The AND gate (e.g., AND gates 306a, 306b-306n) delay and the comparator (e.g., delay comparators 308a, 308b-308n) delay are functions of the input signal delay, according to an example. The input signal delay is the delay between the signal received by the AND gate or the signal received by the delay comparator. As shown, the AND gate delay 602 contributed by each AND gate is linearly related to the absolute value of the input signal delay T_IN, where the input signal delay T_IN is the timing difference between the signals AN and BN input to each AND gate, and N is an integer, where N is equal to 1 for the first stage 310a and N is equal to 2 for the second stage 310b. In the illustrated configuration, the relationship of the AND gate delay 602 to the input signal delay T_IN is linear regardless of whether AN and BN are leading or following.

[0075] Signals AN and BN are also applied to inputs of a delay comparator, causing the delay comparator to generate a corresponding signal BN'. For each one of the delay comparators (e.g., 308a and 308b), the timing of the rising edge of signal BN' tracks the timing of the rising edge of the earlier arriving signals AN and BN. In particular, for each one of the delay comparators, the timing of the rising edge of signal BN' is equal to (1) the rising edge timing of the earlier arriving signals AN and BN plus (2) a comparator delay 604 that is logarithmically inversely related to the absolute value of the input signal delay T_IN (in other words, the comparator delay is larger for more similar input values, and the larger the difference between the two inputs to that comparator, the smaller the comparator delay).

[0076] 7 is a graph illustrating the output signal delay of a stage as a function of the input signal delay of the back-end ADC stage according to an example. The AND gate delay 602 is subtracted from the comparator delay 604 to obtain the output signal delay T_OUT for any given single-bit stage, e.g., the first stage 310a. When the absolute value of the input signal delay T_IN is less than the threshold delay T_THRES, the output signal delay T_OUT is positive (meaning that the rising edge of the signal BN' generated by the respective delay comparator delays the rising edge of the signal AN' generated by the respective AND gate). On the other hand, when the absolute value of the input signal delay T_IN is greater than the threshold delay T_THRES, the output signal delay T_OUT is negative (meaning that the rising edge of the signal AN' leads the rising edge of the corresponding signal BN'). The positive or negative nature of the output signal delay T_OUT is reported to the calibration engine 102.

[0077] In operation, the delay comparator 308a issues a first code signal ("1" or "0") to the calibration engine 102. The first code signal (an example of a digital signal according to the present description) is based on which of the rising edges of signals A1 and B1 is received first by the delay comparator 308a such that the first code signal reflects the order of the rising edges of signals A1 and B1 applied to the delay comparator 308a. The AND gate 306a and the delay comparator 308a generate signals A1' and B1' that are applied to the second stage 310b. The delay comparator 308b outputs a second code signal ("1" or "0") to the calibration engine 102. The second code signal is based on which of the rising edges of signals A2 and B2 is received first by delay comparator 308b such that the second code signal reflects the order of the rising edges of signals A2 and B2 applied to delay comparator 308b.

[0078] Since the delay between signals A1 and B1 is predictable as a function of the input voltage Vin110 and vice versa, and the delay between signals AN' and BN' output by successive stages is predictable as a function of the signals AN and BN received from the previous stage and vice versa, the code signals output by the delay comparators of successive stages are predictable as a function of the input voltage Vin110 and vice versa. Thus, the code of the code signals may be reliably compared with a pre-determined correlation to determine an approximation of the input voltage Vin110. In operation, the timing of signals A1 and B1 is functionally (i.e., predictably) related to the timing of signals OUT_P and OUT_M, whose timing correlates with the input voltage Vin110 as described above. The timing of signals AT and BT is functionally (i.e., predictably) related to the timing of signals A1 and B1, etc. Thus, since the timing of signals OUT_P and OUT_M is functionally (i.e., predictably) related to the input voltage Vin110, the timing of lines A1, B1, A1', B1', etc., which determine the sign signal of the output code, is also functionally related to the input voltage Vin110.

[0079] 8A and 8B are graphs illustrating the output signal delay of different stages as a function of the input signal delay of the back-end ADC according to an example. As described in relation to FIG. 7, the AND gate delay 602 is subtracted from the comparator delay 604 to obtain the output signal delay T_OUT for any given single-bit stage, e.g., the first stage 310a. When the absolute value of the input signal delay T_IN is less than the threshold delay T_THRES, the output signal delay T_OUT is positive (meaning that the rising edge of the signal BN' generated by the respective delay comparator delays the rising edge of the signal AN' generated by the respective AND gate). On the other hand, when the absolute value of the input signal delay T_IN is greater than the threshold delay T_THRES, the output signal delay T_OUT is negative (meaning that the rising edge of the signal AN' leads the rising edge of the corresponding signal BN').

[0080] Graph 802a shows the output signal delay for the first and second stages in the conventional circuit. Graph 802b shows the output signal delay for the first stage 310a and the second stage 310b of the circuit 100. Graph 804a shows the output signal delay for the third and fourth stages in the conventional circuit. Graph 804b shows the output signal delay for the third stage 310c and the fourth stage 310d of the circuit 100. Thus, from graph 802a, the gain profile of the second stage is asymmetric, with higher gain at the toggle point and lower gain at the limit point. Also, if correction is made to correct the asymmetry of the second stage, it will cause errors during the calibration of the subsequent stage. Also, the calibration of the second stage at the toggle point of the third stage will cause errors during the calibration of the subsequent stage. However, the circuit 100 can address all of these difficulties. As depicted in graph 802b, the circuit 100 provides a symmetric gain profile for the second stage 310b. The circuit 100 employs a delay calibration mode that ensures that the delay value of each stage in the back-end ADC 124 is calibrated. Similarly, graph 804b illustrates that the circuit 100 provides a symmetric gain profile for the third stage 310c and the fourth stage 310d.

[0081] The calibration engine 102 measures an error number for each of the stages in the back-end ADC 124 over multiple cycles and stores a delay value for each stage of the back-end ADC 124. The error number is the absolute difference in the number of ones and zeros in the digital code generated by a stage. The delay value (or calibrated delay value) for each of the stages in the back-end ADC 124 is then used during other operation modes of the circuit 100. These delay values ​​(or calibrated delay values) for each stage are distributed asymmetrically across the range of input codes to make the gain uniform. Thus, as illustrated by graphs 802b and 804b, the delay calibration mode ensures that the delay values ​​for each stage are optimally calibrated for the circuit 100 to operate as a high-speed ADC. The calibration mode ensures a better standard deviation, resulting in a more uniform gain across multiple regions. The circuit 100 also averages each stage during delay calibration, making it more robust to noise.

[0082] 9 is a block diagram of an example device 900 in which aspects of the examples can be implemented. Device 900 may be, be incorporated within, or be part of a server farm, a vehicle, a communication device, a transceiver, a personal computer, a gaming platform, a computing device, or any other type of electronic system. Device 900 may include one or more conventional components not described herein for brevity of explanation.

[0083] In one example, device 900 includes a processor 902 and memory 906. Processor 902 can be a CISC (Complex Instruction Set Computer) CPU, a RISC (Reduced Instruction Set Computer) CPU, a Digital Signal Processor (DSP), a processor, a CPLD (Complex Programmable Logic Device), or an FPGA (Field Programmable Gate Array).

[0084] Memory 906 (which may be memory such as RAM, flash memory, or disk storage) stores one or more software applications (e.g., embedded applications) that, when executed by processor 902, perform any suitable functions associated with device 900.

[0085] The processor 902 may include memory and logic to store information that is frequently accessed from the memory 906. The device 900 includes a circuit 910. In one example, the processor 902 may be disposed on the same printed circuit board (PCB) or card as the circuit 910. In another example, the processor 902 is external to the device 900. The circuit 910 may function as an analog-to-digital converter.

[0086] The circuit 910 is similar in connection and operation to the circuit 100 of Figure 1. The circuit 910 includes a calibration engine (e.g., calibration engine 102), a digital-to-analog converter (DAC) (e.g., DAC 104), a multiplexer (e.g., multiplexer M112), a voltage delay (VD) block (e.g., VD block 106), a back-end analog-to-digital converter (ADC) (e.g., back-end ADC 124), and a storage circuit (e.g., storage circuit 108). The VD block includes a preamplifier array (e.g., preamplifier array 116) and a delay multiplexer DM (e.g., delay multiplexer DM 120). The multiplexer receives an input voltage Vin. The preamplifier array includes a plurality of preamplifiers (as shown in Figure 2).

[0087] The VD block implements the voltage delay function. The back-end ADC implements the delay-to-digital function. Similar to the above description, the circuit 910 operates in a delay calibration mode, a memory calibration mode, and a mission mode.

[0088] The term "coupled" is used throughout the specification. This term may encompass any connection, communication, or signal path that allows for a functional relationship consistent with this description. For example, in a first example, device A is coupled to device B when device A provides a signal to control device B to perform a certain action, or in a second example, device A is coupled to device B via an intervening component C, where the intervening component C does not substantially change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal provided by device A.

[0089] A device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by a manufacturer to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may occur through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnections of the device, or from a combination thereof.

[0090] As used herein, "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are used generally to mean an interconnection or termination between device elements, circuit elements, integrated circuits, a device, or other electronic or semiconductor components.

[0091] A circuit or device described herein as including certain components may instead be adapted to be combined with those components to form the described circuit or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (voltage and / or current sources) may instead include only the semiconductor elements (e.g., a semiconductor die and / or integrated circuit (IC) package) in a single physical device and may be adapted to be combined with at least some of the passive elements and / or sources to form the described structure during or after manufacture, e.g., by an end user and / or a third party.

[0092] Although the use of particular transistors is described herein, other transistors (or equivalent devices) may be substituted. For example, a p-type metal oxide silicon FET ("MOSFET") may be substituted for an n-type MOSFET with little or no modification to the circuit. Also, other types of transistors (such as bipolar transistors (BJTs)) may be used.

[0093] The circuits described herein are reconfigurable to include replaced components to provide functionality at least partially similar to that available prior to the replacement of the components. A component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown, unless otherwise stated. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in series between the same two nodes, respectively, as a single resistor or capacitor.

[0094] Use of the term "ground" in the preceding description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, shared ground, and / or any other form of ground connection applicable or suitable to the teachings of the present description. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means ±10 percent of the stated value.

[0095] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the appended claims.

Claims

1. 1. An analog-to-digital converter (ADC), comprising: a voltage delay (VD) block configured to generate a delay signal in response to a calibration signal; a back-end ADC coupled to the VD block and configured to receive the delayed signal, the back-end ADC including a plurality of stages including a first stage; a calibration circuit coupled to the plurality of stages and to the VD block, determining an error number for the first stage in response to the delayed signal; storing the delay value of the first stage which has the smallest error number; The calibration circuit is configured to An ADC comprising:

2. 2. The ADC of claim 1 , an AND gate coupled to the delay block; and a delay comparator coupled to the delay block and to the calibration circuit.

3. 2. The ADC of claim 1 , The ADC, wherein the calibration circuit includes an accumulator, the calibration circuit further configured to generate a plurality of input codes.

4. 4. The ADC of claim 3, The ADC further includes a digital-to-analog converter (DAC) coupled to the calibration circuit, the DAC configured to generate the calibration signal in response to an input code of the plurality of input codes.

5. 5. The ADC of claim 4, the ADC is configured to operate in a delay calibration mode, a memory calibration mode, and a mission mode; the delay calibration mode includes a plurality of cycles, and in a cycle of the plurality of cycles, the calibration circuit is further configured to modify a delay value of a first delay block in the first stage to generate the plurality of input codes; the VD block is further configured to generate a plurality of delayed signals in response to the plurality of input codes; the first stage configured to generate a digital code in response to the plurality of delayed signals; The ADC, wherein the accumulator is configured to determine the error number of the first stage, the error number being an absolute difference in a number of ones and zeros in the digital code.

6. 6. The ADC of claim 5, The delay value for which the first stage error number is the smallest is stored in the calibration circuit as the first stage delay value.

7. 7. The ADC of claim 6, the plurality of stages of the back-end ADC further comprising a second stage coupled to the first stage and configured to receive an output of the first stage; In the delay calibration mode, the calibration circuit is further configured to modify a delay value of a second delay block in the second stage to generate the plurality of input codes; the VD block is further configured to generate a plurality of delayed signals in response to the plurality of input codes; the second stage further configured to generate a digital code in response to the plurality of delayed signals; The ADC, wherein the accumulator is further configured to measure an error number of the second stage, the error number being an absolute difference in a number of ones and zeros in the digital code.

8. 8. The ADC of claim 7, The delay value for which the error number of the second stage is the smallest is stored in the calibration circuit as the delay value of the second stage.

9. 9. The ADC of claim 8, The ADC further includes a storage circuit coupled to the back-end ADC.

10. 10. The ADC of claim 9, In the memory calibration mode, the calibration circuitry is further configured to generate a plurality of input codes; the DAC is further configured to generate a calibration signal in response to an input code of the plurality of input codes; the VD block is further configured to generate a delayed signal in response to the calibration signal; the back-end ADC is further configured to generate an output code in response to the delayed signal; The storage circuit is configured to store the input code at an address corresponding to the output code.

11. 6. The ADC of claim 5, In the mission mode, the VD block is further configured to generate a delayed signal in response to the input voltage; the back-end ADC is further configured to generate a low code in response to the delayed signal; The input code stored at the address corresponding to the row code is generated as a final output of the ADC.

12. 5. The ADC of claim 4, The ADC further includes a multiplexer coupled to the DAC, the multiplexer configured to receive an input voltage and the calibration signal.

13. 13. The ADC of claim 12, The VD block is one or more preamplifiers, each preamplifier configured to compare one of the input voltage and the first calibration signal to a threshold voltage; a delay multiplexer coupled to the plurality of preamplifiers, the delay multiplexer configured to generate the delayed signal based on an output of one of the preamplifiers; An ADC comprising:

14. 1. A method of operating an analog-to-digital converter (ADC), comprising: generating a delayed signal in response to the calibration signal; providing the delayed signal to a back-end ADC including a plurality of stages, the plurality of stages including a first stage; determining an error number of the first stage with a calibration circuit, the error number being an absolute difference in the number of ones and zeros produced by the first stage; and storing the delay value of the first stage having the smallest error number in the calibration circuit; A method comprising:

15. 15. The method of claim 14, generating a plurality of input codes with the calibration circuit; generating the calibration signal in response to an input code of the plurality of input codes; The method further comprises:

16. 15. The method of claim 14, Measuring the error number includes performing a plurality of cycles, and in a cycle of the plurality of cycles: modifying a delay value of a first delay block in the first stage; generating said plurality of input codes by said calibration circuit; generating a digital code by the first stage in response to the plurality of input codes; measuring an absolute difference in the number of 1s and 0s in the digital code.

17. 17. The method of claim 16, The method further comprising storing the delay value with the smallest error number for the first stage as the delay value for the first stage.

18. 20. The method of claim 17, The method further comprising providing an output of the first stage to a second stage in the back-end ADC.

19. 20. The method of claim 18, modifying a delay value of a second delay block in the second stage; generating the plurality of input codes by the calibration engine; generating a digital code by the second stage in response to the plurality of input codes; determining an absolute difference in the number of ones and zeros in the digital code; storing the delay value with the smallest error number for the second stage as the delay value for the second stage; The method further comprises:

20. A device, comprising: A processor; a memory coupled to the processor; an analog-to-digital converter (ADC) coupled to the processor and to the memory, a voltage delay (VD) block configured to generate a delay signal in response to a calibration signal; a back-end ADC coupled to the VD block and configured to receive the delayed signal, the back-end ADC including a plurality of stages including a first stage; a calibration circuit coupled to the plurality of stages and to the VD block, determining an error number for the first stage in response to the delayed signal; storing the delay value of the first stage which has the smallest error number; The calibration circuit is configured to The ADC comprising: Including, the device.

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