Digital-to-analog converter circuit, electronic device including the same, and method for controlling the same

Abstract

A digital-to-analog converter (DAC) circuit, an electronic device including the digital-to-analog converter circuit, and a control method of the digital-to-analog converter circuit are provided. The DAC circuit includes: a serializer circuit including a plurality of multiplexers and configured to convert a parallel code in digital form into a serial code using the plurality of multiplexers; and a cell array including a plurality of unit cells and configured to output an analog signal based on the serial code. The serializer circuit includes: a pseudo-random number generation circuit configured to generate a random number in response to an edge of a first clock signal; a first switching circuit connected to the first multiplexer; a second switching circuit connected to the second multiplexer; and a random number circuit configured to transmit different random numbers generated by the pseudo-random number generation circuit in response to different edges of the first clock signal to the first switching circuit and the second switching circuit, respectively.

Description

[0001] Cross-reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0164865 filed in the Korean Intellectual Property Office on November 23, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a digital-to-analog converter circuit, an electronic device including the digital-to-analog converter circuit, and a control method of the digital-to-analog converter circuit. Background Art

[0004] Analog signals can be converted into digital form, which can be easily processed by modern digital systems. In addition, in many systems, these digital signals can be converted back into analog form to perform actual functions.

[0005] The circuit that performs this conversion may be referred to as a digital-to-analog converter (hereinafter referred to as a "DAC") circuit. Furthermore, the output of these DAC circuits is used to drive various devices. DAC circuits may often be integrated into digital systems, where the analog signal is digitized and processed by an analog-to-digital converter (hereinafter referred to as an "ADC"), and then converted back to an analog form of the signal by the DAC circuit.

[0006] Generally, a DAC circuit includes a current array including a plurality of unit cells responsible for output, and various studies are being conducted to improve mismatch between the unit cells.

[0007] For example, recently, in order to improve such mismatch between unit cells, application of a dynamic element matching (DEM) method to a DAC circuit operating at high resolution and high speed is being studied. Summary of the invention

[0008] One or more embodiments provide a DAC circuit that generates codes to which different random numbers are applied through a plurality of switch circuits connected between a plurality of multiplexers, thereby improving the quality of an analog signal with low power consumption.

[0009] According to one aspect of the embodiment, a digital-to-analog converter (DAC) circuit includes: a serializer circuit including a plurality of multiplexers and configured to convert a parallel code in digital form into a serial code using the plurality of multiplexers; and a cell array including a plurality of unit cells and configured to output an analog signal based on the serial code. The serializer circuit includes: a pseudo-random number generation circuit configured to generate a random number in response to an edge of a first clock signal; a first switch circuit connected to the first multiplexer; a second switch circuit connected to the second multiplexer; and a random number circuit configured to send different random numbers generated by the pseudo-random number generation circuit in response to different edges of the first clock signal to the first switch circuit and the second switch circuit, respectively.

[0010] In addition, according to an aspect of the embodiment, a method for controlling a DAC circuit includes: applying a first clock signal to a pseudo-random number generation circuit, wherein the pseudo-random number generation circuit generates a random number in response to an edge of the applied clock signal; sending different random numbers generated by the pseudo-random number generation circuit in response to different edges of the first clock signal to a first switching circuit connected to a first multiplexer and a second switching circuit connected to a second multiplexer, respectively; and generating an analog signal based on a serial code including codes output from the first switching circuit and the second switching circuit, wherein the codes output from the first switching circuit and the second switching circuit are generated based on the random numbers.

[0011] In addition, according to one aspect of the embodiment, an electronic device for transmitting and receiving RF (radio frequency) signals includes: a DAC circuit configured to convert a digital signal into an analog signal; and an antenna configured to output the analog signal as an RF signal. The DAC circuit includes: a serializer circuit including a plurality of multiplexers and configured to convert a parallel code in digital form into a serial code using the plurality of multiplexers; and a cell array including a plurality of unit cells and configured to output an analog signal based on the serial code. The serializer circuit includes: a pseudo-random number generation circuit configured to generate a random number in response to an edge of a first clock signal; a first switch circuit connected to the first multiplexer, and a second switch circuit connected to the second multiplexer; and a random number circuit configured to send different random numbers generated by the pseudo-random number generation circuit in response to different edges of the first clock signal to the first switch circuit and the second switch circuit, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects and features will be more clearly understood from the following description of example embodiments taken in conjunction with the accompanying drawings.

[0013] Figure 1 is a block diagram showing a DAC circuit according to an embodiment.

[0014] Figure 2is a circuit diagram showing a configuration of a serializer according to an embodiment.

[0015] Figure 3A is a circuit diagram showing a configuration of controlling a first switch circuit using a random number according to an embodiment.

[0016] Figure 3B is a configuration showing that a random number is applied to an input code through a first switch circuit according to an embodiment.

[0017] Figure 4A is a circuit diagram showing a configuration of a serializer according to an embodiment.

[0018] Figure 4B 2 is a diagram illustrating a serial code generated by a serializer according to an embodiment.

[0019] Figure 5A is a circuit diagram showing a configuration of a serializer according to an embodiment.

[0020] Figure 5B Serial codes generated by a serializer according to an embodiment are shown.

[0021] Figure 6 is a circuit diagram showing a configuration of a serializer according to an embodiment.

[0022] Figure 7 is a flow chart illustrating a method for controlling a DAC circuit according to an embodiment.

[0023] Figure 8 is a flowchart illustrating a method of generating a random number code to which different random numbers are applied using a first switch circuit and a second switch circuit according to an embodiment.

[0024] Fig. 9 is a circuit diagram showing a configuration of a serializer including a first decoder and a second decoder according to an embodiment.

[0025] Fig.10 is a circuit diagram showing a configuration of a serializer including first to fourth decoders according to an embodiment.

[0026] Fig.11 is a circuit diagram showing a configuration of a DAC circuit including a decoder connected to a serializer according to an embodiment.

[0027] Fig.12 is a block diagram illustrating an electronic device including a DAC circuit and an antenna according to an embodiment. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments will be described with reference to the accompanying drawings. The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto, and may be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment that is also provided herein or is not provided herein but is consistent with the present disclosure. Statements such as "at least one of..." modify the entire list of elements when following a list of elements, rather than modifying individual elements in the list. For example, the statement "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0029] Figure 1 is a block diagram showing a DAC circuit according to an embodiment. Figure 2 is a circuit diagram showing a configuration of a serializer (eg, a serializer circuit) according to an embodiment.

[0030] refer to Figure 1 , a digital-to-analog converter (hereinafter referred to as “DAC”) circuit 100 according to an embodiment may include a serializer 110 and a cell array 120 .

[0031] According to an embodiment, the unit array 120 may include a plurality of unit cells UC1 to UCn. For example, the plurality of unit cells UC1 to UCn may be arranged in a matrix form.

[0032] According to an embodiment, the cell array 120 converts an input digital signal (eg, a serial code SDI) into an analog signal AO for output using at least some of the plurality of unit cells UC1 to UCn.

[0033] In more detail, the unit cell may be selected based on the serial code SDI input from the serializer 110 , and the cell array 120 may output the analog signal AO using the unit cell selected based on the serial code SDI.

[0034] For example, the cell array 120 may apply a preset current to the unit cells selected based on the serial code SDI. In addition, the cell array 120 may output an analog signal AO including a voltage signal output when a current is applied to at least some of the unit cells.

[0035] In this case, for example, each of the plurality of unit cells UC1 to UCn may be referred to as a current cell including at least one resistance element, but the embodiment is not limited thereto.

[0036] Furthermore, the DAC circuit 100 according to the embodiment may include a serializer 110 that converts codes input in parallel into codes in a serial form for output.

[0037] In more detail, the DAC circuit 100 may include a serializer 110 that converts a parallel code PDI in digital form into a serial code SDI for output using a plurality of multiplexers. The serializer 110 may include a plurality of inputs DI1 to DI16. The parallel code PDI may be provided to the plurality of inputs DI1 to DI16 of the serializer 110.

[0038] In this case, the parallel code PDI and the serial code SDI each have a resolution of 16 bits and may be referred to as a signal consisting of 7-bit data, but the embodiment is not limited thereto.

[0039] Also refer to Figure 1 and Figure 2 , the serializer 110 according to the embodiment may include a plurality of multiplexers M1 to M15 arranged to be connected to each other.

[0040] In this case, the plurality of multiplexers M1 to M15 may be composed of a plurality of stages, for example, stages S1 to S4.

[0041] For example, the plurality of multiplexers M1 to M15 include: a first stage S1 including seventh to fourteenth multiplexers M7 to M14; a third stage S3 including the first multiplexer M1 and the second multiplexer M2; and a fourth stage S4 including the output multiplexer M15.

[0042] In more detail, each of the multiplexers M1 to M15 according to the embodiment may convert two input signals input in parallel into a serial signal for output in response to a clock signal.

[0043] For example, the seventh multiplexer M7 can output the first input DI1 in response to the rising edge of the divided-by-16 clock signal CK1 / 16, and can output the second input DI2 in response to the falling edge of the divided-by-16 clock signal CK1 / 16. The divided-by-16 clock signal CK1 / 16 can be understood as a generated clock signal having a speed of one sixteenth of the clock signal.

[0044] In this way, the seventh multiplexer M7 can output a signal composed of the first input DI1 and the second input DI2 in series. In this case, for example, the signal composed of the first input DI1 and the second input DI2 in series can have a speed twice that of the first input DI1 and the second input DI2.

[0045] Accordingly, the serializer 110 may output a serial code SDI in which a plurality of inputs DI1 to DI16 input in parallel are serially combined using the plurality of multiplexers M1 to M15 .

[0046] In this case, when the parallel code PDI including the plurality of inputs DI1 to DI16 is composed of 7-bit data, it can be understood that each of the plurality of multiplexers M1 to M15 includes 7 multiplexers connected in parallel to each other.

[0047] Furthermore, according to an embodiment, the serializer 110 may include a pseudo random number generator PRNG (eg, a pseudo random number generating circuit) that generates a random number RN in response to an edge of the first clock signal CK1 .

[0048] In more detail, the pseudo random number generator PRNG may generate a random number RN according to a specified probability in response to a rising edge of the first clock signal CK1. The pseudo random number generator PRNG may generate random numbers different from each other in response to consecutive rising edges in the first clock signal CK1.

[0049] When the activation signal EN is input, the pseudo random number generator PRNG may generate a random number RN according to a designated probability in response to a rising edge of the first clock signal CK1 .

[0050] In this case, the pseudo-random number generator PRNG may generate a pseudo-random number according to a specified probability in response to a rising edge of the first clock signal CK1 .

[0051] Furthermore, the serializer 110 according to the embodiment may include at least two or more switch circuits SW1 and SW2 respectively connected between two or more multiplexers among the plurality of multiplexers M1 to M15 .

[0052] In more detail, the serializer 110 may include a first switch circuit SW1 connected to the first multiplexer M1 and a second switch circuit SW2 connected to the second multiplexer M2 .

[0053] The serializer 110 may include a first switch circuit SW1 receiving the first digital code DC1 output from the first multiplexer M1. In addition, the serializer 110 may include a second switch circuit SW2 receiving the second digital code DC2 output from the second multiplexer M2.

[0054] In this case, the first switch circuit SW1 and the second switch circuit SW2 may be disposed between a plurality of stages S1 to S4 consisting of some of the multiplexers M1 to M15 .

[0055] For example, the first switch circuit SW1 and the second switch circuit SW2 may be respectively disposed between the first multiplexer M1 and the second multiplexer M2 included in the third stage S3 and the output multiplexer M15 included in the fourth stage S4 .

[0056] However, the arrangement of the first switch circuit SW1 and the second switch circuit SW2 is not limited to the above example.

[0057] Furthermore, the serializer 110 according to the embodiment may include a random number circuit RNC that transmits different random numbers among the random numbers RN generated by the pseudo random number generator PRNG to the first switch circuit SW1 and the second switch circuit SW2 , respectively.

[0058] In more detail, the random number circuit RNC may send different random numbers RN1 and RN2 generated by the pseudo random number generator PRNG in response to different edges of the first clock signal CK1 to the first switch circuit SW1 and the second switch circuit SW2 , respectively.

[0059] For example, the random number circuit RNC may transmit the first random number RN1 generated by the pseudo random number generator PRNG in response to one rising edge of the first clock signal CK1 to the first switch circuit SW1 .

[0060] Furthermore, the random number circuit RNC may transmit a second random number RN2 generated by the pseudo random number generator PRNG in response to another rising edge of the first clock signal CK1 to the second switch circuit SW2 .

[0061] In this case, the random number circuit RNC may include: a plurality of synchronization circuits for sending different random numbers RN1 and RN2 to the first switch circuit SW1 and the second switch circuit SW2 respectively in response to different clock signals.

[0062] According to an embodiment, the first switch circuit SW1 may output a first random number code RC1 obtained by applying the first random number RN1 to the first digital code DC1 output from the first multiplexer M1 .

[0063] In addition, the second switch circuit SW2 may output a second random number code RC2 obtained by applying the second random number RN2 to the second digital code DC2 output from the second multiplexer M2.

[0064] According to an embodiment, the serializer 110 may output a serial code SDI including a code to which different random numbers generated by a pseudo random number generator PRNG are applied.

[0065] In more detail, the serializer 110 may output a serial code SDI composed of serial random number codes RC1 and RC2 , in which the random numbers RN1 and RN2 are applied to at least some of the plurality of input codes DI1 to DI16 input in parallel.

[0066] In this case, for example, the speed of the serial code SDI may be an integral multiple of the speeds of the plurality of input codes DI1 to DI16.

[0067] Furthermore, in this case, the operation of the serializer 110 applying different random numbers RN1 and RN2 to at least some of the plurality of input codes DI1 to DI16 using the plurality of switch circuits SW1 and SW2 may be referred to as a dynamic element matching technique.

[0068] With reference to the above configuration, the serializer 110 according to the embodiment includes a plurality of switch circuits SW1 and SW2 receiving an output of each of the multiplexers M1 to M14 excluding the output multiplexer M15 among the multiplexers M1 to M15 .

[0069] In this case, the speed of the serial code SDI output from the output multiplexer M15 may be relatively high compared with the code output from each of the multiplexers M1 to M14 except the output multiplexer M15.

[0070] Therefore, the plurality of switch circuits SW1 and SW2 may operate at relatively low power when receiving the output of each of the multiplexers M1 to M14 except the output multiplexer M15 , compared to the case of receiving the serial code SDI output from the output multiplexer M15 .

[0071] Specifically, since the plurality of switch circuits SW1 and SW2 are disposed between the plurality of stages S1 to S4 composed of the plurality of multiplexers M1 to M15, the plurality of switch circuits SW1 and SW2 can operate at relatively low power compared to the case of being connected to the output multiplexer M15 and receiving the serial code SDI.

[0072] In this way, the DAC circuit 100 according to the embodiment can reduce power consumed in the operation of a switch circuit that applies a random number to a digital code (eg, the serial code SDI) output through the serializer 110 .

[0073] Furthermore, referring to the above configuration, the serializer 110 according to the embodiment may transmit different random numbers RN1 and RN2 among random numbers generated by the pseudo random number generator PRNG to each of the switch circuits SW1 and SW2 using the random number circuit RNC.

[0074] Accordingly, the serializer 110 may apply different random numbers RN1 and RN2 to the digital codes DC1 and DC2 output from different multiplexers M1 and M2 .

[0075] In this way, the serializer 110 can increase the randomness of the code included in the serial code SDI.

[0076] Furthermore, the serializer 110 may increase randomness of a code included in the serial code SDI to minimize quality degradation of the analog signal AO due to mismatching between the plurality of unit cells UC1 to UCn.

[0077] Therefore, the DAC circuit 100 according to the embodiment may improve the quality (eg, linearity) of the analog signal AO output based on the serial code SDI.

[0078] Figure 3A is a circuit diagram showing a configuration of controlling a first switch circuit using a random number according to an embodiment. Figure 3B is a configuration showing that a random number is applied to an input code through a first switch circuit according to an embodiment.

[0079] Also refer to Figure 3A and Figure 3B According to an embodiment, the first switch circuit SW1 may include: a plurality of switch multiplexers SM1 , SM2 and SM3 , which are controlled by bits of a first random number RN1 [2:0] generated by a pseudo random number generator PRNG.

[0080] In more detail, the first switch circuit SW1 may change the arrangement order of bits included in the first digital code DC1 [6:0] using a plurality of switch multiplexers SM1 , SM2 , and SM3 controlled by bits of the first random number RN1 [2:0] .

[0081] In this case, the first digital code DC1 can be understood as a 7-bit thermometer code. Accordingly, the first switch circuit SW1 can use a plurality of switch multiplexers SM1, SM2 and SM3 to change the arrangement order of the seven bits of the first digital code DC1[6:0]. For example, the thermometer code can represent a unary code, based on unary encoding, in which a natural number n is represented by a code of length n+1 (or n), usually n 1s followed by a 0.

[0082] The first switch circuit SW1 may include a first switch multiplexer SM1 controlled by a first bit RN1 [ 0 ] of a first random number RN1 [ 2 : 0 ] .

[0083] In more detail, the first switch multiplexer SM1 may change the arrangement order of some bits in the first digital code DC1 [6:0] by 3 bits in response to the first bit RN1 [0] of the first random number RN1 [2:0].

[0084] According to an embodiment, the first switch multiplexer SM1 can output a 1-1 digital code DC1_1[6:0] obtained by changing the arrangement order of at least some bits among the bits of the first digital code DC1[6:0] by 3 bits in response to the first bit RN1[0] of the first random number RN1[2:0].

[0085] For example, the first switch multiplexer SM1 may output a 1-1 digital code DC1_1[6:0] having the 7th bit DC1[6] among the bits of the first digital code DC1[6:0] as the 4-1 bit DC1_1[3] in response to the first bit RN1[0] of the first random number RN1[2:0].

[0086] According to another embodiment, the first switch multiplexer SM1 may output a 1-1 digital code DC1_1[6:0] having the same arrangement order as the bits of the first digital code DC1[6:0] in response to the first bit RN1[0] of the first random number RN1[2:0].

[0087] For example, the first switch multiplexer SM1 may output a 1-1 digital code DC1_1[6:0] having the 7th bit DC1[6] among the bits of the first digital code DC1[6:0] as the 7-1 bit DC1_1[6] in response to the first bit RN1[0] of the first random number RN1[2:0].

[0088] Furthermore, the second switch multiplexer SM2 may change the arrangement order of at least some of the bits of the 1-1 digital code DC1_1[6:0] by 2 bits in response to the second bit RN1[1] of the first random number RN1[2:0].

[0089] According to an embodiment, the second switch multiplexer SM2 can output a 1-2 digital code DC1_2[6:0] obtained by changing the arrangement order of at least some bits among the bits of the first digital code DC1_1[6:0] by 2 bits in response to the second bit RN1[1] of the first random number RN1[2:0].

[0090] For example, the second switch multiplexer SM2 may output a 1-2 digital code DC1_2[6:0] using 7-1 bits DC1_1[6] among bits of the 1-1 digital code DC1_1[6:0] as 5-2 bits DC1_2[4] in response to the second bit RN1[1] of the first random number RN1[2:0].

[0091] According to another embodiment, the second switch multiplexer SM2 may output a 1-2 digital code DC1_2[6:0] having the same arrangement order of bits as the 1-1 digital code DC1_1[6:0] in response to the second bit RN1[1] of the first random number RN1[2:0].

[0092] For example, the second switch multiplexer SM2 may output a 1-2 digital code DC1_2[6:0] using 7-1 bits DC1_1[6] among bits of the 1-1 digital code DC1_1[6:0] as 7-2 bits DC1_2[6] in response to the second bit RN1[1] of the first random number RN1[2:0].

[0093] In addition, the third switch multiplexer SM3 may change the arrangement order of some bits of the 1-2 digital code DC1_2[6:0] by one bit in response to the third bit RN1[2] of the first random number RN1[2:0].

[0094] According to an embodiment, the third switch multiplexer SM3 can output the first random number code RC1[6:0] obtained by changing the arrangement order of at least some bits among the bits of the 1-2 digital code DC1_2[6:0] by 2 bits in response to the third bit RN1[2] of the first random number RN1[2:0].

[0095] For example, the third switch multiplexer SM3 may output the first random number code RC1[6:0] using the 7-2 bits DC1_2[6] among the bits of the 1-2 digital code DC1_2[6:0] as the sixth random number bit RC1[5] in response to the third bit RN1[2] of the first random number RN1[2:0].

[0096] According to another embodiment, the third switch multiplexer SM3 may output the first random number code RC1[6:0] having the same arrangement order as the bits of the 1-2 digital code DC1_2[6:0] in response to the third bit RN1[2] of the first random number RN1[2:0].

[0097] For example, the third switch multiplexer SM3 may output the first random number code RC1[6:0] using the 7-2 bit DC1_2[6] among the bits of the 1-2 digital code DC1_2[6:0] as the seventh random number bit RC1[6] in response to the third bit RN1[2] of the first random number RN1[2:0].

[0098] Referring to the above configuration, the first switch circuit SW1 may output the first random number code RC1 [6:0] obtained by applying the first random number RN1 [2:0] to the first digital code DC1 using the plurality of switch multiplexers SM1 , SM2 , and SM3 .

[0099] In more detail, the first switch circuit SW1 may use a plurality of switch multiplexers SM1 , SM2 , and SM3 controlled by bits of the first random number RN1 [2:0] to output the first random number code RC1 by changing an arrangement order of bits included in the first digital code DC1 .

[0100] In addition, refer to Figure 2 and Figure 3A , it can be understood that the second switch circuit SW2 according to the embodiment has substantially the same configuration as the first switch circuit SW1.

[0101] Therefore, the operation of each of the switch circuits SW1 and SW2 according to the embodiment applying the random numbers RN1 and RN2 to the digital codes DC1 and DC2 can be understood as an operation of changing the arrangement order of bits included in the digital codes DC1 and DC2 based on the random numbers RN1 and RN2.

[0102] Furthermore, the operation of applying the random numbers RN1 and RN2 to the digital codes DC1 and DC2 through the switch circuits SW1 and SW2 may be referred to as a dynamic element matching (DEM) technique.

[0103] Also refer to Figure 2 , Figure 3A and Figure 3B , the first switch circuit SW1 may receive an output of one multiplexer (eg, the first multiplexer M1 ) among the plurality of multiplexers M1 to M15 excluding the output multiplexer M15 .

[0104] In this case, the code output by each of the multiplexers M1 to M14 except the output multiplexer M15 may have a relatively low speed compared with the speed of the serial code SDI output from the output multiplexer M15.

[0105] Therefore, when receiving the first digital code DC1 [6:0] as the output of the first multiplexer M1, the first switch circuit SW1 can be implemented with relatively fewer components compared to the case of receiving the serial code SDI output from the output multiplexer M15.

[0106] Furthermore, when receiving the first digital code DC1 [6:0] as the output of the first multiplexer M1, the first switch circuit SW1 may operate with relatively low power compared to the case of receiving the serial code SDI output from the output multiplexer M15.

[0107] In this way, the DAC circuit 100 according to the embodiment can reduce power consumed in the operation of a switch circuit that applies a random number to a digital code (eg, the serial code SDI) output through the serializer 110 .

[0108] Figure 4A is a circuit diagram showing a configuration of a serializer according to an embodiment. Figure 4B Shown by Figure 4A The serial code generated by the serializer.

[0109] Also refer to Figure 4A and Figure 4B , the serializer 110A according to the embodiment may include a plurality of multiplexers M1 to M15 , a first switch circuit SW1 , a second switch circuit SW2 , a pseudo random number generator PRNG, a first synchronization circuit sync1 , and a second synchronization circuit sync2 .

[0110] Figure 4A The serializer 110A shown in FIG. 1 can be understood as Figure 2 Accordingly, the same reference numerals are used for components that are the same or substantially the same as those described above, and additional descriptions that may overlap with the above will be omitted to avoid redundancy.

[0111] According to an embodiment, the serializer 110A may include a first synchronization circuit sync1 and a second synchronization circuit sync2 connected to a pseudo random number generator PRNG.

[0112] In more detail, the serializer 110A may include: a first synchronization circuit sync1 and a second synchronization circuit sync2 that transmit random numbers generated by a pseudo random number generator PRNG at different times to the first switch circuit SW1 and the second switch circuit SW2 in response to different clock signals CK2 and CK3, respectively.

[0113] The serializer 110A may include a first synchronization circuit sync1 that transmits a first random number RN1 among random numbers RN generated by a pseudo random number generator PRNG to the first switch circuit SW1 in response to a second clock signal CK2 .

[0114] For example, the first synchronization circuit sync1 may send the random number (e.g., RN(n), RN(n+2) to RN(n+8)) generated by the pseudo-random number generator PRNG to the first switch circuit SW1 when the rising edge of the second clock signal CK2 occurs. For example, the first synchronization circuit sync1 may send the first random number (e.g., RN(n)) to the first switch circuit SW1 when the rising edge of the second clock signal CK2 occurs for the first time, send the second random number (e.g., RN(n+2)) to the first switch circuit SW1 when the rising edge of the second clock signal CK2 occurs for the second time, and send the third random number (e.g., RN(n+8)) to the first switch circuit SW1 when the rising edge of the second clock signal CK2 occurs for the third time.

[0115] Furthermore, the serializer 110A may include a second synchronization circuit sync2 that transmits a second random number RN2 among the random numbers RN generated by the pseudo random number generator PRNG to the second switch circuit SW2 in response to the third clock signal CK3 .

[0116] For example, the second synchronization circuit sync2 may send the random numbers (e.g., RN(n-1), RN(n+1) to RN(n+9)) generated by the pseudo-random number generator PRNG to the second switch circuit SW2 when the rising edge of the third clock signal CK3 occurs. For example, the second synchronization circuit sync2 may send the first random number (e.g., RN(n-1)) to the second switch circuit SW2 when the rising edge of the third clock signal CK3 occurs for the first time, send the second random number (e.g., RN(n+1)) to the second switch circuit SW2 when the rising edge of the third clock signal CK3 occurs for the second time, and send the third random number (e.g., RN(n+9)) to the second switch circuit SW2 when the rising edge of the third clock signal CK3 occurs for the third time.

[0117] In this case, for example, the second clock signal CK2 and the third clock signal CK3 may each have a half speed of the first clock signal CK1. In addition, for example, the second clock signal CK2 and the third clock signal CK3 may have opposite phases to each other.

[0118] In addition, in this case, the first random number RN1 and the second random number RN2 can be understood as random numbers generated by the pseudo-random number generator PRNG at different times.

[0119] Accordingly, the first synchronization circuit sync1 and the second synchronization circuit sync2 may send different random numbers generated in response to different rising edges of the first clock signal CK1 of the pseudo random number generator PRNG to the first switch circuit SW1 and the second switch circuit SW2 , respectively.

[0120] According to an embodiment, the first switch circuit SW1 may output a first random number code RC1 obtained by applying the first random number RN1 to the first digital code DC1.

[0121] In more detail, the first switch circuit SW1 may output the first random number code RC1 obtained by applying the first random number RN1 transmitted from the first synchronization circuit sync1 to the first digital code DC1 output from the first multiplexer M1 .

[0122] In this case, the first random number code RC1 may be understood as a thermometer type digital code in which at least some bits included in the first digital code DC1 are rearranged based on the first random number RN1.

[0123] Furthermore, the second switch circuit SW2 may output a second random number code RC2 obtained by applying the second random number RN2 to the second digital code DC2.

[0124] In more detail, the second switch circuit SW2 may output the second random number code RC2 obtained by applying the second random number RN2 transmitted from the second synchronization circuit sync2 to the second digital code DC2 output from the second multiplexer M2.

[0125] In this case, the second random number code RC2 may be understood as a thermometer type digital code in which at least some bits included in the second digital code DC2 are rearranged based on the second random number RN2.

[0126] According to an embodiment, the serializer 110A may include an output multiplexer M15 that converts the first random number code RC1 and the second random number code RC2 into a serial code and outputs the serial code SDI.

[0127] The output multiplexer M15 may receive the first random number code RC1 and the second random number code RC2 from the first switch circuit SW1 and the second switch circuit SW2 , respectively.

[0128] In addition, the output multiplexer M15 may serially convert the first random number code RC1 and the second random number code RC2 received in parallel to output them in response to the divided-by-2 clock signal CK1 / 2 .

[0129] For example, the output multiplexer M15 may output the first random number code RC1 in response to a rising edge of the divided-by-2 clock signal CK1 / 2 , and may output the second random number code RC2 in response to a falling edge of the divided-by-2 clock signal CK1 / 2 .

[0130] In this case, the divided-by-2 clock signal CK1 / 2 may be understood as a clock signal generated with half the speed of the first clock signal CK1. In addition, for example, the divided-by-2 clock signal CK1 / 2 may have the same speed and phase as the second clock signal CK2.

[0131] In this way, the output multiplexer M15 can output the serial code SDI at a speed twice that of the first random number code RC1 and the second random number code RC2.

[0132] In this case, when the first and second digital codes DC1 and DC2 are received at a relatively low speed, the first and second switch circuits SW1 and SW2 may operate with relatively fewer elements than when the serial code SDI having a relatively high speed is received.

[0133] In this case, when the first and second digital codes DC1 and DC2 are received at a relatively low speed, the first and second switch circuits SW1 and SW2 may operate at relatively low power compared to a case where the serial code SDI having a relatively high speed is received.

[0134] In this way, the DAC circuit 100 according to the embodiment can reduce power consumed in the operation of the switch circuit that applies the random number to the serial code SDI output through the serializer 110A.

[0135] Furthermore, the serial code SDI may include a first random number code RC1 and a second random number code RC2 obtained by applying different random numbers to data of the first digital code DC1 and data of the second digital code DC2, respectively.

[0136] For example, refer to Figure 4B The serial code SDI may include data of a first random number code RC1 obtained by applying a random number "RN(n+2)" to "DC1(n+1)" of a first digital code DC1, and data of a second random number code RC2 obtained by applying a random number "RN(n+3)" to "DC2(n+1)" of a second digital code DC2.

[0137] In addition, the serial code SDI may include data of a first random number code RC1 of "DC1(n+2)" which applies a random number "RN(n+4)" to the first digital code DC1, and data of a second random number code RC2 of "DC2(n+2)" which applies a random number "RN(n+5)" to the second digital code DC2.

[0138] Referring to the above configuration, the serializer 110A may transmit mutually different random numbers RN1 and RN2 generated by the pseudo random number generator PRNG to the plurality of switch circuits SW1 and SW2 , respectively, using the plurality of switch circuits SW1 and SW2 and the plurality of corresponding synchronization circuits sync1 and sync2 .

[0139] Therefore, the serializer 110A may output a serial code SDI including random number codes RC1 and RC2 in which different random numbers RN1 and RN2 are applied to digital codes DC1 and DC2 output from different multiplexers M1 and M2 .

[0140] In this way, the serializer 110A can increase the randomness of the code included in the serial code SDI.

[0141] Furthermore, the serializer 110A may minimize quality degradation of the analog signal AO due to mismatching between the plurality of unit cells UC1 to UCn included in the cell array 120 by increasing randomness of a code included in the serial code SDI.

[0142] Therefore, the DAC circuit 100 according to the embodiment can improve the linearity of the analog signal AO output based on the serial code SDI. Specifically, the DAC circuit 100 according to the embodiment can improve the quality of the analog signal AO output based on the serial code SDI.

[0143] Figure 5A is a circuit diagram showing a configuration of a serializer according to an embodiment. Figure 5B Shown by Figure 5A The serial code generated by the serializer.

[0144] Also refer to Figure 5A and Figure 5B According to the embodiment, the serializer 110B may include a plurality of multiplexers M1 to M15, a first switch circuit SW1, a second switch circuit SW2, a third switch circuit SW3, a fourth switch circuit SW4, a pseudo-random number generator PRNG, a first synchronization circuit sync1, a second synchronization circuit sync2, a third synchronization circuit sync3, and a fourth synchronization circuit sync4.

[0145] Figure 5A The serializer 110B shown in FIG. 1 can be understood as Figure 2 Therefore, the same reference numerals are used for components that are the same or substantially the same as those described above, and additional descriptions that may overlap with the above will be omitted to avoid redundancy.

[0146] According to an embodiment, the serializer 110B may include a first synchronization circuit sync1 , a second synchronization circuit sync2 , a third synchronization circuit sync3 , and a fourth synchronization circuit sync4 connected to a pseudo random number generator PRNG.

[0147] In more detail, the serializer 110B may include: a first synchronization circuit sync1, a second synchronization circuit sync2, a third synchronization circuit sync3 and a fourth synchronization circuit sync4, which respectively send random numbers generated by a pseudo-random number generator PRNG at different times to corresponding switch circuits SW1, SW2, SW3 and SW4 in response to different clock signals CK2, CK3, CK4 and CK5.

[0148] The serializer 110B may include a first synchronization circuit sync1 that transmits a first random number RN1 among random numbers RN generated by a pseudo random number generator PRNG to a first switch circuit SW1 in response to a second clock signal CK2 .

[0149] For example, the first synchronization circuit sync1 may send random numbers (e.g., RN(n), RN(n+4), and RN(n+8)) generated by the pseudo-random number generator PRNG to the first switch circuit SW1 when the rising edge of the second clock signal CK2 occurs. For example, the first synchronization circuit sync1 may send a first random number (e.g., RN(n)) to the first switch circuit SW1 when the rising edge of the second clock signal CK2 occurs for the first time, send a second random number (e.g., RN(n+4)) to the first switch circuit SW1 when the rising edge of the second clock signal CK2 occurs for the second time, and send a third random number (e.g., RN(n+8)) to the first switch circuit SW1 when the rising edge of the second clock signal CK2 occurs for the third time.

[0150] Furthermore, the serializer 110B may include a second synchronization circuit sync2 that transmits a second random number RN2 among the random numbers RN generated by the pseudo random number generator PRNG to the second switch circuit SW2 in response to the third clock signal CK3 .

[0151] For example, the second synchronization circuit sync2 can send the random numbers (e.g., RN (n-3), RN (n+1), RN (n+5), and RN (n+9)) generated by the pseudo-random number generator PRNG to the second switch circuit SW2 when the rising edge of the third clock signal CK3 occurs. For example, the second synchronization circuit sync2 can send the first random number (e.g., RN (n-3)) to the second switch circuit SW2 when the rising edge of the third clock signal CK3 appears for the first time, send the second random number (e.g., RN (n+1)) to the second switch circuit SW2 when the rising edge of the third clock signal CK3 appears for the second time, send the third random number (e.g., RN (n+5)) to the second switch circuit SW2 when the rising edge of the third clock signal CK3 appears for the third time, and send the fourth random number (e.g., RN (n+9)) to the second switch circuit SW2 when the rising edge of the third clock signal CK3 appears for the fourth time.

[0152] Furthermore, the serializer 110B may include a third synchronization circuit sync3 that transmits a third random number RN3 among the random numbers RN generated by the pseudo random number generator PRNG to the third switch circuit SW3 in response to the fourth clock signal CK4 .

[0153] For example, the third synchronization circuit sync3 may send random numbers (e.g., RN (n-2), RN (n+2), and RN (n+6)) generated by the pseudo-random number generator PRNG to the third switch circuit SW3 when the rising edge of the fourth clock signal CK4 occurs. For example, the third synchronization circuit sync3 may send a first random number (e.g., RN (n-2)) to the third switch circuit SW3 when the rising edge of the third clock signal CK3 occurs for the first time, send a second random number (e.g., RN (n+2)) to the third switch circuit SW3 when the rising edge of the third clock signal CK3 occurs for the second time, and send a third random number (e.g., RN (n+6)) to the third switch circuit SW3 when the rising edge of the third clock signal CK3 occurs for the third time.

[0154] In this case, the fourth clock signal CK4 can be understood as a clock signal having the same speed and opposite phase as the second clock signal CK2.

[0155] Therefore, the third synchronization circuit sync3 can send the random numbers (eg, RN(n-2), RN(n+2), and RN(n+6)) generated by the pseudo random number generator PRNG to the third switch circuit SW3 when the falling edge of the second clock signal CK2 occurs.

[0156] Furthermore, the serializer 110B may include a fourth synchronization circuit sync4 that transmits a fourth random number RN4 among the random numbers RN generated by the pseudo random number generator PRNG to the fourth switch circuit SW4 in response to the fifth clock signal CK5 .

[0157] For example, the fourth synchronization circuit sync4 may send random numbers (e.g., RN (n-1), RN (n+3), and RN (n+7)) generated by the pseudo-random number generator PRNG to the fourth switch circuit SW4 when the rising edge of the fifth clock signal CK5 occurs. For example, the fourth synchronization circuit sync4 may send a first random number (e.g., RN (n-1)) to the fourth switch circuit SW4 when the rising edge of the fifth clock signal CK5 occurs for the first time, send a second random number (e.g., RN (n+3)) to the fourth switch circuit SW4 when the rising edge of the fifth clock signal CK5 occurs for the second time, and send a third random number (e.g., RN (n+7)) to the fourth switch circuit SW4 when the rising edge of the fifth clock signal CK5 occurs for the third time.

[0158] In this case, the fifth clock signal CK5 can be understood as a clock signal having the same speed and opposite phase as the third clock signal CK3.

[0159] Therefore, the fourth synchronization circuit sync4 can send the random numbers (eg, RN(n-1), RN(n+3), and RN(n+7)) generated by the pseudo random number generator PRNG to the third switch circuit SW3 when the falling edge of the third clock signal CK3 occurs.

[0160] In this case, for example, the second to fifth clock signals CK2 to CK5 may each have a ¼ speed of the first clock signal CK1 .

[0161] In addition, the first random number RN1, the second random number RN2, the third random number RN3 and the fourth random number RN4 may be understood as random numbers generated by a pseudo-random number generator PRNG at different times.

[0162] Accordingly, the first to fourth synchronization circuits sync1 to sync4 may send different random numbers RN1 to RN4 generated by the pseudo random number generator PRNG in response to different rising edges of the first clock signal CK1 to the first to fourth switch circuits SW1 to SW4 , respectively.

[0163] According to an embodiment, the first switch circuit SW1 may output a first random number code RC1 obtained by applying the first random number RN1 to the first digital code DC1.

[0164] In more detail, the first switch circuit SW1 may output the first random number code RC1 obtained by applying the first random number RN1 transmitted from the first synchronization circuit sync1 to the first digital code DC1.

[0165] In this case, the first digital code DC1 can be understood as a code that the first multiplexer M1 converts a parallel input code into a serial code for output in response to the 8-frequency divided clock signal CK1 / 8.

[0166] Furthermore, the first random number code RC1 may be understood as a thermometer type digital code in which at least some bits included in the first digital code DC1 are rearranged based on the first random number RN1.

[0167] Furthermore, the second switch circuit SW2 may output a second random number code RC2 obtained by applying the second random number RN2 to the second digital code DC2.

[0168] In more detail, the second switch circuit SW2 may output the second random number code RC2 applying the second random number RN2 transmitted from the second synchronization circuit sync2 to the second digital code DC2.

[0169] In this case, the second digital code DC2 can be understood as a code that the second multiplexer M2 responds to the 8-frequency-divided clock signal CK1 / 8 and converts the parallel input code into a serial code for output.

[0170] Furthermore, the second random number code RC2 may be understood as a thermometer type digital code in which at least some bits included in the second digital code DC2 are rearranged based on the second random number RN2.

[0171] Furthermore, the third switch circuit SW3 may output a third random number code RC3 applying a third random number RN3 to the third digital code DC3.

[0172] In more detail, the third switch circuit SW3 may output the third random number code RC3 applying the third random number RN3 transmitted from the third synchronization circuit sync3 to the third digital code DC3.

[0173] In this case, the third digital code DC3 can be understood as a code in which the third multiplexer M3 responds to the 8-frequency-divided clock signal CK1 / 8 and converts the parallel input code into a serial code for output.

[0174] In addition, the third random number code RC3 may be understood as a thermometer type digital code in which at least some bits included in the third digital code DC3 are rearranged based on the third random number RN3.

[0175] Furthermore, the fourth switch circuit SW4 may output a fourth random number code RC4 obtained by applying the fourth random number RN4 to the fourth digital code DC4.

[0176] In more detail, the fourth switch circuit SW4 may output a fourth random number code RC4 applying the fourth random number RN4 transmitted from the fourth synchronization circuit sync4 to the fourth digital code DC4.

[0177] In this case, the fourth digital code DC4 can be understood as a code in which the fourth multiplexer M4 responds to the 8-frequency-divided clock signal CK1 / 8 and converts the parallel input code into a serial code for output.

[0178] Furthermore, the fourth random number code RC4 may be understood as a thermometer type digital code in which at least some bits included in the fourth digital code DC4 are rearranged based on the fourth random number RN4.

[0179] According to an embodiment, the serializer 110B may include a thirteenth multiplexer M13 that serially converts the first random number code RC1 and the third random number code RC3 and outputs a fifth random number code RC5.

[0180] The thirteenth multiplexer M13 may receive the first random number code RC1 and the third random number code RC3 from the first switch circuit SW1 and the third switch circuit SW3 , respectively.

[0181] Furthermore, the thirteenth multiplexer M13 may serially convert the first random number code RC1 and the third random number code RC3 received in parallel to output them in response to the 4-divided clock signal CK1 / 4.

[0182] For example, the thirteenth multiplexer M13 may output the first random number code RC1 in response to a rising edge of the divided-by-4 clock signal CK1 / 4, and output the third random number code RC3 in response to a falling edge of the divided-by-4 clock signal CK1 / 4.

[0183] In addition, the serializer 110B may include a fourteenth multiplexer M14 that serially converts the second random number code RC2 and the fourth random number code RC4 and outputs a sixth random number code RC6.

[0184] The fourteenth multiplexer M14 may receive the second random number code RC2 and the fourth random number code RC4 from the first switch circuit SW2 and the fourth switch circuit SW4 , respectively.

[0185] In addition, the fourteenth multiplexer M14 may serially convert the second random number code RC2 and the fourth random number code RC4 received in parallel to output them in response to the 4-divided clock signal CK1 / 4.

[0186] For example, the fourteenth multiplexer M14 may output the second random number code RC2 in response to a rising edge of the divided-by-4 clock signal CK1 / 4, and output the fourth random number code RC4 in response to a falling edge of the divided-by-4 clock signal CK1 / 4.

[0187] In this case, the 4-frequency clock signal CK1 / 4 can be understood as a clock signal generated with 1 / 4 speed of the first clock signal CK1. In addition, for example, the 4-frequency clock signal CK1 / 4 can have the same speed as each of the second clock signal CK2 to the fifth clock signal CK5.

[0188] In addition, the serializer 110B may include an output multiplexer M15 that converts the fifth random number code RC5 and the sixth random number code RC6 into serial codes and outputs the serial code SDI.

[0189] The output multiplexer M15 may receive the fifth random number code RC5 and the sixth random number code RC6 from the thirteenth multiplexer M13 and the fourteenth multiplexer M14, respectively.

[0190] In addition, the output multiplexer M15 may serially convert the fifth random number code RC5 and the sixth random number code RC6 received in parallel to output them in response to the divided-by-2 clock signal CK1 / 2.

[0191] For example, the output multiplexer M15 may output the fifth random number code RC5 in response to a rising edge of the divided-by-2 clock signal CK1 / 2 , and may output the sixth random number code RC6 in response to a falling edge of the divided-by-2 clock signal CK1 / 2 .

[0192] In this case, the divided-by-two clock signal CK1 / 2 may be understood as a clock signal generated with half the speed of the first clock signal CK1.

[0193] In this way, the output multiplexer M15 can output the serial code SDI at a speed four times that of the first to fourth random number codes RC1 to RC4.

[0194] In this case, when receiving digital codes DC1, DC2, DC3 and DC4 having a relatively low speed, the first to fourth switch circuits SW1 to SW4 can operate with relatively fewer elements compared to the case of receiving a serial code SDI having a relatively high speed.

[0195] Furthermore, when receiving the digital codes DC1, DC2, DC3, and DC4 having a relatively low speed, the first to fourth switch circuits SW1 to SW4 may operate at relatively low power compared to the case of receiving the serial code SDI having a relatively high speed.

[0196] In this way, the DAC circuit 100 according to the embodiment can reduce power consumed by the operation of the switch circuits SW1 , SW2 , SW3 , and SW4 when applying random numbers to the serial code SDI output through the serializer 110B.

[0197] Furthermore, the serial code SDI may include first to fourth random number codes RC1 to RC4 in which different random numbers are applied to data of the first to fourth digital codes DC1 to DC4, respectively.

[0198] For example, refer to Figure 5B , the serial code SDI may include data of a first random number code RC1 applying a random number “RN(n)” to “DC1(n)” of a first digital code DC1.

[0199] Furthermore, the serial code SDI may include data of a second random number code RC2 applying a random number “RN(n+1)” to “DC2(n)” of the second digital code DC2.

[0200] Furthermore, the serial code SDI may include data of a third random number code RC3 of "DC3(n)" applying a random number "RN(n+2)" to a third digital code DC3.

[0201] Furthermore, the serial code SDI may include data of a fourth random number code RC4 of "DC4 (n)" applying a random number "RN (n+3)" to a fourth digital code DC4.

[0202] Referring to the above configuration, the serializer 110B may transmit different random numbers RN1 to RN4 among random numbers generated by the pseudo random number generator PRNG to the plurality of switch circuits SW1 to SW4 , respectively, using the plurality of synchronization circuits sync1 to sync4 .

[0203] Therefore, the serializer 110B may output a serial code SDI including random number codes RC1 to RC4 in which different random numbers RN1 to RN4 are respectively applied to digital codes DC1 to DC4 output from different multiplexers M1 to M4 .

[0204] In this way, the serializer 110B can increase the randomness of the code included in the serial code SDI.

[0205] Furthermore, the serializer 110B may minimize quality degradation of the analog signal AO due to mismatching between the plurality of unit cells UC1 to UCn included in the cell array 120 by increasing randomness of a code included in the serial code SDI.

[0206] Therefore, the DAC circuit 100 according to the embodiment can improve the linearity of the analog signal AO output based on the serial code SDI. Specifically, the DAC circuit 100 according to the embodiment can improve the quality of the analog signal AO output based on the serial code SDI.

[0207] Figure 6 is a circuit diagram showing a configuration of a serializer according to an embodiment.

[0208] refer to Figure 6 , the serializer 110C according to the embodiment may include a plurality of multiplexers M1 to M15 , first to eighth switch circuits SW1 to SW8 , a pseudo random number generator PRNG, and first to eighth synchronization circuits sync1 to sync8 .

[0209] Figure 6 The serializer 110C shown in FIG. 1 can be understood as Figure 2 Accordingly, the same reference numerals are used for components that are the same or substantially the same as those described above, and additional descriptions that may overlap with the above will be omitted to avoid redundancy.

[0210] According to an embodiment, the serializer 110C may include first to eighth synchronization circuits sync1 to sync8 connected to the pseudo random number generator PRNG.

[0211] In more detail, the serializer 110C may include: first to eighth synchronization circuits sync1 to sync8 , which respectively send random numbers generated by the pseudo random number generator PRNG at different times to corresponding switch circuits SW1 to SW8 in response to different clock signals CK2 to CK9 .

[0212] The serializer 110C may include a first synchronization circuit sync1 that transmits a first random number RN1 among random numbers RN generated by a pseudo random number generator PRNG to a first switch circuit SW1 in response to a rising edge of a second clock signal CK2 .

[0213] The serializer 110C may include a second synchronization circuit sync2 that transmits a second random number RN2 among the random numbers RN generated by the pseudo random number generator PRNG to the second switch circuit SW2 in response to a rising edge of the third clock signal CK3 .

[0214] The serializer 110C may include a third synchronization circuit sync3 that transmits a third random number RN3 among the random numbers RN generated by the pseudo random number generator PRNG to the third switch circuit SW3 in response to a rising edge of the fourth clock signal CK4 .

[0215] The serializer 110C may include a fourth synchronization circuit sync4 that transmits a fourth random number RN4 among the random numbers RN generated by the pseudo random number generator PRNG to the fourth switch circuit SW4 in response to a rising edge of the fifth clock signal CK5 .

[0216] The serializer 110C may include a fifth synchronization circuit sync5 that transmits a fifth random number RN5 among the random numbers RN generated by the pseudo random number generator PRNG to the fifth switch circuit SW5 in response to a rising edge of the sixth clock signal CK6 .

[0217] The serializer 110C may include a sixth synchronization circuit sync6 that transmits a sixth random number RN6 among the random numbers RN generated by the pseudo random number generator PRNG to a sixth switch circuit SW6 in response to a rising edge of the seventh clock signal CK7 .

[0218] The serializer 110C may include a seventh synchronization circuit sync7 that transmits a seventh random number RN7 among the random numbers RN generated by the pseudo random number generator PRNG to the seventh switch circuit SW7 in response to a rising edge of the eighth clock signal CK8 .

[0219] The serializer 110C may include an eighth synchronization circuit sync8 that transmits an eighth random number RN8 among the random numbers RN generated by the pseudo random number generator PRNG to the eighth switch circuit SW8 in response to a rising edge of the ninth clock signal CK9 .

[0220] In this case, for example, the second to ninth clock signals CK2 to CK9 may each have 1 / 8 of the speed of the first clock signal CK1.

[0221] In addition, the first random number RN1, the second random number RN2, the third random number RN3, the fourth random number RN4, the fifth random number RN5, the sixth random number RN6, the seventh random number RN7 and the eighth random number RN8 can be understood as random numbers generated by the pseudo-random number generator PRNG at different times.

[0222] Accordingly, the first to eighth synchronization circuits sync1 to sync8 can send different random numbers generated by the pseudo random number generator PRNG in response to different rising edges of the first clock signal CK1 to the first to eighth switch circuits SW1 to SW8 , respectively.

[0223] According to an embodiment, the first to eighth switch circuits SW1 to SW8 may respectively output random number codes RC1 to RC8 in which input random numbers RN1 to RN8 are applied to input digital codes DC1 to DC8 .

[0224] For example, the first switch circuit SW1 may output a first random number code RC1 in which the first random number RN1 is applied to the first digital code DC1.

[0225] In this case, the first digital code DC1 can be understood as a code that the first multiplexer M1 converts a parallel input code into a serial code for output in response to the 16-frequency divided clock signal CK1 / 16.

[0226] Furthermore, the first random number code RC1 may be understood as a thermometer type digital code in which at least some bits included in the first digital code DC1 are rearranged based on the first random number RN1.

[0227] As another example, the second switch circuit SW2 may output the second random number code RC2 in which the second random number RN2 is applied to the second digital code DC2.

[0228] In this case, the second digital code DC2 can be understood as a code that the second multiplexer M2 responds to the 16-frequency divided clock signal CK1 / 16 and converts the parallel input code into a serial code for output.

[0229] Furthermore, the second random number code RC2 may be understood as a thermometer type digital code in which at least some bits included in the second digital code DC2 are rearranged based on the second random number RN2.

[0230] According to an embodiment, the serializer 110C may include a ninth multiplexer M9 that serially converts the first random number code RC1 and the fifth random number code RC5 to output.

[0231] In more detail, the ninth multiplexer M9 may serially convert the first random number code RC1 and the fifth random number code RC5 received in parallel to output them in response to the 8-divided clock signal CK1 / 8.

[0232] For example, the output multiplexer M15 may output the first random number code RC1 in response to a rising edge of the divided-by-8 clock signal CK1 / 8, and may output the fifth random number code RC5 in response to a falling edge of the divided-by-8 clock signal CK1 / 8.

[0233] In addition, the serializer 110C may include a tenth multiplexer M10 that serially converts the second random number code RC2 and the sixth random number code RC6 to output.

[0234] In more detail, the tenth multiplexer M10 may serially convert the second random number code RC2 and the sixth random number code RC6 received in parallel to output them in response to the 8-divided clock signal CK1 / 8.

[0235] For example, the tenth multiplexer M10 may output the second random number code RC2 in response to a rising edge of the divided-by-8 clock signal CK1 / 8, and may output the sixth random number code RC6 in response to a falling edge of the divided-by-8 clock signal CK1 / 8.

[0236] In addition, the serializer 110C may include an eleventh multiplexer M11 that serially converts the third random number code RC3 and the seventh random number code RC7 to output.

[0237] In more detail, the eleventh multiplexer M11 may serially convert the third random number code RC3 and the seventh random number code RC7 received in parallel to output them in response to the 8-divided clock signal CK1 / 8.

[0238] For example, the eleventh multiplexer M11 may output the third random number code RC3 in response to a rising edge of the divided-by-8 clock signal CK1 / 8, and may output the seventh random number code RC7 in response to a falling edge of the divided-by-8 clock signal CK1 / 8.

[0239] In addition, the serializer 110C may include a twelfth multiplexer M12 that serially converts the fourth random number code RC4 and the eighth random number code RC8 to output.

[0240] In more detail, the twelfth multiplexer M12 may serially convert the fourth random number code RC4 and the eighth random number code RC8 received in parallel to output them in response to the 8-divided clock signal CK1 / 8.

[0241] For example, the twelfth multiplexer M12 may output the fourth random number code RC4 in response to a rising edge of the divided-by-8 clock signal CK1 / 8, and may output the eighth random number code RC8 in response to a falling edge of the divided-by-8 clock signal CK1 / 8.

[0242] In this case, the 8-frequency-divided clock signal CK1 / 8 may be understood as a clock signal generated with 1 / 8 of the speed of the first clock signal CK1.

[0243] Furthermore, the serializer 110C may include an output multiplexer M15 that converts two codes converted into serial by each of the plurality of multiplexers M1 to M14 and received in parallel into serial and outputs a serial code SDI.

[0244] In more detail, the output multiplexer M15 may output codes to which different random numbers RN1 to RN8 are applied in response to rising and falling edges of the divided-by-2 clock signal CK1 / 2 .

[0245] In this way, the output multiplexer M15 can output the serial code SDI having eight times the speed of the first to eighth random number codes RC1 to RC8.

[0246] In this case, when receiving the digital codes DC1 to DC8 having a relatively low speed, each of the first to eighth switch circuits SW1 to SW8 may be operated with relatively fewer elements than in the case of receiving the serial code SDI having a relatively high speed.

[0247] Furthermore, when receiving the digital codes DC1 to DC8 having a relatively low speed, each of the first to eighth switch circuits SW1 to SW8 can be operated with relatively low power compared to the case of receiving the serial code SDI having a relatively high speed.

[0248] In this way, the DAC circuit 100 according to the embodiment can reduce power consumed by the operation of the switch circuits SW1 to SW8 when the serial code SDI to which the random number is applied is output through the serializer 110C.

[0249] Furthermore, the serial code SDI may include first to eighth random number codes RC1 to RC8 , in which different random numbers are applied to data of the first to eighth digital codes DC1 to DC8 , respectively.

[0250] Referring to the above configuration, the serializer 110C may transmit different random numbers RN1 to RN8 among random numbers generated by the pseudo random number generator PRNG to the plurality of switch circuits SW1 to SW8 , respectively, using the plurality of synchronization circuits sync1 to sync8 .

[0251] Therefore, the serializer 110C may output a serial code SDI including random number codes RC1 to RC8 , in which different random numbers RN1 to RN8 are respectively applied to digital codes DC1 to DC8 output from different multiplexers M1 to M8 .

[0252] In this way, the serializer 110C can increase the randomness of the code included in the serial code SDI.

[0253] Furthermore, the serializer 110C may minimize quality degradation of the analog signal AO due to mismatching between the plurality of unit cells UC1 to UCn included in the cell array 120 by increasing randomness of a code included in the serial code SDI.

[0254] Therefore, the DAC circuit 100 according to the embodiment can improve the linearity of the analog signal AO output based on the serial code SDI. Specifically, the DAC circuit 100 according to the embodiment can improve the quality of the analog signal AO output based on the serial code SDI.

[0255] Figure 7 is a flow chart illustrating a method for controlling a DAC circuit according to an embodiment.

[0256] refer to Figure 7 , the DAC circuit 100 according to the embodiment may transmit different random numbers to the plurality of switch circuits SW1 and SW2 , and may output a serial code SDI including a code to which the different random numbers are applied.

[0257] In more detail, the DAC circuit 100 may transmit different random numbers generated by a pseudo random number generator PRNG to the plurality of switch circuits SW1 and SW2 using the random number circuit RNC, and may output a serial code SDI including a code to which the different random numbers are applied.

[0258] In operation S10 , the DAC circuit 100 according to the embodiment may apply the first clock signal CK1 to a pseudo random number generator PRNG.

[0259] In more detail, the DAC circuit 100 may apply the first clock signal CK1 to a pseudo random number generator PRNG that generates different random numbers in response to a rising edge of an input clock signal.

[0260] In this case, the pseudo-random number generator PRNG may be referred to as a pseudo-random number generator that generates a pseudo-random number according to a specified probability in response to a rising edge of an input clock signal.

[0261] Furthermore, in this case, the first clock signal CK1 may have the same speed as that of the serial code SDI output by the DAC circuit 100 .

[0262] In operation S20 , the DAC circuit 100 according to the embodiment may transmit random numbers different from each other to the first switch circuit SW1 and the second switch circuit SW2 .

[0263] In more detail, the DAC circuit 100 may transmit random numbers different from each other, generated by the pseudo random number generator PRNG in response to different rising edges of the first clock signal CK1 , to the first switch circuit SW1 and the second switch circuit SW2 , respectively.

[0264] For example, the DAC circuit 100 may use a plurality of synchronization circuits operating in response to clock signals having different phases, and may transmit random numbers generated by the pseudo random number generator PRNG at different times to the first switch circuit SW1 and the second switch circuit SW2 , respectively.

[0265] In operation S30 , the DAC circuit 100 according to the embodiment may generate an analog signal AO based on a serial code SDI including a code to which a random number is applied.

[0266] First, the DAC circuit 100 may generate a serial code SDI including random number codes RC1 and RC2 which are output by applying different random numbers to an input digital code through the switch circuits SW1 and SW2 , respectively.

[0267] For example, the DAC circuit 100 may serially convert codes including random number codes RC1 and RC2 output from the plurality of switch circuits SW1 and SW2 into a serial code using the serializer 110 , and may output a serial code SDI.

[0268] In addition, the DAC circuit 100 may generate an analog signal AO through at least some of the plurality of unit cells UC1 to UCn included in the cell array 120 based on the serial code SDI.

[0269] In more detail, the DAC circuit 100 (or the cell array 120 ) may apply a preset current to at least some of the unit cells selected by the serial code SDI among the plurality of unit cells UC1 to UCn, and may generate the analog signal AO including an output voltage signal.

[0270] In this case, each of the plurality of unit cells UC1 to UCn may be referred to as a current cell including at least one resistance element.

[0271] Referring to the above configuration, the DAC circuit 100 according to the embodiment may use codes to which different random numbers are applied through the plurality of switch circuits SW1 and SW2 to generate the analog signal AO through at least some of the plurality of unit cells UC1 to UCn.

[0272] In this case, the DAC circuit 100 may increase the randomness of the code included in the serial code SDI by generating the serial code SDI to include random codes to which different random numbers are applied.

[0273] Furthermore, the DAC circuit 100 may minimize quality degradation of the analog signal AO due to mismatching between the plurality of unit cells UC1 to UCn included in the cell array 120 by increasing randomness of a code included in the serial code SDI.

[0274] Accordingly, the DAC circuit 100 according to the embodiment can improve the quality of the analog signal AO output based on the serial code SDI.

[0275] Figure 8 is a flowchart illustrating a method of generating a random number code to which different random numbers are applied using a first switch circuit and a second switch circuit according to an embodiment.

[0276] refer to Figure 8 The DAC circuit 100 according to the embodiment may use a plurality of synchronization circuits operating in response to clock signals having different phases, and may send random numbers generated by a pseudo random number generator PRNG at different times to the first switch circuit SW1 and the second switch circuit SW2, respectively.

[0277] In operation S21 , the DAC circuit 100 according to the embodiment may input the second clock signal CK2 to the first synchronization circuit sync1 .

[0278] In more detail, the DAC circuit 100 may input the second clock signal CK2 having a lower speed than the first clock signal CK1 to the first synchronization circuit sync1 .

[0279] In this case, for example, the second clock signal CK2 may have a half speed of the first clock signal CK1 , but the embodiment is not limited thereto.

[0280] The first synchronization circuit sync1 according to an embodiment may transmit some random numbers generated by the pseudo random number generator PRNG to the first switch circuit SW1 in response to the second clock signal CK2 .

[0281] In more detail, when the rising edge of the second clock signal CK2 occurs, the first synchronization circuit sync1 may transmit the first random number RN1 generated by the pseudo random number generator PRNG to the first switch circuit SW1 .

[0282] Furthermore, in operation S22 , the first switch circuit SW1 according to the embodiment may output the first random number code RC1 .

[0283] In more detail, the first switch circuit SW1 may output the first random number code RC1 obtained by applying the first random number RN1 transmitted by the first synchronization circuit sync1 to the first digital code DC1.

[0284] In this case, the first digital code DC1 may be understood as a digital code input to the first switch circuit SW1 from a multiplexer connected to the first switch circuit SW1.

[0285] In operation S23 , the DAC circuit 100 according to the embodiment may input the third clock signal CK3 to the second synchronization circuit sync2 .

[0286] In more detail, the DAC circuit 100 may input the third clock signal CK3 having a lower speed than the first clock signal CK1 to the second synchronization circuit sync2 .

[0287] In this case, for example, the third clock signal CK3 may have a speed half that of the first clock signal CK1 , but the embodiment is not limited thereto.

[0288] In addition, for example, the third clock signal CK3 and the second clock signal CK2 may have opposite phases to each other, but the embodiment is not limited thereto.

[0289] The second synchronization circuit sync2 according to the embodiment may transmit some random numbers generated by the pseudo random number generator PRNG to the second switch circuit SW2 in response to the third clock signal CK3 .

[0290] In more detail, the second synchronization circuit sync2 may transmit the random number generated by the pseudo random number generator PRNG to the second switch circuit SW2 when a rising edge of the third clock signal CK3 occurs.

[0291] In this case, the second digital code DC2 may be understood as a digital code input to the second switch circuit SW2 from a multiplexer connected to the second switch circuit SW2.

[0292] Furthermore, in operation S24 , the second switch circuit SW2 according to the embodiment may output the second random number code RC2 .

[0293] In more detail, the second switch circuit SW2 may output the second random number code RC2 applying the second random number RN2 transmitted by the second synchronization circuit sync2 to the second digital code DC2.

[0294] Referring to the above configuration, the DAC circuit 100 according to the embodiment may transmit different random numbers to the plurality of switch circuits SW1 and SW2 using the plurality of synchronization circuits sync1 and sync2 .

[0295] Furthermore, the DAC circuit 100 may output random number codes RC1 and RC2 to which different random numbers RN1 and RN2 are applied through the plurality of switch circuits SW1 and SW2 .

[0296] In addition, the DAC circuit 100 may generate an analog signal AO through at least some of the plurality of unit cells UC1 to UCn based on the serial code SDI including a random number code to which different random numbers are applied.

[0297] In this case, the DAC circuit 100 may increase the randomness of the code included in the serial code SDI by generating the serial code SDI to include random codes to which different random numbers are applied.

[0298] Furthermore, the DAC circuit 100 may minimize the quality degradation of the analog signal AO due to mismatching between the plurality of unit cells UC1 to UCn included in the cell array 120 by increasing the randomness of the code included in the serial code SDI.

[0299] Therefore, the DAC circuit 100 according to the embodiment may improve the quality (eg, linearity) of the analog signal AO output based on the serial code SDI.

[0300] Fig. 9 is a circuit diagram showing a configuration of a serializer including a first decoder and a second decoder according to an embodiment.

[0301] refer to Fig. 9 , the serializer 110D according to the embodiment may include decoders D1 and D2 connected between switch circuits SW1 and SW2 and multiplexers M1 and M2, respectively.

[0302] in this case, Fig. 9 The serializer 110D shown in FIG. 1 may be understood as Figure 1 and Figure 2Accordingly, the same reference numerals are used for components that are the same or substantially the same as those described above, and additional descriptions that may overlap with the above will be omitted to avoid redundancy.

[0303] In more detail, the serializer 110D may include a first decoder D1 connected between the first multiplexer M1 and the first switch circuit SW1 .

[0304] Furthermore, the serializer 110D may include a second decoder D2 connected between the second multiplexer M2 and the second switch circuit SW2 .

[0305] According to an embodiment, the first decoder D1 and the second decoder D2 may convert digital codes DC1 and DC2 input in a binary form into digital codes DC1_T and DC2_T having a thermometer form for output.

[0306] In more detail, the first decoder D1 may receive the first digital code DC1 in a binary form from the first multiplexer M1. In addition, the first decoder D1 may convert the first digital code DC1 in a binary form into a first thermometer code DC1_T in a thermometer form for output.

[0307] In addition, the second decoder D2 may receive the second digital code DC2 in binary form from the second multiplexer M2. In addition, the second decoder D2 may convert the second digital code DC2 in binary form into a second thermometer code DC2_T in thermometer form for output.

[0308] In this case, each of the thermometer codes DC1_T, DC2_T having a thermometer form may be formed to correspond to each of the plurality of unit cells UC1 to UCn included in the cell array 120 .

[0309] Furthermore, the first switch circuit SW1 and the second switch circuit SW2 may respectively output the first random number code RC1 and the second random number code RC2 applying different random numbers to the codes DC1_T and DC2_T converted into the thermometer form.

[0310] For example, the first switch circuit SW1 may output the first random number code RC1 applying the first random number RN1 to the first thermometer code DC1_T.

[0311] In addition, the second switch circuit SW2 may output a second random number code RC2 obtained by applying the second random number RN2 to the second thermometer code DC2_T.

[0312] According to an embodiment, the serializer 110D (or the output multiplexer M15 ) may output a serial code SDI including random number codes RC1 and RC2 to which different random numbers RN1 and RN2 are applied.

[0313] In more detail, the output multiplexer M15 may output the serial code SDI including the first random number code RC1 and the second random number code RC2.

[0314] For example, the output multiplexer M15 may convert the first random number code RC1 and the second random number code RC2 input in parallel into serial codes and may output them as a serial code SDI.

[0315] Referring to the above configuration, the serializer 110D according to the embodiment may convert a binary form code into a thermometer form code using a plurality of decoders D1 and D2 .

[0316] Furthermore, the serializer 110D may output random number codes RC1 and RC2 obtained by applying different random numbers RN1 and RN2 to the code converted into the thermometer form through the plurality of switch circuits SW1 and SW2 .

[0317] In addition, the DAC circuit 100 may generate an analog signal AO through at least some of the plurality of unit cells UC1 to UCn based on the serial code SDI including the random number codes RC1 and RC2 to which different random numbers RN1 and RN2 are applied.

[0318] In this case, the serializer 110D may increase the randomness of a code included in the serial code SDI by generating the serial code SDI to include random number codes RC1 and RC2 to which different random numbers RN1 and RN2 are applied.

[0319] Furthermore, the DAC circuit 100 may minimize quality degradation of the analog signal AO due to mismatching between the plurality of unit cells UC1 to UCn included in the cell array 120 by increasing randomness of a code included in the serial code SDI.

[0320] Therefore, the DAC circuit 100 according to the embodiment may improve the quality (eg, linearity) of the analog signal AO output based on the serial code SDI.

[0321] Fig.10 is a circuit diagram showing a configuration of a serializer including first to fourth decoders according to an embodiment.

[0322] refer to Fig.10 , the serializer 110E according to the embodiment may include decoders D1 to D4 connected between switch circuits SW1 to SW4 and multiplexers M1 to M4, respectively.

[0323] in this case, Fig.10 The serializer 110E shown in FIG. 1 can be understood as Figure 1 and Figure 2 Accordingly, the same reference numerals are used for components that are the same or substantially the same as those described above, and additional descriptions that may overlap with the above will be omitted to avoid redundancy.

[0324] In more detail, the serializer 110E may include a first decoder D1 connected between the first multiplexer M1 and the first switch circuit SW1. In addition, the serializer 110E may include a second decoder D2 connected between the second multiplexer M2 and the second switch circuit SW2. In addition, the serializer 110E may include a third decoder D3 connected between the third multiplexer M3 and the third switch circuit SW3. In addition, the serializer 110E may include a fourth decoder D4 connected between the fourth multiplexer M4 and the fourth switch circuit SW4.

[0325] According to an embodiment, the first to fourth decoders D1 to D4 may convert digital codes DC1 to DC4 input in a binary form into digital codes DC1_T to DC4_T having a thermometer form, respectively, for output.

[0326] In more detail, the first decoder D1 may convert the first digital code DC1 in a binary form received from the first multiplexer M1 into a first thermometer code DC1_T in a thermometer form for output.

[0327] In addition, the second decoder D2 may convert the second digital code DC2 in a binary form received from the second multiplexer M2 into a second thermometer code DC2_T in a thermometer form for output.

[0328] In addition, the third decoder D3 may convert the third digital code DC3 in a binary form received from the third multiplexer M3 into a third thermometer code DC3_T in a thermometer form for output.

[0329] In addition, the fourth decoder D4 may convert the fourth digital code DC4 in a binary form received from the fourth multiplexer M4 into a fourth thermometer code DC4_T in a thermometer form for output.

[0330] In this case, each of the thermometer codes DC1_T to DC4_T having a thermometer form may be formed to correspond to each of the plurality of unit cells UC1 to UCn included in the cell array 120 .

[0331] Furthermore, the first to fourth switch circuits SW1 to SW4 may respectively output first to fourth random number codes RC1 to RC4 applying different random numbers to the codes DC1_T to DC4_T converted into the thermometer form.

[0332] For example, the first switch circuit SW1 may output the first random number code RC1 obtained by applying the first random number RN1 to the first thermometer code DC1_T.

[0333] In addition, the second switch circuit SW2 may output a second random number code RC2 obtained by applying the second random number RN2 to the second thermometer code DC2_T.

[0334] Furthermore, the third switch circuit SW3 may output a third random number code RC3 obtained by applying the third random number RN3 to the third thermometer code DC3_T.

[0335] Furthermore, the fourth switch circuit SW4 may output a fourth random number code RC4 obtained by applying the fourth random number RN4 to the fourth thermometer code DC4_T.

[0336] According to an embodiment, the serializer 110E (or the output multiplexer M15 ) may output a serial code SDI including random number codes RC1 to RC4 to which different random numbers RN1 to RN4 are applied.

[0337] In more detail, the output multiplexer M15 may output the serial code SDI including the first to fourth random number codes RC1 to RC4.

[0338] For example, the output multiplexer M15 may convert a fifth random number code RC5 composed of the first random number code RC1 and the third random number code RC3 in series and a sixth random number code RC6 composed of the second random number code RC2 and the fourth random number code RC4 in series into serial codes, and may output the conversion results as a serial code SDI.

[0339] Referring to the above configuration, the serializer 110E according to the embodiment may convert a binary form code into a thermometer form code using a plurality of decoders D1 and D4 , respectively.

[0340] Furthermore, the serializer 110E may output random number codes RC1 to RC4 obtained by applying different random numbers RN1 to RN4 to the codes converted into the thermometer form through the plurality of switch circuits SW1 to SW4 .

[0341] Furthermore, the DAC circuit 100 may generate an analog signal AO through at least some of the plurality of unit cells UC1 to UCn based on the serial code SDI including the random number codes RC1 to RC4 to which different random numbers RN1 to RN4 are applied.

[0342] In this case, the serializer 110E may increase the randomness of a code included in the serial code SDI by generating the serial code SDI including the random number codes RC1 to RC4 to which different random numbers RN1 to RN4 are applied.

[0343] Furthermore, the DAC circuit 100 may minimize quality degradation of the analog signal AO due to mismatching between the plurality of unit cells UC1 to UCn included in the cell array 120 by increasing randomness of a code included in the serial code SDI.

[0344] Therefore, the DAC circuit 100 according to the embodiment may improve the quality (eg, linearity) of the analog signal AO output based on the serial code SDI.

[0345] Fig.11 is a circuit diagram showing a configuration of a DAC circuit including a decoder connected to a serializer according to an embodiment.

[0346] refer to Fig.11 The DAC circuit 100A according to the embodiment may further include a decoder 1110 connected to the serializer 110 .

[0347] in this case, Fig.11 The DAC circuit 100A shown in FIG. 1 can be understood as Figure 1 Therefore, the same reference numerals are used for components that are the same as or substantially the same as those described above, and additional descriptions that may overlap with the above will be omitted to avoid redundancy.

[0348] In more detail, the decoder 1110 may convert the parallel code PDI input in a binary form into a thermometer parallel code PDI_T in a thermometer form for output.

[0349] For example, the decoder 1110 may convert a 3-bit parallel code PDI having a binary form into a 7-bit thermometer parallel code PDI_T having a thermometer form for output.

[0350] In this case, the thermometer parallel code PDI_T having a thermometer form may include a code corresponding to each of the plurality of unit cells UC1 to UCn included in the cell array 120 .

[0351] According to an embodiment, the serializer 110 may convert a thermometer parallel code PDI_T having a thermometer form input in parallel into a serial code SDI for output.

[0352] In more detail, the serializer 110 may use a plurality of multiplexers M1 to M15 and may serially output the serial code SDI consisting of codes included in the parallel-input thermometer parallel code PDI_T in the form of a thermometer.

[0353] In this case, the serializer 110 may output a serial code SDI including codes to which different random numbers are applied using a pseudo random number generator PRNG, a plurality of synchronization circuits, and a plurality of switch circuits.

[0354] In this way, the serializer 110 can increase the randomness of the code included in the serial code SDI.

[0355] Furthermore, the cell array 120 according to the embodiment may generate an analog signal AO for output using at least some unit cells selected based on the input serial code SDI among the plurality of unit cells UC1 to UCn.

[0356] For example, the cell array 120 may apply a preset current to unit cells selected based on the serial code SDI input from the serializer 110. Also, the cell array 120 may output an analog signal AO including a voltage signal output when current is applied to at least some of the unit cells.

[0357] In this case, for example, each of the plurality of unit cells UC1 to UCn may be referred to as a current cell including at least one resistance element, but the embodiment is not limited thereto.

[0358] Through the above configuration, the DAC circuit 100A can generate the analog signal AO based on the serial code SDI with increased randomness.

[0359] In this case, as the randomness of the serial code SDI increases, the quality degradation of the analog signal AO due to the mismatch between the unit cells can be minimized.

[0360] Therefore, the DAC circuit 100A according to the embodiment can improve the quality of the analog signal AO output based on the serial code SDI with increased randomness.

[0361] Fig.12 is a block diagram illustrating an electronic device including a DAC circuit and an antenna according to an embodiment.

[0362] refer to Fig.12 , the electronic device 10 according to the embodiment may include a DAC circuit 100B and an antenna 1210 .

[0363] in this case, Fig.12 The DAC circuit 100B shown in FIG. 1 can be understood as Figure 1 Therefore, the same reference numerals are used for components that are the same as or substantially the same as those described above, and additional descriptions that may overlap with the above will be omitted to avoid redundancy.

[0364] In more detail, the electronic device 10 may include a DAC circuit 100B configured to convert a digital signal into an analog signal AO. In this case, the DAC circuit 100B may be understood as having Figure 1 and Figure 2 The DAC circuit 100 shown in FIG. 1 is a circuit of substantially the same configuration.

[0365] According to an embodiment, the serializer 110 may output a serial code SDI by applying a different random number to each code included in the input parallel code PDI.

[0366] In addition, the cell array 120 may generate the analog signal AO using unit cells corresponding to codes to which different random numbers are applied in the serial code SDI.

[0367] In more detail, the cell array 120 may generate the analog signal AO using a unit cell selected by the serial code SDI whose randomness is increased by applying a different random number to each code.

[0368] In this case, each of the plurality of unit cells UC1 to UCn may be understood as a current cell. Accordingly, the cell array 120 may output an analog signal AO including a voltage signal output by applying a preset current to a unit cell selected by the serial code SDI.

[0369] In this case, the serializer 110 of the DAC circuit 100B may output a serial code SDI including codes to which different random numbers are applied, using a pseudo random number generator PRNG, a plurality of synchronization circuits, and a plurality of switch circuits.

[0370] In this way, the serializer 110 can increase the randomness of the code included in the serial code SDI.

[0371] Furthermore, the DAC circuit 100B may minimize quality degradation of the analog signal AO due to mismatching among the plurality of unit cells UC1 to UCn by using the serial code SDI having increased randomness.

[0372] In addition, the electronic device 10 according to the embodiment may include an antenna 1210 that outputs the analog signal AO output by the DAC circuit 100B as a radio frequency RF signal to the outside.

[0373] According to an embodiment, the electronic device 10 may include an analog front end (AFE) to convert the analog signal AO output from the DAC circuit 100B into an RF signal with a preset frequency. In this case, the AFE may be understood as being disposed between the antenna 1210 and the DAC circuit 100B.

[0374] According to an embodiment, the antenna 1210 may transmit the analog signal AO output by the DAC circuit 100B to the outside (eg, a user terminal) as an RF signal having a designated frequency.

[0375] According to an embodiment, the antenna 1210 may receive an RF signal transmitted from the outside.

[0376] As described above, the serializer 110 according to the embodiment may include a plurality of switch circuits SW1 and SW2 receiving outputs of some of the multiplexers M1 to M15 except the output multiplexer M15 .

[0377] In this case, the speed of the serial code SDI output from the output multiplexer M15 may be relatively high compared to the code output from each of the multiplexers M1 to M14 except the output multiplexer M15.

[0378] Therefore, when receiving the outputs of the multiplexers M1 to M14 (excluding the output multiplexer M15 ), the plurality of switch circuits SW1 and SW2 may operate at relatively low power compared to the case of receiving the serial code SDI output from the output multiplexer M15 .

[0379] Furthermore, the serializer 110 according to the embodiment may transmit different random numbers RN1 and RN2 among the random numbers generated by the pseudo random number generator PRNG to the plurality of switch circuits SW1 and SW2 , respectively.

[0380] Accordingly, the serializer 110 may apply different random numbers RN1 and RN2 to the digital codes output from the different multiplexers M1 and M2. In this way, the serializer 110 may increase the randomness of the code included in the serial code SDI.

[0381] Furthermore, the serializer 110 may increase randomness of a code included in the serial code SDI to minimize quality degradation of the analog signal AO due to mismatching between the plurality of unit cells UC1 to UCn.

[0382] Therefore, the DAC circuit 100 according to the embodiment can improve the linearity of the analog signal AO output based on the serial code SDI. Specifically, the DAC circuit 100 according to the embodiment can improve the quality of the analog signal AO output based on the serial code SDI.

[0383] According to an embodiment, a DAC circuit can improve the quality of an analog signal at lower power.

[0384] While various aspects of the embodiments have been particularly shown and described above, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the claims.

Claims

1. A digital-to-analog converter DAC circuit, comprising: a serializer circuit including a plurality of multiplexers and configured to convert the parallel code in digital form into a serial code using the plurality of multiplexers; as well as a cell array including a plurality of unit cells and configured to output an analog signal based on the serial code, Wherein, the serializer circuit comprises: a pseudo-random number generation circuit configured to generate a random number in response to an edge of a first clock signal; A first switch circuit connected to the first multiplexer; a second switch circuit connected to the second multiplexer; and The random number circuit is configured to send different random numbers generated by the pseudo-random number generation circuit in response to different edges of the first clock signal to the first switch circuit and the second switch circuit respectively.

2. The DAC circuit according to claim 1, wherein: The random number circuit comprises: a first synchronization circuit configured to send, in response to a second clock signal, a first random number generated by the pseudo-random number generation circuit in response to a first edge of the first clock signal to the first switch circuit; and The second synchronization circuit is configured to send the second random number generated by the pseudo-random number generation circuit in response to the second edge of the first clock signal to the second switch circuit in response to a third clock signal different from the second clock signal.

3. The DAC circuit according to claim 2, wherein: The first switch circuit is configured to output a first random number code obtained by applying the first random number to a first digital code output from the first multiplexer, and Wherein, the second switch circuit is configured to output a second random number code obtained by applying the second random number to a second digital code output from the second multiplexer.

4. The DAC circuit according to claim 3, further comprising: The output multiplexer is configured to serially convert the first random number code and the second random number code input in parallel to each other to obtain the serial code.

5. The DAC circuit according to claim 3, wherein: The first switch circuit includes a first switch multiplexer, a second switch multiplexer, and a third switch multiplexer connected in series with each other, and The first switch circuit is further configured to use the bits of the first random number to control the first switch multiplexer, the second switch multiplexer and the third switch multiplexer to output the first random number code.

6. The DAC circuit according to claim 2, wherein: The serializer circuit further includes a third switch circuit connected to the third multiplexer and a fourth switch circuit connected to the fourth multiplexer, and Wherein, the random number circuit comprises: a third synchronization circuit configured to send a third random number generated by the pseudo-random number generation circuit in response to a third edge of the first clock signal to the third switch circuit in response to a fourth clock signal different from the second clock signal and the third clock signal; and The fourth synchronization circuit is configured to send the fourth random number generated by the pseudo-random number generation circuit in response to the fourth edge of the first clock signal to the fourth switch circuit in response to a fifth clock signal different from the second clock signal, the third clock signal and the fourth clock signal.

7. The DAC circuit according to claim 3, further comprising: a plurality of decoders configured to convert the binary code into a thermometer code, Wherein, each of the first switch circuit and the second switch circuit is configured to receive a code in the form of a thermometer.

8. The DAC circuit according to claim 7, further comprising: a first decoder connected between the first multiplexer and the first switch circuit and configured to convert the first digital code in binary form output from the first multiplexer into a code in a thermometer form; as well as The second decoder is connected between the second multiplexer and the second switch circuit and is configured to convert the second digital code in a binary form output from the second multiplexer into a code in a thermometer form.

9. The DAC circuit according to claim 1, wherein: The pseudo-random number generation circuit is further configured to generate pseudo-random numbers respectively according to a specified probability in response to an edge of the first clock signal.

10. The DAC circuit according to claim 1, wherein: The cell array is also configured to output the analog signal including a voltage signal generated by applying a preset current to a unit cell selected based on the serial code among the plurality of unit cells.

11. A method for controlling a digital-to-analog converter (DAC) circuit, the method comprising: applying a first clock signal to a pseudo-random number generation circuit, the pseudo-random number generation circuit generating random numbers in response to edges of the applied clock signal; sending different random numbers generated by the pseudo-random number generation circuit in response to different edges of the first clock signal to a first switch circuit connected to a first multiplexer and a second switch circuit connected to a second multiplexer, respectively; as well as An analog signal is generated based on a serial code including codes output from the first switch circuit and the second switch circuit, wherein the codes output from the first switch circuit and the second switch circuit are generated based on the random number.

12. The method according to claim 11, wherein: Sending different random numbers to the first switch circuit and the second switch circuit further includes: applying a second clock signal to a first synchronization circuit connected to the pseudo-random number generation circuit so that the first synchronization circuit outputs a first random number generated by the pseudo-random number generation circuit; and A third clock signal different from the second clock signal is applied to a second synchronization circuit connected to the pseudo-random number generation circuit so that the second synchronization circuit outputs a second random number different from the first random number.

13. The method according to claim 12, further comprising: outputting, by the first switch circuit, a first random number code obtained by applying the first random number to a first digital code output from the first multiplexer; as well as A second random number code obtained by applying the second random number to the second digital code output from the second multiplexer is output by the second switch circuit.

14. The method according to claim 13, further comprising: The first random number code and the second random number code input to the output multiplexer in parallel with each other are converted into the serial code by the output multiplexer.

15. The method according to claim 14, further comprising: The analog signal including a voltage signal generated by applying a preset current to a unit cell selected based on the serial code among a plurality of unit cells is output.

16. An electronic device for sending and receiving radio frequency (RF) signals, the electronic device comprising: A digital-to-analog converter DAC circuit is configured to convert a digital signal into an analog signal; as well as an antenna configured to output the analog signal as the RF signal, Wherein, the DAC circuit comprises: a serializer circuit including a plurality of multiplexers and configured to convert the parallel code in digital form into a serial code using the plurality of multiplexers; and a cell array including a plurality of unit cells and configured to output the analog signal based on the serial code, and Wherein, the serializer circuit comprises: a pseudo-random number generation circuit configured to generate a random number in response to an edge of a first clock signal; a first switch circuit connected to the first multiplexer and a second switch circuit connected to the second multiplexer; and The random number circuit is configured to send different random numbers generated by the pseudo-random number generation circuit in response to different edges of the first clock signal to the first switch circuit and the second switch circuit respectively.

17. The electronic device according to claim 16, wherein: The random number circuit comprises: a first synchronization circuit configured to send, in response to a second clock signal, a first random number generated by the pseudo-random number generation circuit in response to a first edge of the first clock signal to the first switch circuit; and The second synchronization circuit is configured to send the second random number generated by the pseudo-random number generation circuit in response to the second edge of the first clock signal to the second switch circuit in response to a third clock signal different from the second clock signal.

18. The electronic device according to claim 17, wherein: The first switch circuit is configured to output a first random number code obtained by applying the first random number to a first digital code output from the first multiplexer, and Wherein, the second switch circuit is configured to output a second random number code obtained by applying the second random number to a second digital code output from the second multiplexer.

19. The electronic device according to claim 17, wherein: The serializer circuit further includes a third switch circuit connected to the third multiplexer and a fourth switch circuit connected to the fourth multiplexer, and Wherein, the random number circuit comprises: a third synchronization circuit configured to send a third random number generated by the pseudo-random number generation circuit in response to a third edge of the first clock signal to the third switch circuit in response to a fourth clock signal different from the second clock signal and the third clock signal; and The fourth synchronization circuit is configured to send the fourth random number generated by the pseudo-random number generation circuit in response to the fourth edge of the first clock signal to the fourth switch circuit in response to a fifth clock signal different from the second clock signal, the third clock signal and the fourth clock signal.

20. The electronic device according to claim 16, wherein: The cell array is also configured to output the analog signal including a voltage signal generated by applying a preset current to a unit cell selected based on the serial code among the plurality of unit cells.

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