Multistate pulsing for high aspect ratio etching.

Abstract

A method for performing an etching process on a substrate includes applying a bias signal and a source signal to an electrode of a plasma processing system. The bias signal and the source signal are pulsed RF signals that together define repeated pulsed RF cycles, each pulsed RF cycle sequentially including a first state, a second state, a third state, and a fourth state. A power level of the bias signal in the first state is greater than the third state, a power level of the bias signal in the third state is greater than the second state, and a power level of the bias signal in the second state is greater than the fourth state. A power level of the source signal in the first state is greater than the third state, a power level of the source signal in the third state is greater than the second state, and a power level of the source signal in the second state is greater than the fourth state.

Description

[Technical field]

[0001] The present disclosure relates to the fabrication of semiconductor devices. [Background technology]

[0002] Plasma etch processes are often used in the fabrication of semiconductor devices on semiconductor wafers. In plasma etch processes, a semiconductor wafer containing the semiconductor device under fabrication is exposed to a plasma generated in a plasma processing volume. The plasma interacts with materials on the semiconductor wafer to remove material from the semiconductor wafer and / or modify the material to allow for subsequent removal from the semiconductor wafer. The plasma can be generated using specific reactant gases whose components interact with the material to be removed / modified from the semiconductor wafer without significantly interacting with other materials on the wafer that are not to be removed / modified. The plasma is generated by energizing the specific reactant gases using radio frequency signals. These radio frequency signals are transmitted through a plasma processing volume containing the reactant gases, and the semiconductor wafer is held exposed to the plasma processing volume.

[0003] Current state-of-the-art high aspect ratio contact (HARC) etch processes use a three-state RF pulsing scheme, where state 1 is typically a high peak power state that promotes high aspect ratio etching with high selectivity. State 2 is typically set to "0" (essentially zero power) and provides neutral deposition on the mask to improve selectivity. State 3 can be chosen to be a regime that provides passivation to mitigate bowing, or a different regime that improves not-open margin. As a result, there is typically a trade-off involving bowing control vs. selectivity vs. not-open margin.

[0004] It is in this context that the present disclosure arises. Summary of the Invention

[0005] Broadly, embodiments of the present disclosure provide methods and systems for four-state pulsing for high aspect ratio dielectric etching. Current high aspect ratio dielectric etches utilize three-state pulsing, which is sufficient for previous and current technology nodes. However, as pitches for high aspect ratio capacitor structures shrink, four-state pulsing offers more flexibility to adjust and control profile bow, selectivity, and non-open margins in high aspect ratio structures.

[0006] In some embodiments, a method is provided for performing an etch process on a substrate in a plasma processing system, the method comprising applying a bias signal to an electrode of the plasma processing system and applying a source signal to the electrode, the bias signal and the source signal being pulsed RF signals that together define repeated pulsed RF cycles, each pulsed RF cycle sequentially including a first state, a second state, a third state, and a fourth state, the first state being defined by the bias signal pulsed at a first bias power level and the source signal pulsed at a first source power level, and the second state being defined by the bias signal pulsed at a second bias power level and the source signal pulsed at a second source power level. a third state is defined by the bias signal pulsed at a third bias power level and the source signal pulsed at a third source power level; a fourth state is defined by the bias signal pulsed at a fourth bias power level and the source signal pulsed at a fourth source power level, the first bias power level being greater than the third bias power level, the third bias power level being greater than the second bias power level, the second bias power level being greater than the fourth bias power level, the first source power level being greater than the third source power level, the third source power level being greater than the second source power level, and the second source power level being greater than the fourth source RF power level.

[0007] In some implementations, the second bias power level is lower than the second source power level.

[0008] In some embodiments, the second bias power level is between about 1 and 20 percent of the first bias power level, and the second source power level is between about 20 and 70 percent of the first source power level.

[0009] In some embodiments, the third bias power level is between about 30 and 70 percent of the first bias power level, and the third source power level is between about 30 and 80 percent of the first source power level.

[0010] In some embodiments, the fourth bias power level is a substantially zero power level and the fourth source power level is a substantially zero power level.

[0011] In some embodiments, the duty cycle of the first state is about 3 to 30 percent of the period of the pulsed RF cycle.

[0012] In some embodiments, the duty cycle of the second state is about 3 to 30 percent of the period of the pulsed RF cycle.

[0013] In some embodiments, the duty cycle of the third state is about 3 to 30 percent of the period of the pulsed RF cycle.

[0014] In some embodiments, the duty cycle of the fourth state is about 35 to 75 percent of the period of the pulsed RF cycle.

[0015] In some implementations, the first state and the third state are configured to etch a feature on a surface of the substrate.

[0016] In some embodiments, the second state and the fourth state are configured to passivate features on the surface of the substrate.

[0017] In some embodiments, the bias signal has a frequency less than about 10 MHz and the source signal has a frequency greater than about 20 MHz.

[0018] In some embodiments, a controller device is provided, the controller device configured to cause a plasma processing system to perform an etching process on a substrate in the plasma processing system, the method including applying a bias signal to an electrode of the plasma processing system and applying a source signal to the electrode, the bias signal and the source signal being pulsed RF signals that together define repeated pulsed RF cycles, each pulsed RF cycle sequentially including a first state, a second state, a third state, and a fourth state, the first state being defined by the bias signal pulsed at a first bias power level and the source signal pulsed at a first source power level, the second state being defined by the bias signal pulsed at a second bias power level and the source signal pulsed at a second source power level. a first state is defined by a source signal pulsed at a first bias power level, a third state is defined by a bias signal pulsed at a third bias power level and a source signal pulsed at a third source power level, a fourth state is defined by a bias signal pulsed at a fourth bias power level and a source signal pulsed at a fourth source power level, the first bias power level being greater than the third bias power level, the third bias power level being greater than the second bias power level, the second bias power level being greater than the fourth bias power level, the first source power level being greater than the third source power level, the third source power level being greater than the second source power level, and the second source power level being greater than the fourth source RF power level.

[0019] In some embodiments, a method is provided for performing an etch process on a substrate in a plasma processing system, the method including applying a bias signal to a first electrode of the plasma processing system and applying a source signal to a second electrode of the plasma processing system, the bias signal and the source signal being pulsed RF signals that together define repeated pulsed RF cycles, each pulsed RF cycle sequentially including a first state, a second state, a third state, and a fourth state, the first state being defined by a bias signal pulsed at a first bias power level and a source signal pulsed at a first source power level, the second state being defined by a bias signal pulsed at a second bias power level and a source signal pulsed at a second source power level. a third state is defined by a bias signal pulsed at a third bias power level and a source signal pulsed at a third source power level; a fourth state is defined by a bias signal pulsed at a fourth bias power level and a source signal pulsed at a fourth source power level, the first bias power level being greater than the third bias power level, the third bias power level being greater than the second bias power level, the second bias power level being greater than the fourth bias power level, the first source power level being greater than the third source power level, the third source power level being greater than the second source power level, and the second source power level being greater than the fourth source RF power level.

[0020] The above represents a summary of certain embodiments, and further embodiments will become apparent to those skilled in the art once this disclosure is fully appreciated. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a side cross-sectional view of a plasma processing system for use in semiconductor chip manufacturing according to some embodiments.

[0022] [Diagram 2]FIG. 2 is a conceptual diagram illustrating a cross section of a portion of a wafer for etching, according to an embodiment of the present disclosure.

[0023] [Diagram 3] FIG. 3 is a graph conceptually illustrating various power regimes for a four-state RF pulsing regime for high aspect ratio dielectric etching, in accordance with an embodiment of the present disclosure.

[0024] [Figure 4] FIG. 4 conceptually illustrates a graph of RF power versus time for a four-state pulsed RF waveform, in accordance with an embodiment of the present disclosure.

[0025] [Diagram 5] FIG. 5 conceptually illustrates the improved results possible with a four-state RF pulsing configuration, in accordance with an embodiment of the present disclosure.

[0026] [Figure 6] FIG. 6 is an exemplary schematic diagram of the control system of FIG. 1 according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] In the following description, numerous specific details are set forth in order to provide an understanding of the embodiments of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0028] Current state-of-the-art high aspect ratio contact (HARC) etch processes use three-state RF pulsing. In this regime, state 1 is typically a high peak power state that promotes high aspect ratio etching with high selectivity. State 2 is typically set to essentially zero ("0") and provides neutral deposition on the mask to improve selectivity. State 3 can be chosen to be a regime that provides passivation to mitigate bowing, or a different regime that improves NOP margin. As a result, there is typically a trade-off with bowing control vs. selectivity vs. no-open margin. However, the fourth state provides additional knobs and flexibility to tune the high aspect ratio etch profile, the requirements of which are becoming increasingly stringent.

[0029] As described in further detail below, the addition of a fourth state in addition to a specifically selected third state provides flexibility to manage tradeoffs between warpage control, selectivity, and non-open margins. For example, the fourth state can be selected such that non-open margins are enhanced without affecting warpage or selectivity. Several power regimes have been identified that can address specific issues with HARC etching (i.e., warpage, selectivity, non-open margins). Based on the problem statement and desired results, a combination of pulse states can be selected that allows for mitigation and management of the tradeoffs. Thus, the use of a fourth state provides an additional knob that can be used to address issues with HARC etching that were not previously possible using three-state pulsing.

[0030] Various embodiments described herein may be implemented in a plasma processing system. Referring to Figure 1, an exemplary plasma processing system or apparatus may include a chamber 101 having a gas injector / showerhead / nozzle 103 for delivering gases (105, 107, 109) (e.g., reactant gases and purge gases) or other chemicals to the chamber 101, chamber walls 111, and a chuck 113 for holding a substrate or wafer 115 to be processed, which may include an electrostatic electrode for chucking and dechucking the wafer. The chuck 113 is heated for thermal control, allowing the substrate 115 to be heated to a desired temperature.

[0031] In some embodiments, the chuck 113 defines (or includes) a lower electrode of the plasma processing system. In some embodiments, a source radio frequency (RF) signal generator 119 is configured to supply high frequency source RF power to the lower electrode to generate a plasma in a plasma processing region 125 above the substrate 115. In some embodiments, a bias RF signal generator 117 is configured to supply low frequency bias RF power to the lower electrode according to embodiments of the present disclosure.

[0032] In some embodiments, the showerhead 103 defines an upper electrode of the plasma processing system. In some embodiments, source RF power or bias RF power is applied to the upper electrode. In certain embodiments, source RF power is applied to the upper electrode and bias RF power is applied to the lower electrode.

[0033] In some implementations, the chamber walls are heated to support thermal management and efficiency. A vacuum source 127 provides vacuum and exhausts gases from the chamber 101 through an exhaust port. The system or apparatus may include a system controller 129 for controlling some or all of the operation of the chamber or apparatus, such as adjusting the chamber pressure, inert gas flow, plasma source power, plasma source frequency, reactive gas flow, bias power, bias frequency, temperature, vacuum settings, and other process conditions.

[0034] In some embodiments, the system / apparatus may include multiple chambers for processing substrates.

[0035] In some embodiments, the substrate is a semiconductor wafer that has undergone a fabrication procedure. However, it should be understood that in various embodiments, the wafer can be essentially any type of substrate that is subjected to a plasma-based fabrication process. For example, in some embodiments, the wafer can be a substrate formed of silicon, sapphire, GaN, GaAs, or SiC, or other substrate materials, and may include glass panels / substrates, metal foils, metal sheets, polymeric materials, and the like. Also, in various embodiments, the wafer may vary in form, shape, and / or size. For example, in some embodiments, the wafer may correspond to a circular shaped semiconductor wafer on which integrated circuit devices are fabricated. In various embodiments, the circular shaped wafer may have a diameter of 200 mm (millimeters), 300 mm, 450 mm, or another size. Also, in some embodiments, the wafer may correspond to a non-circular substrate, such as a rectangular substrate for a flat panel display, among other shapes.

[0036] In some implementations, a chuck of a plasma processing system includes an electrode positioned on the facility plate and disposed below the upper ceramic layer. The electrode can include an arrangement of temperature control fluid channels through which a temperature control fluid flows to control the temperature of the electrode and therefore the temperature of the wafer. The chuck can include an arrangement of backside gas supply ports (not shown) that are fluidly connected to corresponding backside gas supply channels in the electrode. Lift pins extend through a top surface of the chuck and can be configured to move the wafer vertically relative to the top surface of the chuck.

[0037] The impedance matching system includes an arrangement of inductors and capacitors sized and connected to provide an impedance match so that radio frequency power can be delivered to the plasma processing region 125. In some embodiments, the source RF signal generator 119 is a high frequency radio frequency signal generator and the bias RF signal generator 117 is a low frequency radio frequency signal generator. In some embodiments, the source RF signal generator generates a radio frequency signal in a range of about 50 megahertz (MHz) to about 70 MHz, or in a range of about 54 MHz to about 63 MHz, or about 60 MHz. In some embodiments, the source RF signal generator provides radio frequency power in a range of about 5 kilowatts (kW) to about 25 kW, or in a range of about 10 kW to about 20 kW, or in a range of about 15 kW to about 20 kW, or about 10 kW, or about 16 kW. In some embodiments, the bias RF signal generator 117 generates a radio frequency signal in a range of about 50 kilohertz (kHz) to about 500 kHz, or in a range of about 330 kHz to about 440 kHz, or about 400 kHz. In some embodiments, the bias RF signal generator provides a radio frequency power in a range of about 15 kW to about 100 kW. In an exemplary embodiment, the source RF signal generator 119 is configured to generate a radio frequency signal having a frequency of about 60 MHz and the bias RF signal generator 117 is configured to generate a radio frequency signal having a frequency of about 400 kHz.

[0038] During plasma processing operations in the plasma processing system, one or more process gases are supplied to the plasma processing region 125 via a process gas delivery system. Also, a radio frequency signal is transmitted through a radio frequency signal generator, an impedance match system, a facility plate, an electrode, and through the ceramic layer to the plasma processing region. The radio frequency signal converts the process gases into a plasma in the plasma processing region 125. The ions and / or reactive components of the plasma interact with one or more materials on the wafer W, causing changes in the composition and / or shape of certain materials present on the wafer W.

[0039] 2 conceptually illustrates a cross-section of a portion of a wafer for etching according to an embodiment of the present disclosure. In the illustrated embodiment, a surface section of a wafer containing a typical DRAM capacitor stack structure with high aspect ratio contact holes / vias etched therein is conceptualized.

[0040] As shown, the stack consists of a top silicon, doped silicon mask or carbon mask layer 250, a first silicon nitride (SiN) layer 252, a first (middle) silicon oxide (SiO) layer 254, a second (thin) SiN layer 256, a second (bottom) SiO layer 258, a third (thin) SiN layer 260, and a tungsten (W) etch stop layer 262. For a typical DRAM device, the stack may be on the order of about 1-1.5 microns in height, and the fabrication of such DRAM devices includes the fabrication of capacitors, which involves a capacitor etch process in which high aspect ratio contact vias are etched into the stack. The capacitor etch is one example of a dielectric etch process that requires the proper etching of very high aspect ratio features. By way of non-limiting example, in some implementations, the high aspect ratio features are features having height-to-width ratios of about 60, 70, 80, 90, or 100 to 1 or more.

[0041] It will be appreciated that as pitch sizes continue to scale to smaller sizes and aspect ratios of etched features continue to increase, the tolerance to defects in the etch process decreases. For capacitor etching, by way of non-limiting example, pitch sizes can be less than 50 nm in some implementations, less than 40 nm in some implementations, etc. Although embodiments of the present disclosure are described with reference to HARC etching to form DRAM capacitor structures, it will be appreciated that this is only one example of a feature scenario requiring a very high aspect ratio dielectric etch. It will be appreciated that the principles of the present disclosure can be applied to any high aspect ratio dielectric etch (e.g., 3D NAND, e.g., memory hole etch) in any applicable device scenario.

[0042] RF pulsing technology has progressed from operating in continuous wave mode (CW) to pulsing mode regimes (e.g., on-off, level-level). The current state-of-the-art RF pulsing regime operates using a three-state pulsing method. Advances in multi-state RF pulsing have enabled improvements for high aspect ratio etching by improving process margin vs. etch selectivity, profile bow, critical dimension (CD), and etch rate uniformity. However, as device sizes continue to shrink and pitch sizes are further reduced (e.g., to 50 nm and below), it is difficult to achieve further improvements in the etch selectivity vs. process margin tradeoff, even under the current state-of-the-art three-state RF pulsing technology. Current technology regimes struggle to balance the robustness of high aspect ratio etching while maintaining sufficient process margins (e.g., under-etching, non-opening, capping).

[0043] RF pulsing involves the implementation of pulsed power levels for a high frequency RF signal (also known as source power, e.g., at a frequency of about 60 MHz in some implementations) and a low frequency RF signal (also known as bias power, e.g., at a frequency of about 400 kHz in some implementations). For example, in a two-state RF pulsing regime, "State 1" (or "S1") is typically a high bias power and high source power state, e.g., above 1 kW, with ion energy above 3 keV, and operated at a pressure below 30 mTorr to obtain a narrow ion energy distribution function (IADF). The other state in the pulse, typically referred to as "State 0" (or "S0"), represents a deposition step with low / zero bias and low / zero source power, e.g., below 1 kW, with ion energy below 100 eV. State 0 primarily provides passivation due to different mechanisms such as direct ion deposition and ion activated neutral deposition. Typical pulse repetition rates for operating such an RF pulsing regime are about 100 Hz to 2 kHz.

[0044] A three-state pulsing scheme includes the two states mentioned above, where state 1 is typically a high peak power that promotes high aspect ratio etching with high selectivity, and state 2 is typically set to "0" to perform neutral deposition on the mask to improve selectivity. In contrast to these, state 3 can be selected to be a regime that provides passivation to mitigate bowing, or a different regime that improves non-open margin. Thus, in a three-state pulsing regime, there will typically be a trade-off involving bowing control vs. selectivity vs. non-open margin. Thus, although the addition of a third state provides advantages over two-state RF pulsing, beyond a certain point, these trade-offs make it impossible to further improve the three-state pulsing scheme.

[0045] However, it has been discovered that certain applications of the fourth state provide desirable flexibility to manage tradeoffs between warpage control, selectivity, and non-open margin. For example, the fourth state can be selected such that non-open margin is enhanced without affecting warpage or selectivity. Several power regimes have been identified that can address specific issues with HARC etching (i.e., warpage, selectivity, non-open margin). More specifically, the fourth state in combination with a particular third state has been found to address issues with HARC etching that were not previously possible with three-state pulsing.

[0046] 3 is a graph conceptually illustrating various power regimes for a four-state RF pulsing regime for high aspect ratio dielectric etching according to an embodiment of the present disclosure. In the graph shown, the power of the high frequency RF signal versus the power of the low frequency RF signal is plotted, and power regimes for separate pulsed RF states are shown for the four-state RF pulsing scheme. These power regimes define ranges for the power levels of the high frequency RF signal and the low frequency RF signal for the various pulsed RF states, and further define the relationship or ratio of the power levels of the high frequency RF signal and the low frequency RF signal for the various states.

[0047] In some embodiments, state 1 (S1) is configured with a power regime 300 as conceptually shown in the illustrated graph. State 1 is a high power state configured to provide high aspect ratio etching, where both the high frequency source RF signal and the low frequency bias RF signal are operated (pulsed) at a high power level compared to other states. In some embodiments, the S1 bias (low frequency RF) power level is configured to be in the range of more than 20 kW, and in some embodiments, in the range of about 30-40 kW. In some embodiments, the S1 source (high frequency RF) power level is configured to be in the range of more than 7 kW, and in some embodiments, in the range of about 8-10 kW, and in some embodiments, about 9 kW. In some embodiments, the ratio of bias power level to source power level (for S1) is in the range of about 3:1-4:1. In some embodiments, the S1 duty cycle is in the range of about 3-30 percent (of the total pulsed RF cycle), and in some embodiments, in the range of about 7-9 percent.

[0048] Generally, S1 defines the highest power level for the bias and source RF signals compared to other states of the pulsed RF cycle. S1 provides a high aspect ratio etch with high selectivity to the mask when run at a low duty cycle as currently described. However, while S1 can provide good selectivity, the tradeoff for S1 is that open margins and etch profile (e.g., SiN bow) can be adversely affected.

[0049] In some embodiments, state 2 (S2) is configured with power regime 302. As shown, S2 is a low power state compared to the other states, with both the source RF signal and the bias RF signal operating at relatively low power levels compared to S1. In some embodiments, the S2 bias (low frequency RF) power level is configured to be in the range of about 0.5 kW to 5 kW, and in some embodiments, in the range of about 1 kW to 3 kW. In some embodiments, the S2 source (high frequency RF) power level is configured to be in the range of about 2 kW to 7 kW, and in some embodiments, in the range of about 3 to 5 kW.

[0050] In some embodiments, the S2 bias power level is configured to be within a range of about 1-20 percent of the S1 bias power level, in some embodiments within a range of about 4-9 percent, and in some embodiments within a range of about 5-7 percent. In some embodiments, the S2 source power level is configured to be within a range of about 20-70 percent of the S1 source power level, in some embodiments within a range of about 25-55 percent, and in some embodiments within a range of about 30-40 percent.

[0051] Unlike S1, S2 is configured such that the bias power level is lower than the source power level, in some embodiments the ratio of the bias power level to the source power level (for S2) is in the range of about 1:1 to 1:2, and in some embodiments the ratio is less than about 0.8.

[0052] In some embodiments, the S2 duty cycle is in the range of about 3 to 30 percent of the total cycle, in some embodiments, in the range of about 10 to 20 percent, and in some embodiments, about 15 percent.

[0053] As a non-limiting example, in some embodiments, for an S2 bias power level of about 3 kW, the S2 source power level is about 5 kW, and for an S2 bias power level of about 1.5 kW, the S2 source power level is about 2.5 kW.

[0054] In some embodiments, the State 2 pulsing configuration provides neck trimming, thereby improving open margins, but the tradeoff for S2 is reduced selectivity to the mask.

[0055] In some embodiments, State 3 (S3) is configured to operate in a power regime 304 as conceptually illustrated in the illustrated graph. State 3 is configured as an intermediate power state, with both the high frequency source RF signal and the low frequency bias RF signal operating at intermediate power levels approximately between State 1 and State 2. In some embodiments, the S3 bias (low frequency RF) power level is configured to be in the range of about 10-24 kW, in some embodiments in the range of about 14-20 kW, and in some embodiments in the range of about 16-18 kW. In some embodiments, the S3 source (high frequency RF) power level is configured to be in the range of about 3-7 kW, in some embodiments in the range of about 4-6 kW, and in some embodiments in the range of about 5 kW.

[0056] Typically, the S3 bias and source power levels are between the levels of S1 and S2. In some embodiments, the S3 bias power level is within the range of about 30-70 percent, in some embodiments, about 40-60 percent, and in some embodiments, about 50 percent of the S1 bias power level. In some embodiments, the S3 source power level is within the range of about 30-80 percent, in some embodiments, about 40-70 percent, and in some embodiments, about 50-60 percent of the S1 source power level.

[0057] In some embodiments, the ratio of bias power level to source power level (for S3) is in the range of about 1.3:1 to 3:1. Thus, as a non-limiting example, for a bias power level of 12 kW, the source power level may be about 7 kW in some embodiments. Or for a bias power level of 14 kW, the bias power level may be about 9 kW in some embodiments. These are provided as examples and not as limitations, as other power levels within the ratio are possible for S3. In some embodiments, the ratio of bias power level to source power level for S3 is similar to that of S1, but S3 is configured at a lower power level compared to S1.

[0058] In some embodiments, the S3 duty cycle is in the range of about 3 to 30 percent of the total RF pulsing cycle, in some embodiments in the range of about 15 to 25 percent, and in some embodiments, about 20 percent.

[0059] In some implementations, S3 is configured as a medium power etch state and is configured to provide very good selectivity and reasonably good oxide and nitride profiles in a relative sense, but the tradeoff with S3 is open margin due to necking issues. Compared to S1, S3 can be configured to provide similar selectivity but improved etch profiles with reduced SiN bow and reduced oxide bow.

[0060] In some embodiments, State 4 (S4) operates as a substantially zero power state or a very low power state, with each of the high frequency RF signal and the low frequency RF signal being set to a substantially zero power level, or near zero, or a power level substantially lower than S2. In some embodiments, the S4 bias power is in the range of about 0-1 kW, while in some embodiments, the S4 source power is in the range of about 0-1 kW. In some embodiments, State 4 is referred to as State 0 (S0), which, as described above, provides neutral deposition on the mask, thereby improving selectivity. In some embodiments, the S4 duty cycle is in the range of about 35-75 percent of the total pulsed RF cycle, in some embodiments in the range of about 45-65 percent, and in some embodiments in the range of about 50-60 percent.

[0061] In some embodiments, S4 is configured to perform neutral deposition.

[0062] Having described states S1, S2, S3, and S4 of the four-state RF pulsing scheme, a representative pulsed waveform will now be described for illustrative purposes.

[0063] 4 conceptually illustrates a graph of RF power versus time for a four-state pulsed RF waveform, in accordance with an embodiment of the present disclosure. For purposes of illustrating an example of a four-state pulsed RF waveform, two complete cycles are shown.

[0064] As shown in the illustrated embodiment, S1 is configured in a high peak power state, such that the low frequency (bias) RF signal and the high frequency (source) RF signal have the highest power levels of the pulsed RF cycle (are pulsed at the highest power levels). In the illustrated embodiment, the ratio of power levels of the bias RF signal to the source RF signal is approximately 2:1. However, as noted above, this ratio can vary and is in different embodiments. The duty cycle of S1 is short, e.g., approximately 3-10 percent of the total RF pulsing cycle period.

[0065] S2 follows S1 in the RF pulsing cycle and is a low power state in which the bias and source signals have a relatively low power level (are pulsed at a relatively low power level). In some embodiments, the power level of the bias and / or source signals during S3 is the lowest in the cycle except for S4. In some embodiments, the ratio of bias power to source power is less than 1. In different embodiments, various power ratios are possible for S2, as indicated above. The duty cycle of S2 can be similar to that of S1 as shown in the illustrated embodiment, but can also be greater than that of S1 as previously described.

[0066] S3 follows S2 in the pulsing cycle and is configured as an intermediate power state; that is, the power levels of the bias signal and the source signal are less than the power levels of S1 but greater than the power levels of S2. In the illustrated embodiment, the ratio of the power levels of the bias signal to the source signal for S3 is approximately 3:2. The ratio of the power levels of the bias signal to the source signal for S3 may be similar to the power levels of S1 in some embodiments, while in other embodiments other ratios are possible for S3, as previously discussed. In general, the duty cycle of S3 is greater than S1 in some embodiments.

[0067] S4 follows S3 in the pulsing cycle and is configured as a zero power state, where the power levels of the bias and source signals are zero or substantially zero. That is, during S4, no RF power is actively applied by the RF signal generator to the bias and source signals. S4 has the longest duty cycle of the various states. In some implementations, the duty cycle of S4 is greater than half the total period of the pulsed RF cycle or greater than the total duty cycle of the other states.

[0068] In the illustrated embodiment, the states are repeatedly cycled in the order S1→S2→S3→S4, however, in some embodiments, the states are repeatedly cycled in other orders, such as S1→S2→S4→S3, or S1→S4→S2→S3.

[0069] The implementation of the four-state RF pulsing scheme described in this disclosure provides improved results over the three-state RF pulsing used in current state-of-the-art HARC etching. With a three-state pulsed RF waveform, states S1 and S0 exist, but the third state is selected from either S2 or a similar regime to S3, with the associated trade-offs remaining unmitigated. And, furthermore, selecting a power level between S2 and S3 does not provide the improved results of the four-state RF pulsing scheme disclosed herein.

[0070] FIG. 5 conceptually illustrates the improved results possible with a four-state RF pulsing configuration, in accordance with an embodiment of the present disclosure.

[0071] In the illustrated graph, mask thickness (e.g., R polysilicon (nm)) versus bottom to top critical dimension ratio (B / T ratio) is shown for various RF pulsing regimes. Mask thickness indicates the selectivity of the etch process, and B / T ratio indicates the etched profile (e.g., the amount of tapering or aspect ratio dependent etching (ARDE)). The B / T ratio is generally less than 1 due to tapering and ARDE, and improvements bring the B / T ratio closer to 1. Typically, the tradeoff for the B / T ratio is mask thickness. That is, to open the bottom so that the bottom CD approaches the top CD, the etch process typically must sacrifice mask thickness. However, by utilizing four-state RF pulsing according to embodiments of the present disclosure, improvements in the B / T ratio and mask thickness can be achieved simultaneously.

[0072] As shown, RF pulsing between levels minimizes the amount of mask thickness remaining and minimizes the B / T ratio. Tri-state RF pulsing, which increases the mask thickness and increases the B / T ratio, improves the results. However, while this represents an improvement to the selectivity and etch profile, beyond a certain point it is not possible to achieve further improvement in either selectivity or etch profile without a tradeoff with the other.

[0073] However, as shown in the illustrated graphs, four-state RF pulsing according to embodiments of the present disclosure allows for both selectivity and etch profile improvement, thereby overcoming the current trade-off limitations of three-state RF pulsing and expanding the capabilities of HARC etch processes. In some embodiments, this is accomplished by configuring states S1 and S3 of the four-state RF pulsing cycle to restore mask thickness, and configuring states S2 and S4 to passivate bow in the etched features. The ability of the four-state RF pulsing scheme described herein to simultaneously improve selectivity and etch profile allows for higher aspect ratio etching at smaller pitch sizes, resulting in higher device yields than previously possible.

[0074] It will be appreciated that any of the methods described in this disclosure can be implemented to be performed automatically by the control system 120. In some embodiments, a user interface associated with the control system is configured to allow a user to control various aspects of the etch process according to the above-described embodiments. By way of non-limiting example, these can include interface controls for setting the power levels and duty cycles of different states of the RF pulsing cycle. In some embodiments, if certain settings are user-defined, other settings can be automatically determined by the system based on the user-defined settings, and such automatically determined settings may or may not be further customized by the user. For example, in some embodiments, if the power level and duty cycle for S1 are user-defined, the power levels and duty cycles for S2 and S3 are automatically determined based on S1. In some embodiments, the power levels and duty cycles of S2 and S3 are determined as a function of the power level and duty cycle of S1. In some embodiments, such functions can be user-defined or customized through the user interface. In some embodiments, the user interface provides customization within predefined ranges that can be abstracted for ease of use. For example, the S3 power level may be adjusted along any scale (eg, 1 to 10) provided by the user interface, thereby adjusting the S3 power level in the range of 30 to 70 percent of the S1 power level.

[0075] 6 illustrates an exemplary schematic diagram of the control system 120 of FIG. 1 according to some embodiments. In some embodiments, the control system 120 is configured as a process controller for controlling a semiconductor fabrication process performed in the plasma processing system 100. In various embodiments, the control system 120 includes a processor 1401, a storage hardware unit (HU) 1403 (e.g., memory), an input HU 1405, an output HU 1407, an input / output (I / O) interface 1409, an I / O interface 1411, a network interface controller (NIC) 1413, and a data communication bus 1415. The processor 1401, the storage HU 1403, the input HU 1405, the output HU 1407, the I / O interface 1409, the I / O interface 1411, and the NIC 1413 are in data communication with each other via the data communication bus 1415. The input HU 1405 is configured to receive data communication from a number of external devices. Examples of the input HU 1405 include a data acquisition system, a data acquisition card, and the like. The output HU 1407 is configured to transmit data to a number of external devices. An example of the output HU 1407 is a device controller. Examples of the NIC 1413 include a network interface card, a network adapter, and the like. Each of the I / O interfaces 1409 and 1411 is defined to provide compatibility between different hardware units coupled to the I / O interface. For example, the I / O interface 1409 can be defined to convert signals received from the input HU 1405 to a format, amplitude, and / or speed compatible with the data communication bus 1415. Also, the I / O interface 1407 can be defined to convert signals received from the data communication bus 1415 to a format, amplitude, and / or speed compatible with the output HU 1407.Although various operations are described herein as being performed by processor 1401 of control system 120, it should be understood that in some embodiments, various operations may be performed by multiple processors of control system 120 and / or by multiple processors of multiple computing systems in data communication with control system 120.

[0076] In some embodiments, the control system 120 is used to control devices in various wafer fabrication systems based in part on the sensed values. For example, the control system 120 can control one or more of the valves 1417, the filter heater 1419, the wafer support structure heater 1421, the pump 1423, and other devices 1425 based on the sensed values ​​and other control parameters. The valves 1417 can include valves associated with controlling the backside gas supply system 129, the process gas supply system 191, and the temperature control fluid circulation system 125. The control system 120 receives sensed values, for example, from a pressure gauge 1427, a flow meter 1429, a temperature sensor 1431, and / or other sensors 1433, such as voltage sensors, current sensors, and the like. The control system 120 can also be used to control process conditions in the plasma processing system 100 during performance of plasma processing operations on the wafer W. For example, the control system 120 can control the type and amount of process gas supplied from the process gas supply system 191 to the plasma processing region 182. The control system 120 may also control the operation of the radio frequency signal generator, impedance matching system 143. The control system 120 may also control the operation of the DC power supply 117 for the clamp electrodes. The control system 120 may also control the operation of the lifting device for the lift pins and the operation of the chamber door. The control system 120 also controls the operation of the backside gas supply system and the temperature control fluid circulation system. It should be understood that the control system 120 may be provided for programmatic and / or manual control of any function within the plasma processing system 100.

[0077] In some embodiments, the control system 120 is configured to execute a computer program that includes a set of instructions for controlling process timing, process gas delivery system temperature and pressure differentials, valve positions, process gas mixture, process gas flow rates, backside cooling gas flow rates, chamber pressure, chamber temperature, wafer support structure temperature (wafer temperature), RF power levels, RF frequency, RF pulsing, impedance matching system settings, cantilever arm assembly position, bias power, and other parameters of a particular process. Other computer programs stored in a memory device associated with the control system 120 may be used in some embodiments. In some embodiments, there is a user interface associated with the control system 120. The user interface includes a display 1435 (e.g., a display screen and / or a graphical software display of equipment and / or process conditions) and a user input device 1437, such as a pointing device, keyboard, touch screen, microphone, etc.

[0078] Software for directing the operation of the control system 120 can be designed or configured in many different ways. Computer programs for directing the operation of the control system 120 to perform various wafer fabrication processes in a process sequence can be written in any conventional computer-readable programming language (e.g., assembly language, C, C++, Pascal, Fortran, etc.). The compiled object code or script is executed by the processor 1401 to perform the tasks identified in the program. The control system 120 can be programmed to control various process control parameters related to process conditions such as, for example, filter pressure differential, process gas composition and flow rate, backside cooling gas composition and flow rate, temperature, pressure, plasma conditions such as RF power levels and RF frequency, bias voltage, cooling gas / fluid pressure, and chamber wall temperature. Examples of sensors that can be monitored during the wafer fabrication process include, but are not limited to, mass flow control modules, pressure sensors such as pressure gauge 1427 and temperature sensor 1431. Appropriately programmed feedback and control algorithms can be used with data from these sensors to control / adjust one or more process control parameters to maintain desired process conditions.

[0079] In some implementations, the control system 120 is part of a broader fabrication control system. Such fabrication control systems may include semiconductor processing equipment, including processing tools, chambers, and / or platforms for wafer processing, and / or specific processing components such as wafer pedestals, gas flow systems, etc. These fabrication control systems may be integrated with electronics for controlling system operations before, during, and after wafer processing. The control system 120 may control various components or sub-components of the fabrication control system. The control system 120 may be programmed to control any of the processes disclosed herein depending on the wafer processing requirements. Such processes may include delivery of process gases, delivery of backside cooling gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, wafer loading and unloading from tools and other transfer tools connected or interlocked with the particular system, and / or wafer loading and unloading from load locks.

[0080] Broadly, the control system 120 may be defined as electronic equipment having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable wafer processing operations, enable end point measurements, etc. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, i.e., microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions communicated to the control system 120 in the form of various individual settings (or program files) that define operational parameters for performing a particular process on a wafer W in the system 100. The operational parameters may, in some embodiments, be part of a recipe defined by a process engineer to accomplish one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or one or more processing steps in the fabrication of a wafer die.

[0081] The control system 120 may be part of, coupled to, or a combination of a computer that is integrated or coupled with the plasma processing system 100 or otherwise networked to the system 100 in some implementations. For example, the control system 120 may be in the "cloud" or all or part of a fab host computer system. This allows for remote access of wafer processing. The computer may allow remote access to the system 100 to monitor the current progress of a fabrication operation, review the history of past fabrication operations, review trends or performance criteria from multiple fabrication operations, modify parameters of a current process, set up processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system 100 over a network. Such a network may include a local network or the Internet.

[0082] The remote computer may include a user interface that allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system 100. In some examples, the control system 120 receives instructions in the form of data. Such data identifies parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process performed within the plasma processing system 100. Thus, as described above, the control system 120 may be distributed, for example, by comprising one or more individual controllers that are networked together and cooperate toward a common purpose (such as the processes and controls described herein). An example of a distributed controller for such purposes would include one or more integrated circuits on the plasma processing system 100 that communicate with one or more integrated circuits that are remotely located (e.g., at the platform level or as part of a remote computer) and coupled to control the processes performed on the plasma processing system 100.

[0083] Exemplary systems with which control system 120 may interface include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a tracking chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers. As noted above, depending on one or more process steps performed by the tool, control system 120 may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used for material transport to and from tool locations and / or load ports within a semiconductor manufacturing factory.

[0084] The embodiments described herein may also be implemented in conjunction with a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like. The embodiments described herein may also be implemented in conjunction with distributed computing environments in which tasks are performed by remote processing hardware units linked over a network. It should be understood that the embodiments described herein, particularly those relating to the control system 120, may employ various computer-implemented operations involving data stored in computer systems. These operations are operations requiring physical manipulation of physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations. The embodiments also relate to hardware units or apparatus for performing these operations. An apparatus may be specially constructed for a special-purpose computer. When defined as a special-purpose computer, the computer may also perform other processes, program executions, or routines that are operable for its dedicated purpose, but that are not part of its dedicated purpose. In some embodiments, the operations may be processed by a general-purpose computer selectively activated or configured by one or more computer programs stored in the computer memory, cache, or retrieved over a network. If the data is obtained over a network, the data may be processed by other computers on the network (eg, a cloud of computing resources).

[0085] Various embodiments described herein can be implemented through process control instructions instantiated as computer readable code on a non-transitory computer readable medium. A non-transitory computer readable medium is any data storage hardware unit that can store data, which is then read by a computer system. Examples of non-transitory computer readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disc ROM (CD-ROM), CD recordable (CD-R), CD rewriteable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. A non-transitory computer readable medium can include computer readable tangible media distributed over a network-coupled computer system such that computer readable code is stored and executed in a distributed manner.

[0086] Although the foregoing disclosure includes some details for clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. For example, it should be understood that one or more features of any embodiment disclosed herein can be combined with one or more features of any other embodiment disclosed herein. Thus, the present embodiments should be considered as illustrative rather than restrictive, and the claims should not be limited to the details set forth herein, but may be modified within the scope and equivalents of the described embodiments.

Claims

1. A method for performing an etching process on a substrate in a plasma processing system, applying a bias signal to an electrode of the plasma processing system, applying a source signal to the electrode, comprising: The bias signal and the source signal are pulsed RF signals that together define a repeated pulsed RF cycle, and each pulsed RF cycle sequentially includes a first state, a second state, a third state, and a fourth state, The first state is defined by the bias signal pulsed at a first bias power level and the source signal pulsed at a first source power level, The second state is defined by the bias signal pulsed at a second bias power level and the source signal pulsed at a second source power level, The third state is defined by the bias signal pulsed at a third bias power level and the source signal pulsed at a third source power level, The fourth state is defined by the bias signal pulsed at a fourth bias power level and the source signal pulsed at a fourth source power level, The first bias power level is greater than the third bias power level, the third bias power level is greater than the second bias power level, and the second bias power level is greater than the fourth bias power level, The first source power level is greater than the third source power level, the third source power level is greater than the second source power level, and the second source power level is greater than the fourth source power level, A method.

2. The method according to claim 1, wherein the second bias power level is lower than the second source power level. A method.

3. The method according to claim 1, wherein the second bias power level is about 1 to 20 percent of the first bias power level, and the second source power level is about 20 to 70 percent of the first source power level. Method. **Claim 4** The method according to claim 1, wherein the third bias power level is about 30 to 70 percent of the first bias power level, and the third source power level is about 30 to 80 percent of the first source power level. Method. **Claim 5** The method according to claim 1, wherein the fourth bias power level is a substantially zero power level, and the fourth source power level is a substantially zero power level. Method. **Claim 6** The method according to claim 1, wherein the duty cycle of the first state is about 3 to 30 percent of the period of the pulsed RF cycle. Method. **Claim 7** The method according to claim 1, wherein the duty cycle of the second state is about 3 to 30 percent of the period of the pulsed RF cycle. Method. **Claim 8** The method according to claim 1, wherein the duty cycle of the third state is about 3 to 30 percent of the period of the pulsed RF cycle. Method. **Claim 9** The method according to claim 1, wherein the duty cycle of the fourth state is about 35 to 75 percent of the period of the pulsed RF cycle. Method. **Claim 10** The method according to claim 1, wherein The method, wherein the first state and the third state are configured to etch features on the surface of the substrate. **Claim 11** The method according to claim 10, wherein the second state and the fourth state are configured to passivate the features on the surface of the substrate. **Claim 12** The method according to claim 1, wherein the bias signal has a frequency of less than about 10 MHz and the source signal has a frequency of greater than about 20 MHz. **Claim 13** A controller device configured to cause an etching process to be performed on a substrate in a plasma processing system, the etching process comprising: applying a bias signal to an electrode of the plasma processing system; applying a source signal to the electrode; wherein the bias signal and the source signal are pulsed RF signals that together define a repeated pulsed RF cycle, and each pulsed RF cycle sequentially includes a first state, a second state, a third state, and a fourth state; the first state being defined by the bias signal pulsed at a first bias power level and the source signal pulsed at a first source power level; the second state being defined by the bias signal pulsed at a second bias power level and the source signal pulsed at a second source power level; the third state being defined by the bias signal pulsed at a third bias power level and the source signal pulsed at a third source power level; the fourth state being defined by the bias signal pulsed at a fourth bias power level and the source signal pulsed at a fourth source power level. The first bias power level is greater than the third bias power level, the third bias power level is greater than the second bias power level, the second bias power level is greater than the fourth bias power level, The first source power level is greater than the third source power level, the third source power level is greater than the second source power level, and the second source power level is greater than the fourth source power level. Controller device.

14. The controller device according to claim 13, wherein the second bias power level is lower than the second source power level. Controller device.

15. The controller device according to claim 13, wherein the second bias power level is about 1 to 20 percent of the first bias power level, and the second source power level is about 20 to 70 percent of the first source power level. Controller device.

16. The controller device according to claim 13, wherein the third bias power level is about 30 to 70 percent of the first bias power level, and the third source power level is about 30 to 80 percent of the first source power level. Controller device.

17. The controller device according to claim 13, wherein the fourth bias power level is a substantially zero power level, and the fourth source power level is a substantially zero power level. Controller device.

18. The controller device according to claim 13, The duty cycle of the first state is about 3 to 10 percent of the period of the pulsed RF cycle, the controller device.

19. The controller device according to claim 13, The duty cycle of the second state is about 6 to 25 percent of the period of the pulsed RF cycle, the controller device.

20. The controller device according to claim 13, The duty cycle of the third state is about 10 to 30 percent of the period of the pulsed RF cycle, the controller device.

21. The controller device according to claim 13, The duty cycle of the fourth state is about 35 to 75 percent of the period of the pulsed RF cycle, the controller device.

22. The controller device according to claim 13, The first state and the third state are configured to perform etching of features on the surface of the substrate, the controller device.

23. The controller device according to claim 22, The second state and the fourth state are configured to passivate the features on the surface of the substrate, the controller device.

24. The controller device according to claim 13, The bias signal has a frequency of less than about 10 MHz, and the source signal has a frequency of greater than about 20 MHz, the controller device.

25. A method for performing an etching process on a substrate in a plasma processing system, Applying a bias signal to a first electrode of the plasma processing system, Applying a source signal to a second electrode of the plasma processing system comprising wherein the bias signal and the source signal are pulsed RF signals that together define a repeated pulsed RF cycle, and each pulsed RF cycle sequentially includes a first state, a second state, a third state, and a fourth state wherein the first state is defined by the bias signal pulsed at a first bias power level and the source signal pulsed at a first source power level wherein the second state is defined by the bias signal pulsed at a second bias power level and the source signal pulsed at a second source power level wherein the third state is defined by the bias signal pulsed at a third bias power level and the source signal pulsed at a third source power level wherein the fourth state is defined by the bias signal pulsed at a fourth bias power level and the source signal pulsed at a fourth source power level wherein the first bias power level is greater than the third bias power level, the third bias power level is greater than the second bias power level, and the second bias power level is greater than the fourth bias power level wherein the first source power level is greater than the third source power level, the third source power level is greater than the second source power level, and the second source power level is greater than the fourth source power level Method

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