Metastability correction for ring oscillators with embedded time-to-digital converters

Abstract

The system (100) includes a ring oscillator (108) including an odd number of inverters arranged in a ring. The system (100) also includes a time-to-digital converter (113) including an odd number of flops, each of the flops coupled to an output of a different inverter. The system (100) includes a level shifter (112) coupled to the inverters and the flops. The system (100) also includes a Gray counter (117) coupled to at least one of the flops. The system (100) includes a decoder (128) coupled to the time-to-digital converter (113). The system (100) also includes a phase frequency detector (102) coupled to the decoder (128).

Description

[Technical field]

[0001] A phase-locked loop (PLL) is a system that compares the frequency of a local oscillator with the frequency of a received input signal and uses a feedback loop to lock the frequency of the local oscillator to the frequency of the received input signal. The output frequency of the local oscillator may be a multiple of the input frequency. In a PLL, the phase of the output signal is related to the phase of the input signal. The local oscillator generates a periodic signal and a phase detector compares the phase of the periodic signal with the phase of the input signal. The phase detector then adjusts the oscillator to keep the phase aligned. Phase can be measured using a time-to-digital converter (TDC). A TDC uses a series of delay elements (such as buffers or inverters) and a series of flops that sample the delay elements at certain times. A signal propagates through the delay elements and the samples collected by the flops generate a digital code that represents the phase information of the output signal. Summary of the Invention

[0002] In at least one example, a system includes a phase-locked loop including a ring oscillator. The ring oscillator includes an odd number of inverters arranged in a ring and a set of flops, each flop of the set of flops coupled to an output of a different one of the inverters. The system also includes a decoder configured to receive a code from the set of flops, the code representing a phase of the ring oscillator. In response to the code being invalid, the decoder is configured to decode the invalid code into a valid code. The decoder is also configured to provide the valid code to a phase frequency detector.

[0003] In at least one example, a method includes receiving a reference signal at a set of flops. The method includes capturing outputs of different stages of a multi-stage ring oscillator with each of the set of flops in response to receiving the reference signal. The method also includes providing a code to a decoder, the code based at least in part on the outputs of the stages. The method includes decoding the invalid code into a valid code in response to the code being invalid. The method also includes providing the valid code to a phase frequency detector.

[0004] In at least one example, a system includes a ring oscillator including an odd number of inverters arranged in a ring. The system also includes a time-to-digital converter including an odd number of flops, each of the flops coupled to an output of a different inverter. The system includes a level shifter coupled to the inverters and the flops. The system also includes a Gray counter coupled to at least one of the flops. The system includes a decoder coupled to the time-to-digital converter. The system also includes a phase frequency detector coupled to the decoder. [Brief description of the drawings]

[0005] [Figure 1] In some examples, a system includes a digital PLL with a ring oscillator and an embedded TDC.

[0006] [Diagram 2] FIG. 1 is a timing diagram for a TDC in some examples.

[0007] [Figure 3A] 1 is a circuit diagram of an embedded TDC in some examples.

[0008] [Figure 3B] 1 is a circuit diagram of a dynamic level shifter in accordance with some examples.

[0009] [Figure 4]FIG. 13 is a timing diagram of waveforms provided to a flop by a level shifter in some examples.

[0010] [Diagram 5] 1 is a table of valid codes and invalid codes for a seven-stage ring oscillator with embedded TDC in some examples.

[0011] [Figure 6] 1 is a flowchart of a method for metastability correction according to some examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] A digital PLL operates by using a reference signal F with a relatively stable frequency at its input. REF and having at its output a frequency that is a multiple of the reference signal, F OUT The digital PLL also locks the phase of the output signal with the input signal. To lock the phase of these two signals, the phase error between the two signals is measured. To measure the phase error, a TDC can be useful. A conventional TDC includes a set of inverters arranged in a chain. When an edge of a digital signal (e.g., a rising edge or a falling edge) occurs at the input of the first inverter, the edge propagates through the chain of inverters. Each inverter has a small finite delay between when it receives the edge at its input and when the output of the inverter changes. The output of the inverters in the chain can be sampled at a particular time using a flop. The sample collected by the flop indicates how far the edge has passed through the chain of inverters. For example, if a chain of seven inverters is sampled and the result of the sampling is 1110000, the edge has passed through the first three inverters but not the last four (indicated by three 1s followed by four 0s). These samples allow the edge to be sampled at a specific time, F, as measured by the number of inverter delays. REF and F OUTA digital code is produced which indicates the phase error between the input and output signals. The phase error is useful for phase locking the input and output signals.

[0013] The digital PLL may include a ring oscillator with an embedded TDC. The embedded TDC uses flops to capture phase information directly from the inverters that make up the ring oscillator. The embedded TDC is coupled to the output of each ring oscillator stage and uses the flops to sample data at the output at specific times in response to receiving a reference signal. The samples collected by the flops create a digital code as described above. The value of the digital code indicates the fractional phase information of the ring oscillator (e.g., 2 / 7, 3 / 7, 6 / 7, etc. for a TDC with seven inverters). The fractional phase information is then used to determine the phase error between the input and output signals. In an embedded TDC system, the reference signal that indicates when the inverters should be sampled may arrive near the time of a data transition for one or more flops. If data is sampled near the time of a data transition of the flops, a metastability problem may occur and an old value may be sampled instead of the new value that should have been sampled, or vice versa. Thus, the flops may collect an invalid digital code. Invalid codes can lead to poor jitter performance, slower lock times, and / or the inability of the PLL to stay locked. In some alternative solutions, additional circuitry can be used to mitigate the effects of invalid codes. However, these solutions increase complexity and power consumption. In other alternative solutions, invalid codes can be discarded. Discarding invalid codes can prevent the PLL from adjusting the ring oscillator for that cycle, which can impact jitter.

[0014] This description describes various examples of digital PLLs with embedded TDCs configured to decode invalid codes into the nearest valid codes. In one example, an N-stage ring oscillator with embedded TDC has N periodic TDC states. The rising and falling edges of the output signal of the inverter in the embedded TDC do not rise and fall instantaneously, so short circuit transition states may occur. These transition states are states where some, but not all, of the edge transitions have occurred. The transition states may be decoded and considered as valid codes. The transition states combined with the N periodic valid TDC states result in 2N valid codes, as described below. Codes generated other than the 2N valid codes are decoded into one of the 2N valid codes, rather than being discarded. In the examples herein, a 7-stage ring oscillator is described. However, in other examples, ring oscillators of other sizes may be used.

[0015] FIG. 1 is a system 100 including a digital PLL with a ring oscillator and an embedded TDC in some examples. In one example of the system 100, the components on the left side of FIG. 1 may be digital components, while the components on the right side of FIG. 1 may be analog components. The system 100 includes a phase frequency detector (PFD) 102, a digital filter 104, and a digital-to-analog converter (DAC) 106. The oscillator 108 is a component of an embedded TDC system 110. The embedded TDC system 110 includes the oscillator 108, a level shifter 112, and a TDC 113. The PFD 102 includes a first input 114, a second input 115, a third input 116, and an output 118. The output 118 provides a phase error 119. System 100 includes a Gray counter 117, a feedback loop 120, a link 122, an output 124, an output 126, a decoder 128, and an adder 130. Oscillator 108 provides an output 132, which may include 7 bits, shown in FIG. 1 as <6:0>. Level shifter 112 receives output 132 and provides outputs 134 and 136. Level shifter 112 generates a 7-bit output, labeled B<6:0> at output 134 to TDC 113 and outputs output bits B<6:0> at output 136. <0> The TDC 113 uses bits B<6:0> to generate the TDC_OUT<6:0> value. The Gray Counter 117 uses bits B<6:0> as described below. <0> is used to determine the integer phase information.

[0016] The embedded TDC system 110 receives an input signal at an input 138 of an oscillator 108 and outputs an output frequency signal F at an output 124. OUT The embedded TDC system 110 also generates a TDC_OUT value at output 126, which in some examples is provided to a decoder 128. Details of the embedded TDC system 110 are described below with respect to Figures 3A and 3B. In other examples, various components of the embedded TDC system 110 may be within the oscillator 108 or may be located outside of the oscillator 108.

[0017] In the system 100, a counter (such as the Gray counter 117) increments to represent integer phase information (e.g., INTEGER_COUNT<7:0>) on the feedback loop 120, while the TDC 113 provides fractional phase information. OUT Signal is F REF For example, if the system 100 receives an input signal F REF F, which is four times the frequency OUT When programmed to generate the F OUT If the system 100 is operating as programmed, the F REF Four F per cycle OUT The cycle is completed. The Gray counter 117 provides its information along the feedback loop 120 to the adder 130. The fractional phase information is F OUT F for a single cycle of the signal REF These two pieces of information are captured separately and merged by summer 130 to provide integer and fractional phase information to PFD 102 at third input 116, shown in FIG. 1 as feedback phase. For example, F OUT is the reference signal F at the first input 114. REF If programmed to be 12.5 times larger than F REF Every cycle, the outputs from Gray counter 117 and TDC 113 are added together (by adder 130) and incremented by 12.5 cycles. In this way, system 100 REF At frequencies higher than the output signal F OUT may be provided.

[0018] The system 100 is OUT The phase of F REF Lock with F OUT and F REF To lock the phase of F OUT and F REF The phase error of is measured first and then F OUTIn an alternative system, the phase error is measured with a TDC in the PFD 102. This TDC has a set of buffers or inverters arranged in a chain inside the PFD 102. After an edge of the reference signal occurs (e.g., a rising edge or a falling edge), the edge propagates through the chain of inverters as described above. Each inverter has a small finite delay. Then, when the feedback clock signal reaches the PFD 102, the reference signal propagating through the inverters is sampled using flops in the TDC, with one flop coupled to the output of each inverter. In this alternative system, the sample from the flops may be three 1's (111), followed by some 0's. This is because the reference signal has passed through only three of the inverters in the chain, rather than all of them. The three 1's indicate how much phase error there is between the reference signal and the feedback clock signal, in the amount of inverter delay.

[0019] The TDC in the PFD 102 as described above in the alternative system may require a lot of area and may consume a lot of power. The delays of the inverters in the alternative system also need to be calibrated to know how much time is consumed by each inverter delay. In the example herein, the oscillator 108 is a ring oscillator and includes a chain of inverters arranged in a ring. A ring oscillator includes an odd number N of inverters in a ring and has an output that oscillates between two values. The output of the last inverter is fed back to the first inverter. Adjusting the voltage or current provided to the inverters can change the delay through the inverters and therefore the frequency of the inverters. In this example, no calibration is required as in the alternative system described above.

[0020] The chain of inverters in the oscillator 108 may be used as an embedded TDC in some examples herein. The TDC is embedded in the oscillator 108 and is therefore referred to as an embedded TDC system 110. Here, the TDC 113 is shown as a separate component in FIG. 1 for clarity, but the TDC 113 is actually embedded in the oscillator 108. The data at the output of the inverters in the oscillator 108 may be sampled and used to determine the phase of the signal generated by the oscillator 108. Thus, a portion of the hardware of the oscillator 108 (e.g., the chain of inverters) may be reused for time-to-digital conversion (e.g., the TDC 113) to measure the phase error of the oscillator signal. This hardware reuse may reduce area requirements and power consumption in some examples.

[0021] In the present example, the TDC 113 generates a TDC_OUT signal at output 126 that includes a series of bits that indicate the phase of the signal generated by oscillator 108, as described above. The TDC_OUT signal at output 126 is provided to a decoder 128. If the decoder 128 determines that the TDC_OUT signal is a valid code, the decoder 128 provides the valid code at third input 116 to the PFD 102 via summer 130. The PFD 102 then determines the phase from the valid code and outputs it to the F on second input 115. REF The PFD 102 generates a phase error 119 and provides the phase error 119 to the digital filter 104. The phase error is received by the DAC 106 and then provided to the oscillator 108, which is adjusted in response to the phase error. The adjustments are made to the output signal F OUT The input signal F REF This is done to phase lock the

[0022] If the decoder 128 determines that the TDC_OUT signal is an invalid code, the invalid code is decoded to a valid code as described in the examples herein. The valid code is then provided by the decoder 128 to the PFD 102 via an adder 130, and the PFD 102 calculates the phase error 119 as described above based on the valid code. In some examples, the decoder 128 may be a component of the PFD 102 or may be in another component of the system 100. The decoder 128 is configured to decode the invalid code using any suitable decoding scheme or algorithm. The decoder 128 may be implemented in hardware, software, or a combination of the two. In one example, the decoder 128 decodes the code using a look-up table, as described below with respect to FIG. 5. In one example, a non-transitory computer readable medium is provided. The non-transitory computer readable medium includes any electronic medium or storage, except for signals. The non-transitory computer readable medium stores executable code. When executed by a processor or controller of an electronic device, the executable code performs the steps described herein to determine the validity of the code and decode the invalid code. In one example, some or all of the steps described below with respect to FIG. 6 are performed by a processor or controller executing the executable code. In other examples, additional processes described herein are performed by a processor or controller executing the executable code. In some examples, the processor or controller may be the decoder 128. In other examples, the processor or controller may be a separate entity from the decoder 128.

[0023] 2 is a timing diagram 200 for a TDC in some examples herein. FIG. 2 shows a timing diagram for an example system with a seven-stage ring oscillator operating at 240 MHz. Timing diagram 200 includes a waveform 202, a TDC, IN data 204, and setup 206. Waveform 202 is a reference frequency F that is provided to TDC 113 via link 122. REF F REFQ is a reference signal (e.g., rising) that goes high to indicate that the flops in the TDC 113 should capture the value at their respective inputs (e.g., 0 or 1). For example, a D flip-flop captures the value at its D input when it receives a certain specified edge (e.g., rising or falling) of the clock. After the rising / falling edge, the captured value is available at the Q output of the D flip-flop. However, the flop may have metastability issues. A flop has a setup time and a hold time during operation. In one example, the setup time is the minimum amount of time after the active edge of the clock that the data being sampled must be stable in order to be properly latched by the flop. Violating the setup time may result in incorrect data being captured by the flop, which is known as a setup violation. The hold time is the minimum amount of time that the data must be stable after the active edge of the clock. A hold time violation may result in incorrect data being latched, which is known as a hold violation.

[0024] An example setup / hold time is shown in FIG. 2 as setup 206. In this example, setup 206 is approximately 100 picoseconds. The three states of the TDC 113 are shown in chronological order and labeled N-2, N-1, and N. The seven-stage ring oscillator includes seven inverters, and therefore the TDC 113 captures seven bits, labeled from left to right as bit 6 to bit 0. In this example, N-2 is a periodic valid state with three 1's. A valid state that is generated when no setup or hold violation occurs may be referred to as a periodic valid state. In the illustrated example, each periodic valid state has three 1's (e.g., for N-2, bits 5, 4, and 3 are 1's and bits 6, 2, 1, and 0 are 0's), but the number of 1's and 0's is merely illustrative. Also, N is a periodic valid state with three 1's. In state N, bits 6, 5, and 4 are 1, and bits 3, 2, 1, and 0 are 0. When state N-2 changes to state N, bit 6 changes from 0 to 1, and bit 3 changes from 1 to 0. The other bits remain the same. Thus, 0111000 changes to 1110000. Because the flops within TDC 113 are independent, the bits captured by the flops also change independently of each other.

[0025] In this example, there is a short transition state between states N-2 and N. The transition state is labeled state N-1. In state N-1, bit 6 has changed from 0 to 1, but bit 3 has not yet changed from 1 to 0. Thus, the code for state N-1 has four ones instead of three ones. Codes with four ones are referred to herein as transition states. Transition states can occur between periodic valid states with three ones. In the example of a seven-stage ring oscillator, there are seven periodic valid states with three ones (1110000, 0111000, etc.) and seven transition states with four ones (1111000, 0111100, etc.). As described below, transition states are short in duration and can violate the setup and hold times of the flops. In the example of FIG. 2, transition state N-1 is approximately 70 picoseconds long. The setup 206 is approximately 100 picoseconds, so the N-1 state may violate the setup and hold times.

[0026] F REF The rising edge of the 1 At time t 1 Since time t is close to the window in which the bit is updating from the N-2 state to the N state, metastability may occur. 1 At time t, either or both of bits 6 and 3 may still be updating. 1At the same time, bit 6 may not yet have been updated from 0 to 1, and bit 3 may have been updated from 1 to 0. Thus, in this example, the captured code is 0110000. This code is an invalid code with only two 1's. In the example herein, the invalid code with only two 1's is decoded to the closest transition state with four 1's. In the seven-stage ring oscillator example, only a maximum of two bits change as the data is latched by the flops. In the 0110000 code, bits 6 and 3 are the bits that change. Thus, the 0110000 code is decoded to 1111000, with bits 6 and 3 changing from 0 to 1. A decoder according to the example herein may decode each code with two 1's to a corresponding transition code with four 1's. In other examples, other types of decoding may be implemented. In other examples, other types of codes may be used. As shown in the example of FIG. 2, at time t 1 If the code captured at time t is 0110000, 1 The rising edge in could have occurred during transition state N-1, which would have caused a metastability problem due to the length of the transition state (70 ps) compared to the setup / hold time (100 ps). Thus, a code with two 1s is decoded to the nearest transition code with four 1s.

[0027] In an alternative system, the metastability window of a flop can be made smaller by decreasing the setup and / or hold times. However, this alternative solution may increase power consumption, area, or require more expensive components. In another alternative solution mentioned above, invalid codes may be discarded. However, this alternative solution may impact jitter.

[0028] The examples herein utilize a sequence of three consecutive 1's in an oscillator to decode an invalid code into a valid state. The sequence of three consecutive 1's occurs in a sequence of bits in a seven-stage ring oscillator with a 3 / 7 duty cycle, as described below.

[0029] 3A is a circuit diagram 300 of an embedded TDC in some examples herein. The circuit diagram 300 includes a ring oscillator 302, a dynamic level shifter 304, flip-flops 306A-306G (collectively, flops 306), and an 8-bit gray counter 308. The ring oscillator 302 is a seven-stage ring oscillator that includes seven inverters 310A-310G (collectively, inverters 310). The dynamic level shifter includes a terminal 312 coupled to a voltage source that provides a voltage VDD and a terminal 314 coupled to ground. The reference frequency F REF is provided to the flop 306 via terminal 316. The flop 306 provides TDC_OUT<6:0> at output 318. The 8-bit gray counter 308 <0> and an output 322 that generates INTEGER_COUNT<7:0>.

[0030] The ring oscillator 302 is, in one example, the oscillator 108 of Figure 1. The ring oscillator 302 has a chain of inverters 310 arranged in a ring to generate an output that oscillates between two values. The output of the last inverter 310G is fed back to the first inverter 310A. Also, by adjusting the voltage or current provided to the inverter 310, the delay through that inverter 310 can be changed.

[0031] The output signal from each inverter 310 is provided to the dynamic level shifter 304. In this example, the signal from the inverter 310 output provided to the dynamic level shifter 304 is D <0> ~D <6> Details of dynamic level shifter 304 are described below with respect to FIG.

[0032] Seven output bits are provided by dynamic level shifter 304 to flop 306. These output bits are <0> ~B <6> and represents the bits of the TDC code sampled from the ring oscillator 302 and stored in the flop 306. 1 Flop 306 to signal reference F REFWhen a rising or falling edge of <0> ~B <6> and stores their values ​​in respective flops 306. The values ​​stored in the flops 306 are provided to the output 318 to generate the code TDC_OUT. In this example, the TDC_OUT code has 7 binary digits.

[0033] B offered on flop 306A <0> The value of is also provided to an input 320 of an 8-bit gray counter 308. The gray counter increments by changing only one bit at a time to change to an adjacent state. The 8-bit gray counter 308 counts the number of full revolutions an edge has gone through. The 8-bit gray counter 308 provides an 8-bit INTEGER_COUNT value at output 322 representing the number of full phase revolutions. The INTEGER_COUNT value and the TDC_OUT value are combined to form the digital phase relationship of the ring oscillator 302 in integer and fractional form (via adder 130 shown in FIG. 1) as described above. The INTEGER_COUNT provides integer phase information and the TDC_OUT provides fractional phase information. This measured phase is compared to the expected phase and the phase error is calculated.

[0034] 3B is a circuit diagram of a dynamic level shifter 304 in accordance with some examples herein. The dynamic level shifter 304 converts the value D <6> ~D <0> The dynamic level shifter 304 converts these inverter 310 output samples into output bits B <6> ~B <0> and provides their output bits to a flop 306. The dynamic level shifter 304 converts the value D <0> ~D <6> Receive. D <0> ~D <6> The value of is either 0 or 1 based on the output of the inverter 310. The transistors 350A to 350G are <0> ~D <6> The nodes 352A to 352G (respectively S <0> ~S <6> The voltage value of the <0> ~D <6> Nodes 352A-352G are coupled to the gates of transistors 354A-354G and to transistors 356A-356G, where S <0> The nodes and gates labeled with are tied together and S <1> The nodes and gates labeled S are coupled together, etc. <0> ) is the gate (S <0> ) and the gate (S <0> ) is also coupled to the inverter 310 output. <0> ~D <6> When the value of changes, S <0> ~S <6> The value of also varies across the dynamic level shifter 304.

[0035] The dynamic level shifter 304 performs two operations. First, it shifts from the local supply voltage of the oscillator 108 to the primary digital supply voltage used in the system 100, and performs this shift in a power efficient manner. The dynamic level shifter 304 is dynamic, so it switches and consumes current only when the output changes. Second, the dynamic level shifter 304 shifts the string of 1s and 0s (D <0> ~D <6> ) into a more readable phase signal. For example, if D<6:0> is sampled at any given time, D<6:0> may be 0101010, then 1101010 (when the first bit changes), then 1001010 (when the second bit changes), etc., because the changes to the inverter 310 outputs work their way through the inverter delays in the loop. These inverter 310 outputs are difficult to sample due to the timing of the changes, so the dynamic level shifter 304 logic forces each S bit to go high during its transition (e.g., from 0 to 1) and stay high (1) for three cycles before going low. By staying high for three cycles, the bit S <0> ~S <6> is directly connected to the inverter 310. <0> ~D <6> This makes it easier to capture than to read.

[0036] Bits S<6:0> are read from dynamic level shifter 304 and inverted by inverter 358. Inverter 358 is not shown as being coupled to other circuit elements in FIG. 3B, but is coupled to an appropriate node to receive the seven bits of S<6:0> at the input of inverter 358. In one example, inverter 358 may represent seven inverters, one for each bit. The output of inverter 358 generates the seven bits B<6:0>, which are provided to flops 306A-306G of FIG. 3A. As mentioned above, these bits B<6:0> (which are the inverse of bits S<6,0>) are held high for three cycles so that they can be more easily read from flop 306. The value stored in flop 306 is provided to output 318 to generate code TDC_OUT as described above with respect to FIG. 3A. Thus, dynamic level shifter 304 inverts the output of inverter 310 (D <0> ~D <6> ) and B in Figure 4 <0> ~B <6> , which is provided to flop 306.

[0037] FIG. 4 illustrates waveform B provided to flop 306 by dynamic level shifter 304 in some examples herein. <0> ~B <6> 4 is a timing diagram 400 for a bit B. In timing diagram 400, the y-axis represents voltage in volts and the x-axis represents time in nanoseconds. <0> ~B <6> The timing diagram 400 also corresponds to the voltage values ​​over time for bit B, as described below. <0> ~B <6> 414 includes capture 1 416 and capture 2 418, which are example times at which values ​​of are read out. Waveforms 402, 404, 406, 408, 410, 412, and 414 each have a duty cycle of 3 / 7, or approximately 43%. A duty cycle of 3 / 7 results from a valid digital code having three 1's and four 0's (e.g., periodic valid states). In other words, a bit is high 3 / 7 of the time and low 4 / 7 of the time, followed by three high bits in a row.

[0038] Waveforms 402, 404, 406, 408, 410, 412, and 414 show that there is a delay from one waveform to the next, starting with waveform 402 and ending with waveform 414. The delay corresponds to the delay of the signal traveling from one inverter 310 to the next through the ring oscillator 302. As an example, the first rising edge (B <0> The first rising edge (corresponding to B <1> The first rising edge of waveform 406 (corresponding to B <2> (corresponding to ) occurs at approximately 35.9 nanoseconds. The rising edges of subsequent waveforms 408, 410, 412, and 414 also occur at similar intervals.

[0039] The timing diagram 400 has two acquisition times, acquisition 1 416 and acquisition 2 418. The acquisition times are determined by the time REF The time when the rising edge of the reference signal F REF When the rising edge of <0> ~B <6> is read out. Capture 1 416 occurs at approximately 35.7 nanoseconds. At this time, B <0> , B <1> , B <6> The other bits (B <2> , B <3> , B <4> , B <5> ) is low (0). Therefore, B <6> From B <0> The code up to is 1000011 for acquisition time 1 416. Therefore, TDC_OUT is 1000011, which is a valid code.

[0040] Capture 2 418 is another example of a capture time. At approximately 39.4 nanoseconds, capture 2 418 occurs. At this time, bit B <0> and B. <6> However, this acquisition time is <1> and B. <5> The setup / hold time of the flop 306 corresponding to bit B is violated. <1> and B. <5> has transitioned at capture 2 418. TDC_OUT can be either 1100011, 1100001, 1000001, or 1000011. If TDC_OUT is either 1100001 or 1000011, they are cyclic valid codes with three 1's, and those cyclic valid codes are acceptable valid codes. If TDC_OUT is 1100011, this is a transition state with four 1's. The transition state is also a valid code. If TDC_OUT is 1000001, this is an invalid code with only two 1's. In our example, the invalid code with two 1's is decoded to the closest transition state with four 1's. Thus, 1000001 is decoded to transition state 1100011.

[0041] The state machine may, in one example, decode the data and convert it to an appropriate value. The appropriate value may be F REF is compared to the TDC_OUT code. If the phase error is zero, no changes are made to the oscillator. If the phase error is large, the oscillator is running too fast and the PLL will slow the oscillator down to accumulate less phase. If the phase gets too low, the oscillator is running too slow and the PLL will speed up the oscillator to accumulate more phase. The TDC_OUT code, its correction value, and the INTEGER_COUNT are a representation of the oscillator phase.

[0042] FIG. 5 is a table 500 of valid and invalid codes for a seven-stage ring oscillator with embedded TDC in some examples. Column A contains valid B<6:0> codes, which include periodic valid codes with three 1's and transition states with four 1's. Column B indicates whether the code is a transition state, indicated with a Y if it is a transition state and an N if it is not a transition state. Column C lists the possible TDC_OUT<6:0> codes for each valid state. Column D is a decoder fractional value representing the fractional phase value associated with each possible TDC_OUT<6:0> code.

[0043] Rows 1, 3, 5, 7, 9, 11, and 13 show cyclic valid codes with three 1's. Rows 2, 4, 6, 8, 10, 12, and 14 are valid transition codes with four 1's. In these transition code rows, column C shows the possible codes for each transition state. TDC_OUT codes with two 1's corresponding to each transition state are shown in column C. If a code with two 1's is received, it is decoded to the transition state in the corresponding row of table 500. A lookup table such as table 500 may be used by decoder 128 in some examples to convert the TDC_OUT codes to fractional phase values ​​as shown in column D.

[0044] 6 is a flow chart of a method 600 for metastability correction for a ring oscillator with an embedded TDC in some examples herein. The steps of the method 600 may be performed in any suitable order. The hardware components described above with respect to FIGS. 1, 3A, and 3B may perform the method 600 in some examples. In one example, a processor or controller, such as the decoder 128, may execute executable code to perform at least some of the steps of the method 600.

[0045] The method 600 begins at 610, where a set of flops is REFAs described above, the flops 306 may receive a reference signal via terminal 316. Each flop receives a reference signal, which may be a rising edge or a falling edge. In one example, the N flops of the TDC are coupled to the N inverters of the ring oscillator, one flop coupled to the output of each inverter. In some examples, there is a level shifter between the inverters and the flops. The level shifter receives a first data sample from the N inverters and provides a second data sample to the N flops.

[0046] The method 600 continues at 620, where, in response to receiving the reference signal, each of the flops captures the output of a different stage of a multi-stage ring oscillator, which in some examples may be an inverter, such as inverter 310.

[0047] The method 600 continues at 630 where the flop provides a code to the decoder, the code being based at least in part on the output of the stage. In the above example, the code includes N binary bits that are the output of the N inverters 310. The N binary bits constitute a code that encodes phase information of the oscillator signal.

[0048] The method 600 continues at 640 where, in response to the code being invalid, the invalid code is decoded into a valid code. As mentioned above, some codes are invalid due to metastability issues in the TDC. The invalid code may include two binary 1's (X binary 1's) instead of three (X+1) or four (X+2) binary 1's in some examples. In other examples, other types of valid or invalid codes may exist.

[0049] The method 600 continues at 650 where a valid code is provided to a phase frequency detector, such as the PFD 102. The valid code may be provided to the PFD 102 by the decoder 128. In some examples, the code may be provided to the PFD 102 from a flop 306. The PFD 102 uses the code to determine if a phase error exists between the oscillator phase and the phase of a reference frequency. The PFD 102 provides the phase error, and a phase-locked loop uses the phase error to adjust the oscillator phase if the oscillator is out of phase.

[0050] In the examples herein, the phase predictability of the ring oscillator is exploited to correct phase data damaged by metastability of the TDC. A low-power single-ended ring oscillator topology can also be used. Standard digital library flops with low power and large metastability window can be included to capture the TDC data. The examples herein use an inverter of the ring oscillator as the TDC to save circuit area and power consumption. Also, invalid codes can be decoded instead of being discarded, and the phase can be corrected or verified at each update cycle. The decoding is performed with a simple decoding scheme. The decoding logic can be adjusted as the number of bits changes.

[0051] The term "couple" is used throughout this specification. This term may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, in a first example, device A is coupled to device B if device A generates a signal to control device B to perform a certain action, or in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal generated by device A, where the intervening component C does not substantially change the functional relationship between devices A and B.

[0052] A device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or hardwired) to perform that task or function by a manufacturer at the time of manufacture, or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, through the configuration and / or layout of hardware components, through the interconnections of the device, or through a combination thereof.

[0053] A circuit or device described herein as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacture, e.g., by an end user and / or a third party, to form the described structure.

[0054] The circuits described herein are reconfigurable to include replaced components to provide functionality at least partially similar to the functionality available prior to the component replacement.

[0055] Use of the term "ground" in the preceding description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable for the teachings of the present description. Unless otherwise specified, "approximately," "near," or "substantially" preceding a value means + / - 10% of the stated value. Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the present claims.

Claims

1. A system comprising: A phase-locked loop, comprising: A set of inverters; and A set of flip-flops, each flip-flop of the set of flip-flops being coupled to an output of a different inverter of the set of inverters; The phase-locked loop; A decoder, configured to: Receive a code representing the phase of the phase-locked loop from the set of flip-flops; In response to the code being invalid, decode the invalid code into a valid code; and Provide the valid code to a phase frequency detector; The decoder; The system.

2. The system according to claim 1, wherein The phase-locked loop includes a 7-stage ring oscillator.

3. The system according to claim 1, wherein The phase frequency detector is configured to determine a phase error between the phase of the phase-locked loop and the phase of a reference signal in response to receiving the valid code.

4. The system according to claim 3, wherein The phase frequency detector is further configured to adjust the phase of the phase-locked loop in response to the phase error.

5. The system according to claim 1, further comprising A level shifter configured to receive a first data sample from the set of inverters and provide a second data sample to the set of flip-flops.

6. The system according to claim 1, wherein The decoder is further configured to decode the invalid code into the nearest valid code.

7. The system according to claim 1, wherein The invalid code includes X binary 1s, and the valid code includes X + 1 or X + 2 binary 1s.

8. The system according to claim 1, wherein The decoder is further configured to decode the invalid code having X binary 1s into the valid code having X + 2 binary 1s.

9. The system according to claim 1, wherein Each flip-flop of the set of flip-flops is configured to sample the output of the inverter in response to receiving a reference signal.

10. A method comprising: Receiving a reference signal at a set of flip-flops; In response to receiving the reference signal, capturing the outputs of different stages of the ring oscillator using each of the set of flip-flops; Providing a decoder with a code based at least in part on the output of the ring oscillator; In response to the code being invalid, decoding the invalid code into a valid code; Providing the valid code to a phase frequency detector; A method comprising the above steps. **Claim 11** The method according to claim 10, further comprising: Determining a phase error between the phase of the ring oscillator and the phase of the reference signal in response to receiving the valid code. **Claim 12** The method according to claim 11, further comprising: Adjusting the phase of the ring oscillator in response to the phase error. **Claim 13** The method according to claim 10, wherein: Decoding the invalid code includes decoding the invalid code into the nearest valid code. **Claim 14** The method according to claim 10, wherein: Decoding the invalid code includes decoding an invalid code having X binary 1s into a valid code having X + 2 binary 1s. **Claim 15** The method according to claim 10, wherein: The ring oscillator generates an output signal that is a multiple of the reference signal. **Claim 16** The method according to claim 10, wherein: The reference signal reaches the set of flip-flops during the setup time of at least one set of flip-flops in the set of flip-flops. **Claim 17** A system comprising: A ring oscillator including a set of inverters; A time-to-digital converter including a set of flip-flops, each of the set of flip-flops being coupled to the output of a different inverter in the set of inverters; A level shifter coupled to the set of inverters and the set of flip-flops; A gray counter coupled to at least one of the set of flip-flops; A decoder coupled to the time-to-digital converter; A phase frequency detector coupled to the decoder; The system comprising the above components. **Claim 18** The system according to claim 17, wherein: A system, wherein the phase frequency detector is configured to determine a phase error between a phase of the ring oscillator and a phase of a reference signal in response to receiving a code from the time-to-digital converter, and the code represents the phase of the ring oscillator. **Claim 19** The system according to claim 18, wherein the decoder is configured to decode an invalid code into the nearest valid code. **Claim 20** The system according to claim 18, wherein the decoder is configured to decode an invalid code having X binary 1s into a valid code having X + 2 binary 1s.

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