SPLIT-DIE INTEGRATED CIRCUIT (IC) PACKAGE EMPLOYING DIE-TO-DIE (D2D) INTERCONNECTS IN A DIE-TO-SUBSTRATE STANDOFF CAVITY AND ASSOCIATED MANUFACTURING METHODS - Patent application

Abstract

A split-die IC package employing a D2D interconnect structure in a die-substrate standoff cavity (i.e., cavity) to provide D2D connections, and related manufacturing methods. To facilitate D2D communication between multiple dies in the split-die IC package, the package substrate also includes a D2D interconnect structure (e.g., interconnect bridge) including D2D interconnects (e.g., metal interconnects) coupled to the multiple dies to provide D2D signal routing between the multiple dies. The D2D interconnect structure is disposed in a cavity formed in the die standoff area between the die and the package substrate as a result of the die interconnects being disposed between the die and the package substrate and the die being spaced from the package substrate. The D2D interconnect structure can be provided in a cavity in the IC package outside the package substrate to provide more area in the package substrate for other interconnects.

Description

[Technical field]

[0001] Priority Application This application claims priority to U.S. patent application Ser. No. 17 / 443,740, filed July 27, 2021, and entitled “SPLIT DIE INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING DIE-TO-DIE (D2D) CONNECTIONS IN DIE-SUBSTRATE STANDOFF CAVITY, AND RELATED FABRICATION METHODS,” which is incorporated herein by reference in its entirety.

[0002] Field of the Disclosure The field of the disclosure relates to integrated circuit (IC) packages, and more particularly, to split semiconductor die IC packages. [Background technology]

[0003] Integrated circuits (ICs) are the basis of electronic devices. ICs are packaged in IC packages, also called "semiconductor packages" or "chip packages." An IC package includes one or more semiconductor dies as IC(s), which are attached and electrically coupled to a package substrate to provide physical support and an electrical interface to the semiconductor die(s). The package substrate includes one or more metallization layers including electrical traces (e.g., metal lines), and vertical interconnect accesses (vias) couple the electrical traces to each other between adjacent metallization layers to provide an electrical interface between the semiconductor die(s). The semiconductor die(s) are attached and electrically interfaced to exposed metal interconnects at the top or outer layer of the package substrate to electrically couple the semiconductor die(s) to the electrical traces of the package substrate. The package substrate includes an outer outer layer having metal interconnects to provide an external interface between the semiconductor die(s) in the IC package and external circuitry.

[0004] There are many types of IC packages based on the intended application. A split semiconductor die IC package ("split die" IC package) is a package that includes two or more semiconductor dies that are conventionally arranged next to each other. The semiconductor dies are mounted and electrically coupled on a package substrate to provide physical support and an electrical interface to the semiconductor dies. According to the design operation of the split die IC package, it may be necessary to provide a signal interface between the split dies for die-to-die (D2D) communication. For example, each split die may include a D2D interface circuit that provides an internal circuit and a communication signal interface to another die. In this regard, the split die IC package may include a D2D interconnect structure that includes a D2D connection between the D2D interface circuit of each die to provide a signal interface between the dies. Conventional split die IC packages employ a D2D interposer to provide the D2D interconnect structure. For example, the D2D interposer may be provided as a silicon interposer in the package substrate that acts like a signal interface bridge. As another example, the D2D interposer may be an embedded wafer level package (eWLP) that includes multiple redistribution layers (RDLs) as metallization layers to support the D2D connections. In either case, however, providing additional metallization layers to provide the D2D connections may undesirably increase the package height of the IC package. Summary of the Invention [Means for solving the problem]

[0005] Embodiments disclosed herein include an exemplary split-die integrated circuit (IC) package that employs a D2D interconnect structure within a die-substrate standoff cavity (i.e., cavity) to provide die-to-die (D2D) connections. Related manufacturing methods are also disclosed. In an exemplary embodiment, the split-die IC package includes at least two semiconductor dies ("dies") coupled to a package substrate. The package substrate includes one or more metallization layers each having metal interconnects (e.g., metal lines or traces) that can provide signal routing between the die and external interconnects (e.g., solder bumps). The split-die IC package includes a plurality of die interconnects (e.g., die bumps with solder joints) between the die and the package substrate that electrically couple the die to the package substrate for signal routing. In an exemplary embodiment, to facilitate D2D communication between the multiple dies in the split-die IC package, the package substrate also includes a D2D interconnect structure (e.g., interconnect bridge) that includes D2D interconnects (e.g., metal interconnects) coupled to the multiple dies to provide D2D signal routing between the multiple dies. The D2D interconnect structure is disposed in a cavity formed in the die standoff area between the die and the package substrate as a result of the die interconnects being disposed between the die and the package substrate and the die being spaced from the package substrate. In this manner, the D2D interconnect structure can be disposed in the cavity of the IC package outside of the package substrate, reserving more area in the package substrate for other interconnects, such as between the die and external interconnects. Providing the D2D interconnect structure outside of the package substrate can also reduce the overall height of the split-die IC package, since the area of ​​the package substrate that would otherwise be consumed by the metal interconnects for the D2D connections can be used for other signal routing and / or other devices (e.g., passive devices). Providing the D2D interconnect structure in the cavity also allows the D2D interconnects to be located closer to the die than if they were disposed in the package substrate, thus reducing their length, thereby reducing resistance and improving D2D signaling speed.

[0006] In certain exemplary aspects, the D2D interconnect structure is formed by one or more redistribution layers (RDLs) built on the die module adjacent to the active surface of the die. The RDLs are built on the die module and are coupled to the die interconnects of the die used for D2D communication. The RDLs can also be built on the die module in limited areas that form the die standoff area, without the need to build the RDLs across the entire horizontal area between the die module and the package substrate, which would increase the height of the split-die IC package. Providing the D2D interconnect structure as RDL(s) can facilitate thinner metallization layers with smaller patterning sizes (i.e., lines (L) / spaces (S) (L / S)) of metal interconnects for the D2D interconnects than can be fabricated in traditional laminate substrates. Thus, providing the D2D interconnects in the RDLs can facilitate higher density D2D interconnects in the split-die IC package. The RDLs also do not require solder joints to be used to connect the D2D interconnect structure to the die interconnects of the die. This may be particularly useful in dies with high density die interconnects coupled to D2D interconnects to provide D2D communication.

[0007] In another example, the RDL layer of the D2D interconnect structure is formed on the die module as a reconfigured wafer forming a reconfigured die module. In this regard, the die may be formed on an initial wafer and then diced and rearranged on the reconfigured wafer as part of a fan-out wafer level packaging (FOWLP) process. The die on the reconfigured wafer may be diced to provide the die module as a reconfigured die module. Providing the die module as a reconfigured die module may allow for better control of die placement, allowing the die to be placed closer to each other to further reduce package size. Providing the die module as a reconfigured die module may also provide a convenient process for building RDLs for the D2D interconnects on a reconfigured die module where multiple dies are present. In this manner, the RDLs may be bonded to the die interconnects of the die module as the RDLs are fabricated on the reconfigured die module. The die module incorporating the RDLs forming the D2D interconnects may then be bonded to a package substrate as part of the fabrication of a split die IC package.

[0008] It should be noted that providing the D2D interconnect structures within the outer die standoff area of ​​the package substrate of a split-die IC package does not preclude metallization layers within the package substrate from also being used to provide the D2D interconnects. By including the D2D interconnect structures within the outer die standoff area of ​​the package substrate, the need for D2D connections within the package substrate can be reduced or minimized.

[0009] In this regard, in one exemplary aspect, an IC package is provided. The IC package includes a package substrate, a first die, and a second die. The IC package also includes a first plurality of die interconnects coupled to the package substrate and the first die and forming a die standoff area between the first die and the package substrate. The IC package also includes a second plurality of die interconnects disposed in the die standoff area and coupled to the package substrate and the second die. A cavity is formed in the die standoff area between the first plurality of die interconnects and the second plurality of die interconnects. The IC package also includes a D2D interconnect structure disposed in the cavity. The D2D interconnect structure includes a plurality of D2D interconnects coupled to the first die and the second die.

[0010] In another exemplary aspect, a method of fabricating an IC package is provided. The method includes forming a die module including a first die including an active surface, a first active surface adjacent to the active surface, and a second die including a second active surface adjacent to the active surface, the second die being horizontally adjacent to the first die. The method also includes forming a D2D interconnect structure adjacent to the active surface of the die module, the D2D interconnect structure including a plurality of D2D interconnects. The method also includes forming a first plurality of die interconnects coupled to the first active surface of the first die. The method also includes forming a second plurality of die interconnects coupled to the second active surface of the second die to form a cavity between the first plurality of die interconnects and the second plurality of die interconnects, within which the D2D interconnect structure is disposed. The method also includes disposing the die module on a package substrate, coupling a first plurality of die interconnects to the package substrate, and coupling a second plurality of die interconnects to the package substrate. [Brief description of the drawings]

[0011] [Figure 1A]FIG. 1 illustrates a top view of a split semiconductor die ("die") integrated circuit (IC) package that includes a die-to-die (D2D) connection interposer within a package substrate to provide D2D connections. [Figure 1B] 1 is a cross-sectional side view of a split semiconductor die ("die") integrated circuit (IC) package that includes a die-to-die ("D2D") connection interposer within a package substrate to provide D2D connections. [Figure 2A] 1 is a top view of an example split-die IC package employing a D2D interconnect structure within a die-substrate standoff cavity (i.e., cavity) to provide D2D connections. [Figure 2B] 1 is a cross-sectional side view of an example split-die IC package employing a D2D interconnect structure within a die-substrate standoff cavity (i.e., cavity) to provide D2D connections. [Diagram 3] FIG. 2C is another side view of the split-die IC package of FIG. 2B showing further details of the D2D interconnect structure within the cavity that provides the D2D connection. [Figure 4] FIG. 4 is a flowchart illustrating an example process for manufacturing a split-die IC package that employs a D2D interconnect structure within a cavity to provide D2D connectivity, including but not limited to the example split-die IC packages of FIGS. [Figure 5A] FIG. 4 is a flowchart illustrating another exemplary process for manufacturing a split-die IC package that employs a D2D interconnect structure within a cavity to provide D2D connectivity, including (but not limited to) the exemplary split-die IC packages of FIGS. [Figure 5B] FIG. 4 is a flowchart illustrating another exemplary process for manufacturing a split-die IC package that employs a D2D interconnect structure within a cavity to provide D2D connectivity, including (but not limited to) the exemplary split-die IC packages of FIGS. [Figure 5C]FIG. 4 is a flowchart illustrating another exemplary process for manufacturing a split-die IC package that employs a D2D interconnect structure within a cavity to provide D2D connectivity, including (but not limited to) the exemplary split-die IC packages of FIGS. [Figure 6A] 5A-5C show exemplary manufacturing stages in manufacturing a split-die IC package employing an intra-cavity D2D interconnect structure to provide D2D connectivity, including (but not limited to) the exemplary split-die IC packages of FIGS. 2A-3, according to the exemplary manufacturing process of FIGS. 5A-5C. [Figure 6B] 5A-5C show exemplary manufacturing stages in manufacturing a split-die IC package employing an intra-cavity D2D interconnect structure to provide D2D connectivity, including (but not limited to) the exemplary split-die IC packages of FIGS. 2A-3, according to the exemplary manufacturing process of FIGS. 5A-5C. [Figure 6C] 5A-5C show exemplary manufacturing stages in manufacturing a split-die IC package employing an intra-cavity D2D interconnect structure to provide D2D connectivity, including (but not limited to) the exemplary split-die IC packages of FIGS. 2A-3, according to the exemplary manufacturing process of FIGS. 5A-5C. [Figure 6D] 5A-5C show exemplary manufacturing stages in manufacturing a split-die IC package employing an intra-cavity D2D interconnect structure to provide D2D connectivity, including (but not limited to) the exemplary split-die IC packages of FIGS. 2A-3, according to the exemplary manufacturing process of FIGS. 5A-5C. [Figure 6E] 5A-5C show exemplary manufacturing stages in manufacturing a split-die IC package employing an intra-cavity D2D interconnect structure to provide D2D connectivity, including (but not limited to) the exemplary split-die IC packages of FIGS. 2A-3, according to the exemplary manufacturing process of FIGS. 5A-5C. [Figure 6F]5A-5C show exemplary manufacturing stages in manufacturing a split-die IC package employing an intra-cavity D2D interconnect structure to provide D2D connectivity, including (but not limited to) the exemplary split-die IC packages of FIGS. 2A-3, according to the exemplary manufacturing process of FIGS. 5A-5C. [Figure 6G] 5A-5C show exemplary manufacturing stages in manufacturing a split-die IC package employing an intra-cavity D2D interconnect structure to provide D2D connectivity, including (but not limited to) the exemplary split-die IC packages of FIGS. 2A-3, according to the exemplary manufacturing process of FIGS. 5A-5C. [Figure 6H] 5A-5C show exemplary manufacturing stages in manufacturing a split-die IC package employing an intra-cavity D2D interconnect structure to provide D2D connectivity, including (but not limited to) the exemplary split-die IC packages of FIGS. 2A-3, according to the exemplary manufacturing process of FIGS. 5A-5C. [Figure 7] FIG. 4 is a block diagram of an exemplary processor-based system including components that may be packaged in a split-die IC package(s) employing a D2D interconnect structure within a cavity to provide D2D connectivity, including but not limited to the exemplary split-die IC packages of FIGS. 2A-3 and according to the exemplary manufacturing process of FIGS. 4-6H. [Figure 8] FIG. 4 is a block diagram of an exemplary wireless communication device including radio frequency (RF) components that may be packaged in a split-die IC package(s) employing a D2D interconnect structure within a cavity to provide D2D connectivity, including but not limited to the exemplary split-die IC packages of FIGS. 2A-3 and according to the exemplary manufacturing process of FIGS. 4-6H. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Some exemplary aspects of the present disclosure will now be described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0013] Embodiments disclosed herein include an exemplary split-die integrated circuit (IC) package that employs a D2D interconnect structure within a die-substrate standoff cavity (i.e., cavity) to provide die-to-die (D2D) connections. Related manufacturing methods are also disclosed. In an exemplary embodiment, the split-die IC package includes at least two semiconductor dies ("dies") coupled to a package substrate. The package substrate includes one or more metallization layers each having metal interconnects that can provide signal routing between the die and external interconnects (e.g., solder bumps). The split-die IC package includes a plurality of die interconnects (e.g., die bumps with solder joints) between the die and the package substrate that electrically couple the die to the package substrate for signal routing. In an exemplary embodiment, to facilitate D2D communication between the multiple dies in the split-die IC package, the package substrate also includes a D2D interconnect structure (e.g., interconnect bridge) that includes D2D interconnects (e.g., metal lines) coupled to the multiple dies to provide D2D signal routing between the multiple dies. The D2D interconnect structure is disposed in a cavity formed in the die standoff area between the die and the package substrate as a result of the die interconnects being disposed between the die and the package substrate and the die being spaced from the package substrate. In this manner, the D2D interconnect structure can be disposed in the cavity of the IC package outside of the package substrate, reserving more area in the package substrate for other interconnects, such as between the die and external interconnects. Providing the D2D interconnect structure outside of the package substrate can also reduce the overall height of the split-die IC package, since the area of ​​the package substrate that would otherwise be consumed by the metal interconnects for the D2D connections can be used for other signal routing and / or other devices (e.g., passive devices). Providing the D2D interconnect structure in the cavity also allows the D2D interconnects to be located closer to the die than if they were disposed in the package substrate, thus reducing their length, thereby reducing resistance and improving D2D signaling speed.

[0014] Before describing an example of a split-die IC package that employs a D2D interconnect structure within a cavity to provide D2D connections between multiple dies within a package, beginning with FIG. 2A, a split-die IC package that does not include a D2D interconnect structure within a cavity will first be described below with reference to FIG. 1A and FIG. 1B.

[0015] In this regard, FIGS. 1A and 1B are top and cross-sectional side views, respectively, of a split semiconductor die ("die") IC package 100 including a D2D interposer 102 in a package substrate 104 to provide D2D connectivity. The split die IC package 100 in FIG. 1B is shown as a cross-section along line A1-A1' in FIG. 1A. With reference to FIGS. 1A and 1B, the split die IC package 100 includes at least two semiconductor dies ("die") 106(1), 106(2) coupled to a package substrate 104. The dies 106(1), 106(2) are disposed horizontally adjacent to each other in the X-axis direction in this example, with a die separation region 108 formed between the dies 106(1), 106(2). The package substrate 104 includes one or more metallization layers, each having metal interconnects (e.g., metal lines or traces) that can provide signal routing between the dies 106(1), 106(2) and external interconnects 110 (e.g., solder balls). As shown in FIG. 1B , the split-die IC package 100 includes a plurality of die interconnects 112 (e.g., die bumps having solder joints) between the dies 106(1), 106(2) and the package substrate 104 that electrically couple the dies 106(1), 106(2) to the package substrate 104 for signal routing. The die interconnects 112, in this example, include metal pillars 114 coupled to die pads (not shown) on the active surfaces 116(1), 116(2) of the respective dies 106(1), 106(2). The metal pillars 114 are coupled to the package substrate 104 by solder joints 118 formed on the metal pillars 114 and coupled to the package substrate 104 .

[0016] To facilitate D2D communication between the multiple dies 106(1), 106(2) in the split-die IC package 100 of FIG. 1A and FIG. 1B, the package substrate 104 also includes a D2D interposer 102. The D2D interposer 102 is disposed in the package substrate 104 below the die isolation region 108 in this example. The D2D interposer 102 includes D2D interconnects 120 (e.g., metal lines) coupled to specific die interconnects 112 coupled to the respective dies 106(1), 106(2), where the D2D interconnects 120 are dedicated to D2D signal routing between the dies 106(1), 106(2) for D2D communication. This D2D signal routing can be, by way of example, the coupling of communication signals and common power rails. To shorten the length of the D2D interconnects 120 to reduce resistance and improve signaling speed, the D2D interposer 102 is conventionally placed on the top metallization layer of the package substrate 104.

[0017] The inclusion of the D2D interposer 102 in the package substrate 104 consumes space in the metallization layers of the package substrate 104. This may increase the height H1 of the package substrate in the Z-axis direction, and therefore the overall height H2 of the split-die IC package in the Z-axis direction, as shown in FIG. 1B. Also, the inclusion of the D2D interconnect 120 in the package substrate 104 may position the D2D interconnect 120 close to other metal interconnects (such as power rails) in the package substrate 104, which may cause signal interference. The D2D communication signals transmitted through the D2D interconnect 120 may be higher speed signals as part of the D2D bus interface between the dies 106(1), 106(2) and may be particularly sensitive to interference. Also, the location of the D2D interposer 102 adjacent below the die isolation region 108 may impact the routing space in the package substrate 104. Other metal interconnects in the package substrate 104 that route signals other than D2D communication signals must be separated from the D2D interposer 102 and therefore routed in other areas outside the area of ​​the D2D interposer 102. This may impact routing options and capabilities within the package substrate 104. For example, the D2D interposer 102 may interfere with the routing paths of the power distribution network in the package substrate 104, which may lengthen the power distribution paths. This may result in increased voltage drops in the power distribution network in the package substrate 104. Furthermore, as the number and / or density of the D2D interconnects 120 increase, the D2D interposer 102 will likely be placed on additional metallization layers of the package substrate 104, consuming additional area that could be used for other signal routing. Alternatively, to prevent the D2D interposer 102 from consuming additional space within the package substrate 104, the additional D2D interconnects from one die 106(1), 106(2) may have to be routed through the package substrate 104 to the external interconnects 110 back to the other die 106(2), 106(1).

[0018] 2A and 2B are top and cross-sectional side views, respectively, of another exemplary split-die IC package 200 that employs a D2D connection structure to replace the D2D interposer 102 in the split-die IC package 100 of FIGS. 1A and 1B so as to avoid consuming space in the package substrate for the D2D connections. In this regard, as described in further detail below, the split-die IC package 200 of FIGS. 2A and 2B includes a D2D interconnect structure 202 for providing the D2D connections that is disposed within a die-to-substrate standoff cavity (i.e., cavity) 204. The die-to-substrate standoff cavity 204 is an area formed in a die standoff region 228 between semiconductor die ("die") 206(1), 206(2) and the package substrate 208 as a result of die interconnects 210 coupling the die 206(1), 206(2) to the package substrate 208 being disposed between the die 206(1), 206(2) and the package substrate 208. The die-to-substrate standoff cavity 204, in one example, does not include the package substrate 208 or the space inside the die 206(1), 206(2). The die interconnects 210 "stand off" the die 206(1), 206(2) from the package substrate 208 by a respective height H3 of the die interconnects 210 to form the die-to-substrate standoff cavity 204 disposed between the die 206(1), 206(2) and the package substrate 208.

[0019] 2B, the D2D interconnect structure 202 is disposed outside of the package substrate 208 and within the die-to-substrate standoff cavity 204 of the split-die IC package 200. This allows more area to be provided within the package substrate 208 for other interconnects, such as between the dies 206(1), 206(2) and the external interconnects 211 (e.g., solder balls). Disposing the D2D interconnect structure 202 outside of the package substrate 208 also allows the height H4 of the package substrate 208 to be reduced relative to the height of the package substrate 208 if the D2D interconnect structure 202 were included within the package substrate 208. By reducing the height H4 of the package substrate 208, the overall height H5 of the split-die IC package 200 is also reduced because the area of ​​the package substrate 208 that would otherwise be consumed by interconnects (e.g., metal lines, metal traces, vertical interconnect access (vias), pads) for the D2D connections can be used for other signal routing and / or other devices (e.g., passive devices). Also, by providing the D2D interconnect structure 202 in the die-to-substrate standoff cavity 204 of the split-die IC package 200, the D2D interconnects in the D2D interconnect structure 202 can be located closer to the dies 206(1), 206(2) than if they were provided in the package substrate 208. This allows the length of the D2D interconnects to be reduced, which reduces resistance and improves the D2D signaling speed between the dies 206(1) and 206(2).

[0020] 2A and 2B, the split-die IC package 200 of FIG. 2B is shown as a cross-section taken along line A2-A2′ of FIG. 2A. The dies 206(1), 206(2) are coupled to a package substrate 208. The dies 206(1), 206(2) are disposed horizontally adjacent to one another in an X-axis direction, in this example, with a die separation region 212 having an area distance D1 between the dies 206(1), 206(2). In this example, the dies 206(1), 206(2) are included in a die module 214. The first and second dies 206(1), 206(1) are disposed above the package substrate 208 in a vertical direction along a Z-axis, in this example, perpendicular to the horizontal direction along the X-axis. The die module 214 includes the dies 206(1), 206(2) and an overmold compound 216 (e.g., epoxy) formed around the dies 206(1), 206(2) and within the die isolation region 212. For example, as described in more detail below, the die module 214 may include a reconfigured wafer 218 fabricated according to a fan-out wafer level packaging (FOWLP) process. Providing the die module 214 as a reconfigured wafer 218 may allow for better die placement control and may allow the dies 206(1), 206(2) to be placed closer together to further reduce the width of the die isolation region 212 in the horizontal X-axis direction to reduce package size. A dielectric layer 220 is disposed over the die module 214. A packaging compound 222, such as a mold compound, is disposed over the dielectric layer 220 as part of the split-die IC package 200.

[0021] As shown in FIG. 2B , first and second plurality of die interconnects 210(1), 210(2) are coupled to the package substrate 208 and to respective first and second dies 206(1), 206(2). The first and second dies 206(1), 206(2) have respective active sides 224(1), 224(2) and back sides 226(1), 226(2). The die interconnects 210(1) are coupled to the active side 224(1) of the die 206(1) and to the package substrate 208. The die interconnects 210(2) are coupled to the active side 224(2) of the die 206(2) and to the package substrate 208. The first and second plurality of die interconnects 210(1), 210(2) coupled to the package substrate 208 and the respective first and second dies 206(1), 206(2) form a die standoff region 228 between the first and second dies 206(1), 206(2) and the package substrate 208. A die-to-substrate standoff cavity 204 is formed in the die standoff region 228 between the die interconnects 210(1) and 210(2). The D2D interconnect structure 202 is disposed within the die-to-substrate standoff cavity 204. As described in more detail below with respect to FIG. 3, the D2D interconnect structure 202 includes D2D interconnects 232 coupled to the first die 206(1) and the second die 206(2) to provide a D2D connection between the dies 206(1), 206(2). In this example, the die 206(1) includes a D2D interface circuit 234(1) that provides a D2D communication interface to the die 206(2). The D2D interface circuit 234(1) is horizontally adjacent to the die isolation region 212. Also in this example, the die 206(2) includes a D2D interface circuit 234(2) that provides a D2D communication interface to the die 206(1). The D2D interface circuit 234(2) is also horizontally adjacent to the die isolation region 212. The D2D interface circuits 234(1), 234(2) are disposed on and in contact with the D2D interconnect structure 202 and are coupled to the D2D interconnect 232 such that the D2D interface circuits 234(1), 234(2) are coupled to each other for D2D communication.

[0022] In this example, the D2D interconnect structure 202 and its D2D interconnects 232 are not disposed within the package substrate 208. In this example, to avoid consuming area within the package substrate 208 for the D2D connections provided by the D2D interconnect structure 202, the D2D interconnects 232 are not coupled to the package substrate 208, including metal interconnects (e.g., metal lines, metal traces, vertical interconnect access (vias), pads) in a metallization layer of the package substrate 208.

[0023] 3 is another cross-sectional side view of split-die IC package 200 of FIGS. 2A and 2B to illustrate additional example details including D2D interconnect structure 202 within die-to-substrate standoff cavity 204. The cross-sectional side view of split-die IC package 200 of FIG. 3 is also taken along line A2-A2′ of split IC die package 200 of FIG. 2A.

[0024] 3, in this example, the die module 214 has an active surface 236 adjacent to the package substrate 208. The first and second active surfaces 224(1), 224(2) of the first and second die 206(1), 206(2) are disposed on the active surface 236 of the package substrate 208, and connections can be formed between the first and second die 206(1), 206(2) and the package substrate 208 via respective first and second die interconnects 210(1), 210(2). The first die interconnect 210(1) is coupled to the first active surface 224(1) of the first die 206(1). The second die interconnect 210(2) is coupled to the second active surface 224(2) of the second die 206(2). Each of the first and second die interconnects 210(1), 210(2) includes a metal pillar 238(1), 238(2) (e.g., a copper pillar) coupled to a die pad on the respective first and second active surfaces 224(1), 224(2) of the respective first and second die 206(1), 206(2). Interconnect bumps 240(1), 240(2) (e.g., solder bumps or caps) are disposed on the metal pillars 238(1), 238(2) and form an electrical connection to the package substrate 208. The package substrate 208 includes one or more metallization layers 242(1)-242(3) to form an electrical connection between the dies 206(1), 206(2) via the die interconnects 210(1), 210(2). Die interconnects 210(1), 210(2) are coupled to one or more metal interconnects 243(1)-243(3) (e.g., metal lines, metal traces, vertical interconnect access (vias), pads) in metallization layers 242(1)-242(3) of package substrate 208. A height H3 of die interconnects 210(1), 210(1) defines a height H3 of die-to-substrate standoff cavity 204 in the vertical direction of the Z-axis.The D2D interconnect structure 202 has a height H6 in the vertical direction of the Z-axis that is less than a height H3 of the die-to-substrate standoff cavity 204, such that the D2D interconnect structure 202 can be disposed within the die-to-substrate standoff cavity 204, if necessary, without consuming area within the package substrate 208. The overmold compound 216 is disposed adjacent to first and second backside surfaces 226(1), 226(2) of the first and second die 206(1), 206(2).

[0025] As an example, as described in further detail below, die module 214 can be a reconfigured die module fabricated according to a FOWLP process, which allows D2D interconnect structure 202 to be more easily built on die module 214 in one or more metallization layers as part of the manufacturing process of split-die IC package 200. For example, D2D interconnect structure 202 can include one or more metallization layers 244(1)-244(3), which are RDLs 246(1)-246(3), each of which includes metal interconnects 248(1)-248(3) (e.g., metal lines, metal traces, vertical interconnect access (vias), pads). For example, if metallization layers 244(1)-244(3) are RDLs 246(1)-246(3), it may be easier to achieve a smaller L / S ratio in metal interconnects 248(1)-248(3) in metallization layers 244(1)-244(3). For example, the L / S ratio of metal interconnects 248(1)-248(3) may be 2 / 2 or 1 / 1. As an example, height H3 of die interconnects 210(1), 210(2) may be 30-40 micrometers (μm), the height of each of RDLs 246(1)-246(3) may be 7 μm or less, and metal interconnects 248(1)-248(3) may have an L / S ratio of 2 / 2 or less.

[0026] The first die 206(1), and more particularly the D2D interface circuitry 234(1), may be coupled to metal interconnects 248(1) in a first RDL 246(1) that is coupled to the D2D interconnect structure 202. The second die 206(1), and more particularly the D2D interface circuitry 234(2), may also be coupled to metal interconnects 248(1) in a first RDL 246(1) that is coupled to the D2D interconnect structure 202. In this manner, the D2D interface circuits 234(1), 234(2) may be coupled to each other for D2D communication via the D2D interconnect structure 202. To make connectivity more spatially efficient, the D2D interface circuits 234(1), 234(2) in the first and second die 206(1), 206(2) may be positioned above and / or overlap or partially overlap the die-to-substrate standoff cavity 204 in the vertical direction of the Z axis to provide connection to the D2D interconnect structure 202.

[0027] Figure 4 is a flow chart illustrating an example process 400 for manufacturing a split-die IC package that employs D2D interconnect structures in die-substrate standoff cavities to provide D2D connections, including but not limited to the example split-die IC package 200 of Figures 2A-3. Although the example process 400 of Figure 4 is described with respect to the split-die IC package 200 of Figures 2A-3 as an example, the process is also applicable to other split-die IC packages that employ D2D interconnect structures in die-substrate standoff cavities to provide D2D connections.

[0028] In this regard, with reference to Figure 4, a first manufacturing step includes forming a die module 214 comprising a first die 206(1) including an active surface 236, a first active surface 224(1) adjacent to the active surface 236, and a second die 206(2) including a second active surface 224(1) adjacent to the active surface 236, where the second die 206(2) is horizontally adjacent to the first die 206(1) (block 402 of Figure 4). The next manufacturing step in the process 400 includes forming a D2D interconnect structure 202 adjacent to the active surface 236 of the die module 214, where the D2D interconnect structure 202 includes a plurality of D2D interconnects 232 (block 404 of Figure 4). The next manufacturing step in the process 400 includes forming a first plurality of die interconnects 210(1) coupled to the first active surface 224(1) of the first die 206(1) (block 406 of FIG. 4). The next manufacturing step in the process 400 includes forming a second plurality of die interconnects 210(2) coupled to the second active surface 224(2) of the second die 206(2) to form a die-substrate standoff cavity 204 between the first plurality of die interconnects 210(1) and the second plurality of die interconnects 210(2), with the D2D interconnect structure 202 disposed within the die-substrate standoff cavity 204 (block 408 of FIG. 4). The next manufacturing step in the process 400 includes disposing the active surface 236 of the die module 214 on the package substrate 208 (block 410 of FIG. 4). Placing the active surface 236 of the die module 214 on the package substrate 208 includes bonding a first plurality of die interconnects 210(1) to the package substrate 208 (block 412 of FIG. 4) and bonding a second plurality of die interconnects 210(2) to the package substrate 208 (block 414 of FIG. 4).

[0029] 5A-5C are flow charts illustrating another exemplary process 500 for manufacturing a split-die IC package employing a D2D interconnect structure in a die-substrate standoff cavity to provide D2D connections, including but not limited to the exemplary split-die IC package of FIGS. 2A-3. FIGS. 6A-6H illustrate exemplary manufacturing stages 600A-600H of a split-die IC package employing a D2D interconnect structure in a die-substrate standoff cavity to provide D2D connections according to the exemplary manufacturing process 500 of FIGS. 5A-5C. The manufacturing process 500 of FIGS. 5A-5C is described below in conjunction with the exemplary manufacturing stages 600A-600H of FIGS. 6A-6H.

[0030] In this regard, with reference to process 500 of FIG. 5A, a first step in the manufacturing of split-die IC package 200 may be to fabricate die module 214 as a reconfigured die module. As shown in manufacturing stage 600A of FIG. 6A, this includes providing a carrier 602 including a first surface 604 to form reconfigured die module 214 as a reconfigured wafer 606, and placing (and positioning) dies 206(1), 206(2) horizontally adjacent to one another in the X-axis direction on carrier 602 (block 502 of FIG. 5A). Carrier 602 provides a structure that allows for positioning and manipulation of dies 206(1), 206(2) to form die module 214. As described below, providing the die module 214 as a reconstituted wafer 606 may provide the ability to form the D2D interconnect structure 202 on the die module 214 adjacent to the active surfaces 224(1), 224(2) of the dies 206(1), 206(2) before the die module 214 is placed on the package substrate 208. For example, the D2D interconnect structure 202 may preferably be formed on the die module 214 as one or more RDLs, such as RDLs 246(1)-246(3) of FIG. 3. A temporary adhesive film 608 may be disposed on the first surface 604 of the carrier 602 before the dies 206(1), 206(2) are placed on the adhesive film 608 to provide an adhesive for securely attaching the dies 206(1), 206(2) to the carrier 602.

[0031] As shown in next manufacturing stage 600B of FIG. 6B, the next step in forming the die module 214 as a reconstituted wafer 606 is to dispose an overmold compound 216 (e.g., an epoxy mold) on the first surface 604 of the carrier and on and above the first and second backside surfaces 226(1), 226(2) of the respective first and second dies 206(1), 206(2) to secure the dies 206(1), 206(2) and provide dielectric isolation for the dies 206(1), 206(2) (block 504 of FIG. 5A). As shown in next manufacturing stage 600C of FIG. 6C, the next step in forming die module 214 as reconstituted wafer 606 is to grind top surface 612 (FIG. 6B) of overmold compound 216 down to back surfaces 226(1), 226(2) of dies 206(1), 206(2) down to surface 614 reduced to desired thickness D2 (block 506 of FIG. 5A). Alternatively, overmold compound 216 can be ground down to back surfaces 226(1), 226(2) of dies 206(1), 206(2).

[0032] As shown in next manufacturing stage 600D of FIG. 6D , the next step is to remove carrier 602 from reconfigured wafer 606 and attach a second carrier 616 to reconfigured wafer 606 adjacent backsides 226(1), 226(2) of dies 206(1), 206(2) (block 508 of FIG. 5B ). Removing carrier 602 exposes active surfaces 224(1), 224(2) of dies 206(1), 206(2), and more particularly D2D interface circuitry 234(1), 234(2), to prepare D2D interconnect structure 202 formed on reconfigured wafer 606 and coupled to active surfaces 224(1), 224(2) of dies 206(1), 206(2) and D2D interface circuitry 234(1), 234(2) of dies 206(1), 206(2). As shown in FIG. 6D , to secure the reconstructed wafer 606 to the second carrier 616, an adhesive layer 618 can first be placed on the second carrier 616 before the reconstructed wafer 606 is attached to the second carrier 616.

[0033] Next, as shown in FIG. 6E, the next step is to form the D2D interconnect structure 202 on a portion of the first active surface 224(1) of the first die 206(1) and a portion of the second active surface 224(2) of the second die 206(2) in an area that will be formed as the die-substrate standoff cavity 204 in a later manufacturing stage (block 510 in FIG. 5B). The D2D interconnect structure 202 is disposed vertically adjacent in the Z-axis direction to the horizontal die isolation region 212 between the first die 206(1) and the second die 206(2). The manufacturing stage 600E shows that a first RDL 246(1) coupled to the D2D interface circuits 234(1), 234(2) of the dies 206(1), 206(2) is formed on the reconstructed wafer 606 as part of the D2D interconnect structure 202. As shown in a next manufacturing stage 600F in FIG. 6F, additional RDL(s) 246(2) may be formed on the first RDL 246(1) to form part of the D2D interconnect structure 202 (block 512 in FIG. 5B). The formation of the RDLs 246(1), 246(2) in this example may include a conventional process for forming RDLs, including providing a coating layer on the die module 214, removing portions of the coating by a patterning process to expose die pads for the D2D interface circuitry 234(1), 234(2), depositing a seed layer, and performing a lithography process to form metal interconnects in the RDLs 246(1), 246(2). A solder resist layer 620 may also be formed over the D2D interconnect structure 202 when fully constructed to protect the RDLs 246(1), 246(2) from solder exposure when forming the die interconnects 210(1), 210(2).

[0034] As shown in next manufacturing stage 600G of FIG. 6G, the next step is to form die interconnects 210(1), 210(2) on reconstructed wafer 606 in contact with die 206(1), 206(2) (block 514 of FIG. 5C). This includes forming metal pillars 238(1), 238(2) and interconnect bumps 240(1), 240(2). As described above, this forms die standoff regions 228 in the areas between die interconnects 210(1), 210(2) when die module 214 is formed from reconstructed wafer 606. The cavity formed by die standoff regions 228 between die module 214 and package substrate 208 (FIGS. 2B and 3) forms die-to-substrate standoff cavity 204 that retains room and space for D2D interconnect structure 202 to reside in final split-die IC package 200 without having to consume area in package substrate 208. If multiple die modules 214 are formed as part of reconstituted wafer 606, die singulation can be used to separate the die modules 214. As shown in next manufacturing stage 600H of FIG. 6H, the next step is to remove second carrier 616 and place active surface 236 of die module 214 onto package substrate 208 and bond die interconnects 210(1), 210(2) to package substrate 208 to form split-die IC package 200 (block 516 of FIG. 5C).

[0035] Split-die IC package(s) employing D2D interconnect structures within die-substrate standoff cavities to provide D2D connections, including but not limited to the exemplary split-die IC packages of Figures 2A-3 and according to the exemplary manufacturing processes of Figures 4-6H, may be provided in or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communications devices, fixed position data units, mobile position data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0036] In this regard, FIG. 7 illustrates an example of a processor-based system 700. A component of the processor-based system 700 is an IC 702. Some or all of the IC 702 in the processor-based system 700 may be provided in a split-die IC package(s) 704, including but not limited to the example split-die IC packages of FIGS. 2A-3, and employing D2D interconnect structures in die-substrate standoff cavities (i.e., cavities) to provide D2D connections, according to the example manufacturing processes of FIGS. 4-6H, and according to any aspect disclosed herein. In this example, the processor-based system 700 may be formed as a split-die IC package 704 and as a system-on-chip (SoC) 706. The processor-based system 700 includes a CPU 708 including one or more processors 710, which may be referred to as CPU cores or processor cores. The CPU 708 may have a cache memory 712 coupled to the CPU 708 for quick access to temporarily stored data. The CPU 708 is coupled to a system bus 714, which may interconnect master and slave devices included in the processor-based system 700. As is well known, the CPU 708 communicates with these other devices by exchanging address, control, and data information over the system bus 714. For example, the CPU 708 may communicate bus transaction requests to a memory controller 716, which is an example of a slave device. Although not shown in FIG. 7, multiple system buses 714 may be provided, with each system bus 714 constituting a different fabric.

[0037] Other master and slave devices may be connected to the system bus 714. As shown in FIG. 7, these devices may include, by way of example, a memory system 720 including a memory controller 716 and memory array(s) 718, one or more input devices 722, one or more output devices 724, one or more network interface devices 726, and one or more display controllers 728. Each of the memory system 720, the one or more input devices 722, the one or more output devices 724, the one or more network interface devices 726, and the one or more display controllers 728 may be provided in the same or different IC packages. The input device(s) 722 may include any type of input device including, but not limited to, input keys, switches, voice processors, and the like. The output device(s) 724 may include any type of output device including, but not limited to, audio, video, other visual indicators, and the like. The network interface device(s) 726 may be any device configured to be able to exchange data with the network 730. The network 730 can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a Bluetooth network, and the Internet. The network interface device(s) 726 can be configured to support any type of communication protocol, as desired.

[0038] The CPU 708 may also be configured to access a display controller(s) 728 through the system bus 714 to control information sent to one or more displays 732. The display controller(s) 728 send information to be displayed to the display(s) 732 via one or more video processors 734, which process the information to be displayed into a format suitable for the display(s) 732. The display controller(s) 728 and the video processor(s) 734 may be included in the same or different IC package as the split die IC package 704, and may be included in the same or different IC package that includes the CPU 708, as an example. The display(s) 732 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

[0039] FIG. 8 illustrates an exemplary wireless communication device 800 including a radio frequency (RF) component formed from one or more ICs 802, any one of which may include split-die IC package(s) 803 employing a D2D interconnect structure within a die-substrate standoff cavity (i.e., cavity) to provide D2D connectivity, including, but not limited to, the exemplary split-die IC packages of FIGS. 2A-3 according to the exemplary manufacturing process of FIGS. 4-6H and according to any aspect disclosed herein. The wireless communication device 800 may include or be provided within any of the above-mentioned devices, as examples. As shown in FIG. 8, the wireless communication device 800 includes a transceiver 804 and a data processor 806. The data processor 806 may include a memory for storing data and program codes. The transceiver 804 includes a transmitter 808 and a receiver 810 supporting bidirectional communication. In general, the wireless communication device 800 may include any number of transmitters 808 and / or receivers 810 for any number of communication systems and frequency bands. All or a portion of the transceiver 804 may be implemented on one or more analog ICs, RFICs, mixed-signal ICs, etc.

[0040] The transmitter 808 or receiver 810 may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In a super-heterodyne architecture, the signal is frequency converted between RF and baseband in multiple stages, e.g., in the receiver 810, the signal is frequency converted from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct-conversion architecture, the signal is frequency converted between RF and baseband in one stage. The super-heterodyne architecture and the direct-conversion architecture may use different circuit blocks and / or have different requirements. In the wireless communication device 800 in FIG. 8, the transmitter 808 and the receiver 810 are implemented using a direct-conversion architecture.

[0041] On the transmit path, a data processor 806 processes data to be transmitted and provides I and Q analog output signals to a transmitter 808. In the example wireless communications device 800, the data processor 806 includes digital-to-analog converters (DACs) 812(1) and 812(2) to convert digital signals generated by the data processor 806 into I and Q analog output signals, e.g., I and Q output currents, for further processing.

[0042] Within the transmitter 808, low pass filters 814(1) and 814(2) filter the I and Q analog output signals, respectively, to remove unwanted signals generated by previous digital-to-analog conversion. Amplifiers (AMPs) 816(1), 816(2) amplify the signals from low pass filters 814(1), 814(2), respectively, and provide I and Q baseband signals. An upconverter 818 upconverts the I and Q baseband signals with I and Q TX LO signals from a transmit (TX) local oscillator (LO) signal generator 822 through mixers 820(1), 820(2) to provide an upconverted signal 824. A filter 826 filters the upconverted signal 824 to remove unwanted signals generated by frequency upconversion and noise in the receive frequency band. A power amplifier (PA) 828 amplifies the upconverted signal 824 from filter 826 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 830 and transmitted via an antenna 832.

[0043] In the receive path, an antenna 832 receives a signal transmitted by a base station and provides a received RF signal, which is routed through a duplexer or switch 830 and provided to a low noise amplifier (LNA) 834. The duplexer or switch 830 is designed to operate at a particular RX to TX duplexer frequency separation such that the receive (RX) signal is separated from the TX signal. The received RF signal is amplified by the LNA 834 and filtered by a filter 836 to obtain a desired RF input signal. Downconversion mixers 838(1), 838(2) mix the output of the filter 836 with I and Q RX LO signals (i.e., LO_I and LO_Q) from a RX LO signal generator 840 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 842(1), 842(2) and further filtered by low pass filters 844(1), 844(2) to obtain I and Q analog input signals, which are provided to data processor 806. In this example, data processor 806 includes analog-to-digital converters (ADCs) 846(1), 846(2) to convert the analog input signals to digital signals for further processing by data processor 806.

[0044] In the wireless communication device 800 of FIG. 8, a TX LO signal generator 822 generates I and Q TX LO signals used for frequency up-conversion, and a RX LO signal generator 840 generates I and Q RX LO signals used for frequency down-conversion. Each LO signal is a periodic signal having a particular fundamental frequency. A TX phase-locked loop (PLL) circuit 848 receives timing information from the data processor 806 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 822. Similarly, a RX PLL circuit 850 receives timing information from the data processor 806 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 840.

[0045] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or a combination of both. The memory disclosed herein may be of any type and size and may be configured to store any type of information desired. To clearly illustrate this compatibility, various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0046] The various example logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0047] Aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, which may be present in, for example, a random access memory (RAM), a flash memory, a read only memory (ROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, a base station, or a server.

[0048] It should also be noted that the operation steps described in any of the exemplary aspects herein are described to provide examples and explanations. The operations described may be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operation step may actually be performed in several different steps. In addition, one or more operation steps discussed in the exemplary aspects may be combined. It should be understood that the operation steps shown in the flow chart may be subject to many different modifications, as will be readily apparent to those skilled in the art. Those skilled in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0049] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0050] Example implementations are described in the following numbered aspects / clauses. 1. An integrated circuit (IC) package comprising: A package substrate; A first die; A second die; a first plurality of die interconnects coupled to the package substrate and to the first die, the first die forming a die standoff region between the first die and the package substrate; a second plurality of die interconnects disposed at the die standoff region and coupled to the package substrate and to the second die; a cavity formed in the die standoff region between the first plurality of die interconnects and the second plurality of die interconnects; a die-to-die (D2D) interconnect structure disposed within the cavity, the D2D interconnect structure including a plurality of D2D interconnects coupled to a first die and a second die; An IC package comprising: 2. The IC package of clause 1, wherein the plurality of D2D interconnects are not coupled to a package substrate. 3. The second die is horizontally adjacent to the first die in the horizontal direction; a first active surface of the first die disposed adjacent to the package substrate in a vertical direction perpendicular to the horizontal direction; a second active surface of the second die disposed adjacent to the package substrate in a vertical direction; 3. An IC package as defined in any of clauses 1 and 2. 4. The IC package of clause 3, wherein a height of the D2D interconnect structure in the vertical direction is less than a height of the die-to-substrate standoff cavity in the vertical direction. 5. The second die is horizontally adjacent to the first die at a separation distance that forms a horizontal die separation region between the first die and the second die; the die-to-substrate standoff cavity is disposed vertically partially adjacent to the horizontal die isolation region; 5. An IC package as defined in any of clauses 3 and 4. 6. The IC package of any of clauses 3-5, wherein a height of the first plurality of die interconnects and the second plurality of die interconnects in the vertical direction defines a height of the cavity in the vertical direction. 7. An IC package as described in any of clauses 3-6, wherein the D2D interconnect structure comprises a redistribution layer (RDL) including at least one metal interconnect coupled to the first die and the second die. 8. The IC package of clause 7, wherein the RDL comprises a plurality of metal interconnects having a line-space (L / S) ratio of 2 / 2 or less. 9. The height of the first plurality of die interconnects and the second plurality of die interconnects is between 30 and 40 micrometers (μm); The height of the RDL is 7 μm or less. the RDL comprises a plurality of metal interconnects having a line-space (L / S) ratio of 2 / 2 or less; 10. An IC package as claimed in any of clauses 7 and 8. 10. A first die has a first active surface and a first back surface; the second die has a second active surface and a second back surface; a first plurality of die interconnects coupling the first active surface of the first die to the package substrate; a second plurality of die interconnects coupling the second active surface of the second die to the package substrate; 10. An IC package according to any one of clauses 1 to 9. 11. The method further comprising the steps of: an active surface adjacent to a package substrate; a first die including a first active surface and a first back surface in an active surface; a second die including a second active surface in the active surface and a second back surface; a mold compound disposed adjacent to a first back surface of the first die and adjacent to a second back surface of the second die; Equipped with 11. An IC package according to any one of clauses 1 to 10. 12. The second die is horizontally adjacent to the first die at a separation distance that forms a horizontal die separation region between the first die and the second die; the first die comprises a first D2D interface circuit horizontally adjacent the horizontal die isolation region; the second die comprises a second D2D interface circuit horizontally adjacent to the horizontal die isolation region; the first D2D interface circuit is coupled to the D2D interconnect structure; a second D2D interface circuit coupled to the D2D interconnect structure; the D2D interconnect structure coupling the first D2D interface circuit to the second D2D interface circuit; 12. An IC package according to any one of clauses 1 to 11. 13. A D2D interconnect structure comprising one or more metallization layers each including one or more metal interconnects; the first die is coupled to one or more metal interconnects in one or more metallization layers of the D2D interconnect structure; the second die is coupled to one or more metal interconnects in one or more metallization layers of the D2D interconnect structure; An IC package as described in clause 12. 14. The one or more metallization layers include one or more redistribution layers (RDLs) each including one or more metal interconnects; the first die is coupled to one or more metal interconnects in one or more RDLs of the D2D interconnect structure; the second die is coupled to one or more metal interconnects in one or more RDLs of the D2D interconnect structure; An IC package as described in clause 13. 15. The second die is horizontally adjacent to the first die in the horizontal direction; the first device-to-device interface circuit is disposed above the cavity in a vertical direction perpendicular to the horizontal direction; the second D2D interface circuit is disposed above the cavity in a vertical direction; 15. An IC package according to any one of clauses 12 to 14. 16. The first plurality of die interconnects includes a plurality of metal pillars; the second plurality of die interconnects include a plurality of metal pillars; 16. An IC package according to any one of clauses 1 to 15. 17. The package substrate includes one or more metallization layers each including a plurality of metal interconnects; the first plurality of die interconnects are coupled to one or more metal interconnects of the plurality of metal interconnects in the package substrate; the second plurality of die interconnects are coupled to one or more metal interconnects of the plurality of metal interconnects in the package substrate; 17. An IC package according to any one of clauses 1 to 16. 18. The IC package of any of clauses 1 to 17 incorporated into a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a Global Positioning System (GPS) device, a mobile phone, a cellular phone, a smartphone, a Session Initiation Protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter. 19. A method of manufacturing an integrated circuit (IC) package, comprising: forming a die module comprising: a first die including an active surface, a first active surface adjacent to the active surface, and a second die including a second active surface adjacent to the active surface, the second die being horizontally adjacent to the first die; forming a die-to-die (D2D) interconnect structure adjacent to an active surface of the die module, the D2D interconnect structure including a plurality of D2D interconnects; forming a first plurality of die interconnects coupled to a first active surface of the first die; forming a second plurality of die interconnects coupled to a second active surface of the second die to form a cavity between the first plurality of die interconnects and the second plurality of die interconnects, wherein the D2D interconnect structure is disposed in the cavity; disposing an active surface of the die module on a package substrate; Coupling the first plurality of die interconnects to a package substrate; Coupling the second plurality of die interconnects to a package substrate; and A method comprising: 20. The method of clause 19, further comprising not coupling the plurality of D2D interconnects to a package substrate. 21. Forming a D2D interconnect structure comprises: horizontally coupling a first D2D interface circuit in a first die to a D2D interconnect structure; coupling a second D2D interface circuit in the second die to the D2D interconnect structure to couple the second D2D interface circuit to the first D2D interface circuit; 21. The method of any of clauses 19 and 20, further comprising: 22. Forming a die module comprises: Providing a carrier including a first surface; disposing a first die on a first surface of the carrier; disposing a second die horizontally adjacent to the first die on the first surface of the carrier; Including, 22. The method according to any one of clauses 19 to 21. 23. Forming a die module comprises: Applying an adhesive film to a first surface of the carrier. Further comprising: disposing the first die on the first surface of the carrier includes disposing the first die on an adhesive film; disposing the second die on the first surface of the carrier includes disposing the second die horizontally adjacent to the first die on the adhesive film; The method described in clause 22. 24. The method of any of clauses 22 and 23, further comprising disposing an overmold compound on the first surface of the carrier and on the first back surface of the first die and the second back surface of the second die. 25. The method of claim 24, further comprising grinding a top surface of the overmold compound toward the first back surface of the first die and the second back surface of the second die. 26. Removing the carrier from the die module; attaching a second carrier to the die module adjacent to the first backside of the first die and the second backside of the second die; Further comprising: 26. The method according to any of clauses 24 and 25. 27. The method of clause 26, further comprising forming a D2D interconnect structure on a portion of the first active surface of the first die and on a portion of the second active surface of the second die within the cavity. 28. The method of clause 27, wherein the D2D interconnect structure is disposed vertically adjacent to a horizontal die isolation region between the first die and the second die. 29. Forming a D2D interconnect structure includes: forming a first redistribution layer (RDL) on a first active surface of the first die and on a second active surface of the second die within the cavity; forming one or more additional RDLs on the first RDL; Including, 29. The method according to any of clauses 27 and 28. 30. The method of any of clauses 27-29, further comprising removing the second carrier from the die module. 31. The method of any of clauses 27-30, further comprising coupling the first plurality of die interconnects and the second plurality of die interconnects to a package substrate. [Explanation of symbols]

[0051] 100 Split Die IC Package 102 D2D Interposer 104 Package Substrate 106(1), 106(2) Semiconductor Dies 108 Die Separation Area 110 External interconnect 112 Die Interconnect 114 Metal Pillar 116(1), 116(2) Active surface 118 Solder joint 120 D2D Interconnect 200 Split Die IC Package 202 D2D Interconnect Structure 204 Die-Substrate Standoff Cavity 206(1), 206(2) Semiconductor Dies 208 Package Substrate 210, 210(1), 210(2) Die interconnects 211 External interconnection 212 Die Separation Area 214 Die Module 216 Overmolding Compound 218 Reconstructed Wafer 220 Dielectric layer 222 Packaging Compound 224(1), 224(2) Active surface 226(1), 226(2) back side 228 Die Standoff Area 232 D2D Interconnect 234(1), 234(2) D2D interface circuit 236 Active Surface 238(1), 238(2) Metal pillar 240(1), 240(2) Interconnect Bumps 242(1)~242(3) Metallization Layer 243(1)~243(3) Metallic interconnects 244(1)~244(3) Metallization Layer 246(1)~246(3) RDL 248(1)~248(3) Metallic interconnects 602 Career 604 First Surface 606 Reconstructed Wafer 608 Adhesive Film 612 Top 614 Reduced Surface 616 Second Career 618 Adhesive layer 620 Solder resist layer 700 processor-based systems 702 IC 704 Split Die IC Package 706 System on Chip (SoC) 708 CPU 710 Processor 712 Cache Memory 714 System Bus 716 Memory Controller 718 Memory Array 720 Memory System 722 Input Devices 724 output device 726 Network Interface Device 728 Display Controller 730 Network 732 Display 734 Video processor 800 Wireless communication device 802 IC 803 Split Die IC Package 804 Transceiver 806 Data Processor 808 Transmitter 810 Receiver 812(1), 812(2) Digital-to-Analog Converter (DAC) 814(1), 814(2) Low-pass filter 816(1), 816(2) Amplifier (AMP) 818 Upconverter 820(1), 820(2) Mixer 822 Transmit (TX) Local Oscillator (LO) Signal Generator 824 upconverted signal 826 Filters 828 Power Amplifier (PA) 830 Duplexer or Switch 832 Antenna 834 Low Noise Amplifier (LNA) 836 Filters 838(1), 838(2) Downconversion Mixers 840 RX LO Signal Generator 842(1), 842(2) AMP 844(1), 844(2) Low-pass Filter 846(1), 846(2) Analog-to-Digital Converter (ADC) 848 TX Phase Locked Loop (PLL) Circuit 850 RX PLL circuit

Claims

1. An integrated circuit, IC, package comprising: a package substrate; a first die including a first active surface and a first back surface, wherein the first active surface of the first die is disposed adjacent to the package substrate in a vertical direction orthogonal to the horizontal direction; a second die including a second active surface and a second back surface, wherein the second active surface of the second die is disposed adjacent to the package substrate in the vertical direction, and the second die is horizontally adjacent to the first die with a separation distance forming a horizontal die separation region between the first die and the second die; the first die comprising a first D2D interface circuit horizontally adjacent to the horizontal die separation region; the second die comprising a second D2D interface circuit horizontally adjacent to the horizontal die separation region; a second die; a first plurality of die interconnects coupling the first active surface of the first die to the package substrate and forming a die standoff region between the first die and the package substrate; a second plurality of die interconnects disposed in the die standoff region and coupling the second active surface of the second die to the package substrate; a cavity formed within the die standoff region between the first plurality of die interconnects and the second plurality of die interconnects; a die-to-die, D2D, interconnect structure disposed within the cavity and including a plurality of D2D interconnects coupled to the first die and the second die, the plurality of D2D interconnects not being coupled to the package substrate; comprising; the first D2D interface circuit being coupled to the D2D interconnect structure, the second D2D interface circuit being coupled to the D2D interconnect structure, and the D2D interconnect structure coupling the first D2D interface circuit to the second D2D interface circuit; the first D2D interface circuit being disposed above the cavity in the vertical direction orthogonal to the horizontal direction, and the second D2D interface circuit being disposed above the cavity in the vertical direction; an IC package.

2. The height of the D2D interconnect structure in the vertical direction is smaller than the height of the cavity in the vertical direction, the IC package according to claim 1.

3. The second die is horizontally adjacent to the first die with a separation distance that forms a horizontal die separation region between the first die and the second die, The cavity is disposed adjacent to the horizontal die separation region partially in the vertical direction. The IC package according to claim 1.

4. The height of the first plurality of die interconnect portions and the second plurality of die interconnect portions in the vertical direction defines the height of the cavity in the vertical direction, the IC package according to claim 1.

5. The D2D interconnect structure includes a redistribution layer, RDL, including at least one metal interconnect portion coupled to the first die and the second die, the IC package according to claim 1.

6. Further comprising a reconfigured die module, wherein the reconfigured die module An active surface adjacent to the package substrate, The first die including a first active surface and a first back surface on the active surface, The second die including a second active surface and a second back surface on the active surface, A mold compound disposed adjacent to the first back surface of the first die and the second back surface of the second die, Comprising The IC package according to claim 1.

7. The D2D interconnect structure includes one or more metallization layers each including one or more metal interconnect portions, The first die is coupled to one or more metal interconnect portions within the one or more metallization layers of the D2D interconnect structure, The second die is coupled to one or more metal interconnect portions within the one or more metallization layers of the D2D interconnect structure, The one or more metallization layers each include one or more redistribution layers, RDL, each including one or more metal interconnect portions, The first die is coupled to one or more metal interconnect portions within the one or more RDLs of the D2D interconnect structure, The second die is coupled to one or more metal interconnect portions within the one or more RDLs of the D2D interconnect structure. The IC package according to claim 1.

8. The first plurality of die interconnects includes a plurality of metal pillars, The second plurality of die interconnects includes a plurality of metal pillars, The IC package according to claim 1.

9. The package substrate comprises one or more metallization layers each including a plurality of metal interconnects, The first plurality of die interconnects are coupled to one or more of the metal interconnects among the plurality of metal interconnects in the package substrate, The second plurality of die interconnects are coupled to one or more of the metal interconnects among the plurality of metal interconnects in the package substrate, The IC package according to claim 1.

10. An IC package incorporated in a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communication device, a fixed-position data unit, a mobile position data unit, a global positioning system, GPS, device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol, SIP, phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant, PDA, a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc, DVD, player, a portable digital video player, an automobile, vehicle parts, an avionics system, a drone, and a multicopter. The IC package according to claim 1.

11. A method of manufacturing an integrated circuit, IC, package, Forming a die module comprising a first die including an active surface and a first active surface adjacent to the active surface, and a second die including a second active surface adjacent to the active surface, the second die being horizontally adjacent to the first die with a separation distance forming a horizontal die separation region between the first die and the second die, The first die comprises a first D2D interface circuit horizontally adjacent to the horizontal die separation region, The second die includes a second D2D interface circuit that is horizontally adjacent to the horizontal die separation region, and forming a die-to-die, D2D, interconnect structure adjacent to the active surface of the die module, the D2D interconnect structure including a plurality of D2D interconnect portions; forming a first plurality of die interconnect portions coupled to the first active surface of the first die; forming a second plurality of die interconnect portions coupled to the second active surface of the second die, and forming a cavity between the first plurality of die interconnect portions and the second plurality of die interconnect portions, the D2D interconnect structure being disposed within the cavity; the first D2D interface circuit is disposed above the cavity in a vertical direction orthogonal to the horizontal direction, and the second D2D interface circuit is disposed above the cavity in the vertical direction; and placing the active surface of the die module on a package substrate; coupling the first plurality of die interconnect portions to the package substrate; coupling the second plurality of die interconnect portions to the package substrate; not coupling the plurality of D2D interconnect portions to the package substrate; including; including Forming the D2D interconnect structure includes coupling the first D2D interface circuit within the first die to the D2D interconnect structure; coupling the second D2D interface circuit within the second die to the D2D interconnect structure and coupling the second D2D interface circuit to the first D2D interface circuit; a method including.

12. Forming the die module includes providing a carrier including a first surface; placing the first die on the first surface of the carrier; placing the second die horizontally adjacent to the first die on the first surface of the carrier; including; The method according to claim 11.

13. Forming the die module further includes applying an adhesive film to the first surface of the carrier including further. Placing the first die on the first surface of the carrier includes placing the first die on the adhesive film. Placing the second die on the first surface of the carrier includes placing the second die horizontally adjacent to the first die on the adhesive film. The method according to claim 12.

14. The method according to claim 12, further comprising placing an overmold compound on the first surface of the carrier and on the first back surface of the first die and on the second back surface of the second die.

15. The method according to claim 14, further comprising grinding the upper surface of the overmold compound toward the first back surface of the first die and the second back surface of the second die.

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