Optical interference protection element for joint structures.

Abstract

An optical occlusion protection element for a bonded structure, embodiments disclosed herein relate to structures directly bonded along a bond interface. Specifically, two elements, a semiconductor element and an occluding element, can be directly bonded together along a bond interface without an intervening adhesive. The semiconductor element includes an active circuit that is protected by the occluding element after bonding. The occluding element includes a plurality of optical occlusion layers arranged to prevent optical interrogation of the active circuit. Such layers can further include occlusion strips that may or may not overlap with other occlusion strips from other occlusion layers when the occlusion layers are stacked vertically.

Description

[Technical field]

[0001] The present invention relates to optical interference protection elements for bonded structures and methods of forming the same. [Background technology]

[0002] A semiconductor chip (e.g., an integrated device die) may contain active circuitry including security-sensitive components that contain valuable and / or proprietary information, structures, or devices. For example, such security-sensitive components may include an entity's intellectual property, software or hardware security (e.g., encryption) features, privacy data, or any other components or data that an entity desires to keep safe and hidden from third parties. For example, third party bad actors may attempt to gain access to security-sensitive components using various techniques for economic and / or geopolitical advantage. Thus, there is a continuing need to improve the security of semiconductor chips to prevent access by third parties. Summary of the Invention [Means for solving the problem]

[0003] Disclosed herein is a bonded structure including a semiconductor element including an active circuit and a disturbing element bonded directly to the semiconductor element along a bond interface without the use of an adhesive, the disturbing element including at least one patterned optically occlusive layer disposed over the active circuit to disturb optical reading of the active circuit. In some embodiments, the at least one patterned optically occlusive layer includes a plurality of optically occlusive layers. In some embodiments, the plurality of optically occlusive layers are disposed in an overlapping manner and spaced apart from one another along a direction transverse to the bond interface. In some embodiments, each optically occlusive layer of the plurality of optically occlusive layers includes a non-conductive layer and a patterned opaque material at least partially embedded in the non-conductive layer. In some embodiments, the patterned opaque material includes a plurality of occlusion strips extending along a direction generally parallel to the bond interface. In some embodiments, the plurality of occlusion strips includes one or more conductive materials. In some embodiments, the one or more conductive materials include copper. In some embodiments, the patterned opaque material includes a material that blocks light at wavelengths in the range of 400 nm to 1 mm. In some embodiments, the patterned opaque material includes a material that blocks light with wavelengths in the range of 800 nm to 2500 nm, hi some embodiments, the patterned opaque material is opaque to at least one of infrared light (IR) or near infrared light (NIR).

[0004] In some embodiments, a first optically occluding layer of the plurality of optically occluding layers includes a first opaque pattern and a second optically occluding layer of the plurality of optically occluding layers includes a second opaque pattern that is at least partially non-overlapping with the first opaque pattern, such that in a top view of the occluding element, the first and second opaque patterns occlude a larger portion of the semiconductor element than the first and second opaque patterns alone. In some embodiments, the first opaque pattern includes a first plurality of occluding strips and the second opaque pattern includes a second plurality of occluding strips that are at least partially non-overlapping with the first plurality of occluding strips. In some embodiments, the occluding element further includes at least three optically occluding layers, the patterned occluding material occluding a predetermined area of ​​the semiconductor element in a plane parallel to the optically occluding layers. In some embodiments, the optically occluding layer is configured to provide at least 75% occlusion over the predetermined area. In some embodiments, the optically occluding layer is configured to provide at least 95% occlusion over the predetermined area. In some embodiments, the predetermined area includes at least 75% of the bonding surface of the first semiconductor element. In some embodiments, the predetermined area includes at least 95% of the bonding surface of the first semiconductor element.

[0005] In some embodiments, the semiconductor device has at least one sensitive circuit area and at least one area that does not include sensitive circuitry, and the patterned opaque material occludes at least a portion of the at least one sensitive circuit area and leaves unoccluded the at least one area that does not include sensitive circuitry. In some embodiments, the multiple optically occluding layers include one or more optical filtering layers. In some embodiments, the at least one patterned optically disruptive layer includes a material that refracts, scatters, diffuses, diffracts, or phase shifts light to disrupt optical reading of the active circuitry. In some embodiments, the semiconductor device further includes a bonding layer, and the disruptive element further includes a bonding layer that is bonded directly to the bonding layer of the semiconductor device. In some embodiments, the bonding layer of the disruptive element is metallized to match the metallization pattern of the semiconductor device. In some embodiments, the bonding layer of the semiconductor device includes a plurality of contact pads disposed within the non-conductive layer, and the bonding layer of the disruptive element includes a plurality of contact pads disposed within the non-conductive layer and bonded directly to the contact pads of the semiconductor device. In some embodiments, the bonding layer of the disturbing element and the optically occluding layer vertically spaced apart from the bonding layer along a direction across the bonding interface are connected through at least one vertical interconnect. In some embodiments, at least two of the adjacent multiple occluding layers have no vertical interconnect between them. In some embodiments, the active circuit is disposed at or near the active side of the semiconductor device, and the disturbing element is directly bonded to the back side of the semiconductor device opposite the active side. In some embodiments, a first of the multiple optically occluding layers includes a detection circuit configured to detect an external access of the first occluding layer. In some embodiments, the detection circuit includes a passive electronic circuit element configured to detect an external access. In some embodiments, the passive electronic circuit includes a capacitive circuit element or a resistive circuit element. In some embodiments, the bonding structure further includes a vertical interconnect extending from the detection circuit to a contact pad of the disturbing element.In some embodiments, the interference element is directly bonded to the back surface of the semiconductor element opposite the active surface, and the bonding structure further includes a through-semiconductor via (TSV) extending from a contact pad at or near the active surface of the semiconductor element to a contact pad of the interference element, the TSV providing electrical communication between the semiconductor element and the detection circuit. In some embodiments, the contact pad of the interference element is directly bonded to the contact pad on the active surface of the semiconductor element. In some embodiments, one of the at least one optical interference layers further includes an optical filter.

[0006] Disclosed herein is a bonded structure including a semiconductor device including an active circuit and a disturbing element bonded directly to the semiconductor device along a bonding interface without the use of an adhesive, the disturbing element including a first disturbing layer and a second disturbing layer disposed over the first disturbing layer, the first disturbing layer having a first disturbing pattern and the second disturbing layer having a second disturbing pattern that does not at least partially overlap the first disturbing pattern. In some embodiments, the first and second disturbing patterns cooperate to disturb an optical reading of the active circuit in a top view of the disturbing element. In some embodiments, the disturbing pattern includes one or more conductive materials. In some embodiments, the one or more conductive materials include copper. In some embodiments, the patterned disturbing material includes a material that blocks light having a wavelength in the range of 700 nm to 1 mm. In some embodiments, the patterned disturbing material includes a material that blocks light having a wavelength in the range of 800 nm to 2500 nm. In some embodiments, the patterned disturbing material is opaque to at least one of infrared light (IR) or near infrared light (NIR). In some embodiments, the semiconductor device further includes a bonding layer, and the disturbing element further includes a bonding layer bonded directly to the bonding layer of the semiconductor device. In some embodiments, the bonding layer of the semiconductor device includes a plurality of contact pads disposed in the non-conductive layer, and the bonding layer of the disturbing element includes a plurality of contact pads disposed in the non-conductive layer and bonded directly to the contact pads of the semiconductor device. In some embodiments, the first disturbing layer further includes a detection circuit configured to detect an external access of the first disturbing layer. In some embodiments, the bonding structure includes a vertical interconnect extending from the detection circuit to the contact pad of the disturbing element. In some embodiments, the disturbing element is bonded directly to a back surface opposite the active surface of the semiconductor device, and the bonding structure further includes a through semiconductor via (TSV) extending from a contact pad at or near the active surface of the semiconductor device to the contact pad of the disturbing element, the TSV providing electrical communication between the semiconductor device and the detection circuit.

[0007] Disclosed herein is a method of forming a bonded structure, comprising directly bonding a semiconductor element to a disruptive element without the use of an adhesive, the semiconductor element comprising an active circuit, and the disruptive element comprising at least one patterned optical disruptive layer disposed over the active circuit to disrupt optical reading of the active circuit. In some embodiments, the method comprises forming the disruptive element such that a plurality of optical disruptive layers are spaced apart from one another along a direction across the bonded interface. In some embodiments, the method comprises forming the disruptive element such that each disruptive layer of the plurality of optical disruptive layers comprises a non-conductive layer and a patterned opaque material at least partially embedded in the non-conductive layer. In some embodiments, the method comprises forming the disruptive element such that the patterned opaque material comprises a plurality of occluding strips extending along a direction generally parallel to the bonded interface. In some embodiments, the method comprises forming the disruptive element such that the plurality of occluding strips comprise one or more metals. In some embodiments, the method further comprises forming the disruptive element such that the patterned opaque material comprises a material that blocks light at wavelengths in the range of 700 nm to 1 mm. In some embodiments, the method includes forming the obstructing elements such that the patterned opaque material includes a material that blocks light with wavelengths in the range of 800 nm to 2500 nm.

[0008] In some embodiments, the method includes forming the interference element to include a bonding layer, forming the semiconductor element to include a bonding layer, and bonding the bonding layer of the interference element to the bonding layer of the semiconductor element. In some embodiments, the method includes forming the interference element such that the bonding layer of the interference element is metallized to match a metallization pattern of the semiconductor element. In some embodiments, the method includes forming the interference element such that the bonding layer of the interference element includes a plurality of contact pads disposed in a non-conductive layer and configured to mirror a plurality of contact pads of the bonding layer of the semiconductor element. In some embodiments, the method includes forming the interference element such that a first interference layer of the plurality of optical interference layers includes a detection circuit configured to detect external access of the first interference layer. In some embodiments, the method includes forming the interference element to include a vertical interconnect extending from the detection circuit to the contact pads of the interference element. In some embodiments, the method includes directly bonding a disturbance element to a back surface of the semiconductor element diametrically opposite the active surface of the semiconductor element, the active circuitry of the semiconductor element being disposed at or near the active surface of the semiconductor element, and further including through-semiconductor vias (TSVs) extending from contact pads at or near the active surface of the semiconductor element to contact pads of the disturbance element, the TSVs providing electrical communication between the semiconductor element and the detection circuitry.

[0009] Disclosed herein is a bonding structure including a semiconductor device including an active circuit and a disturbing element directly bonded to the semiconductor device over the active circuit along a bonding interface without the use of adhesive, the disturbing element including a plurality of conductive layers, the plurality of conductive layers including a detection circuit for monitoring a passive electrical characteristic of the disturbing element, the detection circuit electrically communicating with the active circuit. In some embodiments, the active circuit is configured to detect a change in the passive electrical characteristic of the disturbing element. In some embodiments, the active circuit is configured to send an alert message to an external system or a user upon detecting a change in the passive electrical characteristic. In some embodiments, the passive electrical characteristic includes a capacitance of the disturbing element. In some embodiments, the plurality of conductive layers includes a first conductive layer, a second conductive layer, and a dielectric layer between the first and second conductive layers. In some embodiments, the disturbing element is directly bonded to a back side of the semiconductor device opposite a front side of the semiconductor device, the active circuit being disposed closer to the front side than the back side. In some embodiments, the bonding structure includes a through-substrate via (TSV) providing electrical communication between the active circuit and the detection circuit. In some embodiments, the plurality of conductive layers functions as an optical interference structure that interferes with optical reading of the active circuitry. In some embodiments, the plurality of conductive layers includes a first interference pattern and a second interference pattern that does not at least partially overlap the first interference pattern.

[0010] This specification discloses a joint structure including a semiconductor element having a front surface and a back surface opposite the front surface, the semiconductor element including an active circuit disposed closer to the front surface than the back surface, and a disturbance element bonded directly to the back surface of the semiconductor element over the active circuit along a bonding interface without the use of an adhesive, the disturbance element including a detection circuit that monitors a passive electrical characteristic of the disturbance element, the detection circuit electrically communicating with the active circuit. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is an example of near-infrared (NIR) imaging of a semiconductor chip. [Figure 2A] 1 is a schematic cross-sectional side view of a protection element having multiple blocking layers. [Figure 2B] 1 is a schematic cross-sectional side view of a protection element having multiple blocking layers. [Diagram 3] FIG. 2 is a schematic cross-sectional top view of a protective element showing overlapping of blocking layers. [Figure 4A] 2 is a schematic cross-sectional side view of a protective chip bonded to an active surface of an active chip. [Figure 4B] 1 is a schematic cross-sectional side view of a protection chip bonded to a passive surface of an active chip. [Figure 5A] 1 is a schematic cross-sectional side view of a protective chip incorporating an optical filter layer bonded to the active surface of the active chip. [Figure 5B] FIG. 1 is a schematic cross-sectional side view of a protection chip combining an optical filter layer bonded to the active surface of the active chip and an embedded random reflective pattern. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] As described herein, a third party (such as a third party malicious actor) may attempt to access security-sensitive components on a device such as an integrated device die. In some devices, security-sensitive components may be protected by a combination of netlist data and non-volatile memory (NVM) data. However, a third party may attempt to tamper with security-sensitive components by a combination of destructive and non-destructive techniques, such as probing and / or delaying the device to expose or otherwise access the security-sensitive components. In some cases, a third party may attempt to tamper with security-sensitive components by pulsing electromagnetic (EM) waves onto the active circuitry of the device, using fault injection techniques, triggering a near-infrared (NIR) laser or modifying the circuitry with a focused ion beam (FIB), chemical etching techniques, other physical, chemical, and / or electromagnetic hacking tools, and even reverse engineering. These techniques can be used to physically access sensitive circuits of microdevices, such as integrated circuits, to directly read encrypted information, externally trigger the circuits to release information that would have been encrypted, understand the manufacturing process, or ultimately extract enough information to clone the sensitive design. For example, in some cases, a hacker may attempt to access an encryption key that may be stored in the circuit design, memory, or a combination of both. Techniques may also be used to indirectly read sensitive information by analyzing the resulting output based on fault injection inputs and identifying the encryption key or data content through recursive analysis. It is difficult to structurally secure security-sensitive components on elements such as integrated device dies or chips.

[0013] Therefore, it is important to improve the security of elements (such as semiconductor integrated device dies) that include security-sensitive components. Various embodiments disclosed herein relate to bonded structures that include a first semiconductor element bonded to a second semiconductor element. The second semiconductor element can include a protection or obstruction element that includes at least one (e.g., multiple) patterned obstruction layers disposed over active circuitry of the first semiconductor element and configured to prevent optical interrogation or optical access of the active circuitry.

[0014] FIG. 1 illustrates a conventional approach to imaging a semiconductor device 100, for example, using a near-infrared (NIR) optical probe 126 to probe sensitive circuits of the semiconductor device 100. As illustrated in FIG. 1, optical probing techniques can be used to access the active circuits 116 of the semiconductor device 100. The optical probing techniques can allow an attacker to reconfigure the sensitive circuits to compromise the confidentiality and security of the sensitive circuits. Unlike the front side 114 of the semiconductor device 100, the optical probe 126 from the back side is not blocked by wiring or metallizations, so the optical probing techniques can be used to access the active circuits 116 from the back side 112 of the semiconductor device 100. The optical probe 126 includes a laser source 122, a beam splitter 120, a detector 124, and an objective lens 118. A laser source 122 can generate a laser beam and direct it to a beam splitter 120, which can split the beam into a first component that is directed through objective lens 118 to semiconductor device 100 and a second component that is directed to mirror 128 and detector 124. Back side optical intrusion techniques can also be used to monitor circuit activity and gather bitstream information to extract encryption keys and leak encrypted information.

[0015] Therefore, to ensure the security of semiconductor devices that contain security-sensitive components, it is important to prevent optical intrusion. A conventional technique may include packaging the semiconductor device 100 with an occluding casing. However, conventional packaging is susceptible to polishing, chemical etching, and other relatively simple removal processes that leave sensitive circuitry exposed and susceptible to optical probing. It may therefore be desirable to include protection against optical intrusion by directly bonding a protective or occluding element to the semiconductor device 100. The semiconductor device 100, such as an integrated device die or chip, may be mounted or stacked on other devices. For example, the semiconductor device 100 may be mounted on a carrier, such as a package substrate, an interposer, a reconfigured wafer, or a device. As another example, the semiconductor device 100 may be stacked on another semiconductor device 100, such as a first integrated device die on a second integrated device die. In some configurations, through-substrate vias (TSVs) may penetrate vertically through the thickness of the semiconductor device 100 to transfer electrical signals through the semiconductor device 100 from a first surface of the semiconductor device 100 to a second opposing surface of the semiconductor device 100, etc. Embodiments of the present disclosure relate to bonding structures that include a protective chip that includes a jamming layer bonded directly to an active chip that may include security-sensitive circuitry or circuit elements.

[0016] 2A-2B are side cross-sectional views of a protection chip 300 including at least one obstruction layer (also referred to herein as an obstruction chip). In the embodiment of FIG. 2A-2B, the at least one obstruction layer includes multiple stacked occlusion (e.g., light blocking) layers (layers L1-L4 101-104 shown in FIG. 2A and layers L1-L3 105-107 shown in FIG. 2B) according to various embodiments. Conventional light occlusion techniques outside the semiconductor industry typically include solid sheets or layers of metal or other occlusion material surrounding sensitive circuitry. However, a single occlusion layer may not be suitable for incorporation into a semiconductor device, particularly due to the different thermomechanical properties of the occlusion material and the semiconductor material. For example, if the semiconductor device includes a single blanket layer of metal (such as copper), a large continuous metal sheet may induce thermomechanical stresses during processing at high temperatures. Thus, in various processes, the maximum metal coverage of a typical complementary metal oxide semiconductor (CMOS) in a particular layer can be within the range of 15%-45%, 20%-40%, 22%-35%, or 25%-33% of the total area of ​​the layer to prevent destructive thermo-mechanical stresses between the materials.

[0017] To increase the degree of interference while limiting thermomechanical stresses, multiple layers can be arranged in the occlusion structure of the protection element or interference element (e.g., protection chip 300). FIG. 2A shows a cross-section of an example semiconductor element 300 formed from a four-layer semiconductor element, each layer being partially metallized. The illustrated layers can include multiple (e.g., four) patterned back-end-of-line layers, such as occlusion layers L1-L4 (101, 102, 103, and 104), each layer L1-L4 including a non-conductive material 110 (such as a dielectric material like silicon oxide or silicon nitride) and an occlusion (e.g., metal, opaque) strip 108 or other shaped pattern formed within the layer. In various embodiments that block an incident light beam, the strip 108 can include a conductive material, such as copper or any other suitable metal.

[0018] Thus, the occluding material (e.g., the opaque strip 108) can include a material that blocks the transmission of light (or a majority of light) through the obstructing chip 300. In embodiments utilizing an obstructing strip, the occluding material can include a material that is opaque to (e.g., absorbs or reflects) light at the wavelengths of the incident beam. For example, in the exemplary embodiment of FIG. 2A, the occluding strip 108 includes an opaque material such as a metal (e.g., copper in some embodiments). In other embodiments, the occluding material can include other types of materials that block or substantially block the transmission of light at the wavelength(s) of the incident beam(s). For example, in other embodiments, the patterned occluding material can include one or more filtering layers that transmit at least some light at one or more first wavelengths and block (e.g., through absorption and / or interference) at least some light at one or more second wavelengths. Thus, various obstructive optical materials can block (or substantially block) light using opaque materials or materials that filter light at various wavelengths. Additionally or alternatively, in some embodiments, the obstructive optical material can include optical materials that obstruct light in other ways. For example, in such embodiments, the obstructing material can change the direction of an incoming or outgoing beam (e.g., refract), focus or defocus (e.g., lens), scatter, spread, diffract (e.g., grating), phase / wavelength shift, etc. Thus, the optical obstructing material described herein refers to a light blocking or light modifying material that blocks or modifies incident light utilized in attempts to tamper with sensitive circuits. Some of the obstructing materials can include roughened materials to achieve the desired effects described above. As described herein in the context of the opaque occlusion strip 108, the obstructing material layer can be patterned to form at least one optical obstructing layer (e.g., multiple obstructing layers) that impede optical reading of the active circuitry.

[0019] In the example of FIG. 2A, the occlusion strips 108 may be disposed generally parallel to the mating surface of the cover element 300 such that they extend parallel to one another. In some embodiments, the strips 108 may extend across a majority of the width of the chip 300, such as across substantially the entire width of the chip 300, when viewed from a top view. As used herein, a patterned opaque material includes one or more occlusion strips 108 of a single occlusion layer (e.g., one of 101-104). In some embodiments, as described herein, the patterned opaque material of an occlusion layer includes occlusion strips 108 formed of a material that occludes (e.g., blocks) at least 90% of light in the range of 400 nm to 1 mm, at least 90% of light in the range of 800 nm to 2500 nm, such as at least 90% of near infrared (NIR) light. In various embodiments, the patterned opaque material of the occlusion layers 101-104 can block at least 95% or at least 99% of light in the range of 400 nm to 1 mm, at least 90% of light in the range of 800 nm to 2500 nm, such as at least 90% of near infrared (NIR) light. Additionally or alternatively, the patterned opaque material can block at least 90%, at least 95%, or at least 99% of infrared (IR) light or ultraviolet (UV) light. In such embodiments utilizing an optical interference material that includes an occlusion layer, the material can include an opaque layer (e.g., metal strip 108), one or more filtering layers, or any other light-blocking layer.

[0020] As discussed above, in other embodiments, the optical jamming material can include other types of light modifying materials, such as materials that refract, reflect, scatter, diffuse, or phase shift at least 90%, at least 95%, or at least 99% of light having wavelengths in the ranges of 400 nm to 1 mm, 800 nm to 2500 nm, near infrared (NIR), infrared (IR), or ultraviolet light. In embodiments utilizing a non-occlusive jamming material, at least a portion of the incident light can pass through the jamming element 300, impinge on the active circuit 116, and be reflected back through the jamming element 300. However, the non-occlusive jamming material can interact with the reflected light to modify the amplitude and / or phase of the light, thereby preventing an optical readout of the active circuit by the optical probe.

[0021] In the exemplary occlusion example of FIG. 2A, the occlusion pattern of strips 108 of layers 101-104 (or layers 102-104) can cooperate to form an optical obstruction structure that substantially or completely blocks a light beam used to probe active circuitry in the underlying active chip 310. For example, in some embodiments, the occlusion pattern can block 90%-100% or 95%-100% of light incident on the occluding (e.g., opaque) strips 108. For example, the strips 108 can be selected to be opaque to light, such as NIR light used in optical probes. The occluding layer, when provided in an at least partially non-overlapping manner as described herein, can substantially block light from probing techniques. Thus, a plurality of occluding or opaque strips 108 can be arranged such that, when viewed from a top view, the strips cooperate to form an optical obstruction structure that impedes (e.g., substantially prevents) light from impinging on sensitive circuitry, thus preventing optical reading of the active circuitry. Thus, each individual occluding layer (e.g., one of 101-104) is only partially occluding. For example, occluding layer 101 alone may block only 20%-40% of the incident light. However, when combined (e.g., FIGS. 2A-2B), the layers may form a substantially complete occluding element that blocks or suppresses most or all of the incident light and is opaque to light insertion. As shown in FIG. 2A, complete occlusion (e.g., occlusion) or substantially complete occlusion (e.g., occlusion) may be achieved when the maximum metal coverage per layer is about 25% of the total area of ​​each layer. Thus, in such an arrangement, four layers may be provided one on top of the other, with the optically occluding (e.g., opaque) strips 108 staggered to completely or substantially completely cover at least the sensitive circuitry of the underlying active chip when viewed from a top view. In some embodiments, the opaque strips 108 may cooperate to completely or substantially completely cover the entire active surface of the underlying chip, or the entire top surface of the underlying chip or die when viewed from a top view.In other embodiments, the opaque strips 108 may cooperate to completely or substantially completely cover sensitive portions of the active circuitry of the underlying chip when viewed from a top perspective.

[0022] Fewer layers may be used to achieve the same degree of occlusion with higher metal coverage. Unless otherwise indicated, the components of FIG. 2B may be the same or substantially similar to the same numbered components of FIG. 2A. For example, FIG. 2B shows a cross-section of an example semiconductor device 300 formed from three layers, where the metallization of each layer may cover up to 33% of the layer surface. The illustrated layers may include multiple (e.g., three) patterned back-end layers L1-L3 (105, 106, and 107), each layer L1-L3 including a non-conductive material 110 (such as a dielectric material such as silicon oxide or silicon nitride) and occluding (e.g., metal, opaque) strips 108 or other shaped patterns formed within the layers that cooperate to form a patterned optical interference material. As described in more detail below, metallization patterning may also be employed to achieve occlusion of sensitive areas while limiting the total metallization of the occluding elements 101-104. In some embodiments, the occluding material of the strip 108 can be a metal such as copper. In other embodiments, different occluding or obstructing materials can be used. In some embodiments, as described above, the materials can be selected to occlude (e.g., be opaque or reflective) or otherwise obstruct (e.g., select to refract, scatter, diffuse, phase shift, etc., at least 90%, at least 95%, or at least 99%) light with wavelengths in the range of 400 nm to 1 mm. In various embodiments, the materials can be selected to obstruct (e.g., block, refract, reflect, scatter, diffuse, phase shift, etc., at least 90%, at least 95%, or at least 99%) light with wavelengths in the range of 800 nm to 2500 nm. In various embodiments, the materials can be selected to obstruct near infrared (NIR), infrared, or ultraviolet light.

[0023] FIG. 3 is an overhead view of an exemplary embodiment of an optical interference semiconductor device 300 including layers 202 and 204. As shown in FIG. 3, the surface of each layer 202, 204 can be partially metallized with an interference layer including an occlusion strip 208 to provide an optical occlusion barrier. Furthermore, each layer can be metallized according to a different pattern. By way of example, the at least partially non-overlapping metallization patterns of the separate layers 202, 204 can be stacked together to form an overlapping (or substantially overlapping) occlusion barrier when viewed from above. For example, device 300 shows an overhead view of layers 202 and 204 with overlapping metallization patterns 208. In this manner, multiple partially metallized layers can be formed within a single protection semiconductor device 300 to provide a higher degree of occlusion than can be achieved with a single layer. It should be understood by those skilled in the art that the protection chip 300 shown in FIG. 3 is merely exemplary and other embodiments can have more than two layers. Other embodiments may also employ different metallization patterns 208 to achieve occlusion. For example, other complementary patterns of layers 202, 204 may be used, so long as the complementary patterns of layers 202, 204 substantially occlude at least the sensitive portions of the underlying active circuitry when viewed from a top perspective. In still other embodiments, such as those utilizing non-occluding obstruction materials, the obstruction materials may be patterned within a layer. For example, in embodiments that scatter, diffract, or diffuse light, the obstruction layers may be patterned such that at least some light passes through the obstruction element 300, is reflected or scattered from the active chip 310, and is absorbed or cancelled through interference from the patterned obstruction layer(s). Further examples of optical interference materials can be found throughout U.S. Patent Application No. 16 / 844,932, published as U.S. Patent Publication No. 2020 / 0328162 (including at least paragraphs

[0030] ,

[0036] ,

[0051] , and

[0066] -

[0067] ), the contents of which are incorporated by reference in their entirety and for all purposes.

[0024] Furthermore, in some embodiments, one or more of the blocking layers (e.g., the metallization pattern 208 of the blocking structure) may be irregular or cover only a portion of the area of ​​the chip 206. For example, an active chip may have sensitive circuitry that covers only a portion of the area of ​​the chip. To improve cost and performance characteristics, the protection chip 300 may be configured to block (e.g., block) only the sensitive portions of the active circuitry and not block (e.g., block or shield) other portions of the chip that do not contain circuitry or that contain non-sensitive circuitry. Furthermore, in some embodiments, complete blockage or blockage may not be necessary to thwart an optical probe attack. In these embodiments, the blocking layers (e.g., the blockage layers 202, 204) of the protection chip 300 may be configured to provide partial blockage or blockage of the sensitive areas of the bonded active chip. For example, an active chip that uses only partial blockage may be bonded to a protection chip 300 that includes overlapping blockage layers 202, 204 patterned by a low-precision, low-cost process. Thus, the less precision can provide sufficient partial occlusion area to provide the desired protection over the sensitive areas of the active chip at a lower cost per chip. For example, the occlusion layer can be configured to provide the desired protection over an area of ​​the active chip in the range of 50%-75%, 75%-95%, or 95%-100% of the sensitive circuit area, or in some embodiments, 50%-75%, 75%-95%, or 95%-100% of the total active area of ​​the chip 310.

[0025] FIG. 4A illustrates active-side bonding of the protective chip 300 and the active chip 310 prior to direct bonding across the bonding interface 315. Unless otherwise indicated, the components and functionality of the structure of FIG. 4A can be the same or generally similar to those of FIGS. 2A-3. As discussed above, non-bonded protective structures may be susceptible to removal via various removal techniques, such as grinding or etching. It may therefore be desirable to directly bond the protective chip 300 and the active chip 315 to form a bonded structure. In some embodiments, the bonding interface 315 may include a bond between a bonding layer 340A of the protective chip 300 and a bonding layer 340B of the active chip 310. In some embodiments, the direct bond may include a nonconductive non-adhesive bond in which nonconductive field regions 341A, 341B (e.g., dielectric materials) of the elements (e.g., the protective chip 300 and the active chip 310) are directly bonded together. In other embodiments, such as the embodiment shown in FIG. 4A, the direct bonding may include hybrid bonding, in which the contact pads 350B of the active chip 310 are directly bonded to the corresponding contact pads 350A of the protective chip 300, and the non-conductive regions (e.g., non-conductive field regions 341B) of the active chip 310 are directly bonded to the corresponding non-conductive regions (e.g., non-conductive field regions 341A) of the protective chip 300. As shown in FIG. 4A, the bonding layer 340A, 340B of each chip 300, 310 may include a plurality of contact pads 350A, B disposed on the non-conductive field regions 341A, 341B, such as a dielectric layer (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). In some embodiments, the field regions 341A, 341B may include the same material as the non-conductive layer 305. In other embodiments, the field regions 341A, 341B may include a different material than the non-conductive layer 304. The contact pads 350A,B may include a conductive material such as a metal, such as copper, prepared for direct hybrid bonding.In these embodiments, contact pads 350A of the protective chip 300 can be configured to mirror and / or correspond to contact pads 350B of the active chip 310. The pads can provide electrical and / or mechanical connections between the protective chip and the active chip. As used herein, pads can include exposed ends of through-substrate vias (TSVs) 330 or vertical interconnects 360 (e.g., designated as pads 350A), or discrete pads at least partially embedded in the field regions (e.g., designated as pads 350B).

[0026] As shown in FIG. 4A, the protective chip can include multiple occlusion layers 301-304, shown here as L1-L4. Each occlusion layer 301-304 can include a non-conductive material 305 and a conductive occlusion material 306. In some embodiments, the occlusion material 306 can be arranged in strips or patterns such that each layer together provides partial occlusion of the active chip 310. For example, as shown in FIG. 4A, the occlusion layers 301-304 can be patterned to provide a composite occlusion effect as described above. As described above, in other embodiments, other types of patterned optical obstruction materials can be used for the layers 301-304.

[0027] As mentioned above, the bonding structure may be subject to invasive tampering. For example, focused ion beam (FIB) techniques may be used to ablate the protective layer of the chip. Such techniques may therefore allow an attacker to remove occluding material from the protected chip 300 to expose the active circuitry of the active chip 310 for further optical probing. It may therefore be desirable to detect ablation of the protected chip 300. In some embodiments, contact pads 350A of the bonding layer 340A of the protected chip may be further connected to one or more occluding layers 302-304 of the protected chip 300 by vertical interconnects 360. Similarly, contact pads 350B of the bonding layer 340B of the active chip 310 may be connected to the active circuitry 116 of the active chip 310 through conductive traces (not shown). Thus, in some embodiments, by bonding contact pads 350A of the protection chip 300 to corresponding contact pads 350B of the active chip, a bonding structure can have an electrical connection between the active circuitry of the active chip 310 and one or more occlusion layers 301-304, L1-L4 of the protection chip 300. In embodiments disclosed herein, one or more occlusion layers can include bonding layer 340A such that occlusion layer 301 can be the same as or can include at least bonding layer 340A. In some embodiments, bonding layer 340A can be patterned to aid in occlusion (or otherwise optically obstruct), while in other embodiments, layers 302-304, L2-L4 can cooperate to occlude, e.g., prevent incident light from interacting with the underlying sensitive circuitry, without bonding layer 340A substantially contributing to occlusion.

[0028] In the illustrated embodiment, the protective chip 300 includes four occlusion layers 301-304, L1-L4, and may have a vertical interconnect 360 that provides an electrical connection between the top occlusion layer 304 L4 and a contact pad 350A of the bonding layer 340A. In these embodiments, the active chip 310 may be configured to monitor one or more attributes of the protective chip 300 through an electrical connection between one or more layers of the protective chip 300 and the active chip 310. In some embodiments, multiple optical occlusion layers 301-304 may be overlapping and spaced apart from one another across the bonding interface 315.

[0029] For example, in some embodiments, the active chip 310 can be configured to measure a passive electrical property (e.g., capacitance) of one or more layers 301-304, portions of layers 301-304, or strips 306 within layers of the protective chip 300. In other embodiments, the active chip 310 can be configured to measure resistance of elements 306 within layers 301-304, portions of layers 301-304, or layers 301-304 of the protective chip 300. In these embodiments, ablative hacking techniques can be detected by measuring changes in attributes of the protective chip 300 (e.g., by measuring changes in resistance and / or capacitance and / or impedance of the occluding layers 301-304, portions of layers 301-304, or elements 306 within layers 301-304 to which the active circuitry is connected). For example, a FIB probe can be used to ablate a portion of the occlusion layers 301-304 of the protective chip 300 that are electrically connected to the active chip 310. As an example, the metallization in layer 304 can function as a first terminal of a capacitive circuit, the metallization in layer 302 can function as a second terminal of the capacitive circuit, and the intervening dielectric material 305 in layer 303 can function as a dielectric of the capacitive circuit. The active chip 310 can detect a change in capacitance (or resistance in other embodiments) of the protective chip 300 that results from ablation of the metallizations of the occlusion layers 301-304. In these embodiments, the active chip 310 can be configured to disable operation of the sensitive circuitry and / or send an alert message to an external system or user when ablation is detected. In some embodiments, two or more adjacent layers of the occlusion element can have no electrical connection between them. For example, the protection chip 300 may have a first occlusion layer (e.g., layer 304) connected to one or more contact pads 350A of the bonding layer 340A by vertical interconnects 360, and a second occlusion layer 303 that is not electrically connected to the bonding layer 350A or the first occlusion layer (e.g., functions as an intervening dielectric for a capacitive circuit).In some embodiments, when the second occluding layer 303 is located between the bonding layer 340A and the first occluding layer 304, the first occluding layer 304 can be connected to the bonding layer with a vertical interconnect 360 that functions as a bypass via that skips the second occluding layer 303 and connects to the layer 304 as a terminal of the capacitive circuit. In some embodiments, the active chip 310 can continuously measure the attribute of the protection chip 300. In other embodiments, the active chip 310 can periodically measure the attribute of the protection chip 300. In some embodiments, the active chip 310 can be configured to detect a relative change in the attribute of the protection chip 300 (e.g., a change in capacitance) over a period of time. In other embodiments, the active chip 310 can be configured to compare the attribute of the protection chip 300 to a predetermined reference value. Thus, one or more of the occluding layers 301-304 can function as a detection circuit configured to detect external access of one or more of the occluding layers 301-304. Further examples of detection circuits can be found throughout US Pat. No. 11,385,278, the contents of which are incorporated herein by reference in their entirety and for all purposes.

[0030] In the embodiment of FIG. 4A, the protective chip 300 may be bonded to an active surface (e.g., front surface) 370 of the active chip 310, with the contact pads 350A-B electrically connected to the active circuitry at or near the bond interface 315. In the illustrated embodiment, the protective chip 300 is shown covering the entire or substantially the entire surface of the active chip 310 to which it is bonded. In such embodiments, the protective chip 300 may cover at least 10%, at least 90%, or at least 95% of the total active area of ​​the active chip 310. For example, the protective chip 300 may cover 10%-100% of the total active area of ​​the active chip 310, or 90%-99% of the total active area of ​​the active chip 310. As discussed above, in other embodiments, the protective chip 300 may cover only a portion of the area of ​​the active chip 310, such as covering only the sensitive circuitry of the active chip 310, or only a portion of the sensitive circuitry. In some embodiments, the sensitive circuitry may be disposed in one or more sensitive areas of the active chip 310 such that the protective chip 300 covers most or all of each of these regions. In some embodiments, the protective chip 300 may cover a portion of each of the one or more sensitive areas such that 1%-25% of each sensitive area is covered. In some embodiments, the protective chip 300 may cover up to 20% of each sensitive area. Thus, the occlusion strips 306 of the protective chip 300 need not be laterally contiguous with one another. Additionally, although not required, the occlusion strips 306 of one layer may overlap the occlusion strips 306 of another layer. In some embodiments shown herein (e.g., FIG. 2B), the occlusion patterns of each of the first and second layers may be at least partially non-overlapping.

[0031] FIG. 4B illustrates the protective chip 300 bonded directly to the active chip 310 at the back surface 372 of the active chip 310. The active circuitry 116 can be located closer to the front surface 370 of the chip 310 than to the back surface 372. As illustrated in FIG. 4B, the bonding interface 315 between the protective chip 300 and the back surface 372 of the active chip 310 can not include contact pads. In other embodiments, the bonding layers 340A,B of the protective chip 300 and the active chip 310 can include contact pads. Additionally, in some embodiments, the contact pads 350A,B can provide electrical connections between the active circuitry 116 of the active chip 310 and one or more occlusion layers 301-304 of the protective chip 300 to monitor electrical properties of the occlusion layers 301-304 to detect intrusions such as FIB attacks, as described above. For example, in the illustrated embodiment, one or more through-substrate vias (TSVs) 330 can connect contact pad(s) 350B on the front active surface of the active chip 310 to corresponding contact pad(s) 350A on the protective chip 300. A vertical interconnect (see FIG. 4A ) on the protective chip 300 can connect the contact pad(s) 350A of the protective chip 300 to one or more of the metal materials 306 of one or more occlusion layers L1-L4 (301-304). Still other embodiments can include multiple protective chips 300 bonded directly to the active chip 310 across the active and passive surfaces of the active chip 310. In these embodiments, the protective chips 300 can protect both sides of the active chip 310 from optical probing.

[0032] FIG. 5A shows an exemplary embodiment of a protection chip 300 bonded directly to the active surface 370 of the active chip 310 across the bond interface 315, and the protection chip 300 further includes an optical filter layer 420 incorporating an optical filter element. To increase the analysis cost of a high-sensitivity chip, it may be desirable to provide an attacker with misleading or confusing data to slow down the analysis process. Thus, instead of or in addition to blocking the optical signal, it may be beneficial to modify the signal. In some embodiments, the optical filter element may be configured to induce a phase shift in the incident light beam. Thus, in these embodiments, the optical filter element (which may include a patterned filter element) may generate positive or negative interference that disrupts the attacker's signal. In some embodiments, the optical filter element may include a metallization layer. In some embodiments, the optical filter may include a refractive filter. In other embodiments, the optical material may include other materials and structures suitable for filtering, refracting, and / or diffracting light. In some embodiments, the optical filter element may include multiple layers in the protection chip 300.

[0033] 5B shows an exemplary embodiment of the protection chip 300 bonded directly to the active surface of the active chip 310 across the bond interface 315, and further includes an optical filter layer 420 that combines with the embedded random reflective pattern to form a reflective filter element 457. As shown in FIG. 5B, the reflective filter element 457 can be used to alter the optical signal from the laser probe. In these embodiments, the incident light beam 455 reflects 456 away from the probe, altering the apparent intensity of the received light. This can cause, for example, the NIR probe to report an inaccurate density reading for the area of ​​the circuit probed.

[0034] Referring again to FIG. 5A, in some embodiments, the optical filter element 420 can include a single layer of the protective chip 300. In these embodiments, the optical filter element 420 can be bonded to the protective chip 300, which further includes one or more blocking layers 301-303 and bonding layers 340A, B, and the layer 301 can be a bonding layer. In other embodiments, multiple optical filter layers 420 and / or blocking layers 301-303 can be combined in the protective chip 300. Furthermore, one optical filter element can include multiple layers. For example, one optical filter element can include a single or multiple layers configured to function as a Fresnel lens. In some embodiments, the optical filter element can cover only the high sensitivity area of ​​the active chip 310. In other embodiments, the optical filter element can be configured to cover the entire area of ​​the active chip 310.

[0035] Although the embodiments shown herein (e.g., FIGS. 1-5) show directly bonded jamming and active chips (e.g., 300 and 310), in other embodiments, jamming element 300 can be bonded to active chip 310 using an adhesive such as solder, non-conductive paste, etc. Additionally, in some embodiments, jamming element 300 can include no active circuitry (e.g., no transistors).

[0036] Examples of direct bonding methods and structures Various embodiments disclosed herein relate to direct bond structures in which two elements (e.g., elements 300, 310) can be directly bonded to one another without an intervening adhesive. One or more semiconductor elements (e.g., integrated device dies, wafers, etc.) can be stacked or bonded to one another to form the bond structure. Conductive contact pads of one element can be electrically connected to corresponding conductive contact pads (e.g., contact pads 350A, B) of another element. Any suitable number of elements can be stacked in the bond structure.

[0037] In some embodiments, the elements are directly bonded to each other without the use of adhesive. In various embodiments, the non-conductive or dielectric material of a first element (e.g., a protective or occluding element) can be directly bonded to the corresponding non-conductive or dielectric field area (e.g., 341A, B) of a second element (e.g., an active chip) without the use of adhesive. The non-conductive material can be referred to as the non-conductive bonding area or bonding layer (e.g., 340A, B) of the first element. In some embodiments, the non-conductive material of the first element can be directly bonded to the corresponding non-conductive material of the second element using dielectric-to-dielectric bonding techniques. For example, the dielectric-to-dielectric bond can be formed without the use of adhesive using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0038] In various embodiments, a hybrid direct bond can be formed without an intervening adhesive. For example, the dielectric bonding surfaces can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to plasma and / or etchants to activate the surfaces. In some embodiments, the surfaces can be terminated with species after or during activation (e.g., during plasma and / or etch processes). Without being bound by theory, in some embodiments, an activation process is performed to break chemical bonds at the bonding surfaces, and a termination process can provide additional species at the bonding surfaces that enhance the bonding energy during direct bonding. In some embodiments, activation and termination are performed in the same step, for example, activating and terminating the surfaces with plasma or wet etchants. In other embodiments, the bonding surfaces can be terminated with a separate process to provide additional species for direct bonding. In various embodiments, the terminating species can include nitrogen. Additionally, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, there can be one or more fluorine peaks near the layers and / or bonding interface. Thus, in a direct bond structure, the bond interface (e.g., 315) between the two dielectric materials can include a very smooth interface with high nitrogen content and / or fluorine peaks at the bond interface. Further examples of activation and / or termination treatments can be found throughout U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0039] In various embodiments, the conductive contact pads of a first element can also be directly bonded to the corresponding conductive contact pads of a second element. For example, hybrid bonding techniques can be used to provide conductor-conductor direct bonds along a bonding interface that includes a covalently directly bonded dielectric-dielectric surface prepared as described above. In various embodiments, direct bonding techniques disclosed in at least U.S. Patent Nos. 9,716,033 and 9,852,988 can be used to form conductor-conductor (e.g., contact pad-contact pad) direct bonds and dielectric-dielectric hybrid bonds, the contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0040] For example, the dielectric bonding surfaces can be prepared and bonded directly to each other without an intervening adhesive as described above. The conductive contact pads (which can be surrounded by a non-conductive dielectric field region) can also be bonded directly to each other without an intervening adhesive. In some embodiments, each contact pad can be recessed below the outer surface (e.g., top surface) of the dielectric field region or non-conductive bonding region by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, such as within the range of 2 nm to 20 nm or 4 nm to 10 nm. In some embodiments, the non-conductive bonding regions can be bonded directly to each other at room temperature without the use of an adhesive, and the bonded structure can then be annealed. Upon annealing, the contact pads can expand and contact each other to form a metal-metal direct bond. Using hybrid bonding technology such as Direct Bond Interconnect or DBI®, available from Xperi, Inc. of San Jose, Calif., can advantageously increase the density of connected pads across the direct bond interface (e.g., small or fine pitch for regular array structures). In some embodiments, the pitch of the bond pads, or the pitch of the conductive traces embedded in the bonding surface of one of the bonded elements, can be less than 40 microns, or less than 10 microns, or even less than 2 microns. In some applications, it is desirable for the ratio of the bond pad pitch to one of the bond pad dimensions to be less than 5, or less than 3, and sometimes less than 2. In other applications, the width of the conductive traces embedded in the bonding surface of one of the bonded elements can be in the range of 0.3 to 3 microns. In various embodiments, the contact pads and / or traces can include copper, although other metals may be suitable.

[0041] Thus, in a direct bonding process, the first element can be directly bonded to the second element without an intervening adhesive. In some configurations, the first element can include a singulated element, such as a singulated integrated device die, or a singulated protective or occluding element. In other configurations, the first element can include a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element can also include a singulated element, such as a singulated integrated device die. In other configurations, the second element can include a carrier or substrate (e.g., a wafer).

[0042] As described herein, the first and second elements can be directly bonded to each other without the use of adhesive, which is distinct from a deposition process. In one application, the width of the first element in the bonded structure can be similar to the width of the second element. In some other embodiments, the width of the first element in the bonded structure can be different from the width of the second element. The width or area of ​​the larger element in the bonded structure can be at least 10% greater than the width or area of ​​the smaller element. Thus, the first and second elements can include non-deposited elements. Furthermore, unlike deposited layers, the direct bonded structure can include defective regions along the bonded interface where nanovoids exist. The nanovoids can be formed due to activation (e.g., exposure to plasma) of the bonded surfaces. As discussed above, the bonded interface can include concentrations of materials from the activation process and / or the final chemical treatment process. For example, in an embodiment utilizing nitrogen plasma for activation, a nitrogen peak can be formed at the bonded interface. In an embodiment utilizing oxygen plasma for activation, an oxygen peak can be formed at the bonded interface. In some embodiments, the bond interface can include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond can include a covalent bond that is stronger than a van der Waals bond. The bond layer can also include a polished surface that is planarized to a high degree of smoothness.

[0043] In various embodiments, the metal-to-metal bond between the contact pads can be bonded such that the copper grains grow together across the bond interface. In some embodiments, the copper can have grains oriented along crystal planes to enhance diffusion of the copper across the bond interface. The bond interface can extend substantially completely to at least a portion of the bonded contact pads such that there are substantially no gaps between the non-conductive bond regions at or near the bonded contact pads. In some embodiments, a barrier layer (which can include, for example, copper) can be provided below the contact pads. However, in other embodiments, there can be no barrier layer below the contact pads, as described, for example, in U.S. Patent Application Publication No. 2019 / 0096741, which is incorporated herein by reference in its entirety for all purposes.

[0044] Unless the context clearly requires otherwise, throughout this specification and the claims, words such as "comprise, comprising, include, including" and the like are to be interpreted in their inclusive sense rather than their exclusive or exhaustive sense, i.e., "including, but not limited to." The word "coupled" as generally used herein means two or more elements that can be connected directly or through one or more intermediate elements. Similarly, the word "connected" as generally used herein means two or more elements that can be connected directly or through one or more intermediate elements. Also, when the words "herein," "above," "below," and words of similar import are used in this application, these words refer to this application as a whole and not to any particular portion of this application. Furthermore, when a first element is described herein as being "on" or "over" a second element, the first element can be directly on or over the second element such that the first and second elements are in direct contact, or indirectly on or over the second element such that there are one or more intervening elements between the first and second elements. In the above Detailed Description, words using the singular or plural number may also include the plural or singular number respectively where the context allows. The word "or" when referring to a list of two or more items covers all interpretations of the word, such as any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0045] Additionally, as used herein, inter alia, conditional terms such as "can, could, might, may" and "eg, for example, such as" are generally intended to convey that some embodiments include certain features, elements and / or conditions and other embodiments do not include them, unless expressly stated otherwise or understood otherwise within the context of use. Thus, such conditional terms are generally not intended to imply that features, elements and / or conditions are in any way required for one or more embodiments.

[0046] Although several embodiments have been described, these embodiments are presented as examples only and are not intended to limit the scope of the present disclosure. Indeed, the novel apparatus, method and system described herein may be embodied in various other forms, and various omissions, substitutions and modifications of the forms of the methods and systems described herein may be made without departing from the spirit of the present disclosure. For example, although blocks are shown in a given arrangement, another embodiment may perform similar functions using different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The appended claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the present disclosure.

Claims

1. A bonding structure, comprising a semiconductor element including an active circuit, and a disturbing element directly bonded to the semiconductor element along a bonding interface without using an adhesive, wherein the disturbing element includes at least one patterned optical disturbing layer disposed to cover the active circuit and to prevent optical reading of the active circuit. The bonding structure.

2. The bonding structure according to claim 1, wherein the at least one patterned optical disturbing layer includes a plurality of optical blocking layers. The bonding structure according to claim 1.

3. The bonding structure according to claim 2, wherein each of the plurality of optical blocking layers includes a non-conductive layer and a patterned opaque material at least partially embedded in the non-conductive layer. The bonding structure according to claim 2.

4. The bonding structure according to claim 3, wherein the patterned opaque material includes a material that blocks light having a wavelength in the range of 400 nm to 1 mm. The bonding structure according to claim 3.

5. The bonding structure according to claim 3, wherein the patterned opaque material is opaque to at least one of infrared light (IR) or near-infrared light (NIR). The bonding structure according to claim 3.

6. The bonding structure according to claim 3, wherein a first optical blocking layer among the plurality of optical blocking layers includes a first opaque pattern, and a second optical blocking layer among the plurality of optical blocking layers includes a second opaque pattern that at least partially does not overlap with the first opaque pattern, so that, from an upper viewpoint of the disturbing element, the first and second opaque patterns block a wider portion of the semiconductor element than the first and second opaque patterns alone. The bonding structure according to claim 3.

7. The bonding structure according to any one of claims 3 to 6, wherein the semiconductor element has at least one high-sensitivity circuit region and at least one region not including a high-sensitivity circuit, and the patterned opaque material blocks at least a part of the at least one high-sensitivity circuit region and leaves at least one region not including a high-sensitivity circuit unblocked. The bonding structure according to any one of claims 3 to 6.

8. The bonding structure according to claim 1, wherein the at least one patterned optical disturbing layer includes a material that refracts, scatters, diffuses, diffracts, or phase-shifts light to prevent optical reading of the active circuit. The bonding structure according to claim 1.

9. The bonding structure according to any one of claims 1 to 6, wherein the semiconductor element further includes a bonding layer, and the disturbing element further includes a bonding layer directly bonded to the bonding layer of the semiconductor element. The bonding structure according to any one of claims 1 to 6.

10. The bonding layer of the semiconductor element includes a plurality of contact pads disposed in a non-conductive layer, and the bonding layer of the interference element includes a plurality of contact pads disposed in the non-conductive layer and directly bonded to the contact pads of the semiconductor element. The bonding structure according to claim 9.

11. The active circuit is disposed on or near the active surface of the semiconductor element, and the interference element is directly bonded to the back surface of the semiconductor element on the side opposite to the active surface. The bonding structure according to any one of claims 1 to 6.

12. A first blocking layer among the plurality of optical blocking layers includes a detection circuit configured to detect external access to the first blocking layer. The bonding structure according to any one of claims 2 to 6.

13. One of the at least one patterned optical interference layer further includes an optical filter. The bonding structure according to any one of claims 1 to 6.

14. A bonding structure, a semiconductor element including an active circuit, an interference element directly bonded to the semiconductor element along a bonding interface without using an adhesive, wherein the interference element includes a first interference layer and a second interference layer disposed to cover the first interference layer, the first interference layer has a first interference pattern, and the second interference layer has a second interference pattern that at least partially does not overlap with the first interference pattern. Bonding structure.

15. When viewed from above the interference element, the first and second interference patterns cooperate to prevent optical reading of the active circuit. The bonding structure according to claim 14.

16. The first and second interference patterns include one or two or more conductive materials. The bonding structure according to claim 14.

17. The semiconductor element further includes a bonding layer, and the interference element further includes a bonding layer directly bonded to the bonding layer of the semiconductor element. The bonding structure according to any one of claims 14 to 16.

18. A method for forming a bonding structure, including directly bonding a semiconductor element to an interference element without using an adhesive, wherein the semiconductor element includes an active circuit, and the interference element includes at least one patterned optical interference layer disposed to cover the active circuit and prevent optical reading of the active circuit. Method for forming a bonding structure.

19. The method further includes forming the interfering element such that a plurality of optical interference layers are spaced apart from each other along a direction crossing a bonding interface between the semiconductor element and the interfering element, and each interference layer of the plurality of optical interference layers includes a non-conductive layer and a patterned opaque material at least partially embedded in the non-conductive layer. The method according to claim 18.

20. Forming the interfering element to include a bonding layer; Forming the semiconductor element to include a bonding layer; Bonding the bonding layer of the interfering element to the bonding layer of the semiconductor element; The method according to claim 18 or 19, further comprising:

21. The method further includes forming the interfering element such that the bonding layer of the interfering element is metallized to match a metallization pattern of the semiconductor element. The method according to claim 20.

22. The method further includes forming the interfering element such that a first interference layer of the at least one patterned optical interference layer includes a detection circuit configured to detect an external access to the first interference layer. The method according to claim 18 or 19.

23. A bonding structure, comprising: A semiconductor element including an active circuit; An interfering element directly bonded to the semiconductor element covering the active circuit along a bonding interface without using an adhesive; The interfering element includes a plurality of conductive layers, the plurality of conductive layers include a detection circuit for monitoring passive electrical characteristics of the interfering element, and the detection circuit communicates electrically with the active circuit. Bonding structure.

24. The active circuit is configured to detect a change in the passive electrical characteristics of the interfering element. The bonding structure according to claim 23.

25. When the active circuit detects a change in the passive electrical characteristics, the active circuit is configured to send an alert message to an external system or a user. The bonding structure according to claim 24.

26. The passive electrical characteristics include a capacitance of the interfering element. The bonding structure according to any one of claims 23 to 25.

27. A bonding structure, comprising: A semiconductor element having a front surface and a back surface opposite to the front surface, and including an active circuit disposed closer to the front surface than the back surface; An interfering element directly bonded to the back surface of the semiconductor element covering the active circuit along a bonding interface without using an adhesive; comprising, wherein the interference element includes a detection circuit that monitors passive electrical characteristics of the interference element, and the detection circuit communicates electrically with the active circuit Bonding structure

Images