Ultra-shallow dopant and ohmic contact regions by solid-state diffusion

Abstract

1. A method for processing a substrate, the method comprising: loading a substrate including a semiconductor raised feature into a processing chamber; forming a conformal dopant layer on the raised feature by atomic layer deposition (ALD); forming a metal layer on the raised feature; heat treating the dopant layer to form a very shallow dopant region in the raised feature by diffusion of dopant from the dopant layer into the raised feature; and heat treating the metal layer to form an ohmic contact region in the raised feature by diffusion of metal from the metal layer into the raised feature.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63 / 235,595, filed August 20, 2021, which is incorporated herein by reference.

[0002] The present invention relates generally to methods of processing substrates and, in particular embodiments, to forming ultra-shallow dopant and ohmic contact regions by solid-state diffusion. [Background technology]

[0003] The semiconductor industry is characterized by a trend towards producing larger and more complex circuits on a given semiconductor chip. Larger and more complex circuits are achieved by reducing the size of individual devices within the circuit and placing the devices closer together. As the dimensions of individual components within a device, such as a metal oxide semiconductor (MOS) or bipolar transistor, are reduced and the device components are closer together, improved electrical performance can be obtained. However, care must be taken in the formation of doped regions in the substrate to ensure that deleterious electric field conditions do not result. Summary of the Invention [Means for solving the problem]

[0004] According to an embodiment of the invention, a method of processing a substrate includes loading a substrate including a semiconductor raised feature into a processing chamber, forming a conformal dopant layer on the raised feature by atomic layer deposition (ALD), forming a metal layer on the raised feature, heat treating the dopant layer to form a very shallow dopant region in the raised feature by diffusion of dopant from the dopant layer into the raised feature, and heat treating the metal layer to form an ohmic contact region in the raised feature by diffusion of metal from the metal layer into the raised feature.

[0005] According to an embodiment of the present invention, a method for forming a semiconductor device includes forming a dopant layer in direct contact with a silicon (Si) feature on a substrate, forming a metal layer on the dopant layer containing a metal that forms a metal silicide in the Si feature, and performing a thermal treatment to form ultra-shallow dopant regions and metal silicide regions by diffusion of the dopant and metal into the substrate, the thermal treatment including heating the substrate to an annealing temperature, wherein after forming the dopant layer and prior to the thermal treatment, the substrate is maintained below the annealing temperature.

[0006] According to an embodiment of the invention, a method of processing a substrate includes loading a substrate into a processing chamber, the substrate comprising a vertical recess having a sidewall, the sidewall comprising a feature protruding laterally from a major surface of the sidewall, the feature having at least three sides exposed; forming a dopant layer on the feature by atomic layer deposition (ALD) at a first temperature range, the dopant layer conformally coating the at least three sides of the feature; forming a metal layer on the feature at a second temperature range; heat treating the dopant layer by maintaining the substrate above the first temperature range and the second temperature range to form an ultra-shallow dopant region in the feature; and heat treating the metal layer by maintaining the substrate above the first temperature range and the second temperature range to form an ohmic contact region in the feature. [Brief description of the drawings]

[0007] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0008] [Figure 1A]1A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to one embodiment, where FIG. 1A shows an incoming substrate, FIG. 1B shows the substrate after forming a dopant layer, FIG. 1C shows the substrate after forming a metal layer, FIG. 1D shows the substrate during heat treatment, FIG. 1E shows the substrate after heat treatment, and FIG. 1F shows the substrate after removing the residue of the metal layer. [Figure 1B] 1A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to one embodiment, where FIG. 1A shows an incoming substrate, FIG. 1B shows the substrate after forming a dopant layer, FIG. 1C shows the substrate after forming a metal layer, FIG. 1D shows the substrate during heat treatment, FIG. 1E shows the substrate after heat treatment, and FIG. 1F shows the substrate after removing the residue of the metal layer. [Figure 1C] 1A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to one embodiment, where FIG. 1A shows an incoming substrate, FIG. 1B shows the substrate after forming a dopant layer, FIG. 1C shows the substrate after forming a metal layer, FIG. 1D shows the substrate during heat treatment, FIG. 1E shows the substrate after heat treatment, and FIG. 1F shows the substrate after removing the residue of the metal layer. [Figure 1D] 1A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to one embodiment, where FIG. 1A shows an incoming substrate, FIG. 1B shows the substrate after forming a dopant layer, FIG. 1C shows the substrate after forming a metal layer, FIG. 1D shows the substrate during heat treatment, FIG. 1E shows the substrate after heat treatment, and FIG. 1F shows the substrate after removing the residue of the metal layer. [Figure 1E] 1A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to one embodiment, where FIG. 1A shows an incoming substrate, FIG. 1B shows the substrate after forming a dopant layer, FIG. 1C shows the substrate after forming a metal layer, FIG. 1D shows the substrate during heat treatment, FIG. 1E shows the substrate after heat treatment, and FIG. 1F shows the substrate after removing the residue of the metal layer. [Figure 1F]1A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to one embodiment, where FIG. 1A shows an incoming substrate, FIG. 1B shows the substrate after forming a dopant layer, FIG. 1C shows the substrate after forming a metal layer, FIG. 1D shows the substrate during heat treatment, FIG. 1E shows the substrate after heat treatment, and FIG. 1F shows the substrate after removing the residue of the metal layer. [Figure 2A] 2A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to another embodiment, where FIG. 2A shows the incoming substrate, FIG. 2B shows the substrate after forming the dopant layer, FIG. 2C shows the substrate during a first heat treatment, FIG. 2D shows after forming the metal layer, FIG. 2E shows the substrate during a second heat treatment, FIG. 2F shows the substrate after the second heat treatment, and FIG. 2G shows the substrate after removing the residue of the metal layer. [Figure 2B] 2A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to another embodiment, where FIG. 2A shows the incoming substrate, FIG. 2B shows the substrate after forming the dopant layer, FIG. 2C shows the substrate during a first heat treatment, FIG. 2D shows after forming the metal layer, FIG. 2E shows the substrate during a second heat treatment, FIG. 2F shows the substrate after the second heat treatment, and FIG. 2G shows the substrate after removing the residue of the metal layer. [Figure 2C] 2A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to another embodiment, where FIG. 2A shows the incoming substrate, FIG. 2B shows the substrate after forming the dopant layer, FIG. 2C shows the substrate during a first heat treatment, FIG. 2D shows after forming the metal layer, FIG. 2E shows the substrate during a second heat treatment, FIG. 2F shows the substrate after the second heat treatment, and FIG. 2G shows the substrate after removing the residue of the metal layer. [Figure 2D]2A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to another embodiment, where FIG. 2A shows the incoming substrate, FIG. 2B shows the substrate after forming the dopant layer, FIG. 2C shows the substrate during a first heat treatment, FIG. 2D shows after forming the metal layer, FIG. 2E shows the substrate during a second heat treatment, FIG. 2F shows the substrate after the second heat treatment, and FIG. 2G shows the substrate after removing the residue of the metal layer. [Figure 2E] 2A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to another embodiment, where FIG. 2A shows the incoming substrate, FIG. 2B shows the substrate after forming the dopant layer, FIG. 2C shows the substrate during a first heat treatment, FIG. 2D shows after forming the metal layer, FIG. 2E shows the substrate during a second heat treatment, FIG. 2F shows the substrate after the second heat treatment, and FIG. 2G shows the substrate after removing the residue of the metal layer. [Figure 2F] 2A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to another embodiment, where FIG. 2A shows the incoming substrate, FIG. 2B shows the substrate after forming the dopant layer, FIG. 2C shows the substrate during a first heat treatment, FIG. 2D shows after forming the metal layer, FIG. 2E shows the substrate during a second heat treatment, FIG. 2F shows the substrate after the second heat treatment, and FIG. 2G shows the substrate after removing the residue of the metal layer. [Figure 2G] 2A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to another embodiment, where FIG. 2A shows the incoming substrate, FIG. 2B shows the substrate after forming the dopant layer, FIG. 2C shows the substrate during a first heat treatment, FIG. 2D shows after forming the metal layer, FIG. 2E shows the substrate during a second heat treatment, FIG. 2F shows the substrate after the second heat treatment, and FIG. 2G shows the substrate after removing the residue of the metal layer. [Figure 3A]3A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to another embodiment, where FIG. 3A shows an incoming substrate with a patterned mask layer, FIG. 3B shows the substrate after forming a dopant layer and a metal layer, FIG. 3C shows the substrate during a thermal treatment, and FIG. 3D shows the substrate after removing the residue of the metal layer, the dopant layer, and the patterned mask layer. [Figure 3B] 3A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to another embodiment, where FIG. 3A shows an incoming substrate with a patterned mask layer, FIG. 3B shows the substrate after forming a dopant layer and a metal layer, FIG. 3C shows the substrate during a thermal treatment, and FIG. 3D shows the substrate after removing the residue of the metal layer, the dopant layer, and the patterned mask layer. [Figure 3C] 3A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to another embodiment, where FIG. 3A shows an incoming substrate with a patterned mask layer, FIG. 3B shows the substrate after forming a dopant layer and a metal layer, FIG. 3C shows the substrate during a thermal treatment, and FIG. 3D shows the substrate after removing the residue of the metal layer, the dopant layer, and the patterned mask layer. [Figure 3D] 3A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate according to another embodiment, where FIG. 3A shows an incoming substrate with a patterned mask layer, FIG. 3B shows the substrate after forming a dopant layer and a metal layer, FIG. 3C shows the substrate during a thermal treatment, and FIG. 3D shows the substrate after removing the residue of the metal layer, the dopant layer, and the patterned mask layer. [Figure 4A] 4A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant regions in raised features on a substrate according to yet another embodiment, where FIG. 4A shows an incoming substrate having a fin feature, FIG. 4B shows the substrate after forming a dopant layer and a metal layer, FIG. 4C shows the substrate after a heat treatment, and FIG. 4D shows the substrate after removing the residue of the metal layer and the dopant layer. [Figure 4B] 4A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant regions in raised features on a substrate according to yet another embodiment, where FIG. 4A shows an incoming substrate having a fin feature, FIG. 4B shows the substrate after forming a dopant layer and a metal layer, FIG. 4C shows the substrate after a heat treatment, and FIG. 4D shows the substrate after removing the residue of the metal layer and the dopant layer. [Figure 4C] 4A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant regions in raised features on a substrate according to yet another embodiment, where FIG. 4A shows an incoming substrate having a fin feature, FIG. 4B shows the substrate after forming a dopant layer and a metal layer, FIG. 4C shows the substrate after a heat treatment, and FIG. 4D shows the substrate after removing the residue of the metal layer and the dopant layer. [Figure 4D] 4A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant regions in raised features on a substrate according to yet another embodiment, where FIG. 4A shows an incoming substrate having a fin feature, FIG. 4B shows the substrate after forming a dopant layer and a metal layer, FIG. 4C shows the substrate after a heat treatment, and FIG. 4D shows the substrate after removing the residue of the metal layer and the dopant layer. [Figure 5A] 5A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant regions in raised features on a substrate according to yet another embodiment, where FIG. 5A shows an incoming substrate having nanowire features, FIG. 5B shows the substrate after forming a dopant layer and a metal layer, FIG. 5C shows the substrate after a heat treatment, FIG. 5D shows the substrate after removing the residues of the metal layer and the dopant layer, and FIG. 5E shows the substrate after epitaxial growth of source / drain regions. [Figure 5B] 5A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant regions in raised features on a substrate according to yet another embodiment, where FIG. 5A shows an incoming substrate having nanowire features, FIG. 5B shows the substrate after forming a dopant layer and a metal layer, FIG. 5C shows the substrate after a heat treatment, FIG. 5D shows the substrate after removing the residues of the metal layer and the dopant layer, and FIG. 5E shows the substrate after epitaxial growth of source / drain regions. [Figure 5C] 5A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant regions in raised features on a substrate according to yet another embodiment, where FIG. 5A shows an incoming substrate having nanowire features, FIG. 5B shows the substrate after forming a dopant layer and a metal layer, FIG. 5C shows the substrate after a heat treatment, FIG. 5D shows the substrate after removing the residues of the metal layer and the dopant layer, and FIG. 5E shows the substrate after epitaxial growth of source / drain regions. [Figure 5D] 5A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant regions in raised features on a substrate according to yet another embodiment, where FIG. 5A shows an incoming substrate having nanowire features, FIG. 5B shows the substrate after forming a dopant layer and a metal layer, FIG. 5C shows the substrate after a heat treatment, FIG. 5D shows the substrate after removing the residues of the metal layer and the dopant layer, and FIG. 5E shows the substrate after epitaxial growth of source / drain regions. [Figure 5E] 5A shows a cross-sectional schematic of a process flow for forming ultra-shallow dopant regions in raised features on a substrate according to yet another embodiment, where FIG. 5A shows an incoming substrate having nanowire features, FIG. 5B shows the substrate after forming a dopant layer and a metal layer, FIG. 5C shows the substrate after a heat treatment, FIG. 5D shows the substrate after removing the residues of the metal layer and the dopant layer, and FIG. 5E shows the substrate after epitaxial growth of source / drain regions. [Figure 6A] 6A-6C depict process flow diagrams of methods for forming ultra-shallow dopant regions according to various embodiments, with FIG. 6A depicting one embodiment, FIG. 6B depicting another embodiment, and FIG. 6C depicting an alternative embodiment. [Figure 6B] 6A-6C depict process flow diagrams of methods for forming ultra-shallow dopant regions according to various embodiments, with FIG. 6A depicting one embodiment, FIG. 6B depicting another embodiment, and FIG. 6C depicting an alternative embodiment. [Figure 6C] 6A-6C depict process flow diagrams of methods for forming ultra-shallow dopant regions according to various embodiments, with FIG. 6A depicting one embodiment, FIG. 6B depicting another embodiment, and FIG. 6C depicting an alternative embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] This application relates to a method of processing a substrate, and in particular to forming ultra-shallow dopant and ohmic contact regions by solid-state diffusion. As the dimensions of device components, such as transistor gates in MOS devices and emitter regions in bipolar devices, are reduced, the junction depth of doped regions formed in semiconductor substrates must also be reduced. The formation of shallow junctions with uniform doping profiles and high surface concentrations has proven to be extremely difficult to achieve. A commonly used technique is to implant dopant atoms into a substrate by an ion implanter. In ion implantation, energetic dopant atoms impact the surface of the substrate at high speed and are driven into the substrate by a subsequent annealing process. While this method has proven effective in forming doped regions with reasonably deep junctions, the formation of ultra-shallow junctions using ion implantation is extremely difficult. Both the path of the energized dopant atoms within the substrate and the implant uniformity are difficult to control at the low energies required to form shallow implanted junctions. The implantation of energized dopant atoms damages the crystal lattice in the substrate, which is difficult to repair. Dislocations resulting from lattice damage can easily spike across shallow junctions, causing current leakage across the junctions. Moreover, implantation of p-type dopants such as boron, which diffuses quickly in silicon, results in excessive dispersion of the dopant atoms after they are introduced into the substrate. In that case, it becomes difficult to form a highly confined concentration of p-type dopant atoms in a specific region within the substrate, especially at the surface of the substrate.

[0010] In addition, new device structures for transistors and memory devices are being implemented that utilize doped three-dimensional structures. Examples of such devices include, but are not limited to, fin field effect transistors (FinFETs), tri-gate FETs, recessed channel transistors (RCATs), and embedded dynamic random access memory (EDRAM) trenches. It is desirable to have a conformal doping method to uniformly dope these structures. The ion implantation process is essentially line-of-sight and therefore requires special substrate orientation to uniformly dope the fin and trench structures. In addition, at high device densities, shadowing effects make uniform doping of fin structures by ion implantation techniques extremely difficult or even impossible. Conventional plasma doping and atomic layer doping are techniques that have demonstrated conformal doping of three-dimensional semiconductor structures, but each of these is limited to the range of dopant densities and depths that can be accessed under ideal conditions. Furthermore, contact resistance is becoming increasingly problematic at advanced semiconductor nodes due to the inability to continue to increase dopant levels as well as Schottky barriers resulting from Fermi level pinning.

[0011] Embodiments of the present application provide methods for forming ultra-shallow dopant and ohmic contact regions that overcome some of these difficulties. The ohmic contact regions may comprise low resistance junctions (non-rectifying) in which the current varies linearly with applied voltage.

[0012] In various embodiments, methods are disclosed for forming ultra-shallow dopant and ohmic contact regions in semiconductor devices by solid-state diffusion into a substrate layer. The formation of the ohmic contact regions (by reactions forming a metal / semiconductor composite, e.g., NiSi or TiSi) is believed to enhance dopant diffusion into the substrate layer due to the "snowplow effect" and activation of dopants that tend to substitutionally dope the semiconductor substrate.

[0013] In various embodiments, methods for ultra-shallow dopant and ohmic contact regions by solid-phase diffusion may provide various advantages over conventional ion implantation processes, including low resistance junctions and applicability in 3D structures (i.e., non-planar structures). Atomic layer deposition (ALD) may be used to form conformal dopant layers applicable to various 3D structures. Thus, the methods disclosed herein may be used to replace or, in certain embodiments, complement ion implantation processes, and may be used in combination.

[0014] The ultra-shallow dopant and ohmic contact regions may include, for example, source-drain extensions for planar transistors, FinFETs, or tri-gate FETs. Other applications of the ultra-shallow dopant and ohmic contact regions may include, but are not limited to, channel doping in replacement gate process flows to set threshold voltage (Vt), channel doping at the fin / STI interface for FinFETs to set Vt or to prevent electrical punch-through in bulk FinFETs, or for ultra-thin silicon-on-insulator (ET-SOI) devices, ground plane doping for ET-SOI devices including planar or FinFETs, and doping trenches for embedded DRAM capacitors. Devices with ultra-thin replacement semiconductor channels, such as germanium-on-insulator devices (GeOI) or Ge FinFETs, and compound semiconductor channel devices such as GaAs, InSb, InAs, InGaAs, or InGaSb FinFETs, may also be doped using the disclosed methods. Additionally, devices formed in amorphous Si or polycrystalline Si layers, such as EDRAM devices, may utilize the disclosed methods to adjust Si doping levels.Furthermore, embodiments of the present disclosure may be applied to CMOS devices, including gate-all-around (GAA) and nanowire transistor structures.

[0015] In the following, a method for forming ultra-shallow dopant and ohmic contact regions by solid-phase diffusion with a common heat treatment for both dopant and metal diffusion is described with reference to Figures 1A-1F. Next, a method with separate heat treatment is described with reference to Figures 2A-2G. Further embodiments are described with reference to Figures 3A-3D (with patterned mask layer), Figures 4A-4D (for fin structures), and Figures 5A-5E (for nanowire structures). Exemplary process flow diagrams are shown in Figures 6A-6C. All figures in this disclosure are drawn for illustrative purposes only and are not necessarily drawn to scale, including aspect ratios of features.

[0016] Those skilled in the relevant art will recognize that various embodiments can be practiced without one or more of the specific details, or with other alternative and / or additional methods, materials, or elements. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are disclosed in order to provide a thorough understanding of the invention. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0017] 1A-1F show cross-sectional schematics of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate 100 according to one embodiment.

[0018] Figure 1A shows a schematic cross-section of a substrate 100. In various embodiments, the substrate 100 may be part of a semiconductor device, or may include a semiconductor device, and may, for example, have undergone several processing steps following a conventional process. Accordingly, the substrate 100 may comprise semiconductor layers useful in various microelectronics. For example, the semiconductor structure may comprise a substrate 100 on which various device regions are formed. The substrate 100 may be of any size, for example, a 200 mm substrate, a 300 mm substrate, or even a larger substrate. According to one embodiment, the substrate 100 may contain Si, for example, crystalline Si, polycrystalline Si, or amorphous Si. In one example, the substrate 100 may be a strained Si layer. According to another embodiment, the substrate 100 may contain or consist of Ge or a Si x Ge 1-x compound, where x is the atomic fraction of Si and 1 - x is the atomic fraction of Ge, and 0 < x < 1. Exemplary Si x Ge 1-x compounds are Si 0.1 Ge 0.9 Si 0.2 Ge 0.8 Si 0.3 Ge 0.7 Si 0.4 Ge 0.6 Si 0.5 Ge 0.5 Si 0.6 Ge 0.4 Si 0.7 Ge 0.3 Si 0.8 Ge 0.2 Si 0.9 Ge 0.1 Ge buffer layer. In one example, the substrate 100 is a compressive strained Ge layer or a tensile strained Si 0.5 Ge 0.5 deposited on a x Ge 1-x(x>0.5). According to some embodiments, substrate 100 may comprise silicon-on-insulator (SOI). Additionally, substrate 100 may comprise a compound semiconductor, such as GaAs, GaN, InP, InSb, InAs, InGaAs, InGaSb, etc. In various embodiments, substrate 100 may be patterned or embedded with other components of a semiconductor device.

[0019] FIG. 1B shows a schematic cross-sectional view of a substrate 100 with a dopant layer 102 in direct physical contact with the substrate 100 .

[0020] The dopant layer 102 may be deposited by atomic layer deposition (ALD) as a blanket film and then patterned to form the dopant layer 102 over a portion of the substrate 100. For example, conventional photolithographic patterning and etching methods may be used to pattern the dopant layer 102. ALD is well suited for conformally depositing the dopant layer 102 over 3D structures having large aspect ratios (e.g., FIGS. 4A and 5A).

[0021] In various embodiments, the dopant layer 102 may include an n-type dopant or a p-type dopant. The dopant layer 102 may include one or more dopants from the following Group IIIA of the periodic table: boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl), and the following Group VA: nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). According to some embodiments, the dopant layer 102 may contain low dopant levels, for example, between about 0.5 and about 5 atomic percent dopant. According to other embodiments, the dopant layer 102 may contain medium dopant levels, for example, between about 5 and about 20 atomic percent dopant. According to yet other embodiments, the dopant layer may contain high dopant levels, for example, greater than 20 atomic percent dopant. In some embodiments, the thickness of the dopant layer 102 may be 4 nm or less, for example, between 1 nm and 4 nm, between 2 nm and 4 nm, or between 3 nm and 4 nm, although other thicknesses may be used in other embodiments.

[0022] The dopant layer 102 may include an oxide, a nitride, an oxynitride, or other material containing one or more dopants. In one embodiment, the dopant layer 102 may include an oxide of a dopant, a nitride of a dopant, or an oxynitride of a dopant. In one example, the one or more dopants may be at least approximately uniformly distributed throughout the dopant layer 102. In other examples, the one or more dopants may be non-uniformly distributed throughout the dopant layer 102. In other examples, the concentration of the one or more dopants may decrease or increase across the thickness of the dopant layer 102 away from the interface between the dopant layer 102 and the substrate 100. A concentration gradient of the dopant within the dopant layer 102 may be advantageously utilized to adjust the doping rate. According to some embodiments, the dopant layer 102 may contain or consist of a doped high-k dielectric material in the form of an oxide material, a nitride material, or an oxynitride material. The dopant in the high-k dielectric material may be selected from the list of dopants above. The high-k dielectric material may contain one or more metal elements selected from alkaline earth elements, rare earth elements, and elements from Groups IIIA, IVA, and IVB of the Periodic Table of Elements. Alkaline earth metal elements include beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba). Exemplary oxide materials include magnesium oxide, calcium oxide, and barium oxide, and combinations thereof. The rare earth elements may be selected from the group of scandium (Sc), yttrium (Y), lutetium (Lu), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb). Group IVB elements include titanium (Ti), hafnium (Hf), and zirconium (Zr).According to some embodiments of the present invention, the high-k dielectric material may contain HfO2, HfON, HfSiON, ZrO2, ZrON, ZrSiON, TiO2, TiON, Al2O3, La2O3, W2O3, CeO2, Y2O3, or Ta2O5, or a combination of two or more thereof, although other dielectric materials are contemplated and may be used.

[0023] FIG. 1C shows a simplified cross-sectional view of a substrate 100 having a metal layer 104 formed on a dopant layer 102 .

[0024] The metal layer 104 may be deposited as a blanket film and then patterned to form the metal layer 104. For example, conventional photolithographic patterning and etching methods may be used to form the metal layer 104. According to another embodiment, the dopant layer 102 and the metal layer 104 may both be deposited as blanket films and then both be patterned to form the film structure shown diagrammatically in FIG. 1C.

[0025] The metal layer 104 contains or consists of a metal that can form an ohmic contact region when reacting with the substrate 100. For example, in the case of a Si substrate, the metal can form a metal silicide contact region. In the case of germanium (Ge), the metal can form a metal germanide contact region. Furthermore, the metal can react with a III-V semiconductor to form a metal-semiconductor alloy that is an ohmic conductor. In non-limiting examples, the metal may include titanium (Ti), nickel (Ni), platinum (Pt), or tungsten (W), or a combination of two or more thereof. The metal layer 104 may be deposited, for example, by physical vapor deposition (PVD), ALD, or CVD. In some embodiments, the thickness of the metal layer 104 may be between 1 nm and 100 nm, between 2 nm and 50 nm, or between 2 nm and 20 nm.

[0026] FIG. 1D shows a schematic cross-sectional view of the substrate 100 during thermal processing.

[0027] The patterned film structure of FIG. 1C may be heat treated to diffuse both the dopant (e.g., B, Al, Ga, In, Tl, N, P, As, Sb, or Bi) and the metal (e.g., Ti, Ni, Pt, or W). During the heat treatment, the dopant diffuses into the substrate 100, changing the chemical composition of the substrate 100 locally, especially near the surface. The diffusion of the dopant from the dopant layer 102 into the substrate 100 is indicated by arrows 103 in FIG. 1D, and as a result of the doping, ultra-shallow dopant regions 108 may be formed in the substrate 100 below the dopant layer 102. The heat treatment further activates the dopant in the dopant regions 108 and also diffuses metal atoms from the metal layer 104 into the substrate 100, as indicated by arrows 105, forming ohmic contact regions 106. The ohmic contact region 106 may be, for example, a metal silicide of Ti, Ni, Pt, or W. In various embodiments, the dopant region 108 and the ohmic contact region 106 may spatially overlap. In various embodiments, the ohmic contact formation improves dopant diffusion into the substrate 100 and activation of the dopants in the dopant region 108.

[0028] Figure IE shows a schematic cross-sectional view of the substrate 100 after heat treatment, and Figure IF shows a schematic cross-sectional view of the substrate 100 after removal of the metal layer residues.

[0029] In some embodiments, the thickness of ultra-shallow dopant region 108 and ohmic contact region 106 may be between 1 nm and 10 nm, or between 2 nm and 5 nm. However, one skilled in the art will readily appreciate that the lower boundaries of the regions in substrate 100 (i.e., ohmic contact region 106 and ultra-shallow dopant region 108) may not be abrupt, but rather may be characterized by a gradual decrease in dopant and metal concentrations.

[0030] After the thermal treatment, a residual metal layer 110 may be present on the substrate 100. This is shown in FIG. 1E. The residual metal layer 110 may be removed from the substrate 100 using a dry or wet etching process. The resulting structure is shown in FIG. 1F. In some embodiments, an additional thermal treatment may be used after removing the residual metal from the substrate 100. Such additional treatment may further activate the dopants. In some embodiments, the additional thermal treatment may be performed after depositing a protective capping layer, e.g., an oxide or nitride, such as silicon oxide, silicon nitride, or a combination thereof. The protective capping layer may prevent outgassing of the dopants during a subsequent annealing process. The subsequent annealing process may be selected to activate the dopants without increasing the out-diffusion of metal atoms from the ohmic contact region 108.

[0031] 2A-2G show cross-sectional schematic diagrams of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate 100 according to another embodiment. In this embodiment, two heat treatments may be performed separately for the dopant layer and the metal layer. The materials (e.g., compositions of the substrate, dopant layer, dopant, and metal layer), process steps, process conditions (e.g., deposition methods and heat treatment conditions), and layer thicknesses already described above with reference to FIGS. 1A-1F may be easily used in the embodiment diagrammatically illustrated in FIGS. 2A-2G, whereby some details will not be repeated.

[0032] FIG 2A shows a schematic cross-sectional view of substrate 100, and FIG 2B shows a schematic cross-sectional view of substrate 100 after forming a dopant layer 102 in direct contact with substrate 100. FIG 2C shows a schematic cross-sectional view of substrate 100 during a first thermal treatment. Dopant layer 102 in FIG 2B may be thermally treated to diffuse dopants from dopant layer 102 into substrate 100 as shown by arrows 103 in FIG 2C to form ultra-shallow dopant regions 108 in substrate 100 beneath dopant layer 102. The first thermal treatment may further activate the dopants in dopant regions 108.

[0033] FIG. 2D shows a schematic cross-sectional view of substrate 100 after forming metal layer 104, FIG. 2E shows a schematic cross-sectional view of substrate 100 during a second thermal treatment, FIG. 2F shows a schematic cross-sectional view of substrate 100 after the second thermal treatment, and FIG. 2G shows a schematic cross-sectional view of substrate 100 after removing the residues of the metal layer.

[0034] Metal layer 104 may be deposited as a blanket film and then patterned to form metal layer 104 in Figure 2D. Metal layer 104 may be heat treated to diffuse metal from metal layer 104 into substrate 100, as shown by arrows 105 in Figure 2E, to form ohmic contact regions 106. Dopant regions 108 and ohmic contact regions 106 may spatially overlap, although dopant regions 108 are expected to extend deeper into substrate 100 than ohmic contact regions 106.

[0035] After the second heat treatment, a residual metal layer 110 may be present on the substrate 100. This is shown in Figure 2F. The residual metal layer 110 may be removed from the substrate 100 using a dry or wet etching process. The resulting structure is shown in Figure 2G.

[0036] 3A-3D show cross-sectional schematics of a process flow for forming ultra-shallow dopant and ohmic contact regions in a substrate 300 according to an alternative embodiment. In this embodiment, the substrate 300 may have a mask layer that defines areas for the ultra-shallow dopant and ohmic contact regions. The materials (e.g., substrate, dopant layer, dopant, and cap layer compositions), processing conditions (e.g., deposition methods and thermal treatment conditions), and layer thicknesses already described above with reference to FIGS. 1A-1F may be readily used in the embodiment diagrammatically illustrated in FIGS. 3A-3D.

[0037] 3A shows a simplified cross-sectional view of a substrate 300 containing a patterned mask layer 307 formed thereon to define dopant windows (wells) 301 in the patterned mask layer 307 above the substrate 300. The patterned mask layer 307 may be, for example, a nitride hard mask (e.g., a SiN hard mask) that may be formed using conventional photolithographic patterning and etching methods.

[0038] FIG. 3B illustrates a simplified cross-sectional view of substrate 300 after dopant layer 302 has been formed.

[0039] A dopant layer 302 may be deposited by ALD in the dopant window 301 and on the patterned mask layer 307 in direct contact with the substrate 300. In Figure 3B, a metal layer 304 may also be deposited on the dopant layer 302. The dopant layer 302 may contain an n-type dopant or a p-type dopant.

[0040] FIG. 3C shows a simplified cross-sectional view of the substrate 300 during thermal processing.

[0041] As shown in Figure 3C, the film structure in Figure 3B may be heat treated to diffuse the dopant 303 from the dopant layer 302 into the substrate 300 and form a very shallow dopant region 308 in the substrate 300 below the dopant layer 302 in the dopant window 301. The heat treatment activates the dopant in the dopant region 308 and also diffuses the metal from the metal layer 304 into the substrate 300 as shown by arrows 305 to form an ohmic contact region 306. The dopant region 308 and the ohmic contact region 306 spatially overlap, but because the dopant layer 302 is closer to the substrate 100 than the metal layer 304, the dopant region 308 is expected to extend deeper into the substrate 300 than the ohmic contact region 306. The ohmic contact formation improves dopant diffusion into the substrate 300 and activation of the dopant in the dopant region 308.

[0042] FIG. 3D shows a simplified cross-sectional view of the substrate 300 after the residual layer has been removed.

[0043] After the thermal treatment, the remaining metal layer, the remaining dopant layer, and the patterned mask layer 307 may be removed from the substrate 100 using a dry or wet etching process. The resulting structure is shown in Figure 3D.

[0044] According to another embodiment, similar to the previous embodiment having two separate heat treatments described with reference to FIGS. 2A-2G, before forming metal layer 304 on substrate 300, substrate 300 may be heat treated to form ultra-shallow dopant regions 308, and then metal layer 304 may be formed on substrate 300, and substrate 300 may be heat treated again to form ohmic contact regions 306.

[0045] 4A-4D show cross-sectional schematic diagrams of a process flow for forming ultra-shallow dopant regions in raised features on a substrate 400 according to yet another embodiment.

[0046] FIG. 4A shows a schematic cross-sectional view of a raised feature (fin) 404 and an oxide layer (e.g., SiO2) 402 on a substrate 400. The materials of the substrate 400 and the raised feature 404 may include one or more of the materials described above for the substrate 100 of FIG. 1A. In one embodiment, the substrate 400 and the raised feature 404 may contain or consist of the same material (e.g., Si). Those skilled in the art will readily appreciate that embodiments of the present invention may be applied to other simple or complex raised features on a substrate. According to one embodiment, the raised feature may be located at the bottom of a recessed feature. The recessed feature may include, for example, a via, a trench. In one embodiment, the raised feature may include a fin of a FinFET. In FIG. 4A, the raised feature 404 may have three faces (i.e., a top surface and two sidewalls in FIG. 4A) that are exposed and available for film formation, as described below.

[0047] FIG. 4B shows a cross-sectional schematic of substrate 400 having a conformal dopant layer 406 and a conformal metal layer 408 deposited on raised feature 407 and on oxide layer 402 .

[0048] The material of conformal dopant layer 406 may include one or more of the materials described above for dopant layer 102 of Figure 1B. The metal of conformal metal layer 408 may include one or more of the metals described above for metal layer 104 of Figure 1C. As shown in Figure 4B, all sides of exposed raised feature 404 (including the three visible sides in Figure 4A) may be conformally covered by the layer stack of dopant layer 406 and metal layer 408.

[0049] FIG. 4C shows a simplified cross-sectional view of the substrate 400 after thermal treatment.

[0050] The structure in Figure 4B may be heat treated to diffuse the dopant from dopant layer 406 and the metal from metal layer 408 into raised feature 404 to form ultra-shallow dopant and ohmic contact region 403. Although ultra-shallow dopant and ohmic contact region 403 is shown as a single region, it may include overlapping ultra-shallow dopant and ohmic contact regions as shown in Figure IF. The heat treatment further activates the dopants in ultra-shallow dopant and ohmic contact region 403. After the heat treatment, a residual metal layer 412 and a residual dopant layer 410 may be present.

[0051] The heat treatment may include heating the substrate 400 in an inert atmosphere (e.g., argon (Ar) or nitrogen (N2)), an oxidizing atmosphere (e.g., oxygen (O2) or water vapor (HO)), or a reducing atmosphere (e.g., ammonia). The heat treatment may be selected based on the composition of the metal layer 408. For example, if the metal layer 408 includes nickel, the heat treatment may be performed at a temperature between 300°C and 600°C for 10 seconds to 10 minutes. If the metal layer 408 includes titanium, the heat treatment may be performed at a temperature between 400°C and 700°C for 10 seconds to 10 minutes. In some cases, more than one heat treatment may be used, for example, multiple heat treatments may be used to diffuse the dopant into the substrate to form the first metal semiconductor composite, to form the second metal semiconductor composite, and to activate the dopant. In various embodiments, the temperature for the heat treatment may be selected to allow diffusion of the dopant and the metal. In one embodiment where the metal includes Ni, the temperature may be, for example, between 450 and 550° C. In another embodiment where the metal includes Ti, the temperature may be between 550 and 650° C. In some embodiments, the heat treatment may include rapid thermal annealing (RTA), spike annealing, or laser spike annealing.

[0052] In various embodiments, the formation of the dopant layer 406 and the metal layer 408 may occur below the temperature of the heat treatment to prevent undesired solid state diffusion prior to the heat treatment. Thus, in one embodiment, the formation of the dopant layer 406 may occur at a first temperature range and the formation of the metal layer 408 may occur at a second temperature range, where both the first and second temperature ranges are below the temperature range of the heat treatment.

[0053] Advantageously, in one or more embodiments, the source / drain regions of the transistor may be formed in the absence of heavy implantation processes through the use of solid-state doping. The absence of implantation avoids the formation of shadow regions in complex non-planar structures. Highly active abrupt junctions may be formed due to preferential segregation of dopant atoms into the silicon lattice during silicide formation. Such junctions may not be achievable with conventional doping techniques using solid-state diffusion.

[0054] FIG. 4D shows a simplified cross-sectional view of the substrate 400 after the residual layer has been removed.

[0055] The residual layers after the heat treatment (eg, the residual metal layer 412 and the residual dopant layer 410 in FIG. 4C) may be removed from the substrate 400 using a dry or wet etching process.

[0056] 5A-5E show schematic cross-sectional views of a device in the process of fabricating a process flow for forming ultra-shallow dopant regions in raised features on a substrate 500 according to yet another embodiment. In this embodiment, the raised features may be part of or may include a nanowire that is positioned laterally to fabricate a nanowire FET.

[0057] Figure 5A shows a schematic cross-sectional view of a raised feature (nanowire 504) formed within a recessed feature 501. The materials of the substrate 500 and the nanowire 504 may include one or more of the materials described above for the substrate 100 of Figure 1A. In one embodiment, the substrate 500 and the nanowire 504 may contain or consist of the same material (e.g., Si).

[0058] As shown in FIG. 5A, the substrate 500 may comprise a plurality of nanowires 504. In particular, the nanowires 504 are embedded in different materials. The nanowires 504 may be spaced apart from one another by one or more sacrificial layers 520 of a plurality of sacrificial layers. Thus, the substrate 500 comprises alternating layers of sacrificial layers 520 and nanowires 504. In various embodiments, the nanowires 504 may form a transistor channel at the end of the fabrication, while the sacrificial layers 520 are removed in a later step of the fabrication to free void space for the formation of a gate dielectric and a gate terminal. In various embodiments, the nanowires 504 have a thickness of a few nanometers to tens of nanometers, for example, in one embodiment, about 1 nm to about 20 nm. In another embodiment, the nanowires 504 have a thickness of about 1 nm to about 10 nm in one embodiment.

[0059] In one particular embodiment, the sacrificial layer 520 comprises silicon germanium (SiGe) and the nanowires 504 comprise silicon. In an alternative embodiment, the sacrificial layer 520 comprises silicon and the nanowires 504 comprise silicon germanium.

[0060] 5A, the sacrificial layer 520 may be shorter in the lateral direction of the cross-section than the nanowires 504, resulting in a lateral recess 505 that exposes the tip of the nanowire 504. Such a feature may be created, for example, by a lateral recess etch (cavity etch) to selectively remove a portion of the sacrificial layer 520 relative to the nanowires 504.

[0061] Further, in various embodiments, an inner spacer 590 may be formed to cover the surface of the sacrificial layer 520. The inner spacer 590 may include silicon-containing dielectric materials such as silicon nitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron carbonitide (SiBCN). Formation of the second sidewall spacer layer 190 may be performed by deposition from a gas phase using, for example, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other deposition processes. In a particular embodiment, a blanket deposition of the inner spacer material may be performed, followed by an etch-back process to expose the tips of the nanowires 504.

[0062] As further shown in FIG. 5A, the substrate 500 may include a dielectric blocking layer 540 over the alternating layer stack of nanowires 504 and sacrificial layer 520. The dielectric blocking layer 140 may be an oxide layer in one embodiment. Over the dielectric blocking layer 540, the substrate 500 may further include a dummy gate 550. The dummy gate 550 may include polysilicon or amorphous silicon, by way of example only. The dummy gate 550 may have a thickness of about 50 nm to about 500 nm in various embodiments.

[0063] 5A, a patterned hardmask 560 is formed over the dummy gate 550 and may comprise silicon oxide in one embodiment. In various embodiments, the hardmask 560 may comprise silicon nitride, silicon carbonitride (SiCN), or silicon oxycarbide (SiOC). In alternative embodiments, the hardmask 560 may comprise titanium nitride. The hardmask 560 may have a thickness of about 5 nm to about 50 nm in various embodiments.

[0064] In a particular embodiment, a first sidewall spacer layer 570 may be formed covering the dummy gate 550. The first sidewall spacer layer 570 may include a dielectric material including an oxide or a nitride. In some embodiments, the first sidewall spacer layer 570 may include a silicon-containing dielectric material, such as silicon oxide, silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and silicon boron carbonitride (SiBCN). The first sidewall spacer layer 570 may have a thickness of about 1 nm to about 10 nm in various embodiments. In a particular embodiment, the first sidewall spacer layer 570 may be a stacked layer, for example, comprising two or more layers using two different materials.

[0065] FIG. 5B shows a simplified cross-sectional view of substrate 500 after dopant layer 506 and metal layer 508 have been formed.

[0066] The dopant layer 506 may be deposited by atomic layer deposition (ALD) as a conformal blanket film. ALD is particularly suitable for forming conformal films on 3D structures with multiple sides, which are difficult to achieve with ion implantation techniques. For example, all sides of the exposed nanowire 504 of FIG. 5A may be conformally covered by the conformal dopant layer 506, as shown in FIG. 5B.

[0067] In various embodiments, the conformal dopant layer 506 may include an n-type dopant or a p-type dopant. N-type dopants for silicon may be arsenic, phosphorus, and antimony, while a p-type dopant for silicon may be boron. The conformal dopant layer 506 may include an oxide, nitride, oxynitride, or other material containing one or more dopants. The conformal dopant layer 506 may further include one or more metallic elements selected from alkaline earth elements, rare earth elements, and elements from Groups IIIA, IVA, and IVB of the Periodic Table of Elements.

[0068] The metal of conformal metal layer 508 may include titanium (Ti), nickel (Ni), platinum (Pt), or tungsten (W), or a combination of two or more thereof. Conformal metal layer 508 may be deposited by, for example, physical vapor deposition (PVD), ALD, or CVD.

[0069] FIG. 5C shows a simplified cross-sectional view of the substrate 500 after heat treatment.

[0070] The structure in FIG. 5B may be heat treated to diffuse the dopant from dopant layer 506 and the metal from metal layer 508 into the nanowires 504 to form ultra-shallow dopant and ohmic contact regions 503. Although ultra-shallow dopant and ohmic contact regions 503 are shown as a single region, they may include overlapping ultra-shallow dopant and ohmic contact regions as shown in FIG. 1F. The heat treatment may include heating the substrate 500 at a temperature between 450° C. and 650° C. for 10 seconds to 10 minutes in an inert atmosphere (e.g., argon (Ar) or nitrogen (N2)), in an oxidizing atmosphere (e.g., oxygen (O2) or water vapor (H2O)), or in a reducing atmosphere (e.g., ammonia). As with the previous embodiment described in FIGS. 4A-4D, the temperature for the heat treatment may be selected to allow diffusion of the dopant and metal. The heat treatment further activates the dopant in the ultra-shallow dopant and ohmic contact regions 503. After the heat treatment, a residual metal layer 512 and a residual dopant layer 510 may be formed.

[0071] FIG. 5D shows a simplified cross-sectional view of the substrate 500 after the residual layer has been removed.

[0072] The residual layers after the heat treatment (eg, the residual metal layer 512 and the residual dopant layer 510 in FIG. 5C) may be removed from the substrate 500 using a dry or wet etching process.

[0073] FIG. 5E shows a schematic cross-sectional view of the substrate 500 after epitaxial growth of the source / drain regions.

[0074] After forming the ultra-shallow dopant and ohmic contact regions 503 and removing the residual layers, subsequent fabrication processes may continue. In one or more embodiments, as shown in FIG. 5E, source / drain regions 515 may be formed around the ultra-shallow dopant and ohmic contact regions 503. The source / drain regions 515 fill the lateral recesses 505 (shown in FIG. 5D) and the exposed tips of the nanowires 504. The formation of the source / drain regions 515 may be performed, for example, by epitaxial growth. Although not shown, the source / drain regions 515 formed by an epitaxial growth process typically have a faceted outer surface. In various embodiments, the source / drain material includes silicon-germanium, which may be doped by p-type doping during the deposition process. In some embodiments, the source / drain material includes silicon or silicon-carbon, which may be doped by n-type doping during the deposition process.

[0075] Figures 6A-6C show process flow diagrams of methods for forming ultra-shallow dopant regions according to various embodiments, with Figure 6A showing one embodiment, Figure 6B showing another embodiment, and Figure 6C showing an alternative embodiment. The process flow can follow the figures discussed above (e.g., Figures 1B-1F, 2B-2G, and 4A-4D) and therefore will not be described again.

[0076] In FIG. 6A, the process flow 60 begins with forming a dopant layer on a substrate (block 610, e.g., FIG. 2B). The dopant layer may then be heat treated to form ultra-shallow dopant regions in the substrate by diffusion of dopants from the dopant layer into the substrate (block 620, e.g., FIG. 2C) to expose a portion of the conductive layer comprising the first conductive material of the substrate. A metal layer may then be formed on the substrate (block 630, e.g., FIG. 2D). The metal layer may then be heat treated to form ohmic contact regions in the substrate by diffusion of metal from the metal layer into the substrate (block 640, e.g., FIG. 2E-2F). In certain embodiments, residues of the metal layer may be removed (block 650, e.g., FIG. 2G). In an alternative embodiment, the metal layer may be formed prior to heat treating the dopant layer, as shown in FIG. 6B.

[0077] In Figure 6B, process flow 62 begins with forming a dopant layer on a substrate (block 610, e.g., Figure 1B). Next, a metal layer may then be formed over the dopant layer (block 630, e.g., Figure 1C). Both the dopant layer and the metal layer may then be heat treated to form ultra-shallow dopant regions and ohmic contact regions in the substrate (block 642, e.g., Figures 1D-1E).

[0078] In FIG. 6C, process flow 64 begins with loading a substrate into a processing chamber, where the substrate comprises a semiconductor raised feature, such as a fin or nanowire structure (block 605, e.g., FIG. 4A). A dopant layer may then be formed on the raised feature by atomic layer deposition (ALD) (block 614, e.g., FIG. 4B), followed by forming a metal layer on the raised feature (block 634, e.g., FIG. 4B). The dopant layer may then be heat treated to form ultra-shallow dopant regions in the raised feature (block 620, e.g., FIG. 4C). The metal layer may then be heat treated to form ohmic contact regions in the raised feature (block 640, e.g., FIG. 4C). In certain embodiments, the two heat treatments, one for the dopant layer and the other for the metal layer, may be performed as a single heat treatment to allow for simultaneous diffusion of the dopant and metal.

[0079] Exemplary methods for depositing a dopant layer on a substrate according to various embodiments of the present invention will now be described.

[0080] According to one embodiment, the boron dopant layer may include boron oxide, boron nitride, or boron oxynitride. According to other embodiments, the boron dopant layer may contain or consist of a boron doped high-k material in the form of an oxide layer, a nitride layer, or an oxynitride layer. In one example, the boron oxide dopant layer may be deposited by ALD by a) providing a substrate in a process chamber configured to perform an ALD process, b) exposing the substrate to a gas phase boron amide or organoborane precursor, c) purging / evacuating the process chamber, d) exposing the substrate to a reactive gas containing H2O, O2, or O3, or a combination thereof, e) purging / evacuating the process chamber, and f) repeating steps b)-e) any number of times until the boron oxide dopant layer has a desired thickness. According to other embodiments, the boron nitride dopant layer may be deposited in step d) using a reaction gas containing NH3, or the boron oxynitride dopant layer may be deposited in step d) using a reaction gas containing 1) HO, O, or O, and NH3, or 2) NO, NO, or N2O, and optionally one or more of HO, O, O, and NH3.

[0081] According to an embodiment of the present invention, the boron amide may include a boron compound of the form LnB(NR1R2)3, where L is a neutral Lewis base, n is 0 or 1, and each of R1 and R2 may be selected from alkyl, aryl, fluoroalkyl, fluoroaryl, alkoxyalkyl, and aminoalkyl. Examples of boron amides include B(NMe2)3, (Me3)B(NMe2)3, and B[N(CF3)2]3. According to an embodiment of the present invention, the organoborane may include a boron compound of the form LnBR1R2R3, where L is a neutral Lewis base, n is 0 or 1, and each of R1, R2, and R3 may be selected from alkyl, aryl, fluoroalkyl, fluoroaryl, alkoxyalkyl, and aminoalkyl. Examples of boron amides include BMe3, (Me3N)BMe3, B(CF3)3, and (Me3N)B(CF3).

[0082] According to one embodiment, the arsenic dopant layer may comprise arsenic oxide, arsenic nitride, or arsenic oxynitride. According to other embodiments, the arsenic dopant layer may contain or consist of an arsenic doped high-k material in the form of an oxide layer, a nitride layer, or an oxynitride layer. In one example, the arsenic oxide dopant layer may be deposited by ALD by a) providing a substrate in a process chamber configured to perform an ALD process, b) exposing the substrate to an arsenic-containing gas phase precursor, c) purging / evacuating the process chamber, d) exposing the substrate to H2O, O2, or O3, or a combination thereof, e) purging / evacuating the process chamber, and f) repeating steps b)-e) any number of times until the arsenic oxide dopant layer has a desired thickness. According to other embodiments, the arsenic nitride dopant layer may be deposited in step d) using NH3, or the arsenic oxynitride dopant layer may be deposited in step d) using: 1) H2O, O2, or O3, and NH3, or 2) NO, NO2, or N2O, and optionally one or more of H2O, O2, O3, and NH3. According to some embodiments of the present invention, the arsenic-containing gas phase precursor may include an arsenic halide, such as AsCl3, AsBr3, or AsI3.

[0083] According to one embodiment, the phosphorus dopant layer may include phosphorus oxide, phosphorus nitride, or phosphorus oxynitride. According to other embodiments, the phosphorus dopant layer may contain or consist of phosphorus doped high-k material in the form of an oxide layer, a nitride layer, or an oxynitride layer. In one example, the phosphorus oxide dopant layer may be deposited by ALD by a) providing a substrate in a process chamber configured to perform an ALD process, b) exposing the substrate to a gas phase precursor containing phosphorus, c) purging / evacuating the process chamber, d) exposing the substrate to a reactive gas containing H2O, O2, or O3, or a combination thereof, e) purging / evacuating the process chamber, and f) repeating steps b)-e) any number of times until the boron oxide dopant layer has a desired thickness. According to other embodiments, the phosphorus nitride ... depositing a phosphorus nitride dopant layer in step d). Alternatively, the phosphorus oxynitride dopant layer may be deposited in step d) using a reactive gas containing: 1) H2O, O2, or O3, and NH3, or 2) NO, NO2, or N2O, and optionally one or more of H2O, O2, O3, and NH3. According to some embodiments of the invention, the phosphorus-containing gas phase precursor may include [(CH3)2N]3PO, P(CH3)3, PH3, OP(C6H5)3, OPCl3, PCl3, PBr3, [(CH3)2N]3P, P(C4H9)3.

[0084] Exemplary embodiments of the present invention are summarized below: Other embodiments can be seen from the full specification and the appended claims.

[0085] Example 1. A method of processing a substrate, the method including: loading a substrate including a semiconductor raised feature into a processing chamber; forming a conformal dopant layer on the raised feature by atomic layer deposition (ALD); forming a metal layer on the raised feature; heat treating the dopant layer to form ultra-shallow dopant regions in the raised feature by diffusion of dopant from the dopant layer into the raised feature; and heat treating the metal layer to form ohmic contact regions in the raised feature by diffusion of metal from the metal layer into the raised feature.

[0086] Example 2. The method of example 1, wherein heat treating the dopant layer occurs before heat treating the metal layer.

[0087] Example 3. The method of any one of Examples 1 or 2, wherein the dopant layer comprises an oxide of a dopant, a nitride of a dopant, or an oxynitride of a dopant, and the ohmic contact region comprises a metal silicide.

[0088] Example 4. The method of one of Examples 1-3, wherein the dopant is selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), and the metal comprises titanium (Ti), nickel (Ni), platinum (Pt), or tungsten (W).

[0089] Example 5. The method of any one of Examples 1-4, further comprising removing residue of the metal layer from the substrate after heat treating the metal layer.

[0090] Example 6. The method of any one of Examples 1-5, wherein the ultra-shallow dopant region and the ohmic contact region overlap in the substrate, and the ultra-shallow dopant region extends further into the substrate than the ohmic contact region.

[0091] Example 7. A method for forming a semiconductor device, comprising: forming a dopant layer in direct contact with a silicon (Si) feature on a substrate; forming a metal layer on the dopant layer containing a metal that forms a metal silicide in the Si feature; and performing a heat treatment to form ultra-shallow dopant regions and metal silicide regions by diffusion of the dopant and metal into the substrate, the heat treatment comprising heating the substrate to an annealing temperature, wherein after forming the dopant layer and prior to the heat treatment, the substrate is maintained below the annealing temperature.

[0092] Example 8. The method of example 7, wherein forming the dopant layer includes conformally depositing the dopant layer over the substrate by atomic layer deposition (ALD).

[0093] Example 9. The method of any one of Examples 7 or 8, wherein forming the dopant layer includes depositing an oxide, nitride, or oxynitride of the dopant.

[0094] Example 10. The method of any one of Examples 7-9, wherein forming the dopant layer comprises exposing the substrate to a vapor phase boron amide or organoborane precursor.

[0095] Example 11. The method of any one of Examples 7-10, wherein forming the dopant layer comprises exposing the substrate to a gas phase precursor containing arsenic or phosphorus.

[0096] Example 12. The method of any one of Examples 7-11, wherein the Si features include raised features.

[0097] Example 13 The method of one of Examples 7-12, wherein the dopant layer coats more than one side of the substrate.

[0098] Example 14. The method of one of examples 7-13, wherein the dopant is selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), and the metal comprises titanium (Ti), nickel (Ni), platinum (Pt), or tungsten (W).

[0099] Example 15. The method of any one of Examples 7-14, wherein the annealing temperature is between 450°C and 650°C.

[0100] Example 16. A method of processing a substrate, comprising: loading the substrate into a processing chamber, the substrate comprising a vertical recess having a sidewall, the sidewall comprising a feature protruding laterally from a major surface of the sidewall, the feature having at least three sides exposed; forming a dopant layer on the feature by atomic layer deposition (ALD) at a first temperature range, the dopant layer conformally coating at least three sides of the feature; forming a metal layer on the feature at a second temperature range; heat treating the dopant layer by maintaining the substrate at a temperature higher than the first temperature range and the second temperature range to form an ultra-shallow dopant region in the feature; and heat treating the metal layer by maintaining the substrate at a temperature higher than the first temperature range and the second temperature range to form an ohmic contact region in the feature.

[0101] Example 17. The method of example 16, wherein the metal layer is in direct contact with the dopant layer.

[0102] Example 18. The method of one of examples 16 or 17, wherein heat treating the dopant layer occurs before forming the metal layer, and the metal layer is in direct contact with the feature.

[0103] Example 19. The method of any one of Examples 16-18, wherein the heat treating the dopant layer or the heat treating the metal layer is performed under an inert atmosphere or an oxidizing atmosphere.

[0104] Example 20. The method of any one of Examples 16-19, wherein the feature comprises silicon (Si) and the ohmic contact region comprises a metal silicide.

[0105] While the present invention has been described with reference to several exemplary embodiments, it is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to the above description. It is therefore intended that the appended claims cover such modifications or embodiments.

Claims

1. A method for processing a substrate, comprising: loading the substrate into a processing chamber, wherein the substrate has semiconductor raised features; forming a conformal dopant layer on the raised features by atomic layer deposition (ALD); forming a metal layer on the raised features; heat-treating the conformal dopant layer to form an ultra-shallow dopant region in the raised features by diffusion of dopants from the dopant layer into the raised features; heat-treating the metal layer to form an ohmic contact region in the raised features by diffusion of metal from the metal layer into the raised features; and the conformal dopant layer comprises an oxide containing the dopant, a nitride containing the dopant, or a oxynitride containing the dopant, and the ohmic contact region comprises a metal silicide.

2. The method according to claim 1, wherein the step of heat-treating the conformal dopant layer is performed before the step of heat-treating the metal layer.

3. The method according to claim 1, wherein the dopant is selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), and the metal comprises titanium (Ti), nickel (Ni), platinum (Pt), or tungsten (W).

4. The method according to claim 1, further comprising removing residues of the metal layer from the substrate after the step of heat-treating the metal layer.

5. The ultra-shallow dopant region and the ohmic contact region partially overlap in the substrate, and the ultra-shallow dopant region extends further into the substrate than the ohmic contact region.

6. A method for forming a semiconductor device, comprising: forming a dopant layer in direct contact with silicon (Si) features on a substrate, wherein the step of forming the dopant layer comprises depositing an oxide, a nitride, or an oxynitride containing the dopant. Forming a metal layer on the dopant layer, wherein the metal layer contains a metal and a metal silicide is formed on the Si feature portion; Performing a heat treatment to form an ultra-shallow dopant region and a metal silicide region by diffusion of the dopant and the metal into the Si feature portion, the heat treatment including heating the substrate to an annealing temperature; and comprising; A method, wherein after forming the dopant layer and before the heat treatment, the substrate is maintained at a temperature lower than the annealing temperature.

7. The method according to claim 6, wherein the step of forming the dopant layer includes conformally depositing the dopant layer on the substrate by atomic layer deposition (ALD).

8. The method according to claim 6, wherein the step of forming the dopant layer includes exposing the substrate to a vapor-phase boron amide or an organoborane precursor.

9. The method according to claim 6, wherein the step of forming the dopant layer includes exposing the substrate to a vapor-phase precursor containing arsenic or phosphorus.

10. The method according to claim 6, wherein the Si feature portion has a raised feature.

11. The method according to claim 6, wherein the dopant layer covers two or more surfaces of the substrate.

12. The method according to claim 6, wherein the dopant is selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), and the metal includes titanium (Ti), nickel (Ni), platinum (Pt), or tungsten (W).

13. The method according to claim 6, wherein the annealing temperature is between 450°C and 650°C.

14. A method for processing a substrate, comprising: Loading the substrate into a processing chamber, wherein the substrate has a vertical recess with sidewalls, the sidewalls having features protruding laterally from a main surface of the sidewalls, the features having at least three exposed surfaces; In a first temperature range, forming a dopant layer on the feature by atomic layer deposition (ALD), wherein the dopant layer conformally covers at least three surfaces of the feature, and the step of forming the dopant layer includes a step of depositing an oxide containing the dopant, a nitride containing the dopant, or a oxynitride containing the dopant, the step; Forming a metal layer on the feature in a second temperature range; Heat-treating the dopant layer by maintaining the substrate at a temperature exceeding the first temperature range and the second temperature range to form an ultra-shallow dopant region in the feature; Heat-treating the metal layer by maintaining the substrate at a temperature exceeding the first temperature range and the second temperature range to form an ohmic contact region in the feature; A method comprising:

15. The method according to claim 14, wherein the metal layer is in direct contact with the dopant layer.

16. The step of heat-treating the dopant layer is performed before the step of forming the metal layer. The method according to claim 14, wherein the metal layer is in direct contact with the feature.

17. The method according to claim 14, wherein the step of heat-treating the dopant layer or the step of heat-treating the metal layer is performed in an inert atmosphere or an oxidizing atmosphere.

18. The method according to claim 14, wherein the feature includes silicon (Si), and the ohmic contact region includes a metal silicide.

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