Power amplifier with protection loop

Abstract

The power amplifier includes an overcurrent protection loop and / or an overvoltage protection loop to help prevent operation outside of a safe operating zone. In further exemplary embodiments, the triggering of the overcurrent protection loop adjusts the threshold voltage of the overvoltage protection loop. In further exemplary embodiments, the overcurrent protection loop may not only adjust the bias regulator but also provide an auxiliary control signal to further limit the signal reaching the power amplifier. In still further exemplary embodiments, the overvoltage protection loop may operate independently of the overcurrent protection current loop, or the overvoltage protection loop may contribute to the overcurrent protection signal.

Description

[Technical field]

[0001] The techniques of this disclosure relate generally to power amplifier circuits that operate under harsh conditions, such as overcurrent and / or overvoltage conditions. [Background technology]

[0002] Mobile communication devices have become increasingly common in today's society offering wireless communication services. The popularity of these mobile communication devices is driven, in part, by the many features now enabled on such devices. Increased processing power in such devices means that mobile communication devices have evolved from pure communication tools to sophisticated mobile multimedia centers enabling an enhanced user experience.

[0003] Most mobile communication devices include a transmit chain that includes a power amplifier, a power amplifier array, or a series of stages of power amplifiers that boost the signal before transmission through an antenna. Although power amplifiers used in these situations are designed to operate over a wide range of conditions, end users often find ways to stress the power amplifier beyond its intended operating range, either unwittingly or by design. When a power amplifier is subjected to conditions that exceed its design tolerances, the power amplifier can fail, resulting in a malfunction or degraded functioning of the transmit chain with a corresponding loss of functionality to the mobile communication device.

[0004] Recognizing this possibility, some manufacturers of mobile communications devices have issued stringent requirements for power amplifiers. Meeting these stringent requirements presents opportunities for new solutions. Summary of the Invention

[0005] The embodiments of the present disclosure relate to a power amplifier having a protection loop. In particular, the exemplary embodiment contemplates providing an overcurrent protection loop and / or an overvoltage protection loop that helps prevent operation outside of a safe operating zone. In a further exemplary embodiment, the trigger of the overcurrent protection loop adjusts the threshold voltage of the overvoltage protection loop. In a further exemplary embodiment, the overcurrent protection loop may not only adjust the bias regulator but also provide an auxiliary control signal that further limits the signal reaching the power amplifier. In yet a further exemplary embodiment, the overvoltage protection loop may operate independently of the overcurrent protection current loop, or the overvoltage protection loop may contribute to the overcurrent protection signal. The use of such an overcurrent and / or overvoltage protection loop reduces the possibility of the power amplifier operating outside of the safe operating area of ​​the power amplifier, which is likely to meet the testing standards of mobile communication device manufacturers and extend the life of the power amplifier.

[0006] In one aspect, a power amplifier circuit is disclosed. The power amplifier circuit includes a power amplifier. The power amplifier includes an output stage configured to provide an amplified output signal. The power amplifier circuit includes a current detector circuit coupled to the power amplifier and configured to provide a sensed signal to an overcurrent protection block that compares an overcurrent protection threshold and generates a protection control alarm signal that shifts the PA away from a dangerous operating condition. The power amplifier circuit further includes a bias circuit coupled to an input of the power amplifier that uses the protection control alarm signal to change the bias of the PA in a direction that maintains an operating point within the SOA safe operating area.

[0007] In another aspect, a power amplifier system is disclosed. The power amplifier system includes a power amplifier circuit including an output stage configured to provide an amplified output signal. The power amplifier system further includes a current detector circuit coupled to the power amplifier and configured to provide an overcurrent protection signal to a bias regulator circuit that controls a bias circuit for the output stage using the overcurrent protection signal. The power amplifier system further includes a voltage detector circuit coupled to the output stage, the voltage detector circuit configured to generate the overvoltage protection signal when the voltage detector circuit detects a first voltage that exceeds a first overvoltage threshold when an overcurrent condition is not detected. The voltage detector circuit is further configured to generate the overvoltage protection signal when the current detector circuit indicates an overcurrent condition and the voltage detector circuit detects a second voltage that exceeds a second overvoltage threshold that is lower than the first overvoltage threshold.

[0008] In another aspect, a power amplifier circuit is disclosed. The power amplifier circuit includes a power amplifier. The power amplifier includes an output stage configured to provide an amplified output signal, and a current detector circuit coupled to the power amplifier. The current detector circuit is configured to provide an over-current protection signal to a first bias regulator circuit that controls a bias circuit of the output stage using the over-current protection signal, and a second supply regulator circuit that adjusts an input signal driving the output stage using the over-current protection signal.

[0009] In another aspect, a power amplifier circuit is disclosed. The power amplifier circuit includes a power amplifier including an output stage configured to provide an amplified output signal. The power amplifier circuit further includes a current detector circuit coupled to the power amplifier and configured to provide an overcurrent protection signal to a bias regulator circuit that controls a bias circuit for the output stage using the overcurrent protection signal. The power amplifier circuit further includes a voltage detector circuit coupled to the output stage. The voltage detector circuit is configured to generate the overvoltage protection signal when the voltage detector circuit detects a first voltage that exceeds a first overvoltage threshold, and to generate the overvoltage protection signal when the current detector circuit indicates an overcurrent condition and the voltage detector circuit detects a second voltage that exceeds a second overvoltage threshold that is lower than the first overvoltage threshold.

[0010] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawing figures. [Brief description of the drawings]

[0011] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0012] [Figure 1] FIG. 1 is a schematic diagram of an example radio frequency (RF) front-end circuit configured in accordance with one embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic diagram of a wireless device including some of the RF front-end circuits of FIG. [Diagram 3] FIG. 3 is a current versus voltage diagram showing the safe operating area and how excessive current and / or excessive voltage can push the operation of a power amplifier outside of the safe operating area. [Figure 4] FIG. 4 is a standing wave ratio diagram of voltage versus time illustrating the results of an unprotected overcurrent condition. [Diagram 5]FIG. 5 is a block diagram of a conventional power amplifier circuit having an over-current and over-voltage detector circuit that can cause ringing or fail to adequately limit over-current / over-voltage conditions. [Figure 6] FIG. 6 is a block diagram of a power amplifier circuit having separate overcurrent and overvoltage detector circuits, where an overcurrent protection signal from the overcurrent detector circuit is provided to a driver stage of the power amplifier to control the input signal to the output stage of the power amplifier using a regulator circuit. [Figure 7] FIG. 7 is a block diagram of a power amplifier circuit having an overcurrent and overvoltage detector circuit, where an overcurrent protection signal from the overcurrent detector circuit is provided to a driver stage of the power amplifier to control the input signal to the output stage of the power amplifier, and an overvoltage detection circuit provides a signal that is summed with the overcurrent protection signal. [Figure 8] FIG. 8 is a block diagram of a power amplifier circuit having an overcurrent detector circuit and an overvoltage detector circuit, where an overcurrent protection signal from the overcurrent detector circuit is provided to a driver stage of the power amplifier to control the input signal to an output stage of the power amplifier using a second bias circuit. [Figure 9] FIG. 9 is a block diagram of a power amplifier circuit having an overcurrent detector circuit and an overvoltage detector circuit, where an overcurrent protection signal from the overcurrent detector circuit is provided to a clamp to control the input signal to the output stage of the power amplifier. [Figure 10] FIG. 10 is a block diagram of a power amplifier circuit having an overcurrent detector circuit and an overvoltage detector circuit, where an overcurrent protection signal from the overcurrent detector circuit is provided to a bias circuit as well as a regulator circuit. [Figure 11] FIG. 11 is a block diagram of a power amplifier circuit spread across two dies, where the power amplifier is instantiated as a bipolar junction transistor in the first die and the driver circuit is instantiated as a complementary metal-oxide semiconductor (CMOS) field effect transistor (FET) in the second die. [Figure 12]FIG. 12 is a current versus voltage diagram illustrating a safe operating area and how an exemplary embodiment of the present disclosure prevents leaving the safe operating area. [Figure 13] FIG. 13 is a current versus voltage diagram illustrating a safe operating area and how an exemplary embodiment of the present disclosure dynamically reduces the overvoltage threshold level to remain within the safe operating area. [Figure 14] FIG. 14 is a block diagram of a power amplifier circuit having an overcurrent and overvoltage detector circuit, where the overcurrent protection signal from the overcurrent detector circuit provides dynamic adjustment to the overvoltage threshold level. [Figure 15] FIG. 15 is a circuit diagram of a dynamic overvoltage protection loop according to an exemplary embodiment of the present disclosure. [Figure 16] FIG. 16 is a circuit diagram of a voltage detector of the overvoltage protection loop of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The embodiments described below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. After reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and recognize applications of these concepts not specifically described herein. It is understood that these concepts and applications are within the scope of the present disclosure and the accompanying claims.

[0014] As used herein, the terms first, second, etc. may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0015] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that it is directly on or extending directly onto the other element, or that intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements. Similarly, when an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that it is directly on or extending directly onto the other element, or that intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements. Also, when an element is referred to as being "connected" or "coupled" to another element, it will be understood that it is directly connected or coupled to the other element, or that intervening elements are present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0016] Relative terms such as "below" or "above," or "on" or "below," or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as illustrated. It is understood that these terms and phrases described above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0017] The terms used herein are used only for the purpose of describing particular embodiments and are not intended to limit the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms "comprise", "include", "includes" and / or "comprising", as used herein, specify the presence of stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements and / or groups thereof.

[0018] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. Furthermore, it will be understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and related art, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0019] The embodiments of the present disclosure relate to a power amplifier having a protection loop. In particular, the exemplary embodiment contemplates providing an overcurrent protection loop and / or an overvoltage protection loop that helps prevent operation outside of a safe operating zone. In a further exemplary embodiment, the trigger of the overcurrent protection loop adjusts the threshold voltage of the overvoltage protection loop. In a further exemplary embodiment, the overcurrent protection loop may not only adjust the bias regulator but also provide an auxiliary control signal that further limits the signal reaching the power amplifier. In yet a further exemplary embodiment, the overvoltage protection loop may operate independently of the overcurrent protection current loop, or the overvoltage protection loop may contribute to the overcurrent protection signal. The use of such an overcurrent and / or overvoltage protection loop reduces the possibility of the power amplifier operating outside of the safe operating area of ​​the power amplifier, which is likely to meet the testing standards of mobile communication device manufacturers and extend the life of the power amplifier.

[0020] Before addressing specific aspects of the present disclosure, a brief discussion of the situation is provided. Specifically, FIG. 1 illustrates a radio frequency (RF) front-end circuit including a power amplifier that can benefit from the protection loop of the present disclosure. FIG. 2 illustrates a wireless device that can include an RF front-end circuit that can include the power amplifier of FIG. 1. FIG. 3 provides a graphical view of a safe operating area with instances of operation that may leave the safe operating area, and FIG. 4 graphically illustrates the effects that may leave the safe operating area. FIG. 5 provides a description of conventional solutions and their short-term discussion. A discussion of exemplary aspects of the present disclosure begins below with reference to FIG. 6.

[0021] FIG. 1 is a schematic diagram of an exemplary RF front-end circuit 10 configured in accordance with an embodiment of the present disclosure. In the embodiments disclosed herein, the RF front-end circuit 10 may be self-contained in a system-on-chip (SoC) or system-in-package (SiP) to provide all the required functions of an RF front-end module (FEM), as an example. Alternatively, different portions of the RF front-end circuit 10 may be provided on different dies. In some embodiments, the different dies may be made of different materials (e.g., GaAs, GaAn, Si, SiG, SiN, etc.) and / or different technologies (e.g., bipolar junction transistors (BJTs), heterojunction transistors, field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) FETs, etc.). As shown, the RF front-end circuit 10 is configured to include an envelope tracking integrated circuit (ETIC) 12, a target voltage circuit 14, a local transceiver circuit 16, and several power amplifiers 18A(1)-18A(N). The RF front-end circuit 10 may also include several second power amplifiers 18B(1)-18B(N).

[0022] The ETIC 12 has several first output nodes N A1-1 ~N A1-N At some first ET voltage V CCOA-1 ~V CCOA-N The ETIC 12 is also configured to generate a second output node N A2 The second ET voltage V CCDA The ETIC 12 is configured to generate a time-varying ET target voltage V TGTA Based on this, the first ET voltage V CCOA-1 ~V CCOA-N and the second ET voltage V CCDA Generate both a time-varying ET target voltage V TGTA Based on the first ET voltage V CCOA-1 ~V CCOA-N and the second ET voltage V CCDAFor a detailed description of a particular embodiment of ETIC 12 that generates , see U.S. patent application Ser. No. 17 / 142,507, entitled "Envelope Tracking Power Management Apparatus With Multiple Power Amplifiers."

[0023] The target voltage circuit 14 generates a time-varying ET target voltage V based on the input signal 20. TGTA , which may be a modulated carrier signal at millimeter wave (mmWave) frequencies, intermediate frequency (IF), or in-phase / quadrature (I / Q) baseband frequencies. In a non-limiting example, the target voltage circuit 14 includes an amplitude detection circuit 22 and an analog look-up table (LUT) 24. The amplitude detection circuit 22 is configured to detect a time-varying amplitude 26 of a number of input signals 20, and the analog LUT 24 generates a time-varying ET target voltage V based on the time-varying amplitude 26. TGTA The method is configured to generate

[0024] The local transceiver circuit 16 may be coupled to a baseband transceiver circuit (not shown), which is separated from the RF front-end circuit 10 by a conductive distance that may extend to several centimeters. The baseband transceiver circuit may provide an input signal 20 to the local transceiver circuit 16 at an IF to help reduce distortion over the conductive distance. In this regard, in a non-limiting example, the baseband transceiver circuit may upconvert a baseband frequency signal to an IF to form the input signal 20. The local transceiver circuit 16 is configured to generate several RF signals 62A(1)-62A(N) and several second RF signals 62B(1)-62B(N) at an RF frequency (also referred to as a carrier frequency) higher than the IF based on the input signal 20.

[0025] Each of the power amplifiers 18A(1)-18A(N) is coupled to a respective one of several antenna ports 64A(1)-64A(N) and outputs a first ET voltage V CCOA-1 ~V CCOA-N and the second ET voltage V CCDAEach of the second power amplifiers 18B(1)-18B(N) is coupled to a respective one of several second antenna ports 64B(1)-64B(N) and configured to amplify a respective one of the RF signals 62A(1)-62A(N) based on a first ET voltage V CCOA-1 ~V CCOA-N and the second ET voltage V CCDA based on the second RF signals 62B(1) to 62B(N), respectively.

[0026] The antenna ports 64A(1)-64A(N) and the second antenna ports 64B(1)-64B(N) may each be coupled to a respective antenna (not shown) for radiating a respective one of the RF signals 62A(1)-62A(N) and the second RF signals 62B(1)-62B(N). The local transceiver circuitry 16 may each adjust some phase offset to provide necessary phase coherency between the RF signals 62A(1)-62A(N) so that the RF signals 62A(1)-62A(N) may be radiated by the respective antennas via RF beamforming. A1 ~ AN Similarly, the local transceiver circuitry 16 may also be configured to generate RF signals 62A(1)-62A(N) in association with the second RF signals 62B(1)-62B(N), respectively, at several second phase offsets to provide necessary phase coherency between the second RF signals 62B(1)-62B(N) such that the second RF signals 62B(1)-62B(N) may be radiated by the respective antennas via RF beamforming. B1 ~ BN , and configured to generate second RF signals 62B(1)-62B(N) in association with the first RF signal 62A(1)-62A(N). In particular, each of RF signals 62A(1)-62A(N) may be identical to (e.g., have the same content and coding as) a respective one of second RF signals 62B(1)-62B(N). In this manner, RF signals 62A(1)-62A(N) and second RF signals 62B(1)-62B(N) may be simultaneously radiated with different polarizations (e.g., horizontal and vertical polarizations).

[0027] In a non-limiting example, each of the power amplifiers 18A(1)-18A(N) is a multi-stage power amplifier including a driver stage amplifier 66 and one or more output stage amplifiers 68. The driver stage amplifier 66 in each of the power amplifiers 18A(1)-18A(N) is connected to a second ET voltage V CCDA The power amplifiers 18A(1)-18A(N) are configured to amplify a respective one of the RF signals 62A(1)-62A(N) based on a first ET voltage V. The output stage amplifier 68 of each of the power amplifiers 18A(1)-18A(N) is coupled between the driver stage amplifier 66 and a respective one of the antenna ports 64A(1)-64A(N). Thus, the output stage amplifier 68 in each of the power amplifiers 18A(1)-18A(N) is coupled between the driver stage amplifier 66 and a respective one of the antenna ports 64A(1)-64A(N). CCOA-1 ~V CCOA-N Based on each of the RF signals 62A(1) to 62A(N), the amplifier 100 is configured to further amplify each of the RF signals 62A(1) to 62A(N).

[0028] Similarly, each of the second power amplifiers 18B(1) to 18B(N) is a multi-stage power amplifier including a second driver stage amplifier 70 and one or more second output stage amplifiers 72. The second driver stage amplifier 70 in each of the second power amplifiers 18B(1) to 18B(N) outputs a second ET voltage V CCDA The second output stage amplifier 72 in each of the second power amplifiers 18B(1)-18B(N) is configured to amplify a respective one of the second RF signals 62B(1)-62B(N) based on the first ET voltage V. The second output stage amplifier 72 in each of the second power amplifiers 18B(1)-18B(N) is coupled between the second driver stage amplifier 70 and a respective one of the second antenna ports 64B(1)-64B(N). Thus, the second output stage amplifier 72 in each of the second power amplifiers 18B(1)-18B(N) is configured to amplify a respective one of the second RF signals 62B(1)-62B(N) based on the first ET voltage V. CCOA-1 ~V CCOA-N The amplifier 62B is configured to further amplify one of the second RF signals 62B(1) to 62B(N) based on a respective one of the first RF signals 62B(1) to 62B(N).

[0029] The RF front-end circuit 10 may include a calibration circuit 74 and a coupling circuit 76. The coupling circuit 76 may be provided between the power amplifiers 18A(1)-18A(N) and the antenna ports 64A(1)-64A(N) and / or between the second power amplifiers 18B(1)-18B(N) and the second antenna ports 64B(1)-64B(N). The coupling circuit 76 couples the output power P of any of the power amplifiers 18A(1)-18A(N) and / or any of the second power amplifiers 18B(1)-18B(N) to a calibration circuit 74. OUT , may be configured to provide a feedback signal 78 indicative of the analog LUT 24. Accordingly, the calibration circuit 74 may be configured to calibrate the analog LUT 24 based on the feedback signal 78. For a detailed description of a particular embodiment of the calibration circuit 74, see U.S. patent application Ser. No. 17 / 163,685, entitled "Apparatus and Method for Calibrating an Envelope Tracking Lookup Table."

[0030] FIG. 2 is a schematic diagram of a wireless device 100 that includes several RF front-end circuits 102(1)-102(K), which may be the RF front-end circuit 10 of FIG.

[0031] The wireless device 100 includes a baseband transceiver 104 that is separate from any of the RF front-end circuits 102(1)-102(K). The baseband transceiver 104 is configured to generate an input signal 20.

[0032] Each of the RF front-end circuits 102(1)-102(K) is coupled to a first antenna array 106 and a second antenna array 108. The first antenna array 106 includes a number of first antennas 110(1)-110(N), each coupled to a respective one of the antenna ports 64A(1)-64A(N) and configured to radiate a respective one of the RF signals 62A(1)-62A(N) with a first polarization (e.g., horizontal polarization). The second antenna array 108 includes a number of second antennas 112(1)-112(N), each coupled to a respective one of the second antenna ports 64B(1)-64B(N) and configured to radiate a respective one of the second RF signals 62B(1)-62B(N) with a second polarization (e.g., vertical polarization).

[0033] The RF front-end circuits 102(1)-102(K) may be located in different locations on the wireless device 100 to help improve RF performance and enhance the user experience. For example, a portion of the RF front-end circuits 102(1)-102(K) may be provided on a top edge of the wireless device 100 and a portion of the ET RF front-end circuits 102(1)-102(K) is provided on a bottom edge of the wireless device 100.

[0034] While the above discussion has focused on RF front-end circuit 10 suitable for use in fifth generation (5G) cellular networks, the disclosure is not so limited and the disclosure may be implemented in 3G, 4G, 5G networks, etc. Of note is the operation of power amplifiers 18A(1)-18A(N) and power amplifiers 18B(1)-18B(N), and more specifically, output stage amplifiers 68 and 72. While power amplifiers are designed to be robust and operate over a wide range of operating conditions, it should be understood that power amplifiers are the product of design compromises and, as a result, power amplifiers may have an optimum operating region, a region where the power amplifier is safe to operate, and a region where the power amplifier may fail.

[0035] 3 shows a voltage versus current graph 120 having a safe operating area marked by curve 122. As the current varies, as illustrated by line 124, the current may leave the safe operating area (sometimes called the safe operating area (SOA)), as shown by region 126. Similarly, as the voltage varies, as shown by line 128, the voltage may leave the safe operating area, as shown by region 130. Region 126 may be an overcurrent fault and region 130 may be an overvoltage fault.

[0036] Again, power amplifiers are designed to be robust and continue to operate over a wide range of operating conditions, but it may be possible to push the power amplifier outside of its safe operating area and cause it to fail. FIG. 4 provides a voltage versus time graph 140 in which two amplifiers are operated. The first amplifier, indicated by line 142, remains within the safe operating area and continues to function. The second amplifier, indicated by line 144, has an overcurrent condition at time 146 and fails. After a sudden drop 148, operation does not continue for the second amplifier. Such a failure may lead to performance degradation up to and including complete loss of functionality (e.g., referred to as a "bricking" of the device). Perhaps recognizing that such failures may lead to erosion of consumer confidence, manufacturers subject power amplifiers to a myriad of tests to verify that the power amplifier is robust enough to withstand extreme voltage standing wave ratios (e.g., 10:1), large battery voltage levels (VBat), and Vcc voltages (e.g., +0.5V higher than normal). Even when there is no need to meet such manufacturer's robustness tests, it is desirable to provide a power amplifier that can withstand a variety of operating conditions with adequate worst-case margins.

[0037] FIG. 5 provides a block diagram of a power amplifier circuit 160 that employs a conventional protection scheme to help meet robustness testing. In particular, the power amplifier circuit 160 includes an overcurrent protection loop 162 and an overvoltage protection loop 164 that help prevent overcurrent and overvoltage conditions in an output stage 166 of the power amplifier 168. Although not shown, the power amplifier 168 may be a multi-stage power amplifier as illustrated in FIG. 1 for the power amplifier 18A. Additionally, the power amplifier 168 may have a driver amplifier stage 170 that may (or may not) be considered part of the power amplifier 168. The driver amplifier stage 170 may be separated from the output stage 166 by a capacitor 172 that blocks direct current (DC) but passes alternating current (AC). The output stage 168 receives a bias signal from a bias circuit 174 through a resistor 176. The bias circuit 174 may be adjusted by a bias adjuster circuit 178.

[0038] 5, current detector circuit 180 may sense the current provided to bias circuit 174 from bias adjuster circuit 178, with the understanding that this detected current is a reasonable proxy for the current provided to bias circuit 174, and therefore also a reasonable proxy for the current output by output stage 166. Current detector circuit 180 also provides a current protection signal 182 to an adjustable current source 184 associated with bias adjuster circuit 178 when a current level above a predetermined threshold is detected.

[0039] It should be understood that conventional GaAs power amplifiers have difficulty in implementing overcurrent protection loops compared to the voltages required by HBT devices for proper operation. That is, for example, direct Vcc collector current sensing is generally not recommended as it would adversely affect the operation of the power amplifier. On the base side, there is generally not enough voltage headroom at the minimum supply voltage to allow for the inclusion of additional HBT devices for control. Furthermore, GaAs HBT processes do not allow for the implementation of efficient digital control circuits and tunability of the protection loop.

[0040] With continued reference to FIG. 5, the voltage detection circuit 186 detects the voltage level associated with the output stage 166 and provides a voltage protection signal 188 to the bias circuit 174 when the detected voltage level exceeds a predetermined threshold.

[0041] While the current detector circuit 180 and the voltage detector circuit 186 help reduce or eliminate instances where the current and / or voltage exceed design tolerances, at least three limitations have been observed. First, the overcurrent protection signal 182 and the overvoltage protection signal 188 may operate together to make adjustments in the bias regulator circuit 178 that cancel adjustments made in the bias circuit 174, or vice versa. As each circuit compensates the other, the changes may induce ringing in the output stage 166, where the ringing may adversely affect performance. Second, while the current and voltage limits may be in place, the driver amplifier stage 170 may continue to drive the signal 190 to a large value, which may in turn cause the output stage 166 to leave its safe operating area, resulting in failure or damage to the output stage. Third, many overvoltage protection circuits are implemented with diode stacks, which typically require a relatively large area on the die due to the need to hold the limited current. Similarly, the diode stacks only provide a level of electrostatic protection that may not reflect the contours of the safe operating area.

[0042] Exemplary aspects of the present disclosure provide various tools for managing the operation of the power amplifier circuit. Particularly contemplated aspects include providing additional control to the driver amplifier stage through control of a bias circuit or regulator circuit of the driver amplifier stage, or through a clamp circuit on the connection between the driver amplifier stage and the output stage (e.g., thereby clamping the signal 190). A further tool is linking the overvoltage protection signal to the overcurrent protection signal so that ringing is reduced or minimized. Yet another tool is dynamic adjustment of the overvoltage condition based on the presence or absence of an overcurrent condition. That is, when an overcurrent condition occurs, it takes less voltage to induce a fault. Thus, during an overcurrent situation, the threshold of the overvoltage protection signal may be lowered.

[0043] While the illustrated embodiment focuses on a GaAs BJT implementation, it should be understood that the disclosure is not so limited. In exemplary embodiments, the concepts of the disclosure may be applied to amplifiers formed from GaAs, GaAN, SiGe, Si, etc. Similarly, the amplifiers may use transistors that are BJTs, HBTs, FETs, etc. In particularly contemplated embodiments, the power amplifier circuit may provide a hybrid RF path with a CMOS driver and a GaAs (either BJT or HBT) output stage. It should be understood that the concepts disclosed herein are applicable to any power amplifier configuration, including, but not limited to, single-ended, differential, pseudo-differential, quadrature, Doherty, out-of-phase, etc. Additionally, while the description of Figures 1 and 2 reflects a 5G implementation, it should be understood that the concepts disclosed herein are applicable to 3G and / or 4G use cases, and that the digital control circuitry (described in more detail below) may enable switching between different protection limits when switching between 3G, 4G, and 5G use cases when a single mode transmit chain is used.

[0044] As described above, DC sensing may be inappropriate. Thus, in some implementations, indirect current sensing at the base of the device may be appropriate. Similarly, the overcurrent protection loop advantageously has a device with a much lower control voltage level (e.g., Vgs << Vbe) and has a digital circuit that can provide control and adjustability of the overcurrent protection loop settings. Thus, biasing the collector of the emitter follower from a dedicated regulator provides a path for sensing and limiting the collector current, which in turn limits the base current of the output device. Such regulators may be implemented in a silicon process (e.g., CMOS or BiCMOS). A digital-to-analog converter (DAC) can be used to adjust and program the current limit value. However, such an arrangement is not strictly required for all aspects of the present disclosure, but is used to illustrate exemplary aspects of the present disclosure.

[0045] In this regard, FIG. 6 shows a power amplifier circuit 200 including an overcurrent protection loop 202 and an overvoltage protection loop 204 to assist in protecting a power amplifier 206 including an output stage 208. Although not shown, the power amplifier 206 can be a multistage power amplifier as shown in FIG. 1 for the power amplifier 18A. Further, the power amplifier 206 can have a driver amplifier stage 210 that can be considered part of (or not part of) the power amplifier 206. The driver amplifier stage 210 can be separated from the output stage 208 by a capacitor 212 that blocks direct current (DC) but passes alternating current (AC). The output stage 208 receives a bias signal from a bias circuit 214 through a resistor 216. The bias circuit 214 can be adjusted by a bias regulator circuit 218.

[0046] 6, current detector circuit 220 may sense the current provided to bias circuit 214 from bias adjuster circuit 218, with the understanding that this detected current is a reasonable proxy for the current provided to bias circuit 214, and therefore also a reasonable proxy for the current output by output stage 208. Current detector circuit 220 also provides a current protection signal 222 to an adjustable current source 224 associated with bias adjuster circuit 218 when a current level above a predetermined threshold is detected.

[0047] With continued reference to FIG. 6, the voltage detection circuit 226 detects the voltage level associated with the output stage 208 and provides a voltage protection signal 228 to the bias circuit 214 when the detected voltage level exceeds a predetermined threshold.

[0048] To address one of the limitations of the system of FIG. 5, an auxiliary overcurrent protection loop 230 is added. The auxiliary overcurrent protection loop 230 provides a second overcurrent protection signal 232 in a manner that helps limit the driver stage 210. As shown in FIG. 6, the second overcurrent protection signal 232 is provided to a driver regulator circuit 234. The driver regulator circuit 234 regulates the driver stage 210 much like the regulator circuit 218 regulates the output stage 208. It should be noted that in the exemplary embodiment, the regulator circuit 218 and the driver regulator circuit 234 are implemented on a CMOS die, while the bias circuit 214, the output stage 208, and the detector circuits 220, 226 are all implemented on a GaAs die. Additionally, it should be noted that if the overcurrent protection loop 202 and the overvoltage protection loop 204 operate independently, the timing of the overcurrent protection loop 202 may be relatively fast compared to the timing of the overvoltage protection loop 204, resulting in quick changes through the overcurrent protection and gradual changes through the overvoltage loop 204. By having this different timing, the possibility of ringing is reduced.

[0049] To further reduce the possibility of ringing, the power amplifier circuit 200' takes the additional step of coupling the overvoltage protection signal 228 to the overcurrent protection signal 222 via signal 236, as shown in FIG. 7. In most other respects, the power amplifier circuit 200' is substantially identical to the power amplifier circuit 200 of FIG. 6. The net result of adding the overvoltage protection signal 236 to the overcurrent protection signal 222 is a resulting signal 222' that activates the regulator circuit 218 sooner than a high current condition alone. In an exemplary embodiment, only the overvoltage protection signal 236 exceeds a threshold sufficient to trigger the overcurrent protection means (e.g., limit the controller 224). The combined signal 222' also affects the signal 232' that controls the driver regulator circuit 234.

[0050] Instead of controlling the driver regulator circuit 234 as shown in FIG. 6 or FIG. 7, the second overcurrent protection signal 232 or 232′ may instead control a driver bias circuit 240, which biases the driver stage 210 through a resistor 242, as shown in the power amplifier circuit 200″ of FIG. 8. It should be understood that the power amplifier circuit 200″ may have the linked loops 202 and 204 shown in FIG. 7 or the independent loops 202 and 204 shown in FIG. 6.

[0051] Instead of controlling the driver regulator circuit 234 or the bias circuit 240 as shown in FIGS. 6-8, the second overcurrent protection signal 232 or 232′ may instead control a clamp 250 that provides a limit to the output signal 252 of the driver stage 210 as shown in power amplifier circuit 200″ of FIG. 9. It should be understood that power amplifier circuit 200″ may have linked loops 202 and 204 as shown in FIG. 7 or independent loops 202 and 204 as shown in FIG. 6.

[0052] Instead of controlling the driver amplifier 210, it may be possible to provide additional control to the bias circuit 214, as shown in power amplifier circuit 200'''' of FIG. 10. Specifically, signal 232 lowers the bias voltage through bias circuit 214. Because bias circuit 214 receives signals from both loop 202 and loop 204, loop 204 does not need to be linked to loop 202 (although it could).

[0053] As mentioned above, the present disclosure may be implemented across multiple dies, which may have different technology types. For example, as shown in FIG. 11, the power amplifier circuit 270 includes a first die 272, which may be a CMOS die having digital control circuitry and a driver stage, and a second die 274, which may be a GaAs die having relatively high power BJTs therein. More specifically, the first die 272 may include an RF input 276 that receives an RF signal 278. The RF signal 278 passes through an input matching circuit 280, which may include, for example, a variable capacitor (Cin) 282 that receives a 2-bit control word from a control circuit 284. The RF signal 278 is then passed to a CMOS driver stage 286. The CMOS driver stage 286 may receive a driver current (Idrv) from a current source 288, which may receive, for example, a 5-bit control word from the control circuit 284. A variable resistor (Rfb) 290 may be present and couple the input and output of the CMOS driver stage 286 to provide a feedback loop for the driver stage 286. The variable resistor 290 may be controlled, for example, by a two-bit control word from the control circuit 284. The CMOS driver stage 286 may also receive an adjustment signal from a voltage regulator circuit 292. Although FIG. 11 suggests that the voltage regulator circuit 292 may be implemented in CMOS, it should be understood that there are equivalent NMOS circuits that rely on Vcc (rather than Vbat) that may be implemented without departing from this disclosure. The voltage regulator circuit 292 (similar to the regulator circuit 234 of FIG. 6) is controlled by the control circuit 284. Signals from the voltage regulator circuit 292 may also interact with a bias circuit 294 (similar to the bias circuit 240 of FIG. 8), which may be controlled by the control circuit 284. Additionally, the regulator circuit 296 (similar to the regulator circuit 224 of FIG. 6) may be controlled by the control circuit 284. The control circuit 284 may generate the control word and the control signal based on a signal 298 (similar to signals 222, 222′) from the second die 274.

[0054] 11, the second die 274 may include a bias circuit 300 having a plurality of BJTs 302(1)-302(N) therein, including mirror BJTs 302(2) and 302(3). The second die 274 may further include an output stage 304 (similar to 208) having a BJT 306 therein. A current sensor circuit 308 and a voltage sensor circuit 310 may provide an overcurrent protection signal 298 and an overvoltage protection signal 312. While this arrangement is specifically contemplated, other arrangements may be made without departing from this disclosure. For example, sensors (Vbat, Vcc, etc.) may be included on the first die 272.

[0055] Although the above embodiment is good at detecting and preventing overcurrent and overvoltage conditions, the two events do not exist in isolation. Thus, part of the benefit of linking the overvoltage loop to the overcurrent loop is that the detection of an overvoltage condition automatically starts controlling the current. However, controlling the current and voltage alone may not be enough to avoid failure. For example, as illustrated by graph 320 in FIG. 12, with a current threshold (line 322) of 0.4A and a voltage threshold (line 324) of 14V, the current 326 may be clipped in region 328 and the voltage may be clipped in region 330, which may cause a shift 332 resulting in activity in region 334 outside the safe region 336 of operation, resulting in failure of the power amplifier, even though both the current and the voltage are below the corresponding thresholds.

[0056] Exemplary aspects of the present disclosure provide a solution to shift 332 by allowing the voltage threshold to be dynamically changed based on the presence of an overcurrent condition. For example, using control circuit 284 of FIG. 11, the voltage threshold of signal 312 can be adjusted so that the overvoltage protection means engages at a much lower voltage level, thus protecting the output stage from failure in region 334. Additionally, the threshold can vary based on the cellular standard being used (e.g., 3G, 4G, and 5G may all have different base thresholds and may all have different adjusted thresholds). Additionally, the amount of adjustment to the voltage threshold can vary depending on the amount of overcurrent present.

[0057] FIG. 13 illustrates a dynamic threshold graph 320' in which an adjusted voltage threshold 324' curves the current and voltage as described in region 334' (compare region 334 of FIG. 12).

[0058] FIG. 14 provides a block diagram of an exemplary embodiment of how such a dynamic voltage threshold may be implemented. Many of the elements of the power amplifier circuit 350 are the same as those previously discussed. However, in the power amplifier circuit 350, the voltage detector 226 provides a signal 352 to a comparator circuit 354. The comparator circuit 354 generates an overvoltage protection signal 356 when the voltage detected from the signal 352 exceeds a reference voltage (i.e., a threshold) received via signal 358 from a bandgap circuit 360. The bandgap circuit 360 is set by a controller 362, which is in turn coupled to a current limit circuit 364. When the current limit circuit 364 is activated by the current detector 220, the current limit circuit 364 sends a signal 366 to a regulator circuit 362, causing the regulator circuit 362 to modify the bandgap circuit 360.

[0059] One simple way to implement a dynamic voltage threshold is to use a current injected into a resistor placed in series with one or more diode-connected devices. Lowering such a threshold level can be achieved by adjusting the value of the injected current. The output of the overvoltage protection loop can be a current injected into the bias circuit 214, resulting in a reduction in the bias voltage applied to the output stage 208.

[0060] While a variety of circuits can be used, FIG. 15 provides exemplary circuits for bias circuit 214″ and bandgap circuit 360. Specifically, bias circuit 214″ may include transistors 380, 382, ​​and 384, where transistors 382 and 384 are mirrored. Resistors 386 and 388 are placed in series between transistor 380 and transistors 382, ​​384. Bandgap circuit 360 may be a variable current source 390 having a series resistor 392 coupled to ground.

[0061] 16 provides yet another possible implementation of the power amplifier circuit 400 in which the voltage detector 226 includes a diode 402 and a capacitor 404. The voltage detector 226 also includes stacked transistors 406(1) through 406(N) and stacked transistors 408(1) through 408(M), where in FIG. 16 N=3 and M=2. The collector of transistor 408(M) generates the signal 352. The bias circuit 214''' is similar to the bias circuit 214'', but includes an additional resistor and capacitor.

[0062] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure, and all such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. 1. A power amplifier circuit, comprising: a power amplifier including an output stage configured to provide an amplified output signal; an overcurrent protection signal coupled to the power amplifier indicative of an overcurrent condition; a first bias adjuster circuit that uses the overcurrent protection signal to control a bias circuit of the output stage; and a current detector circuit configured to use the overcurrent protection signal to provide to a second supply regulator circuit that adjusts an input signal that drives the output stage.

2. A power amplifier circuit as described in claim 1, further comprising the first bias adjuster circuit.

3. A power amplifier circuit as described in claim 2, further comprising a bias circuit coupled to the first bias adjuster circuit, the bias circuit being coupled to the input of the power amplifier.

4. 3. The power amplifier circuit of claim 2, wherein the bias circuit comprises a mirrored pair of transistors.

5. 3. The power amplifier circuit of claim 2, wherein the bias circuit includes a transistor having an emitter, the emitter configured to bias the output stage.

6. 10. The power amplifier circuit of claim 1 further comprising the second supply regulator circuit.

7. 7. The power amplifier circuit of claim 6, further comprising a driver power amplifier controlled by the second supply regulator circuit.

8. 2. The power amplifier circuit of claim 1, wherein the power amplifier includes at least an input stage coupled to the output stage.

9. 9. The power amplifier circuit of claim 8, wherein the power amplifier includes an intermediate stage positioned between the input stage and the output stage.

10. 10. The power amplifier circuit of claim 1, further comprising a CMOS driver coupled to said power amplifier.

11. A power amplifier circuit, a power amplifier including an output stage configured to provide an amplified output signal; a voltage detection circuit coupled to the output stage; an overcurrent protection signal coupled to the power amplifier; a first bias adjuster circuit that uses the overcurrent protection signal to control a bias circuit of the output stage; and a current detector circuit configured to use the overcurrent protection signal to provide to a second supply regulator circuit that adjusts an input signal that drives the output stage; The power amplifier circuit, wherein the voltage detection circuit is configured to provide an overvoltage protection signal to the first bias adjuster circuit.

12. 12. The power amplifier circuit of claim 11, wherein the voltage detection circuit is coupled to the current detector circuit such that the overcurrent protection signal is summed with the overvoltage protection signal.

13. 12. The power amplifier circuit of claim 11, wherein the voltage detection circuit is configured to generate the overvoltage protection signal when the voltage detection circuit detects a first voltage that exceeds a first overvoltage threshold.

14. 14. The power amplifier circuit of claim 13, wherein the voltage detection circuit is configured to generate the overvoltage protection signal when the current detector circuit indicates an overcurrent condition and the voltage detection circuit detects a second voltage that exceeds a second overvoltage threshold that is lower than the first overvoltage threshold.

15. 1. A power amplifier circuit, comprising: a power amplifier including an output stage configured to provide an amplified output signal; a current detector circuit coupled to the power amplifier and configured to provide an overcurrent protection signal to a bias adjuster circuit that controls a bias circuit of the output stage using the overcurrent protection signal; a voltage detection circuit coupled to the output stage, generating an overvoltage protection signal when the voltage detection circuit detects a first voltage that exceeds a first overvoltage threshold; and a voltage detection circuit configured to generate the overvoltage protection signal when the current detector circuit indicates an overcurrent condition and the voltage detection circuit detects a second voltage that exceeds a second overvoltage threshold that is lower than the first overvoltage threshold.

16. 16. The power amplifier circuit of claim 15, wherein the voltage detection circuit is coupled to the current detector circuit such that the over-current protection signal is summed with the over-voltage protection signal.

17. 16. The power amplifier circuit of claim 15, wherein the power amplifier comprises bipolar or heterojunction transistors.

18. The power amplifier circuit of claim 15, further comprising a bias circuit, the bias circuit comprising a mirror pair of transistors.

19. The power amplifier circuit of claim 15, further comprising a bias circuit, the bias circuit including a transistor having an emitter, the emitter configured to bias the output stage.

20. A method for controlling a power amplifier circuit, comprising: providing an amplified output signal to an output stage of a power amplifier; providing an overcurrent protection signal from a current detector circuit coupled to the power amplifier to a bias adjuster circuit; controlling a bias circuit of the output stage by the bias adjuster circuit based on the overcurrent protection signal; generating an overvoltage protection signal by a voltage detection circuit coupled to the output stage when the voltage detection circuit detects a first voltage exceeding a first overvoltage threshold; generating the overvoltage protection signal when the current detector circuit indicates an overcurrent condition and the voltage detector circuit detects a second voltage exceeding a second overvoltage threshold that is lower than the first overvoltage threshold.

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