Driver Circuitry and Power System

Abstract

In one example, a circuit (100) includes an input stage (106) having a control voltage input, a feedback input, a first control output, and a second control output. The feedback input is coupled to the driver output (102). A first path stage (108) has a first voltage input and a third output. The first voltage input is coupled to the first control output, and the third output is coupled to the driver output. A second path stage (110) has a second voltage input and a fourth output. The second voltage input is coupled to the second control output, and the fourth output is coupled to the driver output (102). A load transistor has a control input coupled to the driver output (102). The input stage (106) is configured to provide gm boosting to the first path stage (108) to turn on the load transistor in response to an output voltage at the voltage output.

Description

[Technical field]

[0001] The present description relates to driver circuitry and systems that employ driver circuitry. [Background technology]

[0002] Low dropout (LDO) voltage regulators provide power in a variety of applications, such as low voltage devices, such as voltage controlled oscillators (VCOs), analog-to-digital converters, digital-to-analog converters (DACs), high-end processors, radio frequency (RF) amplifiers, serializer-deserializer (SerDes) circuits, field programmable gate arrays (FPGAs), etc. The power management circuitry configured to drive the LDO can affect the performance of the LDO. For example, the speed and headroom of the power management circuitry can affect the overall LDO performance. Summary of the Invention

[0003] In a described example, a circuit includes an input stage, first and second path stages, and a load transistor. The input stage has a control voltage input, a feedback input, a first control output, and a second control output. The feedback input is coupled to the driver output. The first path stage has a first voltage input and a third output. The first voltage input is coupled to the first control output, and the third output is coupled to the driver output. The second path stage has a second voltage input and a fourth output. The second voltage input is coupled to the second control output, and the fourth output is coupled to the driver output. The load transistor has a control input and a voltage output. The control input is coupled to the driver output, and the input stage is configured to apply gm boosting to the first path stage to turn on the load transistor in response to an output voltage at the voltage output.

[0004] In another described example, a circuit includes a common path input stage configured to provide a first gm boosted control signal at a first output in response to an error signal requesting a load transistor to be turned on. The common path input stage is configured to provide a second control signal at a second output in response to an error signal requesting a load transistor to be turned off. The first path stage is configured to provide a first voltage to the driver output in response to the first gm boosted control signal. The second path stage is configured to provide a second voltage to the driver output in response to the second control signal. The load transistor is configured to adjust the output voltage in response to the voltage at the driver output by turning on in response to the first voltage and turning off in response to the second voltage.

[0005] In a further described example, a system includes an outer loop circuit, a class AB driver, and a load. The outer loop circuit has a reference input, a feedback voltage input, and an error output. The class AB driver includes a common path stage, a pull-up path circuit, and a pull-down path circuit. The common path stage has an error input, a feedback input, a first gm boost output, and a second output. The error input is coupled to the error output. The pull-up path circuit includes a first buffer and a pull-up transistor. The first buffer has a first buffer input and a first buffer output, the first buffer input being coupled to the first gm boost output. The pull-up transistor has a first control input and a third output. The first control input is coupled to the first buffer output, and the third output is coupled to the driver output. The pull-down path circuit includes a second buffer and a pull-down transistor. The second buffer has a second voltage input and a second buffer output, the second voltage input coupled to the second output. The pull-down transistor has a second control input and a fourth output. The second control input is coupled to the second buffer output and the fourth output is coupled to the driver output. The load has an input and a feedback output, the input coupled to the driver output and the feedback output coupled to the feedback voltage input. The feedback output is configured to provide a signal representative of the output voltage. [Brief description of the drawings]

[0006] [Figure 1] 1 illustrates an example driver circuit coupled to a load.

[0007] [Diagram 2] 1 illustrates an example voltage regulator including a driver circuit.

[0008] [Diagram 3] 1 illustrates an example driver circuit implementation.

[0009] [Figure 4]1 illustrates graphs showing open-loop and closed-loop responses for various example driver circuits.

[0010] [Diagram 5] 2 illustrates another example driver circuit coupled to a load. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Various examples relate to driver circuitry, such as Class AB driver circuits, as well as systems and circuits that implement one or more Class AB driver circuits.

[0012] As an example, a driver circuit includes a common path input stage and first and second output stages coupled in parallel between first and second voltage terminals. Each of the first and second output stages may be implemented as including a respective buffer and output transistor. The output transistors may be coupled between the first and second voltage terminals, with each output transistor coupled to a driver output. The common path input stage has first and second outputs, the first output coupled to an input of a respective buffer of the first output stage and the second output coupled to an input of a respective buffer of the second output stage. The common path input stage is configured to provide a transconductance (gm) boosted control signal at the first output for controlling a respective output transistor of the first output stage in response to an error signal. The common path input stage is configured to provide a second control signal at the second output for controlling a respective output transistor of the second output stage in response to the error signal. The common path input stage is configured to apply a gm boost to the same polarity as the common path input or load transistor being driven. In an example of an n-channel metal oxide semiconductor (NMOS) input or load, the common path input stage is configured to apply a gm boost to the pull-up or turn-on of the load NMOS. In an example of a p-channel metal oxide semiconductor (PMOS) input or load, the common path input stage is configured to apply a gm boost to the pull-down or turn-on of the load PMOS. In some examples, the common path circuit includes a compensation filter to reduce peaking in the closed loop response of the driver circuit.

[0013] The driver circuit described herein can be implemented as a closed-loop class AB driver configured to provide a drive signal to a capacitive circuit adapted to be coupled to the driver output. The capacitive circuit can include a field effect transistor (FET), such as an n-channel field effect transistor (NFET) or a p-channel FET (PFET), a bipolar junction transistor (BJT), such as an NPN or PNP, and / or other devices having an input capacitance. For example, the driver output is coupled to a gate of a low threshold voltage (Vth) low dropout (LDO) power FET. The driver circuit is configured to use gm boosting to turn on the power FET. The driver circuit can also be configured to drive the gate of the LDO power FET close to ground for full turn-off in low input low output (LILO) operation, which allows the driver circuit to achieve low headroom. The driver circuit can further maintain a low output impedance at the driver output for a finite current budget to remain stable in a high bandwidth (e.g., greater than 1 MHz) LDO loop. As such, the Class AB driver circuits and systems described herein can be configured to implement low headroom, high bandwidth driver circuits that can also achieve reduced output impedance using less current to allow the upstream power management implemented by the common path circuitry to have a smaller area and use reduced current compared to many existing designs.

[0014] As used herein, the term "circuit" can include a collection of active and / or passive elements that perform a circuit function, such as an analog or control circuit. Additionally or alternatively, for example, the term "circuit" can include an integrated circuit (IC) in which all and / or some of the circuit elements are fabricated on a common substrate (e.g., a semiconductor substrate such as a die or chip). In one example, the driver circuit 100 is implemented in an integrated circuit (IC) chip or as part of a system-on-chip (SoC).

[0015] 1 illustrates an exemplary Class AB driver circuit 100 having a driver output 102. For example, the driver output 102 is a terminal adapted to be coupled to an output circuit element 104. In one example, the output circuit element 104 includes a capacitive load, such as including a transistor (e.g., FET, BJT, etc.), a capacitor or load device having an input capacitance (e.g., greater than 100 pF) when coupled to the driver output 102. The driver circuit 100 includes a common path input stage 106, a first output stage 108, and a second output stage 110. The common path input stage 106 has an input 112 and first and second outputs 114 and 116. The input 112 is adapted to receive an error signal V_ERROR, such as representing a command to increase or decrease an output voltage provided to or otherwise used by the output circuit element 104. 1, driver circuit 100 is coupled between first and second voltage terminals 118 and 120, shown as voltage VDD and ground. In other examples, other relative voltages can be used to establish a desired voltage potential between terminals 118 and 120.

[0016] The input stage 106 includes an input transistor M1 having a gate coupled to (or providing) the common path input 112. In the example of FIG. 1, M1 is shown as an NFET. In another example, M1 may be implemented as a PFET or another type of transistor. The drain of M1 is coupled to a current mirror 122, the source of M1 is coupled to the driver output 102, and the driver circuit 100 provides the driver output signal VDRV. The current mirror 122 includes transistors M2 and M3, shown as p-channel FETs (PFETs). In another example, the current mirror 122 can be implemented using different types of transistors, with different driver configurations, etc. M2 is diode connected, where the source is coupled to the terminal 118 and the drain is coupled to the drain of M1. The source of M3 is coupled to the terminal 118, and the drain is coupled to a ground terminal 120 via a current source 124. The current source 124, which may be a fixed bias current or a dynamic bias current, etc., is configured to provide a bias current to the drain of M3. A compensation filter network 126 is coupled in parallel to the current source 124. The drain of M3, which is coupled to the current source 124 and the filter network 126, is also coupled to the first output 114 of the input stage 106. The filter network 126 is configured to stabilize the output 114.

[0017] The first output stage 108 includes a buffer 130 and an output transistor M4. An input of the buffer 130 is coupled to the first output 114, and the buffer output is coupled to the gate of M4. M4 is coupled between the voltage terminal 118 and the driver output 102. For example, the input of the buffer 130 has a positive polarity. The input stage 106 is configured to provide a gm boosted control signal at 114 in response to the error signal V_ERROR having a value representing a command to increase (or decrease) the output voltage. Gain boosting circuitry, including, for example, a current source 124 and a filter network 126, is coupled to the output of the current mirror (the drain of M3 and the output 114). As described herein, the gain boosting circuitry provides a gain described by gm of M3 times the output impedance at 114 based on the combined impedance at the drain of M3, the current source 124, and the filter network 126. Thus, the gain boosting circuitry is configured to implement gm boosting for the first output stage 108. As such, input stage 106 is configured to provide a gm boosted control signal to the input of output stage 108. In the example of Figure 1, buffer 130 is configured to pass the gm boosted signal from 114 to the gate of M4, which turns on to couple driver output 102 to terminal 118, thereby pulling up driver output 102. The gm boosted control signal at 114 allows for a stronger turn on for M4, as described herein, to provide improved responsiveness to increased power demands of output circuitry 104.

[0018] The second output stage 110 includes a buffer 132 and an output transistor M5. An input of the buffer 132 is coupled to the second output 116, which is coupled to the common gates of M2 and M3. An output of the buffer 132 is coupled to the gate of M5, which is coupled between the driver output 102 and the voltage terminal 120. For example, the input of the buffer 132 has a negative polarity (e.g., the opposite polarity to that at the input of the buffer 130). The input stage 106 is configured to provide a respective control signal at the second output 116 in response to the error signal V_ERROR requesting a decrease or no change in the output voltage. In the example of FIG. 1, the buffer 132 is configured to pass the second control signal to the gate of M5, which activates M5 to couple the driver output 102 to the terminal 120 and pull the driver output 102 near ground as required. The input stage 106 can be configured to provide the second control signal to the second output stage 110 without gm boost, as provided to the first output stage 108. The gm boosted control signal at 114 enables a stronger turn on for M4 than for M5, thereby reducing undershoot at the output 102 in response to increased voltage and / or current demands of the output circuitry 104 in response to the signal at the output 102.

[0019] In some examples, M5 may be implemented using a transistor of the same flavor of transistor as M4. As used herein, a given type of transistor (e.g., FET or BJT) has multiple subtypes, referred to herein as types (e.g., n- or p-type). For example, a FET transistor type (e.g., MOSFET or junction FET (JFET)) may be implemented in n-channel FET (NFET) and PFET types. Similarly, a BJT type transistor may be implemented in NPN and PNP types. A given driver circuit 100 may include two or more types of transistors, and the different types of transistors may be the same or different types, as described herein. In an example where the driver circuit 100 is implemented using FETs, M4 and M5 are both NFETs, or M4 and M5 are both PFETs. In other examples, such as when M4 and M5 are implemented as bipolar junction transistors (BJTs), M4 and M5 are both NPN BJTs, or M4 and M5 are both PNP BJTs.

[0020] In an example where the output circuit element 104 is implemented to include a load transistor (e.g., an LDO power transistor such as M12 shown in FIG. 2 and FIG. 3) having a control input coupled to the driver output 102, the LDO transistor can be implemented as the same transistor type (e.g., n or p) as both M4 and M5. The LDO transistors coupled at 102 can be the same or different types of transistors as M4 and M5, but can also be implemented as the same type (e.g., n or p). For example, M4 and M5 are NFETs and the LDO transistors are NPN BJTs (e.g., all n-type transistors). In another example, M4 and M5 are PFETs and the LDO transistors are PNP BJTs (e.g., all p-type transistors). Other types and styles of transistors can also be used for M4, M5 and the LDO transistors. Using the same type of transistor for M4 and M5 in the push-pull buffer output stage of the class AB driver can improve the performance of LILO operation. For example, using the same type of transistor can help improve the headroom on M5 during pulldown of the driver output 102 and also help reduce the output impedance (e.g., 1 / gm) at 102 to increase the pullup strength of M4.

[0021] By configuring the input stage 106 to implement gm boosting as described herein, the output impedance at 102 can also be reduced for a given bias current. As a result, the driver circuit 100 can be implemented with low headroom and high bandwidth, making it particularly suitable for LILO operation and high speed. This further allows upstream power management circuitry (e.g., charge pump circuitry (not shown)) to be implemented in a reduced area and configured to operate at lower currents than many existing approaches.

[0022] FIG 2 illustrates an example voltage regulator system 200 configured to provide a regulated output voltage VOUT at an output 202. The regulator system 200 includes a driver circuit 100, such as may be used to implement the driver circuit 100 of FIG 1. The description of FIG 2 also refers to FIG 1. For example, the driver circuit 100 includes an input stage 106, a first output stage 108, and a second output stage 110, which are coupled between first and second voltage terminals 118 and 120, shown as VDD and ground. The output circuit 104 also includes a load transistor M12 and an output 202, and circuitry coupled to 202 (if any).

[0023] The regulator system 200 includes an outer loop circuit 204 configured to control the output voltage VOUT in response to the feedback. In the example of FIG. 2, the outer loop circuit 204 includes an error amplifier 206 having an inverting input coupled to the output 202. In another example, a divider circuit (e.g., a resistive divider) can also be coupled between the output 202 and the inverting input of the error amplifier 206. A non-inverting input of the error amplifier 206 is configured to receive a reference voltage VREF. For example, the non-inverting input is coupled to an output of a reference voltage generator (e.g., a digital-to-analog converter or other DC source) configured to provide the reference voltage VREF. The error amplifier 206 has an output coupled to an input 112 of the input stage 106. A filter network including, for example, a resistor R1 and a capacitor C1 is coupled between the amplifier output and ground. The filter network is configured to help stabilize an error signal V_ERROR to the input 112 that is provided to the input 112 of the driver circuit 100. The error amplifier 206 is configured to provide an error signal V_ERROR to the input 112 in response to VOUT and VREF. The error signal V_ERROR provides a voltage command that indicates whether a higher or lower output voltage should be generated at the output 202.

[0024] The input stage 106 includes an input transistor M1 having a gate coupled to the output of the amplifier 206. A filter 208 is coupled in an inner loop feedback path between a source of M1 and the driver output 102. For example, the filter 208 includes a parallel resistor R2 and a capacitor C2 configured to attenuate peaking of the driver output signal VDRV provided at the output 102. The drain of M1 is coupled to a current mirror 122 formed of FETs M2 and M3. The gate and drain of M2 are coupled to the drain of M1. M2 and M3 have a common gate and a common source coupled to the terminal 118. The drain of M3 is coupled to a ground terminal 120 via a current source 124. The current source 124 is configured to provide a bias current to the drain of M3, such as a fixed or dynamically biased current source. The current source 124 can be implemented to include a current mirror arrangement coupled to a main bias current generator (e.g., within an IC implementing the system 200). In the example of FIG. 2, a compensation filter network 126 coupled in parallel to the current source 124 includes a resistor R3 and a capacitor C3 coupled in series between the output 114 and a terminal 120 (eg, ground).

[0025] The first output stage 108 of the driver circuit 100 includes a PFET M6 coupled in series with respective current sources 210 and 212 between voltage terminals 118 and 120. The gate of M6 is coupled to the output 114 of the input stage 106. The source of M6 is coupled to the gate of an NFET M4, the source of which is coupled to the driver output 102. Another NFET M7 is coupled between the gate of M4 and the ground terminal 120. The gate of M7 is coupled to the drain of M6. Thus, in the example of FIG. 2, the input stage 106 is implemented as a gm boosting buffer for a drive control path (e.g., shown as a turn-on path) configured to control the drive output 102 to pull up, turning on the load transistor M12, in response to the error signal V_ERROR having a value representing a command to increase the output voltage VOUT at 202.

[0026] The second output stage 110 of the driver circuit 100 includes a PFET M8 having a source coupled to a voltage terminal 118 (e.g., VDD) and a drain coupled to the drain of M9 and the gates of both M9 and M10. Like M8, the sources of M9 and M10 are coupled to the voltage terminal 118. A current source 214 is coupled between the drain of M9 and a voltage terminal 120 (e.g., ground). The current source 214 is configured to bias the current mirror network formed by M8, M9, and M10. The drain of M10 is coupled to the drain of an NFET M11, which is diode-connected between M10 and the voltage terminal 120 (e.g., ground). The gate and source of M11 are coupled to the gate of the output FET M5. 2, the buffer formed by M8, M9, M10, M11 and current source 214 is configured to turn on M5 and pull down the driver output 102 in response to a control signal provided by input stage 106 at 116. As mentioned above, input stage 106 is configured to provide a control signal at 116 to activate output FET M5 in response to error signal V_ERROR commanding a decrease or no increase in VOUT.

[0027] The system 200 also includes a load FET M12 having a gate coupled to the driver output 102. The source of M12 is coupled to the output terminal 202, and the drain of M12 is coupled to an input voltage terminal 216 adapted to be coupled to an input voltage VIN. For example, M12 is implemented as an LDO power FET. As described herein, M12 can be implemented as an n- or p-type load transistor. In the example of FIG. 2, M4, M5, and M12 are shown as being implemented as respective NFETs. In another example, M4, M5, and M12 are implemented as PFETs where VDD and VIN are the same voltage supply.

[0028] Each of M4, M5, and M12 can be implemented using the same type of transistor as described herein. In FIG. 2, each of M4, M5, and M12 is implemented using its respective NFET. In an alternative, each of M4, M5, and M12 can be implemented using its respective PFET. In such an alternative, the type of the remaining FETs in the driver circuit is changed (e.g., NFETs become PFETs and PFETs become NFETs), and the relative voltages can be inverted from those illustrated and described. In yet another example where the transistor is implemented using a BJT, each of M4, M5, and M12 can be implemented using the same type of BJT. That is, they can be NPN BJTs or PNP BJTs. Each transistor may be implemented with the same type even if the types are mixed between FETs and BJTs.

[0029] In one example, a regulator system 200 including an outer loop circuit 204, a driver circuit 100, and an output FET M12 is implemented on a single IC (e.g., on a given IC die). In another example, the output FET M12 is part of a separate IC external to the IC implementing the driver circuit 100 and the outer loop circuit 204.

[0030] In the example of FIG. 2, the driver circuit 100 is configured to gm-boost the turn-on path implemented by the output stage 108 in response to the error signal V_ERROR having a value indicating VOUT < VREF. For example, the gain for the driver circuit 100 is expressed as follows. TIFF2024538194000002.tif768Here, gm1 / gm2 represents the gain of the input stage 106 due to M1 and M2, gm8·gm10·gm5 / gm9·gm11 represents the gain of the output stage 110 due to M8, M10, M5, M9, and M11, TIFF2024538194000003.tif635 represents the gain of output stage 108 due to M4 and M3, and the output impedance of M3 in parallel with the impedance of current source 124 in parallel with filter network 126 including resistor R3 and capacitor C3. So, in effect, the component values ​​can be configured to adjust the gm boost applied to the input of output stage 108 during pull-up of VDRV at driver output 102 or when M12 is turned on. For example, current source 124 and filter network 126 are configured to increase the impedance at the gate of M6 (e.g., at output 114) to implement gm boosting to the first path stage, as shown in the equation above. In one example, gm boosting occurs due to an increased impedance at the output 114 of input stage 106 (e.g., TIFF2024538194000004.tif630), the transconductance gain (gm) can be increased by a factor of 100 or more.

[0031] Thus, gm boosting during turn-on of M4 can push the pole of the capacitive power FET gate (or other capacitive load coupled to the driver output 102) out of the LDO loop to a higher frequency while using a small amount of bias current. The second output stage 110 has a saturation voltage V DSAT For example, in response to M5 being turned on to pull down the driver output 102, the drive voltage VDRV is configured to pull M5 (e.g., V DSAT,M5 ) saturation voltage. Such a feature can be implemented (e.g., on an IC) in low-cost, low-bias current circuitry that is useful for high-bandwidth LDO operation.

[0032] In view of the above, voltage regulation system 200 includes a Class AB driver circuit that provides the desired voltage headroom and high bandwidth over a range of expected operating conditions. The driver circuit is particularly efficient and economical for LILO applications.

[0033] FIG. 3 illustrates a high-level circuit diagram of an example regulator system 300 including a closed-loop class AB driver circuit 100 as described herein. The driver circuit 300 can be implemented in accordance with the example drivers described herein, such as the circuits 100 and 200 shown in FIG. 1 and FIG. 2. Accordingly, the description of FIG. 3 also refers to FIG. 1 and FIG. 2. Other configurations of driver circuitry according to this description can also be used in the regulator system 300. The regulator system 300 includes an outer control loop including an error amplifier 206 having an inverting input coupled to the regulator output 202 and a non-inverting input configured to receive a reference voltage VREF. A filter, such as one including R1 and C1, is coupled to the output of the error amplifier 206 to provide an error signal V_ERROR at the input 112 of the driver circuit 100.

[0034] The driver circuit 100 includes a common path input stage 106 and respective output stages 108 and 110. As described herein, the common path input stage 106 is configured to implement a gm boost to the output stage 108. The gm boosting allows the driver circuit to react more quickly to increased current demands and reduce undershoot. As a result, the driver circuit 100 is configured to implement a stronger turn-on for the LDO power FET M12, or pull up VDRV at 102. This is in contrast to some existing designs that tend to be configured to implement a stronger turn-off of the LDO power FET to reduce overshoot transients.

[0035] In one example, the system 300, including the outer loop circuit 204, the driver circuit 100, and the output FET M12, are implemented within a common IC. In another example, the output FET M12 is part of a separate IC external to the IC that implements the driver circuit 100 and the outer loop circuit 204.

[0036] 3, the output circuit element 104 includes an input capacitor COUT coupled to the output 202 in parallel with a load 304. The load 304 can be implemented by a variety of electrical circuits. Examples of electrical circuits that can be implemented as the load 304 include a voltage controlled oscillator (VCO), an analog-to-digital converter, a DAC, a high-end processor, an RF amplifier, a SerDes circuit, and an FPGA. Alternatively, in other examples, M12, COUT, and the load 304 may be replaced with one or more other loads.

[0037] 4 shows graphs 400 and 402 illustrating open-loop and closed-loop gain and phase responses for various example class AB driver circuits at the gate of M4 for regulator system 200 of FIG. 2. Graph 400 includes open-loop response 404 and closed-loop response 406 for driver circuit 100 of FIG. 2, with filter 208 omitted from system 200. As shown in graphs 400 and 402, driver circuit 100 is configured to push the intermediate pole well beyond the unity gain bandwidth of the LDO. However, closed-loop response 406 in graph 400 (without filter 208) shows some peaking, as shown at 408. The peaking occurs just after the unity gain bandwidth of the global control loop for system 200.

[0038] Another graph 402 includes plots 410 and 412 of the respective open-loop and closed-loop phase responses of the driver circuit 100 in the absence of the RC filter 208 shown in Figure 2. When the driver circuit 100 is configured to include the parallel RC filter 208, the peaking 408 from the response 406 is eliminated or attenuated, such that the resulting driver circuit may be more stable over a range of expected operating conditions.

[0039] As another example, FIG. 5 is an exemplary class AB driver circuit 500 shown as a generally inverted version of the circuit 100 of FIG. 1. Accordingly, the description of FIG. 5 also refers to FIG. 1 as necessary. For example, the driver circuit 500 has an output 102 (e.g., a terminal) adapted to be coupled to an output circuit element 104, shown in FIG. 5 as including a PFET M12 (e.g., an LDO power PFET). As described herein, the driver circuit 100 includes a common-path input stage 106, a first output stage 108, and a second output stage 110. The common-path input stage 106 has an input 112 and first and second outputs 114 and 116. The input 112 is adapted to receive an error signal V_ERROR, such as representing a command to increase or decrease an output voltage VOUT at the output 202. In the example of FIG. 1, the driver circuit 100 is coupled between first and second voltage terminals 118 and 120, shown as voltages VDD and ground. In other examples, other relative voltages can be used to establish the desired voltage potential between terminals 118 and 120. Output 202 is coupled to a supply voltage VIN, which can be coupled to terminal 118.

[0040] In the example of FIG. 5, the input stage 106 includes a PFET M1 having a gate coupled to (or providing) the common path input 112. The drain of M1 is coupled to a current mirror 122 and the source of M1 is coupled to the driver output 102. The driver circuit 100 is configured to provide a driver output signal VDRV at 102. The current mirror 122 includes transistors M2 and M3, shown as NFETs. M2 is diode connected, with its source coupled to terminal 120 and its drain coupled to the drain of M1. The source of M3 is coupled to terminal 120 and its source is coupled to terminal 118 via a current source 124. The current source 124 is configured to provide a bias current to the drain of M3, such as a fixed or dynamic bias current. A compensation filter network 126 is coupled in parallel to the current source 124. The drain of M3 is coupled to the current source 124 and the filter network 126, and is also coupled to the first output 114 of the input stage 106. The filter network 126 is configured to stabilize the control signal at the output 114 .

[0041] The first output stage 108 includes a buffer 130 and an output transistor M4. An input of the buffer 130 is coupled to the first output 114, and the buffer output is coupled to the gate of M4. M4 is coupled between the voltage terminal 120 and the driver output 102. For example, the input of the buffer 130 has a negative polarity. The input stage 106 is configured to provide a gm boosted control signal at 114 in response to the error signal V_ERROR having a value representing a command to decrease (or not change) VOUT. Gain boosting circuitry, including for example a current source 124 and a filter network 126, is coupled to the output of the current mirror (the drain of M3 and the output 114). As described herein, the gain boosting circuitry provides a gain represented by gm of M3 times the output impedance at 114 based on the combined impedance at the drain of M3, the current source 124, and the filter network 126. Thus, the gain boosting circuitry is configured to implement gm boosting for the first output stage 108. As such, input stage 106 is configured to provide a gm boosted control signal to the input of output stage 108. In the example of Figure 1, buffer 130 is configured to pass the gm boosted signal from 114 to the gate of M4. M4 turns on in response to the gm boosted signal at 114 and couples the driver output 102 to terminal 120, such that the driver output 102 is pulled down to turn on PFET M12. The gm boosted control signal at 114 allows a stronger turn on for M4 to facilitate the turn on (e.g., pull down) of PFET M12, such as in response to the power demands of a load coupled at 202.

[0042] The second output stage 110 includes a buffer 132 and an output transistor M5. An input of the buffer 132 is coupled to the second output 116, which is coupled to the common gates of M2 and M3. An output of the buffer 132 is coupled to the gate of M5, which is coupled between the driver output 102 and the voltage terminal 118. For example, the input of the buffer 132 has a positive polarity (e.g., opposite to the polarity at the input of the buffer 130). The input stage 106 is configured to provide a respective control signal at the second output 116 in response to an error signal V_ERROR requesting an increase in VOUT. In the example of FIG. 5, the buffer 132 is configured to pass the second control signal to the gate of M5, which activates M5 to couple the driver output 102 to the terminal 118 and pull up the driver output 102, as required.

[0043] In view of the above, the circuits and systems described herein can implement driver circuits with lower headroom, higher bandwidth, and improved transient response. The driver circuits can also be configured with a lower output impedance for a given bias current, allowing the driver circuits to achieve higher bandwidth operation than other driver designs.

[0044] As a result, circuits and systems implementing a Class AB driver circuit as described herein can be used to provide a lower supply voltage to the end equipment load, resulting in power savings. Also, improved transient response, particularly due to reduced undershoot, can further achieve improved speed and higher accuracy. Lower bias currents used in the driver circuit (e.g., by current sources 124, 210, and 212) result in power savings and allow for smaller charge pumps. Taken together, such factors allow the driver circuit to be implemented in a smaller size than comparable existing solutions.

[0045] As used herein, the term "couple" means either an indirect or direct connection. Thus, when a first device couples to a second device, the connection can be through a direct connection or through an indirect connection via other devices and connections. For example, (A) in a first example, device A is coupled to device B if device A generates a signal to control device B to perform a certain action, or (b) in a second example, device A is coupled to device B via an intervening component C, where intervening component C does not change the functional relationship between device A and device B, and thus device B is controlled by device A via a control signal generated by device A.

[0046] The phrase "based on" means "based at least in part on." Thus, if X is based on Y, then X can be a function of Y as well as any number of other factors.

[0047] Modifications may be made to the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. A circuit comprising: an input stage having a control voltage input, a first control output, and a second control output; an input transistor having a control terminal coupled to the control voltage input, a first current terminal, and a second current terminal; a current mirror having a mirror input coupled to the first current terminal of the input transistor, a voltage source input coupled to the first voltage terminal, and a mirror output; a current source coupled between the mirror output and a second voltage terminal; a first filter network coupled in parallel with the current source between the mirror output and the second voltage terminal; an input stage including: a first path stage having a first voltage input coupled to the first control output and the mirror output, and a third output coupled to a driver output; a second path stage having a second voltage input coupled to the second control output and the mirror input, and a fourth output coupled to the driver output; a load transistor having a control input coupled to the driver output and a voltage output; Including, A circuit wherein the input stage is configured to provide gm boosting to the first path stage to turn on the load transistor in response to an output voltage at the voltage output.

2. 10. The circuit of claim 1, The circuit wherein the input transistor has a gate coupled to the control voltage input, a source, and a drain.

3. 3. The circuit of claim 2, the first path stage comprising: a first buffer having a first buffer input coupled to the first control output and a first buffer output; a first path output transistor having a first control terminal coupled to the first buffer output, a second terminal coupled to the first voltage terminal, and a third terminal coupled to the driver output; The circuit includes:

4. 4. The circuit of claim 3, A circuit wherein an impedance at the first control output is configured to implement the gm boosting for the first path stage.

5. 4. The circuit of claim 3, the second path stage comprising: a second buffer having a second buffer input coupled to the second control output and a second buffer output; a second path output transistor having a second control terminal coupled to the second buffer output, a fourth terminal coupled to the second voltage terminal, and a fifth terminal coupled to the driver output; The circuit includes:

6. 6. The circuit of claim 5, A circuit wherein the first path output transistor, the second path output transistor, and the load transistor are each the same type of transistor.

7. 7. The circuit of claim 6, wherein each of the first path output transistor, the second path output transistor, and the load transistor is implemented using a respective n-type transistor, or wherein each of the first path output transistor, the second path output transistor, and the load transistor is implemented using a respective p-type transistor.

8. 8. The circuit of claim 7, The circuit, wherein the input stage further has a feedback input, the input stage further including a second filter network coupled between the feedback input and the driver output.

9. 10. The circuit of claim 1, The circuit further includes an error amplifier having a reference input, a feedback voltage input coupled to said voltage output, and an error output coupled to a control voltage input of said input stage.

10. 10. The circuit of claim 9, The circuit, wherein the error amplifier is configured to provide an error signal to the control voltage input in response to the voltage output and a reference voltage received at the reference input.

11. A circuit comprising: a common path input stage configured to provide a first gm boosted control signal at a first output in response to an error signal requesting a load transistor to be turned on, and to provide a second control signal at a second output in response to said error signal requesting a load transistor to be turned off; an input transistor configured to conduct current from a first voltage terminal in response to the error signal; a current mirror configured to mirror a current from the input transistor and provide a mirrored current at the first output; a first filter network coupled in series between the input transistor and the load transistor; the common path input stage including: a first path stage configured to provide a first voltage to a driver output in response to the first gm boosted control signal; a second path stage configured to provide a second voltage to the driver output in response to the second control signal; Including, the load transistor is configured to adjust the output voltage in response to the voltage at the driver output by turning on in response to the first voltage and turning off in response to the second voltage.

12. 12. The circuit of claim 11, the first path stage includes a first transistor and a first buffer configured to buffer the first gm-boosted control signal to control the first transistor to turn on the load transistor; the second path stage includes a second transistor and a second buffer configured to buffer the second control signal to control the second transistor to turn off the load transistor.

13. 13. The circuit of claim 12, A circuit wherein the first transistor, the second transistor, and the load transistor are each implemented using a respective transistor of the same type.

14. 14. The circuit of claim 13, A circuit wherein each of the first transistor, the second transistor, and the load transistor is implemented with a respective n-channel field effect transistor or a respective p-channel field effect transistor.

15. 13. The circuit of claim 12, the common path input stage: a gain boosting circuit element coupled to the first output, the gain boosting circuit element configured to implement gm boosting for the first path stage in response to an impedance at the first output and the mirrored current; The circuit further comprises:

16. 16. The circuit of claim 15, the gain boosting circuitry comprising: a second filter network configured to stabilize a voltage at an input of the first path stage; a current source coupled in parallel with the second filter network between the first output and a second voltage terminal; Including, The circuit, wherein the current source and the second filter network are configured to provide the impedance to the first output to implement the gm boosting.

17. 17. The circuit of claim 16, A circuit wherein the first filter network is configured to reduce peaking in a closed-loop response of the circuit.

18. 17. The circuit of claim 16, The circuit, wherein the current source is configured to provide a fixed or variable current.

19. 13. The circuit of claim 12, The circuit, wherein the second path stage is configured to turn off the load transistor within a saturation voltage of ground or a supply voltage.

20. 12. The circuit of claim 11, The circuit further includes an error amplifier configured to provide the error signal in response to the output voltage and a reference voltage.

21. 1. A system comprising: an error amplifier having a reference input, a feedback voltage input, and an error output; A class AB driver, a common path stage having an error input coupled to the error output, a feedback input, a first gain-boosted output, and a second output; an input transistor having a current terminal; A current mirror comprising: a first transistor having a control terminal coupled to a current terminal of the input transistor, a first current terminal, and a second current terminal; a second transistor having a control terminal coupled to the second current terminal of the first transistor, a first current terminal coupled to the first gain boost output, and a second current terminal; the current mirror including the common path stage including: A pull-up path circuit, comprising: a first buffer having a first buffer input coupled to the first gain boost output and a first buffer output; a pull-up transistor having a first control input coupled to the first buffer output and a third output coupled to a driver output; the pull-up path circuit, A pull-down path circuit, comprising: a second buffer having a second voltage input coupled to the second output and a second buffer output; a pull-down transistor having a second control input coupled to the second buffer output and a fourth output coupled to the driver output; the pull-down path circuit comprising: the class AB driver, a capacitive load having an input coupled to the driver output and a feedback output coupled to the feedback voltage input, the feedback output configured to provide a signal representative of an output voltage; Including, the system.

22. 22. The system of claim 21, the capacitive load includes a load transistor; the common path stage: providing a gm boost for a circuit path to the driver output that turns on the load transistor; controlling the pull-down path circuit to pull down the driver output to ground or to within a saturation voltage of a supply voltage; The system is configured as follows:

23. 23. The system of claim 22, The system wherein each of the pull-up transistor, the pull-down transistor, and the load transistor is implemented using a respective transistor of the same type.

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