Leakage compensation circuit, chip and electronic device

Abstract

Embodiments of the present disclosure provide a leakage compensation circuit, a chip and an electronic device, and belong to the technical field of integrated circuits. The leakage compensation circuit comprises an output stage circuit, a first sampling circuit, an operational amplifier circuit and a second sampling circuit. The operational amplifier circuit comprises an operational amplifier output stage circuit and an operational amplifier first stage circuit which are coupled to each other. The first sampling circuit samples the leakage current of the output stage circuit to obtain a first sampling current, and provides the first sampling current to the operational amplifier output stage circuit through a first node. The second sampling circuit samples the current of the operational amplifier output stage circuit to obtain a second sampling current, and provides the second sampling current to the output stage circuit through a second node to compensate for the leakage current of the output stage circuit. The operational amplifier first stage circuit clamps the voltage of the first node and the second node.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of integrated circuit technology, and more specifically to a leakage current compensation circuit, chip, and electronic device. Background Technology

[0002] Because a PN junction exists between the source / drain and the substrate of a MOS transistor, leakage current exists even in the off state. This leakage current is particularly significant for high-drive and high-voltage output stages due to the larger size of the MOS transistor. This leakage current flows out from the output port, resulting in excessive leakage current.

[0003] Currently, the general approach to dealing with leakage current is to optimize the manufacturing process, but this does not fundamentally solve the problem of leakage current. Summary of the Invention

[0004] The purpose of embodiments of this disclosure is to provide a leakage current compensation circuit, chip, and electronic device that samples the leakage current of the output stage and inputs the sampled current back to the output stage, thereby compensating for the leakage current in the output stage.

[0005] To achieve the above objectives, according to a first aspect of this disclosure, a leakage current compensation circuit is provided, comprising: an output stage circuit, a first sampling circuit, an operational amplifier circuit, and a second sampling circuit, wherein the operational amplifier circuit includes an operational amplifier output stage circuit and an operational amplifier first stage circuit coupled to each other. The first sampling circuit is configured to sample the leakage current of the output stage circuit to obtain a first sampling current, and provide the first sampling current to the operational amplifier output stage circuit via a first node; the second sampling circuit is configured to sample the current of the operational amplifier output stage circuit to obtain a second sampling current, and provide the second sampling current to the output stage circuit via a second node to compensate for the leakage current of the output stage circuit; the operational amplifier first stage circuit is configured to clamp the voltages of the first node and the second node.

[0006] In some embodiments of this disclosure, the non-inverting input of the first stage of the operational amplifier is coupled to the second node, and the inverting input of the first stage of the operational amplifier is coupled to the first node.

[0007] In some embodiments of this disclosure, the operational amplifier output stage circuit includes: a fifth transistor and a sixth transistor, wherein the control electrode of the fifth transistor is coupled to a first output terminal of the first stage circuit of the operational amplifier, the first electrode of the fifth transistor is coupled to a fifth voltage terminal, and the second electrode of the fifth transistor is coupled to the first node; the control electrode of the sixth transistor is coupled to a second output terminal of the first stage circuit of the operational amplifier, the first electrode of the sixth transistor is coupled to a second voltage terminal, and the second electrode of the sixth transistor is coupled to the first node.

[0008] In some embodiments of this disclosure, the second sampling circuit includes a seventh transistor and an eighth transistor, wherein the control electrode of the seventh transistor is coupled to the first output terminal of the first stage of the operational amplifier circuit, the first electrode of the seventh transistor is coupled to the fifth voltage terminal, the second electrode of the seventh transistor is coupled to the second node, and the aspect ratio of the seventh transistor is a fixed multiple of the aspect ratio of the fifth transistor; the control electrode of the eighth transistor is coupled to the second output terminal of the first stage of the operational amplifier circuit, the first electrode of the eighth transistor is coupled to the second voltage terminal, the second electrode of the eighth transistor is coupled to the second node, and the aspect ratio of the eighth transistor is a fixed multiple of the aspect ratio of the sixth transistor.

[0009] In some embodiments of this disclosure, the operational amplifier output stage circuit further includes: a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the control electrode of the ninth transistor is coupled to a sixth voltage terminal, the first electrode of the ninth transistor is coupled to the second electrode of the seventh transistor, and the second electrode of the ninth transistor is coupled to the second node; the control electrode of the tenth transistor is coupled to the sixth voltage terminal, the first electrode of the tenth transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the tenth transistor is coupled to the first node; the control electrode of the eleventh transistor is coupled to a seventh voltage terminal, the first electrode of the eleventh transistor is coupled to the second electrode of the eighth transistor, and the second electrode of the eleventh transistor is coupled to the second node; the control electrode of the twelfth transistor is coupled to the seventh voltage terminal, the first electrode of the twelfth transistor is coupled to the second electrode of the sixth transistor, and the second electrode of the twelfth transistor is coupled to the first node.

[0010] In some embodiments of this disclosure, the output stage circuit includes: a first transistor and a second transistor, wherein the control electrode of the first transistor is coupled to a third voltage terminal, the first electrode of the first transistor is coupled to a first voltage terminal, and the second electrode of the first transistor is coupled to a second node; the control electrode of the second transistor is coupled to a fourth voltage terminal, the first electrode of the second transistor is coupled to a second voltage terminal, and the second electrode of the second transistor is coupled to the second node; the first sampling circuit includes: a third transistor and a fourth transistor, wherein the control electrode of the third transistor is coupled to the third voltage terminal, the first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the first node; the control electrode of the fourth transistor is coupled to the fourth voltage terminal, the first electrode of the fourth transistor is coupled to the second voltage terminal, and the second electrode of the fourth transistor is coupled to the first node, wherein the aspect ratio of the first transistor is a fixed multiple of the aspect ratio of the third transistor, and the aspect ratio of the second transistor is the fixed multiple of the aspect ratio of the fourth transistor.

[0011] In some embodiments of this disclosure, the output stage circuit includes: a first transistor and a first resistor, wherein the control electrode of the first transistor is coupled to a third voltage terminal, the first electrode of the first transistor is coupled to a first voltage terminal, and the second electrode of the first transistor is coupled to a second node; the first terminal of the first resistor is coupled to the second node, and the second terminal of the first resistor is coupled to a second voltage terminal; the first sampling circuit includes: a third transistor and a second resistor, wherein the control electrode of the third transistor is coupled to the third voltage terminal, the first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the first node; the first terminal of the second resistor is coupled to the first node, and the second terminal of the second resistor is coupled to the second voltage terminal, wherein the aspect ratio of the first transistor is a fixed multiple of the aspect ratio of the third transistor, and the resistance value of the second resistor is a fixed multiple of the resistance value of the first resistor.

[0012] In some embodiments of this disclosure, the output stage circuit includes: a second transistor and a third resistor, wherein the control electrode of the second transistor is coupled to a fourth voltage terminal, the first electrode of the second transistor is coupled to a second voltage terminal, and the second electrode of the second transistor is coupled to a second node; the first terminal of the third resistor is coupled to the second node, and the second terminal of the third resistor is coupled to a first voltage terminal; the first sampling circuit includes: a fourth transistor and a fourth resistor, wherein the control electrode of the fourth transistor is coupled to the fourth voltage terminal, the first electrode of the fourth transistor is coupled to the second voltage terminal, and the second electrode of the fourth transistor is coupled to the first node; the first terminal of the fourth resistor is coupled to the first node, and the second terminal of the fourth resistor is coupled to the first voltage terminal, wherein the aspect ratio of the second transistor is a fixed multiple of the aspect ratio of the fourth transistor, and the resistance value of the fourth resistor is a fixed multiple of the resistance value of the third resistor.

[0013] According to a second aspect of this disclosure, a chip is provided. The chip includes the leakage current compensation circuit described in the first aspect of this disclosure.

[0014] According to a third aspect of this disclosure, an electronic device is provided. The electronic device includes the chip described in the second aspect of this disclosure.

[0015] Other features and advantages of the embodiments disclosed herein will be described in detail in the following detailed description section. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate embodiments of the present disclosure and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present disclosure, but do not constitute a limitation on the embodiments of the present disclosure. In the drawings:

[0017] Figure 1 This is a schematic block diagram of a leakage current compensation circuit according to an embodiment of the present disclosure;

[0018] Figure 2 This is an exemplary circuit diagram of a leakage current compensation circuit according to an embodiment of the present disclosure;

[0019] Figure 3 This is another exemplary circuit diagram of a leakage current compensation circuit according to an embodiment of the present disclosure;

[0020] Figure 4 This is yet another exemplary circuit diagram of a leakage current compensation circuit according to an embodiment of the present disclosure;

[0021] Figure 5 This is an exemplary circuit diagram of the operational amplifier output stage circuit in a leakage current compensation circuit according to an embodiment of the present disclosure.

[0022] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0025] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0026] Figure 1 A schematic block diagram of a leakage current compensation circuit 100 is shown. The leakage current compensation circuit 100 may include: an output stage circuit 110, a first sampling circuit 120, an operational amplifier circuit 130, and a second sampling circuit 140. The operational amplifier circuit 130 includes an operational amplifier output stage circuit 132 and an operational amplifier first stage circuit 131 that are coupled to each other.

[0027] The output stage circuit 110 is coupled to the first sampling circuit 120, the first operational amplifier stage 131, the first voltage terminal V1, the second voltage terminal V2, and the output port Vout. The first sampling circuit 120 is coupled to the output stage circuit 110, the operational amplifier output stage circuit 132, the operational amplifier stage 131, the first voltage terminal V1, the second voltage terminal V2, the third voltage terminal V3, and the fourth voltage terminal V4. The operational amplifier stage 131 is coupled to the operational amplifier output stage circuit 132, the first sampling circuit 120, the output stage circuit 110, and the second sampling circuit 140. The operational amplifier output stage circuit 132 is coupled to the operational amplifier stage 131, the first sampling circuit 120, the second sampling circuit 140, the fifth voltage terminal V5, and the second voltage terminal V2. The second sampling circuit 140 is coupled to the operational amplifier output stage circuit 132, the operational amplifier stage 131, the output stage circuit 110, the fifth voltage terminal V5, and the second voltage terminal V2.

[0028] The first sampling circuit 120 is configured to sample the leakage current of the output stage circuit 110 to obtain a first sampling current, and provide the first sampling current to the operational amplifier output stage circuit 132 via a first node N1. The second sampling circuit 140 is configured to sample the current of the operational amplifier output stage circuit 132 to obtain a second sampling current, and provide the second sampling current to the output stage circuit 110 via a second node N2 to compensate for the leakage current of the output stage circuit 110. The first stage circuit 131 of the operational amplifier is configured to clamp the voltages of the first node N1 and the second node N2.

[0029] The output stage circuit 110 in this embodiment is a high-impedance output stage circuit. A conventional output stage circuit may include a single PMOS transistor; a single NMOS transistor; or a PMOS transistor and an NMOS transistor stacked vertically.

[0030] The following explanations will use the output stage circuit 110 as an example, which is a CMOS output stage, a PMOS output stage, and an NMOS output stage.

[0031] Figure 2 It shows Figure 1 The output stage circuit 110 of the leakage current compensation circuit 100 shown is an exemplary circuit diagram of a CMOS output stage. For example... Figure 2As shown, the output stage circuit 110 may include: a first transistor M1 and a second transistor M2. The control electrode of the first transistor M1 is coupled to a third voltage terminal V3, the first electrode of the first transistor M1 is coupled to a first voltage terminal V1, and the second electrode of the first transistor M1 is coupled to a second node N2. The control electrode of the second transistor M2 is coupled to a fourth voltage terminal V4, the first electrode of the second transistor M2 is coupled to a second voltage terminal V2, and the second electrode of the second transistor M2 is coupled to the second node N2. Correspondingly, the first sampling circuit 120 may include: a third transistor M3 and a fourth transistor M4. The control electrode of the third transistor M3 is coupled to the third voltage terminal V3, the first electrode of the third transistor M3 is coupled to the first voltage terminal V1, and the second electrode of the third transistor M3 is coupled to the first node N1. The control electrode of the fourth transistor M4 is coupled to the fourth voltage terminal V4, the first electrode of the fourth transistor M4 is coupled to the second voltage terminal V2, and the second electrode of the fourth transistor M4 is coupled to the first node N1. The aspect ratio of the first transistor M1 is a fixed multiple n of the aspect ratio of the third transistor M3, and the aspect ratio of the second transistor M2 is a fixed multiple n of the aspect ratio of the fourth transistor M4. Simultaneously, the non-inverting input of the first stage of the operational amplifier circuit 131 is coupled to the second node N2, and the inverting input of the first stage of the operational amplifier circuit 131 is coupled to the first node N1. The output stage circuit 132 of the operational amplifier may include a fifth transistor M5 and a sixth transistor M6. The control electrode of the fifth transistor M5 is coupled to the first output terminal O1 of the first stage of the operational amplifier circuit 131, the first electrode of the fifth transistor M5 is coupled to the fifth voltage terminal V5, and the second electrode of the fifth transistor M5 is coupled to the first node N1. The control electrode of the sixth transistor M6 is coupled to the second output terminal O2 of the first stage of the operational amplifier circuit 131, the first electrode of the sixth transistor M6 is coupled to the second voltage terminal V2, and the second electrode of the sixth transistor M6 is coupled to the first node N1. The second sampling circuit 140 may include a seventh transistor M7 and an eighth transistor M8. In this circuit, the control electrode of the seventh transistor M7 is coupled to the first output terminal O1 of the first stage of the operational amplifier circuit 131, the first electrode of the seventh transistor M7 is coupled to the fifth voltage terminal V5, and the second electrode of the seventh transistor M7 is coupled to the second node N2. The aspect ratio of the seventh transistor M7 is a fixed multiple n of the aspect ratio of the fifth transistor M5. Similarly, the control electrode of the eighth transistor M8 is coupled to the second output terminal O2 of the first stage of the operational amplifier circuit 131, the first electrode of the eighth transistor M8 is coupled to the second voltage terminal V2, and the second electrode of the eighth transistor M8 is coupled to the second node N2. The aspect ratio of the eighth transistor M8 is a fixed multiple n of the aspect ratio of the sixth transistor M6.

[0032] Figure 3 It shows Figure 1 The output stage circuit 110 of the leakage current compensation circuit 100 shown is an exemplary circuit diagram of a PMOS output stage. For example... Figure 3 As shown, the output stage circuit 110 may include: a first transistor M1 and a first resistor R1. The control electrode of the first transistor M1 is coupled to a third voltage terminal V3, the first electrode of the first transistor M1 is coupled to the first voltage terminal V1, and the second electrode of the first transistor M1 is coupled to the second node N2. The first terminal of the first resistor R1 is coupled to the second node N2, and the second terminal of the first resistor R1 is coupled to the second voltage terminal V2. Correspondingly, the first sampling circuit 120 may include: a third transistor M3 and a second resistor R2. The control electrode of the third transistor M3 is coupled to the third voltage terminal V3, the first electrode of the third transistor M3 is coupled to the first voltage terminal V1, and the second electrode of the third transistor M3 is coupled to the first node N1. The first terminal of the second resistor R2 is coupled to the first node N1, and the second terminal of the second resistor R2 is coupled to the second voltage terminal V2. Wherein, the aspect ratio of the first transistor M1 is a fixed multiple n of the aspect ratio of the third transistor M3, and the resistance value of the second resistor R2 is a fixed multiple n of the resistance value of the first resistor R1. Additionally, as... Figure 3 As shown, the connection relationship between the first stage circuit 131 of the operational amplifier, the output stage circuit 132 of the operational amplifier, and the second sampling circuit 140 is as follows: Figure 2 The circuit diagram shown is the same, so it will not be described again here.

[0033] Figure 4 It shows Figure 1 The output stage circuit 110 of the leakage current compensation circuit 100 shown is an exemplary circuit diagram of an NMOS output stage. For example... Figure 4As shown, the output stage circuit 110 may include a second transistor M2 and a third resistor R3. The control electrode of the second transistor M2 is coupled to a fourth voltage terminal V4, the first electrode of the second transistor M2 is coupled to a second voltage terminal V2, and the second electrode of the second transistor M2 is coupled to a second node N2. The first terminal of the third resistor R3 is coupled to the second node N2, and the second terminal of the third resistor R3 is coupled to a first voltage terminal V1. Correspondingly, the first sampling circuit 120 may include a fourth transistor M4 and a fourth resistor R4. The control electrode of the fourth transistor M4 is coupled to the fourth voltage terminal V4, the first electrode of the fourth transistor M4 is coupled to the second voltage terminal V2, and the second electrode of the fourth transistor M4 is coupled to the first node N1. The first terminal of the fourth resistor R4 is coupled to the first node N1, and the second terminal of the fourth resistor R4 is coupled to the first voltage terminal V1. The aspect ratio of the second transistor M2 is a fixed multiple n of the aspect ratio of the fourth transistor M4, and the resistance value of the fourth resistor R4 is a fixed multiple n of the resistance value of the third resistor R3. In addition, such as Figure 4 As shown, the connection relationship between the first stage circuit 131 of the operational amplifier, the output stage circuit 132 of the operational amplifier, and the second sampling circuit 140 is as follows: Figure 2 The circuit diagram shown is the same, so it will not be described again here.

[0034] Furthermore, since there is a voltage deviation between the non-inverting and inverting input terminals of the first-stage operational amplifier circuit 131, in order to isolate this voltage deviation, Figure 2 The output stage circuit 110 of the leakage current compensation circuit 100 shown is an example of a CMOS output stage. Figure 5 As shown, the operational amplifier output stage circuit 132 may further include: a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12. The control electrode of the ninth transistor M9 is coupled to the sixth voltage terminal V6, the first electrode of the ninth transistor M9 is coupled to the second electrode of the seventh transistor M7, and the second electrode of the ninth transistor M9 is coupled to the second node N2. The control electrode of the tenth transistor M10 is coupled to the sixth voltage terminal V6, the first electrode of the tenth transistor M10 is coupled to the second electrode of the fifth transistor M5, and the second electrode of the tenth transistor M10 is coupled to the first node N1. The control electrode of the eleventh transistor M11 is coupled to the seventh voltage terminal V7, the first electrode of the eleventh transistor M11 is coupled to the second electrode of the eighth transistor M8, and the second electrode of the eleventh transistor M11 is coupled to the second node N2. The control electrode of the twelfth transistor M12 is coupled to the seventh voltage terminal V7, the first electrode of the twelfth transistor M12 is coupled to the second electrode of the sixth transistor M6, and the second electrode of the twelfth transistor M12 is coupled to the first node N1.

[0035] exist Figures 1 to 5 In the example, a high-voltage signal VDD is input from the first voltage terminal V1, the second voltage terminal V2 is grounded, the voltage input from the third voltage terminal V3 satisfies the condition that the gate-source voltage of the third transistor M3 is less than the threshold voltage, the voltage input from the fourth voltage terminal V4 is less than the threshold voltage of the fourth transistor M4, a high-voltage signal is input from the fifth voltage terminal V5, and the sixth and seventh voltage terminals V6 and V7 are bias voltages. These bias voltages must ensure that the ninth transistor M9 through the twelfth transistor M12 and the fifth transistor M5 through the eighth transistor M8 are in normal operating condition. In other words, not only must the gate-source voltages of the ninth transistor M9 through the twelfth transistor M12 be greater than the threshold voltage, but the fifth transistor M5 through the eighth transistor M8 must also be in the saturation region. Specifically, the first transistor M1, the third transistor M3, the fifth transistor M5, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10 are all PMOS transistors. The second transistor M2, the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are all NMOS transistors. Those skilled in the art will understand that, based on the above inventive concept, Figures 2 to 5 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figures 2 to 5 The examples shown have different settings.

[0036] The following is combined with Figure 2 The following example illustrates the operation of the leakage current compensation circuit 100 according to an embodiment of the present disclosure.

[0037] When the output stage circuit 110 is in a high-impedance state, both the first transistor M1 and the second transistor M2 are in the off state. Assuming the leakage current of the first transistor M1 is Ip and the leakage current of the second transistor M2 is In, there is a leakage current of Ip-In without compensation. First, the third transistor M3 and the fourth transistor M4 sample the leakage currents of the first transistor M1 and the second transistor M2, respectively. To save area, the aspect ratio of the third transistor M3 and the fourth transistor M4 can be reduced by a factor of n relative to the first transistor M1 and the second transistor M2. That is, the aspect ratio of the first transistor M1 is a fixed multiple n of the aspect ratio of the third transistor M3, and the aspect ratio of the second transistor M2 is the fixed multiple n of the aspect ratio of the fourth transistor M4. Through clamping by a unity-gain negative feedback amplifier, the drain voltages of the third transistor M3 and the fourth transistor M4 are equal to the drain voltages of the first transistor M1 and the second transistor M2. Therefore, the leakage currents of the third transistor M3 and the fourth transistor M4 are Ip / n and In / n, respectively. The difference in leakage current between the third transistor M3 and the fourth transistor M4, i.e., the first sampling current (Ip-In) / n, is provided to the operational amplifier output stage circuit 132 through the first node N1. Then, the currents of the fifth transistor M5 and the sixth transistor M6 in the operational amplifier output stage circuit 132 are sampled through the seventh transistor M7 and the eighth transistor M8. The dimensions of the seventh transistor M7 and the eighth transistor M8 are n times that of the fifth transistor M5 and the sixth transistor M6. That is, the width-to-length ratio of the seventh transistor M7 is a fixed multiple n of the width-to-length ratio of the fifth transistor M5, and the width-to-length ratio of the eighth transistor M8 is a fixed multiple n of the width-to-length ratio of the sixth transistor M6. Therefore, the current difference between the seventh transistor M7 and the eighth transistor M8 is the second sampling current Ip-In. This second sampling current is provided to the output stage circuit 110 via the second node N2. That is, the drain terminals of the seventh transistor M7 and the eighth transistor M8 are connected to the output port of the output stage circuit 110. The leakage current difference Ip-In between the first transistor M1 and the second transistor M2 in the output stage circuit 110 flows entirely into the drain terminals of the first transistor M1 and the second transistor M2, thus achieving no current flowing out of the output port Vout. Therefore, after compensation, the leakage current Leakage is 0.

[0038] Similarly, combining Figure 3 The following example illustrates the operation of the leakage current compensation circuit 100 according to an embodiment of the present disclosure.

[0039] When the output stage circuit 110 is in a high-impedance state, the first transistor M1 is in the off state. Assuming the leakage current of the first transistor M1 is Ip and the leakage current of the first resistor R1 is Ires, there is a leakage current of Ip - Ires without compensation. First, the third transistor M3 and the second resistor R2 sample the leakage currents of the first transistor M1 and the first resistor R1, respectively. To save area, the aspect ratio of the first transistor M1 is a fixed multiple n of the aspect ratio of the third transistor M3, and the resistance value of the second resistor R2 is the same fixed multiple n of the resistance value of the first resistor R1. Through clamping by the unity-gain negative feedback amplifier, the drain voltage of the third transistor M3 and the voltage of the second resistor R2 are equal to the drain voltage of the first transistor M1 and the voltage of the first resistor R1. Therefore, the leakage currents of the third transistor M3 and the second resistor R2 are Ip / n and Ires / n, respectively. The difference between the leakage current of the third transistor M3 and the second resistor R2, i.e., the first sampling current (Ip-Ires) / n, is provided to the operational amplifier output stage circuit 132 through the first node N1. Then, the currents of the fifth transistor M5 and the sixth transistor M6 in the operational amplifier output stage circuit 132 are sampled through the seventh transistor M7 and the eighth transistor M8. The dimensions of the seventh transistor M7 and the eighth transistor M8 are n times that of the fifth transistor M5 and the sixth transistor M6. That is, the width-to-length ratio of the seventh transistor M7 is a fixed multiple n of the width-to-length ratio of the fifth transistor M5, and the width-to-length ratio of the eighth transistor M8 is a fixed multiple n of the width-to-length ratio of the sixth transistor M6. Therefore, the current difference between the seventh transistor M7 and the eighth transistor M8 is the second sampling current Ip-Ires. This second sampling current is provided to the output stage circuit 110 via the second node N2. That is, the drain terminals of the seventh transistor M7 and the eighth transistor M8 are connected to the output port of the output stage circuit 110. The leakage current difference Ip-Ires between the first transistor M1 and the first resistor R1 in the output stage circuit 110 flows entirely into the drain terminal of the first transistor M1 and the first resistor R1, thus achieving no current flowing out of the output port Vout. Therefore, after compensation, the leakage current Leakage is 0.

[0040] Similarly, combining Figure 4 The following example illustrates the operation of the leakage current compensation circuit 100 according to an embodiment of the present disclosure.

[0041] When the output stage circuit 110 is in a high-impedance state, the second transistor M2 is in the off state. Assuming the leakage current of the second transistor M2 is In and the leakage current of the third resistor R3 is Ires, there is a leakage current of Ires - In without compensation. First, the fourth transistor M4 and the fourth resistor R4 sample the leakage currents of the second transistor M2 and the third resistor R3, respectively. To save area, the aspect ratio of the second transistor M2 is a fixed multiple n of the aspect ratio of the fourth transistor M4, and the resistance value of the fourth resistor R4 is the same fixed multiple n of the resistance value of the third resistor R3. Through clamping by the unity-gain negative feedback amplifier, the drain voltage of the fourth transistor M4 and the voltage of the fourth resistor R4 are equal to the drain voltage of the second transistor M2 and the voltage of the third resistor R3. Therefore, the leakage currents of the fourth transistor M4 and the fourth resistor R4 are In / n and Ires / n, respectively. The difference between the leakage current of the third transistor M3 and the second resistor R2, i.e., the first sampling current (Ires-In) / n, is provided to the operational amplifier output stage circuit 132 through the first node N1. Then, the current of the fifth transistor M5 and the sixth transistor M6 in the operational amplifier output stage circuit 132 is sampled through the seventh transistor M7 and the eighth transistor M8. The size of the seventh transistor M7 and the eighth transistor M8 is n times that of the fifth transistor M5 and the sixth transistor M6. That is, the width-to-length ratio of the seventh transistor M7 is a fixed multiple n of the width-to-length ratio of the fifth transistor M5, and the width-to-length ratio of the eighth transistor M8 is a fixed multiple n of the width-to-length ratio of the sixth transistor M6. Therefore, the current difference between the seventh transistor M7 and the eighth transistor M8 is the second sampling current Ires-In. This second sampling current is provided to the output stage circuit 110 via the second node N2. That is, the drain terminals of the seventh transistor M7 and the eighth transistor M8 are connected to the output port of the output stage circuit 110. The leakage current difference Ires-In between the second transistor M2 and the third resistor R3 in the output stage circuit 110 flows entirely into the drain terminal of the second transistor M2 and the third resistor R3, thus achieving no current flowing out of the output port Vout. Therefore, after compensation, the leakage current Leakage is 0.

[0042] In summary, the leakage current compensation circuit according to the embodiments of this disclosure compensates for the leakage current in the high-impedance output stage, and the high-impedance output stage no longer leaks current to the output port.

[0043] Embodiments of this disclosure also provide a chip. This chip includes a leakage current compensation circuit according to embodiments of this disclosure. This chip is, for example, a low-dropout linear regulator chip or a chip requiring leakage current compensation.

[0044] Embodiments of this disclosure also provide an electronic device. This electronic device includes a chip according to embodiments of this disclosure. This electronic device is, for example, an electronic device requiring leakage current compensation.

[0045] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0046] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0047] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0048] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A leakage current compensation circuit, characterized in that, include: The system includes an output stage circuit, a first sampling circuit, an operational amplifier circuit, and a second sampling circuit. The operational amplifier circuit comprises an operational amplifier output stage circuit and an operational amplifier first stage circuit that are coupled to each other. The first sampling circuit is configured to sample the leakage current of the output stage circuit to obtain a first sampling current, and to provide the first sampling current to the operational amplifier output stage circuit via a first node. The second sampling circuit is configured to sample the current of the operational amplifier output stage circuit to obtain a second sampling current, and provide the second sampling current to the output stage circuit via a second node to compensate for the leakage current of the output stage circuit. The first stage of the operational amplifier is configured to clamp the voltages of the first node and the second node.

2. The leakage current compensation circuit according to claim 1, characterized in that, The non-inverting input of the first stage of the operational amplifier is coupled to the second node, and the inverting input of the first stage of the operational amplifier is coupled to the first node.

3. The leakage current compensation circuit according to claim 2, characterized in that, The operational amplifier output stage circuit includes: a fifth transistor and a sixth transistor. The control electrode of the fifth transistor is coupled to the first output terminal of the first stage circuit of the operational amplifier, the first electrode of the fifth transistor is coupled to the fifth voltage terminal, and the second electrode of the fifth transistor is coupled to the first node; The control terminal of the sixth transistor is coupled to the second output terminal of the first stage of the operational amplifier circuit, the first terminal of the sixth transistor is coupled to the second voltage terminal, and the second terminal of the sixth transistor is coupled to the first node.

4. The leakage current compensation circuit according to claim 3, characterized in that, The second sampling circuit includes: a seventh transistor and an eighth transistor. Wherein, the control electrode of the seventh transistor is coupled to the first output terminal of the first stage circuit of the operational amplifier, the first electrode of the seventh transistor is coupled to the fifth voltage terminal, the second electrode of the seventh transistor is coupled to the second node, and the width-to-length ratio of the seventh transistor is a fixed multiple of the width-to-length ratio of the fifth transistor. The control electrode of the eighth transistor is coupled to the second output terminal of the first stage of the operational amplifier circuit, the first electrode of the eighth transistor is coupled to the second voltage terminal, the second electrode of the eighth transistor is coupled to the second node, and the aspect ratio of the eighth transistor is a fixed multiple of the aspect ratio of the sixth transistor.

5. The leakage current compensation circuit according to claim 4, characterized in that, The operational amplifier output stage circuit further includes: a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor. The control terminal of the ninth transistor is coupled to the sixth voltage terminal, the first terminal of the ninth transistor is coupled to the second terminal of the seventh transistor, and the second terminal of the ninth transistor is coupled to the second node; The control terminal of the tenth transistor is coupled to the sixth voltage terminal, the first terminal of the tenth transistor is coupled to the second terminal of the fifth transistor, and the second terminal of the tenth transistor is coupled to the first node; The control terminal of the eleventh transistor is coupled to the seventh voltage terminal, the first terminal of the eleventh transistor is coupled to the second terminal of the eighth transistor, and the second terminal of the eleventh transistor is coupled to the second node. The control terminal of the twelfth transistor is coupled to the seventh voltage terminal, the first terminal of the twelfth transistor is coupled to the second terminal of the sixth transistor, and the second terminal of the twelfth transistor is coupled to the first node.

6. The leakage current compensation circuit according to any one of claims 1-5, characterized in that, The output stage circuit includes: a first transistor and a second transistor. The control terminal of the first transistor is coupled to the third voltage terminal, the first terminal of the first transistor is coupled to the first voltage terminal, and the second terminal of the first transistor is coupled to the second node. The control terminal of the second transistor is coupled to the fourth voltage terminal, the first terminal of the second transistor is coupled to the second voltage terminal, and the second terminal of the second transistor is coupled to the second node; The first sampling circuit includes: a third transistor and a fourth transistor. The control electrode of the third transistor is coupled to the third voltage terminal, the first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the first node; The control electrode of the fourth transistor is coupled to the fourth voltage terminal, the first electrode of the fourth transistor is coupled to the second voltage terminal, and the second electrode of the fourth transistor is coupled to the first node. Wherein, the aspect ratio of the first transistor is a fixed multiple of the aspect ratio of the third transistor, and the aspect ratio of the second transistor is the fixed multiple of the aspect ratio of the fourth transistor.

7. The leakage current compensation circuit according to any one of claims 1-5, characterized in that, The output stage circuit includes: a first transistor and a first resistor. The control terminal of the first transistor is coupled to the third voltage terminal, the first terminal of the first transistor is coupled to the first voltage terminal, and the second terminal of the first transistor is coupled to the second node. The first end of the first resistor is coupled to the second node, and the second end of the first resistor is coupled to the second voltage terminal; The first sampling circuit includes: a third transistor and a second resistor. The control electrode of the third transistor is coupled to the third voltage terminal, the first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the first node; The first end of the second resistor is coupled to the first node, and the second end of the second resistor is coupled to the second voltage terminal. Wherein, the aspect ratio of the first transistor is a fixed multiple of the aspect ratio of the third transistor, and the resistance value of the second resistor is the fixed multiple of the resistance value of the first resistor.

8. The leakage current compensation circuit according to any one of claims 1-5, characterized in that, The output stage circuit includes: a second transistor and a third resistor. The control terminal of the second transistor is coupled to the fourth voltage terminal, the first terminal of the second transistor is coupled to the second voltage terminal, and the second terminal of the second transistor is coupled to the second node; The first end of the third resistor is coupled to the second node, and the second end of the third resistor is coupled to the first voltage terminal; The first sampling circuit includes: a fourth transistor and a fourth resistor. The control electrode of the fourth transistor is coupled to the fourth voltage terminal, the first electrode of the fourth transistor is coupled to the second voltage terminal, and the second electrode of the fourth transistor is coupled to the first node. The first end of the fourth resistor is coupled to the first node, and the second end of the fourth resistor is coupled to the first voltage terminal. Wherein, the aspect ratio of the second transistor is a fixed multiple of the aspect ratio of the fourth transistor, and the resistance value of the fourth resistor is a fixed multiple of the resistance value of the third resistor.

9. A chip, characterized in that, Includes the leakage current compensation circuit according to any one of claims 1-8.

10. An electronic device, characterized in that, Includes the chip according to claim 9.

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