Electronic circuit

Abstract

An electronic circuit comprising a first transistor coupled between a voltage supply and a first node, a second transistor coupled between the voltage supply and a second node, and a differential amplifier comprising first and second input terminals and an output terminal. The differential amplifier is coupled to an input terminal of the first transistor and to an input terminal of the second transistor. The first node is coupled to the first input terminal of the differential amplifier. The second node is coupled to the second input terminal of the differential amplifier.

Description

ELECTRONIC CIRCUITTECHNICAL FIELD

[0001] The present disclosure concerns an electronic circuit. More particularly, but not exclusively, the present disclosure concerns an electronic circuit for use in providing a reference current. In addition, the present disclosure concerns a differential amplifier and an electronic circuit for use in providing a reference voltage.BACKGROUND

[0002] Constant reference currents and voltages are common requirements in high precision analogue circuits and have a wide range of applications.

[0003] Figure 1 shows a schematic view of a prior art complementary metal-oxide- semiconductor (CMOS) electronic circuit 100 for generating a reference current. Such a circuit 100 is commonly referred to as a beta mirror circuit or constant-Gm biasing circuit. In CMOS technology, this circuit comprises an asymmetrical NMOS current mirror with a symmetrical PMOS mirror above. Specifically, a pair of identical PMOS transistors 101 , 102 form a current mirror to source current to an NMOS mirror formed by a pair of NMOS transistors 103, 104 and a resistor 105. The semiconductor channel of NMOS transistor 104 has a larger width to length ratio than that of NMOS transistor 103. Resistor 105, having resistance R, is sometimes referred to as a degradation resistor, because it effectively limits the rate at which current in transistor 104 changes as its gate voltage is altered. In such a circuit 100, the currents ID1 and ID2 are forced to be identical. ID1 and ID2 depend only on R2and the gain of the NMOS transistors 103, 104, which are fixed for a particular manufacturing process. In this manner, the electronic circuit 100 forms an accurate reference current generator, which can be designed to provide a desired reference current through selection of R and the NMOS transistor gain at the point of fabrication.

[0004] Some electronic circuit fabrication technologies are NMOS-only, i.e. PMOS devices are not available for use. Thus, circuit designs implemented using such technologies must employ alternative NMOS-only circuit designs. Other electronic circuit fabrication technologies are PMOS-only, i.e. NMOS devices are not available for use.Thus, circuit designs implemented using these technologies must employ alternative PMOS-only circuit designs.

[0005] The present disclosure seeks to provide electronic circuits for use in the generation of reference currents that do not rely on PMOS devices.SUMMARY

[0006] A first aspect of the present disclosure relates to an electronic circuit comprising a first transistor coupled between a supply voltage and a first node; a second transistor coupled between the supply voltage and a second node; and a differential amplifier comprising first and second input terminals and an output terminal, wherein: the differential amplifier is coupled to an input terminal of the first transistor and to an input terminal of the second transistor; the first node is coupled to the first input terminal of the differential amplifier; and the second node is coupled to the second input terminal of the differential amplifier.

[0007] A second aspect of the present disclosure relates to an electronic circuit comprising a first resistor coupled between a supply voltage and a first node; a second resistor coupled between the supply voltage and a second node; a differential amplifier comprising an inverting input, a non-inverting input and an output terminal; a first transistor coupled between the first node and ground; and a second transistor coupled between the second node and ground, wherein: the differential amplifier is coupled to an input terminal of the first transistor and to an input terminal of the second transistor; the first node is coupled to the non-inverting input; and the second node is coupled to the inverting input.

[0008] A third aspect of the present disclosure relates to a differential amplifier comprising a biasing circuit arranged to reduce or eliminate a DC offset in a differential output of the amplifier arising from an increase or decrease in an amplifier supply voltage relative to ground.

[0009] It will of course be appreciated that features described in relation to one aspect of the present disclosure may be incorporated into other aspects of the present disclosure. For example, the method of the present disclosure may incorporate any of thefeatures described with reference to the apparatus of the present disclosure and vice versa.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 shows a schematic view of a CMOS reference current circuit of the prior art;

[0011] Figure 2 shows a schematic view of a current mirror circuit according to the present disclosure;

[0012] Figures 3 to 5 show schematic views of reference current / voltage circuits according to the present disclosure;

[0013] Figure 6 shows a schematic view of a differential amplifier circuit according to the present disclosure;

[0014] Figure 7 shows a schematic view of an electronic circuit according to the present disclosure;

[0015] Figure 8 shows a schematic view of an integrated circuit according to the present disclosure; and

[0016] Figure 9 shows a schematic view of a device according to the present disclosure.DETAILED DESCRIPTION

[0017] Figure 2 shows a schematic view of an electronic circuit 200 according to the present disclosure. This electronic circuit 200 can replace the PMOS mirror of the prior art circuit shown in Figure 1. A first transistor 201 (e.g. an NMOS thin-film transistor) is coupled between a supply voltage VDD and a first node 202. A second transistor 203 (e.g. NMOS thin-film transistor) is coupled between the supply voltage VDD and a second node 204. A differential amplifier 205 comprises a first input terminal 206 (e.g. inverting input), a second input terminal 207 (e.g. non-inverting input) and an output terminal 208. The output terminal 208 of the differential amplifier 205 is coupled to an input terminal 209 (e.g. gate) of the first transistor 201 and to an input terminal 210 (e.g. gate) of the second transistor 203. The first node 202 is coupled to the first input terminal 206 of thedifferential amplifier 205. The second node 204 is coupled to the second input terminal 207 of the differential amplifier 205.

[0018] The input terminals 209, 210 of the first and second transistors 201 , 203 may comprise gate terminals. The drain terminal of the first transistor 201 may be coupled to the supply voltage VDD, the source terminal of the first transistor 201 may be coupled to the first node 202, the drain terminal of the second transistor 203 may be coupled to the supply voltage VDD, and the source terminal of the second transistor 203 may be coupled to the second node 204. The first transistor 201 and the second transistor 203 may be identical to one another, i.e. they may be of substantially the same specification and geometry within the available manufacturing tolerances.

[0019] The electronic circuit 200 of Figure 2 may be referred to as a self-biasing voltage follower. The circuit 200 may be used as a current mirror in any circuit where one is required, and in particular when a voltage-independent equilibrium point is required, e.g. to replace the PMOS current mirror of a voltage reference circuit, such as the electronic circuit 100 shown in Figure 1. The first and second transistors 201 , 203 effectively behave as variable resistors under the control of the differential amplifier 205. The differential amplifier 205 causes VO1 and VO2 (the voltages at the first node 202 and second node 204 respectively) to be equal: With VO1 and VO2 feeding the differential inputs of the differential amplifier 205 its output can drive the gates of transistors 201 , 203 in a way that opposes any differences between VO1 and VO2. If the first and second transistors 201 , 203 are identical, they will have the same effective channel resistance for a given applied voltage, thereby ensuring that ID1 = ID2, as is desired for a current mirror. Advantageously, the first and second transistors 201 , 203 may be implemented in NMOS, as opposed to PMOS, which is desirable in applications where PMOS fabrication is not available or is undesirable.

[0020] One application of the electronic circuit 200 of Figure 2 may be to form part of a reference current- and / or reference voltage- generating circuit. In this regard, Figure 3 shows a schematic view of an electronic circuit 300 according to the present disclosure which utilizes the current mirror circuit 200 of Figure 2. The electronic circuit 300 is operable to generate a reference current and a reference voltage. This electronic circuit 300 therefore achieves the same / similar function as the prior art circuit 100 of Figure 1.However, the electronic circuit 300 may not require the use of any PMOS devices, i.e. all of the devices may be NMOS, unlike in the circuit 100 of Figure 1 which requires two PMOS transistors in addition to two NMOS transistors.

[0021] The electronic circuit 300 comprises, in part, the electronic circuit 200 described above, to cause the generation of two equal currents ID1 and ID2 (as explained above). In addition to the componentry of electronic circuit 200, a third transistor 301 is coupled between the first node 202 and ground VSS, and a fourth transistor 302 is coupled between the second node 204 and ground VSS via a (degradation) resistor 303. The input (e.g. gate) terminals 304, 305 of the third 301 and fourth 302 transistors are coupled to the first node 202. This means that the third transistor 301 is diode-connected. The semiconductor channel of the fourth transistor 302 may have a greater width to length ratio than that of the third transistor 301. The width to length ratios of the third 301 and fourth 302 transistors may differ by a factor of at least ten. The drain terminal of the third transistor 301 may be coupled to the first node 202, the source terminal of the third transistor 301 may be coupled to ground VSS, the drain terminal of the fourth transistor 302 may be coupled to the second node 204, and the source terminal of the fourth transistor 302 may be coupled to ground VSS via the resistor 303.

[0022] The electronic circuit 300 of Figure 3 may operate as follows. The differential amplifier 205 drives the first transistor 201 as a voltage follower. This provides voltage VO1 , which through the diode-connected third transistor 301 creates the drain current ID1. ID1 then generates ID2 through the mirror circuit 200, and when the circuit is correctly balanced, ID1 = ID2. In other regards, the circuit operates in a similar manner to that of Figure 1. However, unlike the prior art circuit 100, circuits according to the disclosure cannot sustain a zero-current condition. This means there is no requirement for a start-up circuit. In addition, prior art circuits 100 typically have different values of VO1 and VO2, which diverge more as VDD increases. This can impact the accuracy of the current mirrors by creating a different voltage across the mirror device vs. the diode- connected device, causing a slight increase in the reference current. With circuits according to the present disclosure, the requirement that VO1 = VO2 forces the voltages across the third 301 and fourth transistors 302 to be identical and therefore furtherimmune to changes in the supply voltage VDD. VO1 and / or VO2 therefore constitute a stable reference voltage.

[0023] Figure 4 shows a schematic view of an alternative electronic circuit 400 according to the present disclosure which utilizes the current mirror circuit 200 of Figure 2. The electronic circuit 400 is operable to generate a reference current and a reference voltage. In this manner, the circuit 400 achieves the same / similar function as the prior art circuit 100 of Figure 1 . However, the electronic circuit 400 may not require the use of any PMOS devices, i.e. all devices may be NMOS, unlike in the circuit 100 of Figure 1. The electronic circuit 400 of Figure 4 is an alternative arrangement of the electronic circuit of Figure 3.

[0024] The electronic circuit 400 comprises, in part, the electronic circuit 200 described above, in order to generate two equal currents ID1 and ID2 (as explained above). In addition to the componentry of electronic circuit 200, a third transistor 401 is coupled between the first node 202 and ground VSS via a (degradation) resistor 403, and a fourth transistor 402 is coupled between the second node 204 and ground VSS. The input (gate) terminals 404, 405 of the third 401 and fourth 402 transistors are coupled to the first node 202. This means that the third transistor 401 is diode-connected. The semiconductor channel of the third transistor 401 may have a greater width to length ratio than that of the fourth transistor 402. The width to length ratios of the third 401 and fourth 402 transistors may differ by a factor of at least ten. The drain terminal of the third transistor 401 may be coupled to the first node 202, the source terminal of the third transistor 401 may be coupled to ground VSS via the resistor 403, the drain terminal of the fourth transistor 402 may be coupled to the second node 204, and the source terminal of the fourth transistor 402 may be coupled to ground VSS.

[0025] The electronic circuit 400 of Figure 4 operates in a similar manner to the electronic circuit of Figure 3, in order to generate a desired reference current and / or reference voltage. However, a difference between the two circuits is that the componentry in the bottom-half of the circuit (below the first and second nodes) has swapped ‘sides’ (or ‘branches’). This may be beneficial in overcoming a degradation in the gain of the fourth transistor 302 operating as a common source amplifier in Figure 3.

[0026] Figure 5 is a schematic view of an electronic circuit 500 according to the present disclosure. The electronic circuit 500 is operable to generate a reference current and / or a reference voltage. In this manner, the circuit 500 achieves the same / similar function as the prior art circuit 100 of Figure 1. However, the electronic circuit 500 may not require the use of any PMOS devices, i.e. all transistors may be NMOS, unlike in the circuit 100 of Figure 1.

[0027] In the electronic circuit 500, a first resistor 501 is coupled between a supply voltage VDD and a first node 502. A second resistor 503 is coupled between the supply voltage VDD and a second node 504. A first transistor 505 is coupled between the first node 502 and ground VSS. A second transistor 506 is coupled between the second node 504 and ground VSS via a third resistor 513. The output terminal 507 of a differential amplifier 508 is coupled to an input terminal 509 (e.g. gate) of the first transistor 505 and to an input terminal 510 (e.g. gate) of the second transistor 506. The first node 502 is coupled to the non-inverting input 511 of the differential amplifier 508, and the second node 504 is coupled to the inverting input 512 of the differential amplifier 508.

[0028] The second transistor 506 may have a semiconductor channel having a greater width to length ratio than that of the first transistor 505. The first 501 and second 503 resistors may have the same (or approximately the same) resistance.

[0029] The electronic circuit 500 of Figure 5 operates as follows. Compared to the prior art circuit 100 of Figure 1 , the PMOS current mirror is replaced with two identical resistors 501 , 503. It therefore follows that ID1 = ID2 when VO1 = VO2. The differential amplifier 508 is operable to force VO1 and VO2 to be identical, ensuring equal current in the two branches.

[0030] The electronic circuits 200, 300, 400 and 500 according to the present disclosure all utilize a differential amplifier. Figure 6 is a schematic view of a differential amplifier 600 according to the present disclosure. The differential amplifier comprises a biasing circuit 601 that is arranged to reduce or eliminate a DC offset in a differential output of the amplifier 600 arising from an increase or decrease in an amplifier supply voltage VDD relative to ground VSS. In the biasing circuit 601 , a first transistor 602 is coupled to the supply voltage VDD via a first resistor 603 and is coupled to ground VSS via a second resistor 604. The drain terminal of the first transistor 602 is coupled to thesupply voltage VDD via the first resistor 603, the source terminal of the first transistor 602 is coupled to ground VSS via the second resistor 604, and the gate terminal of the first transistor 602 is coupled to the drain terminal of the first transistor - in other words, the first transistor 602 is diode-connected.

[0031] An input stage 610 of the differential amplifier 600 is connected to ground VSS via a second transistor 611. The gate terminal of the second transistor 611 is coupled to the gate terminal of the first transistor 602. The input stage 610 comprises an identical pair of third 612 and fourth 613 transistors. An input terminal of the third transistor 612 is arranged to receive a non-inverting input to the differential amplifier 600 and an input terminal of the fourth transistor 613 is arranged to receive an inverting input to the differential amplifier 600. The third transistor 612 is coupled to the supply voltage VDD via a third resistor 614 and the fourth transistor 613 is coupled to the supply voltage via a fourth resistor 615. The third 612 and fourth 613 transistors are coupled to ground VSS via the second transistor 611. The third and fourth resistors may have the same (or approximately the same) resistance.

[0032] Prior art differential amplifiers are designed to be balanced at a specific DC operating point (value of inputs VO1 and VO2), but this balance is in general only maintained at a fixed value of the supply voltage VDD. Changes in VDD cause DC offset in the amplifier output, which in turn would have an impact on the reference current and voltage generated in any of the circuits 200, 300, 400, 500 of the present disclosure. In the differential amplifier 600 of the disclosure, a fixed bias voltage source of typical designs is replaced by a variable source. The second resistor 604 causes Vmir (the voltage at the input terminal of second transistor 611) to increase as VDD increases. In this manner, the current through the third and fourth resistors 614, 615 loading the differential amplifier increases in line with the supply voltage VDD increase. This results in the differential amplifier 600 remaining balanced at all supply voltages VDD, exhibiting zero DC offset with changing supply VDD even while maintaining constant VO1 , VO2 and VDm (the output of the amplifier).

[0033] Figure 7 is a schematic view of an electronic circuit 700 according to the present disclosure. The electronic circuit 700 is operable to generate a reference current and / or a reference voltage at a first reference voltage supply 714 and a second referencevoltage supply 715. In this manner, the circuit 700 may achieve a similar function as the circuit 100 of Figure 1 . However, the electronic circuit 700 may not require the use of any PMOS devices, i.e. all transistors may be NMOS, unlike in the circuit 100 of Figure 1. In other examples, the electronic circuit is configured as a regulator.

[0034] The electronic circuit 700 of Figure 7 is similar to the electronic circuit 400 described above in relation to Figure 4. In contrast to the electronic circuit 400 of Figure 4, which includes a differential amplifier, the differential amplifier 708 of Figure 7 is a three-stage operational amplifier 708. Other amplifiers are envisaged for other examples.

[0035] The electronic circuit 700 includes a first transistor 701 , a second transistor 702, a third transistor 705, a fourth transistor 706, a first resistor 703, a second resistor 704, a third resistor 713, a voltage supply VDD, a further voltage supply VSS, a three- stage operational amplifier 708, an output node 707, a first node 716, a second node 717, the first reference voltage supply 714, the second reference voltage supply 715, and a current mirror 710. The voltage supply VDD is a drain voltage supply and is configured to supply a drain voltage; the further voltage supply VSS is a source voltage supply and is configured to supply a source voltage.

[0036] The first transistor 701 is coupled between the drain voltage supply VDD and the first node 716. A drain terminal of the first transistor 701 is electrically connected to the drain voltage supply VDD. A gate terminal of the first transistor 701 is electrically connected to a gate terminal of the second transistor 702 and the output node 707. A source terminal of the first transistor 701 is electrically connected to the first resistor 703. The first transistor 701 has a channel of a semiconductor. The semiconductor is indium gallium zinc oxide (herein IGZO); other semiconductors are envisaged for other examples. The first transistor 701 is a thin-film transistor (TFT); in other examples the first transistor is not a TFT.

[0037] The second transistor 702 is coupled between the drain voltage supply VDD and the second node 717. A drain terminal of the second transistor 702 is electrically connected to the drain voltage supply VDD. A source terminal of the second transistor 702 is electrically connected to the second resistor 704. The gate terminal of the second transistor 702 is electrically connected to the gate terminal of the first transistor 701 and the output node 707. The second transistor 702 has a channel of a semiconductor. Thesemiconductor is IGZO; other semiconductors are envisaged for other examples. The second transistor 702 is a TFT; in other examples the second transistor is not a TFT. The second transistor 702 is the same or substantially the same as the first transistor 701. The first transistor 701 and the second transistor 702 may be considered as matched. In other examples, the channel of the second transistor 702 has a greater width to length ratio than the channel of the first transistor 701 . In other examples the channel of the first transistor has a greater width to length ratio than the channel of the second transistor.

[0038] The first resistor 703 is coupled between the drain voltage supply VDD and the first node 716. The first resistor 703 is directly electrically connected to the first transistor 701 and the first node 716. In other examples, the first resistor is directly electrically connected to the drain terminal of the first transistor and the drain voltage supply. The first resistor 703 includes a trace of semiconductor, the semiconductor is IGZO. In other examples the trace is of another semiconductor and / or a metal.

[0039] The second resistor 704 is coupled between the drain voltage supply VDD and the second node 717. The second resistor 704 is directly electrically connected to the second transistor 702 and the second node 717. In other examples, the second resistor is directly electrically connected to the drain terminal of the second transistor and the drain voltage supply. The second resistor 704 includes a trace of semiconductor, the semiconductor is IGZO. In other examples the trace is of another semiconductor and / or a metal. The resistance of the first resistor 703 and the resistance of the second resistor 704 are the same or substantially the same. In other examples, the first resistor and the second resistor have different resistances. In some examples, the resistance of the first resistor 703 and / or the second resistor 704 are 200 Kiloohms, other resistances are envisaged.

[0040] The third transistor 705 is coupled between the source voltage supply VSS and the first node 716. A source terminal of the third transistor 705 is electrically connected to the third resistor 713. A gate terminal of the third transistor 705 is electrically connected to: a gate terminal of the fourth transistor 706, the first node 716, a first input 711 of the three-stage operational amplifier 708, and the first reference voltage supply 714. A drain terminal of the third transistor 705 is electrically connected to the first node 716. The third transistor 705 has a channel of a semiconductor. The semiconductor isIGZO; other semiconductors are envisaged for other examples. The third transistor 705 is a TFT; in other examples the third transistor is not a TFT. The third transistor 705 may be considered as a diode-connected transistor.

[0041] The fourth transistor 706 is coupled between the source voltage supply VSS and the second node 717. A source terminal of the fourth transistor 706 is electrically connected to the source voltage supply VSS. A drain terminal of the fourth transistor 706 is electrically connected to the second node 717. The fourth transistor 706 has a channel of a semiconductor. The semiconductor is IGZO; other semiconductors are envisaged for other examples. The fourth transistor 706 is a TFT; in other examples the second transistor is not a TFT. The fourth transistor 706 is the same or substantially the same as the third transistor 705. The fourth transistor 706 and the third transistor 705 may be considered as matched. In other examples, the channel of the fourth transistor has a greater width to length ratio than the channel of the third transistor. In other examples the channel of the third transistor has a greater width to length ratio than the channel of the fourth transistor. The fourth transistor 706 may be considered as configured to operate as a common source amplifier.

[0042] The third resistor 713 is coupled between the source voltage supply VSS and the first node 716. The third resistor 713 is directly electrically connected to the third transistor 705 and the source voltage supply VSS. The third resistor 713 may be considered a degradation resistor. In other examples, the third resistor is coupled between the source voltage supply and the second node. In some such examples, the third resistor is directly electrically connected to the source voltage supply and the fourth transistor. In some further such examples the third resistor is directly electrically connected to the second node and the fourth transistor. In further other examples, the third resistor is directly electrically connected to the first node and the third transistor. The first resistor 703 includes a trace of semiconductor, the semiconductor is IGZO. In other examples the trace is of another semiconductor and / or a metal. The third resistor may facilitate, when the electronic circuit 700 is in use, overcoming degradation in a gain of the fourth transistor 706 when the fourth transistor 706 is operating as a common source amplifier.

[0043] The current mirror 710 includes the third transistor 705, the fourth transistor 706, and the third resistor 713. The current mirror is configured so that, when the electronic circuit 700 is in use, the electrical current at the first node 716 is the same or substantially the same as the electrical current at the second node 717. Other configurations of the current mirror 710 are envisaged. For example, in other configurations of the current mirror, the current mirror may include further transistors and / or different transistors such as PMOS transistors.

[0044] In other examples, the electronic circuit includes a fourth resistor coupled between the second node and the source voltage supply. In some such examples, the fourth resistor is directly electrically connected to the source voltage supply and the fourth transistor. In some other such examples the fourth resistor is directly electrically connected to the second node and the fourth transistor.

[0045] Each of the first transistor 701 , the second transistor 702, the third transistor 705, and the fourth transistor 706 is an NMOS transistor. In other examples, each of the first transistor, the second transistor, the third transistor, and the fourth transistor are a PMOS transistor.

[0046] The first reference voltage supply 714 is directly electrically connected to the first node 716 and the first input 711 of the three-stage operational amplifier 708. The first reference voltage supply 714 is configured to supply a first reference voltage. The first reference voltage is substantially less than the drain voltage.

[0047] The second reference voltage supply 715 is directly electrically connected to the second node 717 and the second input 712 of the three-stage operational amplifier 708. The second reference voltage supply 715 is configured to supply a second reference voltage. The second reference voltage is substantially less than the drain voltage.

[0048] The three-stage operational amplifier 708 has a first input 711 , a second input 712, and an output node 707. The three-stage operational amplifier 708 is electrically connected to the drain voltage supply and to the source voltage supply. Various structures and / or configurations of the three-stage operational amplifier 708 are envisaged. Other amplifiers are envisaged for other examples. In some examples, the three-stage operational amplifier is an operational amplifier with an odd number of stages. It was found that the operational amplifier having an odd number of stages can facilitatethe electronic circuit 700 being self-starting when in use. In other words, it was found that when the circuit is configured for a non-zero voltage to be supplied by drain voltage supply VDD, and / or the source voltage supply VSS, and / or a difference between a voltage supplied by the drain voltage supply VDD and a voltage supplied by the source voltage supply VSS being non-zero, the electronic circuit is self-starting and will not require a start-up circuit. This is in contrast to previous circuits which require a stimulus to start operating.

[0049] When the electronic circuit 700 is in use, the electrical connection of the output node 707 of the three-stage operational amplifier 707 to the gate terminals of the first transistor 701 and 702 allows the first transistor 701 to be driven as a voltage follower. This causes a feedback loop from the output node 707 to the first node 716 and the second node 717 which, when in use, is modulated by the first transistor 701 and the second transistor 702. This allows a voltage across the first node 716 and the third transistor 705 which drives a first electrical current through the first node 716 and the third transistor 705. The first electrical current causes the current mirror 710 to drive a second electrical current through the second node 717 and the fourth resistor 706. The first electrical current is equal or substantially equal to the second electrical current, other electrical currents are envisaged. The first electrical current being equal or substantially equal to the second electrical current causes a voltage across the third transistor 705 to be equal to a voltage across the fourth transistor 706. This, with the third transistor 795 matched to the fourth transistor 706 may facilitate the same behaviour to occur for the third transistor 705 and the fourth transistor 706. The first electrical current and the second electrical current are also therefore invariant or substantially invariant to: substantially small changes in the voltage supplied by drain voltage supply VDD; substantially small changes in the voltage supplied by the source voltage supply VSS; and / or substantially small changes in a difference between a voltage supplied by the drain voltage supply VDD and a voltage supplied by the source voltage supply VSS. So, the first voltage is output by the first reference voltage supply 714 as a first reference voltage, and the second voltage is output by the second reference voltage supply 715 as a second reference voltage.

[0050] In some further examples, the electronic circuit 700 is configured for use as a regulator. In some such examples, a first regulator voltage may be extracted between the first transistor 701 and the first resistor 703. Further, a second regulator voltage may be extracted between the second transistor 702 and the second resistor 704. It is envisaged that various features of the electronic circuit 700 may be modified for the electronic circuit 700 to be configured as a regulator. For example, it may be desirable to modify a channel size of the first transistor. Other modifications are envisaged.

[0051] It may be that the electronic circuits 200, 300, 400, 500, 600, 700 do not comprise a PMOS transistor. All transistors in the electronic circuits disclosed herein may be NMOS transistors. In particular, they may be thin film transistors (TFTs) implemented in NMOS. Some or all resistors may be implemented as switched capacitor resistors.

[0052] The electronic circuits 200, 300, 400, 500, 600, or 700 may form part of an integrated circuit. Thus, examples of the present disclosure provide an integrated circuit comprising any electronic circuit 200, 300, 400, 500, 600, or 700 as described above.

[0053] An integrated circuit (IC) 892 is now described with reference to Figure 8. The IC 892 includes an electronic circuit of examples herein, such as the electronic circuit 700 of Figure 7.

[0054] The integrated circuit may be a flexible integrated circuit. In accordance with the present disclosure a “flexible integrated circuit” (flexible IC or flexIC) is a type of integrated circuit that is designed to be flexible and conformable, allowing it to bend, twist, and conform to non-flat or irregular surfaces. Unlike traditional rigid ICs, which are typically made on silicon wafers and are inflexible, flexible ICs, in accordance with the present disclosure, are fabricated on flexible substrates using appropriate materials and thin-film processes. The substrate is typically formed of an appropriate flexible polymer material. Nevertheless, the flexible substrate may be formed from any other materials that provide suitable electrical, chemical, mechanical, optical, biological and / or structural properties. The flexible substrate may be formed from a single common material, may be formed from a plurality of different materials, or may be formed from a plurality of different types of the same material. The flexible substrate may, for example, comprise one or more materials selected from the following list of materials: flexible glass, polymermaterials, metal oxide materials, resin materials, resist materials, foil materials, paper, insulator coated metals, or any other suitable material.

[0055] Where a polymer based material is used, the substrate may comprise one or more polymers selected from: polyethylene naphthalates, polyethylene terephthalates; polymethyl methacrylates; polycarbonates, polyvinyl alcohols, polyvinyl acetates, polyvinyl pyrrolidones, polyvinyl phenols, polyvinyl chlorides, polystyrenes, polyimides, polyamides (e.g. Nylon); poly(hydroxy ethers), polyurethanes, polycarbonates, polysulfones, parylenes, polyarylates, polyether ether ketones (PEEKs); acrylonitrile butadiene styrene (ABS), 1 Methoxy 2 propyl acetates, Benzocyclobutenes (BCB), polylactic acid (PLA), polyhydroxyalkanoates (PHAs), polybutylene succinate (PBS), polybutylene adipate terephthalate (PBAT), cellulose polymers, or any other suitable polymer material.

[0056] Where a metal oxide based material is used, the substrate may comprise one or more metal oxides selected from: AI2O3, SiOxNy, SiC>2, SisN4, or any other suitable metal oxide. Where a resin based material is used, the substrate may comprise one or more resins selected from: a UV-curable resin or any other suitable resin. Where a resist based material is used, the substrate may comprise one or more resists selected from: nanoimprint resists, photoresists such as, for example, Bisphenol A novolac epoxy (SU- 8) or polyhydroxybenzyl silsesquioxane, or any other suitable resist. Where a foil based material is used the substrate may comprise one or more foils selected from: polymeric foils or any other suitable foil. Where an insulator-coated metal is used, the substrate may comprise one or more insulator-coated metals selected from: insulator coated stainless- steel or any other suitable insulator-coated metal.

[0057] Additionally or alternatively, a flexible IC may not include the flexible substrate, which, for example, may be removed during a manufacturing step.

[0058] A device 900 is now described with reference to Figure 9. The device 900 comprises a flexible interconnect 994 comprising an integrated circuit 992 as described herein. A first part 996 of the device 900 is flexibly connected to a second part 998 of the device 900. In other examples, the interconnect is an interposer.

[0059] Other devices comprising an IC described herein are envisaged, for example: a radio-frequency identification (RFID) device, a medical device, smart glasses,an augmented reality device, a virtual reality device, a sensing device, an audio device, a communication device, a display device, or a packaging device. Some examples herein relate to a device including a processor and / or a microprocessor comprising an IC described herein. In some such examples, the processor and / or microprocessor is a reduced instruction set computer (RISC) processor. Further devices comprising an integrated circuit (IC) described herein are envisaged, for example: an application-specific integrated circuit (ASIC), a neural network IC, a machine learning IC, an artificial intelligence IC, read-only memory (ROM), programmable ROM (PROM), memory, random-access memory (RAM), dynamic random-access memory (DRAM), static random-access memory (SRAM), and / or non-volatile memory (NVM).

[0060] Whilst the present disclosure has been described and illustrated with reference to particular examples, it will be appreciated by those of ordinary skill in the art that the present disclosure lends itself to many different variations not specifically illustrated herein. By way of example only, certain possible variations will now be described.

[0061] A supply voltage herein is, e.g., a voltage supply, a drain voltage supply, and / or a first voltage supply. In some examples, the voltage supply is configured to supply a supply voltage and / or a drain voltage. Ground herein is, e.g., a second voltage supply. In some examples, the second voltage supply is configured to supply electrical ground, supply ground, supply a source voltage, supply a further supply voltage, and / or is ground. In some examples, a first voltage supply herein is a drain voltage supply. In some examples, the second voltage supply is configured to provide a positive voltage. In some examples the second voltage supply is a source voltage supply. In some examples, the second voltage supply is configured to provide a negative voltage, a zero voltage, a substantially zero voltage, and / or an electrical ground. It will be appreciated that references to “ground” are intended to refer merely to a reference voltage in the electronic circuit and are not limited to a connection to the Earth and / or an electrical ground. The illustrated schematics label ground as “VSS”. However, this notation is not intended to indicate that the circuit has positive and negative voltage supplies. Some variants of the present disclosure do have both positive and negative voltage supplies. Other variants have only a positive voltage supply. Similarly, it will be appreciated that, as ground merelyrefers to a reference voltage within the electronic circuit, alternative labelling for the electronic circuit of the present invention could designate VDD as ground, in which case VSS could instead be considered a negative supply voltage.

[0062] Similarly, whilst the illustrated disclosures may utilise NMOS transistors, it will be appreciated that other types of transistor could alternatively be used. For example, in other variations, the transistors in the electronic circuit comprise NPN Bipolar Junction Transistors (BJTs). In such cases, it will be appreciated that references throughout the specification to a “gate terminal” would instead relate to a “base terminal”, references to a “source terminal” would instead relate to an “emitter terminal”, and references to a “drain terminal” instead relate to a “collector terminal”.

[0063] A polarity of a transistor herein relates to a charge carrier of the semiconductor of the transistor that provides electrical conductivity, e.g., electrons for NMOS, or electron-holes for PMOS. For example, two NMOS transistors have a common polarity; contrastingly a NMOS transistor and a PMOS transistor do not have a common polarity. In some examples herein the transistors are monopolar (otherwise referred to as unipolar and in contrast to bipolar or ambipolar). This may facilitate the electronic circuit to be manufactured with a mono-type semiconductor (a semiconductor that can substantially only support one type of charge carrier: electrons or electron-holes). In some examples, the electronic circuit does not comprise a bipolar transistor. In some examples the electronic circuit does not comprise an ambipolar transistor.

[0064] In some examples, the first, second, third, and fourth transistors are monopolar. In some examples herein a channel of the first, second, third, and fourth transistors herein is a mono-type semiconductor. This may facilitate the transistor(s) to be manufactured with a mono-type semiconductor. In some examples, at least one of the first, second, third, or fourth transistors is a thin film transistor. This may facilitate the transistor(s), electronic circuit and / or IC being flexible and / or bendable, and / or manufacturable with low environmental impact and in a short time.

[0065] A coupling herein is an electrical coupling and may be direct (with no components between the coupled parts) or indirect (with a component between the coupled parts). An electrical coupling may be provided by a trace or line of electrically conductive material, a via, and / or a wire. Other forms of electrical coupling are envisaged.A coupling herein may be an electrical connection, e.g., a first part which is coupled between a second part and a third part is indirectly or directly electrically connected to the second part and the third part.

[0066] A material herein refers to an atomic composition of a trace of a resistor, a channel of a transistor, a substrate, an electrical connection, a component etc. The atomic composition relates to the types of atoms included in the material in question and also to the relative quantities of those types of atoms. For example, zinc oxide (ZnO) is a particular material, while indium gallium zinc oxide (InGaZnO, also referred to as IGZO) is referred to as a different material because it also comprises indium and gallium atoms making the composition different. In some examples herein, a first IGZO with an ln:Ga:Zn stoichiometry of 1 :1 :1 is a different material to a second IGZO with an ln:Ga:Zn stoichiometry of 1 :3:1 because the relative quantities of the types of atoms are different. In other examples, two alloys or compounds that comprise the same elements and have different stoichiometries (e.g., two stoichiometries of IGZO) are the same material.

[0067] A semiconductor herein has a Fermi level within an electronic bandgap between its electronic valence and conduction bands. An energy of the electronic bandgap may be low enough for the conduction band to be thermally populated by electrons or electron holes, e.g., at 298 Kelvin. An electrical conductivity of a semiconductor may increase with temperature. An n-type semiconductor herein is a semiconductor that has been doped with an electron donor. A p-type semiconductor herein is a semiconductor that has been doped with an electron hole donor.

[0068] A semiconductor, e.g., a semiconductor of a channel of a transistor herein may be selected from one or more of: compound semiconductors, metal oxides, metal oxynitrides, inorganic semiconductors, organic semiconductors, polymer semiconductors, 2D semiconductor materials, chalcogenides, perovskites, or any other semiconductor material. For example, semiconductor materials may be selected from one or more of: GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb, ZnO, SnO2, NiO, SnO, Cu2O, ln2O3, LiZnO, ZnSnO, InSnO (ITO), InZnO (IZO), HflnZnO (HIZO), InGaZnO (IGZO) ZnxOyNz amorphous, microcrystalline or nanocrystalline Si, copper(ll) phthalocyanine (CuPc), pentacene, perylenetetracarboxylic dianhydride (PTCDA), methylene blue, Orange G, rubrene; PEDOT:PSS, poly(3-octylthiophene) (POT), poly(3-octylthiophene-2,5-diyl) (P30T), poly(3-hexylthiophene) (P3HT), polyaniline, polycarbazole, graphene, MoS2, GeSbTeSrTiO3, CH3NH3PbCI3, H2NCHNH2PbCI3, CsSnl3, or any other suitable semiconductor material.

[0069] Providing herein may comprise forming, as described below, or other methods of providing such as by a different method or purchase from a supplier.

[0070] Forming herein may comprise a manufacturing process, e.g., using known techniques such as lithography, photolithography, etching, heating, deposition, or spin coating.

[0071] First, second, third, fourth, fifth, and sixth as used herein do not imply the presence of each other. For example, a second resistor herein does not limit a claim or example herein to including a first resistor. Similarly, for example, a first resistor herein does not limit the claim or example herein to including a second resistor. Further, first, second, third, fourth, fifth, and sixth as used herein do not imply an order or chronology unless explicitly stated. Further, features of the examples in the detailed description without an ordinal number (e.g. “first”) such may relate to a claim feature with an ordinal number of the claims. Similarly, the ordinal number use for a feature in the examples of the detailed description may relate to a claim feature with a different ordinal number. Similarly, “further” feature as used herein does not limit a claim or example herein to including a not “further” feature.

[0072] Where in the foregoing description, integers or elements are mentioned which have known, obvious or foreseeable equivalents, then such equivalents are herein incorporated as if individually set forth. Reference should be made to the claims for determining the true scope of the present disclosure, which should be construed so as to encompass any such equivalents. It will also be appreciated by the reader that integers or features of the present disclosure that are described as preferable, advantageous, convenient or the like are optional and do not limit the scope of the independent claims. Moreover, it is to be understood that such optional integers or features, whilst of possible benefit in some aspects of the present disclosure, may not be desirable, and may therefore be absent, in other aspects.

Claims

Claims1 . An electronic circuit comprising: a first transistor coupled between a voltage supply and a first node; a second transistor coupled between the voltage supply and a second node; and a differential amplifier comprising first and second input terminals and an output terminal, wherein: the differential amplifier is coupled to an input terminal of the first transistor and to an input terminal of the second transistor; the first node is coupled to the first input terminal of the differential amplifier; and the second node is coupled to the second input terminal of the differential amplifier.

2. The electronic circuit according to claim 1 , wherein the output terminal of the differential amplifier is coupled to the input terminal of the first transistor and to the input terminal of the second transistor.

3. The electronic circuit according to claim 1 or 2, wherein: the drain terminal of the first transistor is coupled to the voltage supply; the source terminal of the first transistor is coupled to the first node; the drain terminal of the second transistor is coupled to the voltage supply; and the source terminal of the second transistor is coupled to the second node.

4. The electronic circuit according to any preceding claim, wherein the first and second transistors are identical.

5. The electronic circuit according to any preceding claim, wherein: the first input terminal of the differential amplifier is the inverting input; and the second input terminal of the differential amplifier is the non-inverting input.

6. The electronic circuit according to any preceding claim, further comprising: a third transistor coupled between the first node and a further voltage supply; anda fourth transistor coupled between the second node and the further voltage supply, wherein the input terminals of the third and fourth transistors are coupled to the first node.

7. The electronic circuit of claim 6, comprising a resistor coupled: between the first node and the further voltage supply; or between the second node and the further voltage supply.

8. The electronic circuit according to claim 7, wherein the resistor is a switched capacitor resistor.

9. The electronic circuit according to any of claims 6 to 8, wherein: the fourth transistor has a semiconductor channel having a greater width to length ratio than the third transistor; or the third transistor has a semiconductor channel having a greater width to length ratio than the fourth transistor.

10. The electronic circuit according to claim 9, wherein the width to length ratios of the third and fourth transistors differ by a factor of at least ten.11 . The electronic circuit according to any of claims 6 to 10, wherein: the drain terminal of the third transistor is coupled to the first node; the source terminal of the third transistor is coupled to the further voltage supply; the drain terminal of the fourth transistor is coupled to the second node; and the source terminal of the fourth transistor is coupled to the further voltage supply.

12. The electronic circuit according to any one of claims 6 to 11 , wherein the input terminals of the third and fourth transistors are gate terminals.

13. The electronic circuit of any preceding claim, comprising at least one of:a first further resistor coupled between the first node and the first transistor; or a second further resistor coupled between the second node and the second transistor.

14. An electronic circuit comprising: a first resistor coupled between a voltage supply and a first node; a second resistor coupled between the voltage supply and a second node; a differential amplifier comprising an inverting input, a non-inverting input and an output terminal; a first transistor coupled between the first node and a further voltage supply; and a second transistor coupled between the second node and the further voltage supply, wherein: the differential amplifier is coupled to an input terminal of the first transistor and to an input terminal of the second transistor; the first node is coupled to the non-inverting input; and the second node is coupled to the inverting input.

15. The electronic circuit according to claim 14, the output terminal of the differential amplifier is coupled to the input terminal of the first transistor and to the input terminal of the second transistor.

16. The electronic circuit according to claim 14 or 15, wherein: the drain terminal of the first transistor is coupled to the first node; the source terminal of the first transistor is coupled to a further voltage supply; the drain terminal of the second transistor is coupled to the second node; and the source terminal of the second transistor is coupled to the further voltage supply.

17. The electronic circuit according to any one of claims 14 to 16, comprising a third resistor coupled: between the first node and the further voltage supply; or between the second node and the further voltage supply.

18. The electronic circuit according to claim 17, wherein the third resistor is a switched capacitor resistor19. The electronic circuit according to any one of claims 14 to 18, wherein the second transistor has a greater width to length ratio than the first transistor.

20. The electronic circuit according to any one of claims 14 to 19, comprising: a third transistor coupled between the first node and the voltage supply; and a fourth transistor coupled between the second node and the voltage supply.21 . The electronic circuit according to any one of claims 14 to 20, wherein the first and second resistors have the same resistance.

22. The electronic circuit according to any preceding claim, wherein the input terminals of the first and second transistors are gate terminals.

23. The electronic circuit according to any preceding claim, wherein the differential amplifier is a three-stage operational amplifier.

24. The electronic circuit according to any preceding claim, wherein each transistor comprises an N-Channel Metal Oxide Semiconductor (NMOS) transistor.

25. The electronic circuit according to any preceding claim, wherein the voltage supply is configured to supply a positive voltage.

26. The electronic circuit according to any preceding claim, wherein each transistor does not comprise a P-Channel Metal Oxide Semiconductor (PMOS) transistor.

27. An integrated circuit comprising an electronic circuit according to any preceding claim.

28. The integrated circuit according to claim 27, wherein the integrated circuit is a flexible integrated circuit.

29. A differential amplifier comprising a biasing circuit arranged to, when in use, reduce or eliminate a DC offset in a differential output of the amplifier arising from an increase or decrease in an amplifier supply voltage relative to a further voltage supplied by a further voltage supply.

30. The differential amplifier according to claim 29, wherein the biasing circuit comprises a first transistor coupled to a voltage supply via a first resistor and coupled to the further voltage supply via a second resistor.31 . The differential amplifier according to claim 30, wherein: the drain terminal of the first transistor is coupled to the voltage supply via the first resistor; the source terminal of the first transistor is coupled to the further voltage supply via the second resistor; and the gate terminal of the first transistor is coupled to the drain terminal of the first transistor.

32. The differential amplifier according to claim 30 or 31 , wherein an input stage of the differential amplifier is coupled to the further voltage supply via a second transistor, and the gate terminal of the second transistor is coupled to the gate terminal of the first transistor.

33. The differential amplifier according to claim 32, wherein: the input stage comprises an identical pair of third and fourth transistors;an input terminal of the third transistor is arranged to receive a non-inverting input to the differential amplifier; an input terminal of the fourth transistor is arranged to receive an inverting input to the differential amplifier; the third transistor is coupled to the voltage supply via a third resistor; the fourth transistor is coupled to the voltage supply via a fourth resistor; and the third and fourth transistors are coupled to the further voltage supply via the second transistor.

34. The differential amplifier according to claim 33, wherein the third and fourth resistors have the same resistance.

35. An electronic circuit according to any one of claims 1 to 26, wherein the differential amplifier is a differential amplifier according to any one of claims 29 to 34.

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