Controller for Flyback Converter

Abstract

The converter control circuit includes a terminal coupled to the switch node. The converter control circuit includes a valley sensing circuit (150) coupled to the terminal to detect a valley of an oscillating voltage on the switch node. The valley sensing circuit (150) has a first output and asserts a first control signal on the first output indicative of an occurrence of a valley. A logic gate (170) has a second output and asserts a second control signal on the second output to turn on the switching transistor (M1). A switch-on control circuit (165) has a first input and a second input. The first input is coupled to the first output. The second input is coupled to the second output. The switch-on control circuit (165) asserts a third control signal to turn on the switching transistor (M1) in response to the first control signal indicating a valley while the second control signal indicates that the switching transistor (M1) is on.

Description

[Technical field]

[0001] A direct current (DC)-DC or alternating current (AC)-DC flyback converter converts an input voltage to an output voltage and provides galvanic isolation between the two voltages. One category of flyback converter is the quasi-resonant flyback converter, where a variable frequency is used to determine when to turn on valley switching. In the quasi-resonant flyback converter, the turn-on losses due to the switch can be eliminated or reduced by operating in a valley switching mode. Summary of the Invention

[0002] In one example, a control circuit for a converter includes a terminal adapted to be coupled to a switch node of the converter. The control circuit includes a valley sensing circuit coupled to the terminal and configured to detect a valley of an oscillating voltage on the switch node. The valley sensing circuit has a first output and is configured to assert a first control signal on the first output indicative of an occurrence of a valley. A logic gate has a second output. The logic gate is configured to assert a second control signal on the second output to turn on a switching transistor coupled to the switch node. A switch-on control circuit has a first input and a second input. The first input is coupled to the first output. The second input is coupled to the second output. The switch-on control circuit is configured to assert a third control signal to turn on the switching transistor in response to the first control signal indicating an occurrence of a valley while the second control signal indicates that the switching transistor is turned on.

[0003] In another example, a method of controlling a flyback converter includes turning off a switching transistor coupled to a primary coil of a transformer at a switch node, the method including detecting when a current through a secondary coil of the transformer drops to approximately zero amperes. The method further includes determining when each valley of an oscillating voltage on the switch node occurs. In response to receiving a signal to turn on the switching transistor, the method includes turning on the switching transistor at the occurrence of a subsequent valley. [Brief description of the drawings]

[0004] For a detailed description of various examples, reference will now be made to the accompanying drawings.

[0005] [Figure 1] 1 illustrates a schematic diagram of a control circuit for a flyback converter in one example.

[0006] [Diagram 2] 1 illustrates a timing diagram of the operation of a primary-side regulated flyback converter in one example.

[0007] [Diagram 3] 1 illustrates a timing diagram for detecting a switch valley in one example.

[0008] In the drawings, the same reference numbers are used for the same or similar features (either of function and / or structure). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] A flyback voltage converter converts an input voltage (or current) into a desired output voltage (or current) using a transformer having a primary coil and a secondary coil connected between the input and output, respectively. The transformer provides galvanic isolation between the input and output. The converter includes a switching element (e.g., a transistor) connected to the primary coil to turn on and off the current to the primary coil. One type of flyback converter is the quasi-resonant flyback converter. Quasi-resonant flyback converters can operate in continuous conduction mode (CCM), discontinuous conduction mode (DCM), or boundary conduction mode (BCM). During CCM, current flows continuously in the primary coil of the transformer. During DCM, current stops flowing in the transformer for a portion of each switching cycle. BCM refers to the state where the switch turns on as soon as the current in the primary winding drops to zero amperes.

[0010] The embodiments described herein are directed to a control circuit for a quasi-resonant flyback converter capable of operating in DCM. However, the techniques described also apply to BCM operation. The control circuit described herein is particularly useful for a primary-side regulated flyback converter, where the control circuit regulates the current through a primary coil of a transformer, thereby regulating the output voltage on the secondary side of the transformer. The control circuit includes a feedback (FB) node adapted to be coupled to a switch node (SW) of the flyback converter. In one embodiment, the control circuit is fabricated as an integrated circuit (IC), and the FB node is a pin of the IC. The control circuit includes circuit elements that monitor the FB node for three reasons: (1) zero-crossing current sensing, (2) output voltage (VOUT) sampling, and (3) SW node valley sensing. During BCM and DCM operation, after the main switching element (e.g., transistor) turns off, the transformer secondary coil current rises and then begins to decay approximately linearly until the secondary current reaches (crosses) zero current, at which point the SW node voltage begins to ring sinusoidally.

[0011] The ringing SW node voltage has a series of decaying peaks and valleys. The SW node voltage is coupled across the switching element. When the control circuit determines to turn on the switching element, a valley sensing circuit in the control circuit prevents the switching element from turning on until the next SW node voltage valley occurs. By turning on the switching element at the valley of the SW node voltage, switching losses in the switching element are reduced compared to if the switching element were turned on when the SW node voltage was greater than the valley point in the ringing voltage waveform.

[0012] FIG. 1 is a schematic diagram of a DC-DC flyback converter 100 in an example embodiment. In this example, the flyback converter 100 includes an input 108 adapted to receive an input voltage (VIN) and an output 109 providing an output voltage VOUT. The converter 100 also includes a transformer TR1, a diode D1, and a transistor M1 (the switching element described above). The transformer TR1 includes a primary coil L1 and a secondary coil L2. The diode D1 is coupled to the secondary coil L2 and functions to rectify the voltage from the secondary coil. A current Ipri is the current through the primary coil L1, and a current Isec is the current through the secondary coil L2. The converter may also include an output capacitor COUT. The voltage across the capacitor COUT is VOUT. When M1 is on, current flows from VIN, through the primary coil L1, through M1, to ground. When M1 is off, the primary coil current is zero amperes.

[0013] The converter has a control circuit 120 that functions, among other things, to determine when to turn off M1, thereby regulating the current through the primary side of the transformer to regulate VOUT. As such, the flyback converter 100 in Figure 1 employs primary side regulation (PSR). The control circuit 120 includes a valley sensing circuit 150 that ensures that M1 is turned on at the valley of the oscillation phase of the SW node voltage.

[0014] Control circuit 120 regulates VOUT by determining the magnitude of VOUT and adjusting the duty cycle of M1 to maintain VOUT at a target level. However, while VOUT is provided on the secondary side of transformer TR1, the control circuit is connected to the primary side of the transformer. Thus, control circuit 120 does not have a galvanic connection to VOUT. Instead, the control circuit estimates the magnitude of VOUT by monitoring the magnitude of the voltage on the SW node.

[0015] FIG. 2 illustrates waveforms of the flyback converter 100 during a switching cycle. The waveforms include VIN, SW node voltage, and currents Ipri and Isec. When M1 is on, Ipri rises approximately linearly as shown at 201. The time period during which M1 is on is identified in FIG. 2 as Ton. When the control circuit 120 turns M1 off, Ipri drops to zero amperes and Isec rises as shown at 202. Isec then decreases approximately linearly as shown at 203. Eventually Isec reaches zero (point 204). The next switching cycle begins at 210. Between points 202 and 210, M1 is off. This time period is identified in FIG. 2 as Toff. Between points 204 and 210, not only is Ipri equal to zero amperes, but Isec is also equal to zero amperes.

[0016] When M1 is on, the SW node voltage is 0V. As soon as the control circuit 120 turns M1 off, the SW node voltage rises to a value greater than Vin as identified at 220. The magnitude of the SW node voltage is a function of the turns ratio of the transformer, VOUT, the forward voltage drop (Vf) of the diode D1, and the product of Isec and Resr. Resr is the sum of the parasitic resistances of the diode D1 and the capacitor Cout. The voltage of the FB node (Vfb) is directly proportional to the voltage of the SW node, so equation (1) provides the above relationship for Vfb. Vfb=VSW-VIN=Nfs×(VOUT+Vf+(Isec×Resr) (1) where Nfs is the ratio of the number of turns in the primary coil L1 to the number of turns in the secondary coil L2. When Isec reaches zero amperes at point 204, the term Isec x Resr equals zero, so Vfb is a function of Vout plus the forward voltage drop of diode D1 (multiplied by the turns ratio of transformer TR1). Control circuit 120 takes advantage of this fact by sampling Vfb at the instant Isec crosses zero. At that instant, Vfb is just a function of Vout. The sampling instant is identified at 221.

[0017] Because the control circuit 120 does not have direct electrical access to the secondary coil L2, the control circuit 120 estimates when Isec crosses zero by detecting the beginning of an oscillation phase in the SW node voltage. In the embodiment described below, the control circuit includes circuitry to detect the "knee" 225 in the SW node voltage that occurs when Isec crosses zero. The knee is characterized by a dramatic change in the slope of the SW node voltage.

[0018] Referring back to FIG. 1, the inflection point 225 is detected using the current mirror 115, resistor Rset, low pass filter 125, and comparator COMP1. During the off-time (M1 off), the switch node voltage is a function of VIN+VOUT. The current mirror includes transistors M2 and M3, employing a 5:1 current mirror ratio in this example (the current through M3 is 5 times the current through M2). VIN is coupled to the source of M2. The same VIN voltage is also regulated on the source of M3 due to the current mirroring function implemented by M2 and M3. For example, if the source of M3 (VFB) is greater than VIN, M3 sinks more current through resistor RFB and VFB decreases. If VFB is less than VIN, M3 sinks less current and VFB increases. If the SW node voltage is approximately equal to VIN+VOUT and the source voltage of M3 is equal to VIN, the voltage difference across resistor Rfb is approximately VOUT. Therefore, the current through resistor Rfb is approximately equal to Vout / Rfb. The current Ifb through M3 flows down to resistor Rset, thereby generating a voltage on the RSET node that is approximately equal to VOUT x Rset / Rfb. In other words, the voltage on the RSET node is proportional to VOUT.

[0019] As mentioned above, sampling the SW node voltage at the moment Isec crosses 0 provides a satisfactory approximation of V. The RSET node voltage is low-pass filtered by low-pass filter 125 (which in this example includes resistors Rlp and Clp) and sampled by switch S3 and capacitor Ch.

[0020] The current mirror 115, resistor Rset, low pass filter 125, and comparator COMP1 are also used to detect an inflection point 225 in the SW node voltage. As described above, the voltage across resistor Rset is a function of the SW node voltage and therefore has the same or similar waveform shape (including the inflection point 225 and subsequent ringing). The RSET voltage is coupled to the inverting input of comparator COMP1. A low pass filtered version of RSET is coupled to the non-inverting input of comparator COMP1. COMP1 therefore compares a slower changing version of the SW node voltage to the actual unfiltered, faster changing SW node voltage. When the inflection point 225 occurs, the SW node voltage falls more rapidly than the response of the output of low pass filter 125, and therefore the output of COMP1 (ZX) becomes a logic high. Thus, a logic high for ZX indicates that Iset has crossed zero amperes.

[0021] Valley sensing circuit 150 includes OP1, transistor M4, current sources Isrc1 and Iscr2, ramp timer 154, switches SWA and SWB, capacitors CA and CB, and comparator COMP2. FIG. 3 provides additional waveforms illustrating the operation of valley sensing circuit 150. The ringing in the SW node voltage is approximately a damped sinusoidal waveform. Therefore, the time between the peak and the point where Vsw crosses Vin is the same as the time between the point where Vsw crosses Vin and the subsequent valley. Time point 301 is the time when the peak occurs. Point 302 is the zero crossing point. Point 303 identifies the subsequent valley. The time difference between points 301 and 302 is the same as the time difference between points 302 and 303. Valley sensing circuit 150 implements an analog timer to measure and store the time between points 301 and 302, and then uses the measured and stored time to estimate when the subsequent valley will occur.

[0022] Referring again to FIG. 1, as described above, ZX becomes logic high when an inflection point occurs that generally coincides with the peak of the ringing phase of the SW node voltage. The ramp timer 154 responds to ZX being high by closing the switch SWA. Therefore, a current Isrc2 flows into the capacitor CA, charging it. The voltage on the capacitor CA increases approximately linearly while the switch SWA is closed. During the off phase (M1 off), no current flows through the primary coil L1 or through the resistor Rfb. Therefore, the voltage on the FB node is the voltage on the SW node. The voltages on the inverting and non-inverting inputs of OP1 are approximately equal. The voltage on the non-inverting input of OP1, which is the switch node voltage, forces the inverting input voltage to be the switch node voltage as well. If the switch node voltage is higher than Vin, no current flows through the transistor M4, and therefore the input 156 to the ramp timer is logic low.

[0023] When Vsw falls below Vin, current flows through transistor M4, forcing input 156 of ramp timer 154 high. That logic high is thus generated when the switch (or FB) node falls below VIN. Ramp timer 154 responds to the logic high assertion on its input 156 by opening switch SWA. The resulting voltage on capacitor CA is a function of the time between the peak of the SW node voltage and the VIN crossing. That voltage (the CA voltage) is provided to the inverting input of COMP2.

[0024] The capacitance of CB is approximately equal to the capacitance of CA, and the same current source Isrc2 is used to charge capacitor C2 when switch SWB is closed. When switch SWA is opened, the ramp timer also closes switch SWB, thereby initiating a charging cycle for capacitor CB. The voltage on capacitor CB then begins to increase linearly at the same rate as capacitor CA. The output 157 of comparator COMP2 becomes logic high at the moment the voltage on capacitor CB reaches the voltage on capacitor CA, indicating that a valley of the SW node voltage has occurred. FIG. 3 illustrates the waveforms of VA (the voltage on capacitor CA) and VB (the voltage on capacitor CB). As shown, VA is determined during the first period of the ringing SW node voltage ringing and remains fixed to ensure a ringing oscillation for comparison with VB. Capacitor CB is charged and discharged during each oscillation to be compared with VA to determine the occurrence of each valley.

[0025] The output 157 of comparator COMP2 is provided to one shot 162. In one example, the one shot generates a 20 ns output pulse when it detects a logic high at its input. FIG. 3 illustrates that the one shot 162 generates an output pulse 310 that coincides with each valley of the SW node voltage. The output of the one shot 162 is coupled to the input of a switch-on control circuit 165, which in this example includes a D flip-flop (DFF) 167. The output of the one shot 162 is coupled to a clock input of DFF 167. The D input of DFF 167 receives a control signal from an AND gate 170. The inputs to the AND gate 170 are the ZX signal (described above) and the TFMAX signal. The ZX signal indicates when Isec crosses zero amperes. During BCM, the control circuit 120 turns on M1 when ZX goes to logic high. During DCM, the control circuit 120 turns on M1 when TFMAX goes to logic high. TFMAX is generated by a timer 171. Thus, the output signal 172 from the AND gate indicates when a portion of the control circuit 120 has decided to turn M1 on. The switch-on control circuit 165 functions to turn M1 on when two conditions are simultaneously true: (1) the AND gate output signal 172 is a logic high, and (2) the output signal 157 from the comparator COMP2 is also a logic high. In other words, the switch-on control circuit 165 turns M1 on when the signal 172 is high, but only when the comparator COMP2 indicates that the next valley of the SW node voltage is occurring.

[0026] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, (A) in a first example, device A is coupled to device B by a direct connection, where device A generates a signal that controls device B to perform an action, or (b) in a second example, device A is coupled to device B via an intervening component C, such that device B is controlled by device A via a control signal generated by device A, where intervening component C does not change the functional relationship between device A and device B.

[0027] A device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnections of the device, or through a combination thereof.

[0028] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless otherwise noted, these terms are used generally to mean an interconnection between, or the termination of, a device element, a circuit element, an integrated circuit, a device, or other electronic or semiconductor component.

[0029] A circuit or device described herein as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacture, e.g., by an end user and / or a third party, to form the described structure.

[0030] Although the use of particular transistors is described herein, other transistors (or equivalent devices) may be substituted. For example, a p-type metal oxide silicon field effect transistor ("MOSFET") may be substituted for an n-type MOS FET with little or no change to the circuit. Also, other types of transistors may be used, such as bipolar junction transistors (BJTs).

[0031] The circuits described herein are reconfigurable to include additional or different components to provide at least partially similar functionality to that available prior to component replacement. A component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown, unless otherwise noted. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0032] Use of the term "ground" in the preceding description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable for the teachings of the present description. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value. Modifications may be made in the described examples and other embodiments are possible within the scope of the present claims.

[0033] Modifications may be made to the examples described, and other examples are possible, all within the scope of the invention.

Claims

1. 1. A control circuit for a converter, comprising: a valley sense circuit coupled to the switch terminal and having a valley sense output, detecting a valley in the oscillating voltage at the switch terminals; providing a first control signal to the valley sense output in response to the occurrence of a valley; the valley sensing circuit configured as follows: a logic gate having a logic output, the logic gate configured to provide a second control signal to the logic output to turn on a switching transistor coupled to the switch terminal; a switch-on control circuit having a first switch-on input coupled to the valley sense output and a second switch-on input coupled to the logic output, the switch-on control circuit configured to provide a third control signal to turn on the switching transistor in response to the first control signal indicating the occurrence of a valley while the second control signal indicates that the switching transistor should be turned on; a control circuit.

2. 2. The control circuit of claim 1, The control circuit, wherein the switch-on control circuit includes a flip-flop.

3. 3. The control circuit of claim 2, A control circuit wherein the flip-flop has a data input coupled to the logic output and a clock input coupled to the valley sensitive output.

4. 2. The control circuit of claim 1, The valley sensing circuit a current source; a first capacitor coupled in series with a first switch between the current source and a ground terminal; a second capacitor coupled in series with a second switch between the current source and the ground terminal; a comparator having a first comparator input coupled to the first capacitor, a second comparator input coupled to the second capacitor, and a comparator output configured to provide the third control signal; a control circuit.

5. 5. The control circuit of claim 4, The control circuit wherein the switch-on circuit includes a flip-flop having a data input coupled to the logic output and a clock input coupled to the comparator output.

6. 6. The control circuit of claim 5, The control circuit further includes a one-shot coupled between the comparator output and the clock input.

7. 5. The control circuit of claim 4, The control circuit, wherein the capacitances of the first capacitor and the second capacitor are approximately equal.

8. 5. The control circuit of claim 4, The valley sensing circuit is a lamp timer, closing the first switch in response to detecting the onset of oscillation at the switch terminals, and opening the first switch in response to the voltage at the switch terminals falling below an input voltage to the converter; closing the second switch in response to the voltage at the switch terminal falling below the input voltage. a control circuit including the lamp timer configured to:

9. 9. The control circuit of claim 8, A control circuit having a lamp timer input configured to receive a signal indicating that the lamp timer voltage at the switch terminal is below the input voltage.

10. 2. The control circuit of claim 1, The control circuit is adapted to be coupled to a flyback converter.

11. 1. A flyback converter, comprising: a transformer having a primary coil and a secondary coil; a switching transistor coupled to the primary coil at a switch terminal; a control circuit having a feedback input coupled to the switch terminal, detecting a valley of the oscillating voltage at the switch terminal; turning on the switching transistor substantially simultaneously with the occurrence of a valley among the detected valleys; The control circuit is configured as follows: Including, The control circuit a first circuit having a first circuit output, the first circuit configured to detect valleys in the oscillating voltage at the switch terminals when current through the secondary coil reaches zero amperes, and to provide voltage pulses at the first circuit output corresponding to each detected valley; a second circuit having a second circuit output, the second circuit configured to provide a control signal to the second circuit output for turning on the switching transistor; a switch-on control circuit coupled to the first circuit and the second circuit, the switch-on control circuit configured to turn on the switching transistor in response to a control signal from the second circuit output indicating that the switching transistor should be turned on when the first circuit provides a voltage pulse to the first circuit output; Including, a flyback converter.

12. 12. The flyback converter of claim 11, The switch-on control circuit of the flyback converter includes a flip-flop.

13. 13. The flyback converter of claim 12, A flyback converter, wherein the flip-flop has a data input coupled to the second circuit output and a clock input coupled to the first circuit output.

14. 14. The flyback converter of claim 13, The flyback converter further comprising a one-shot coupled between the first circuit output and the clock input.

15. 12. The flyback converter of claim 11, The control circuit a current source; a first capacitor coupled in series with a first switch between the current source and a ground terminal; a second capacitor coupled in series with a second switch between the current source and the ground terminal; a comparator having a first comparator input coupled to the first capacitor, a second comparator input coupled to the second capacitor, and a comparator output, the comparator configured to provide a third control signal to the comparator output; Including, a flyback converter.

16. 16. The flyback converter of claim 15, a one-shot having a one-shot input coupled to the comparator output and a one-shot output; a flip-flop having a clock input coupled to said one-shot output; The flyback converter further comprises:

17. 12. The flyback converter of claim 11, The flyback converter is a quasi-resonant flyback converter.

18. 1. A method of controlling a flyback converter including a transformer and a switching transistor, the transformer having a primary coil and a secondary coil, the switching transistor coupled to the primary coil at a switch terminal, the method comprising: turning off the switching transistor; detecting when the current through the secondary coil drops to approximately zero amperes; determining when each valley of the oscillating voltage at the switch terminal occurs, charging a first capacitor with a current source to about one-quarter of the oscillating voltage; charging a second capacitor with the current source; determining when the voltage on the second capacitor is approximately equal to the voltage on the first capacitor; determining when said occurrence occurs by turning on the switching transistor upon a subsequent occurrence of a valley in response to receiving a signal to turn on the switching transistor; A method comprising:

Images