Wiring board and semiconductor package

Abstract

To provide a wiring board capable of flip-chip mounting a semiconductor chip in which a part of an electrode pad is arranged at a narrow pitch as compared with other electrode pads, and a semiconductor package using the wiring board.SOLUTION: A wiring board 10 for flip-chip mounting a semiconductor chip includes a plurality of first wiring lines 11 provided on one main surface 10a of the wiring board 10 and a plurality of second wiring lines 12 provided on the one main surface 10a of the wiring board 10. The first wiring lines 11 each include a first connection 11a, and the second wiring lines 12 each include a second connection 12a. The second connection 12a has a planar shape different from that of the first connection 11a, and an area of the second connection 12a is the same as an area of the first connection 11a. The first connection 11a is separated from the adjacent first connection 11a by a first pitch P1, and the second connection 12a is separated from the adjacent second connection 12a by a second pitch P2 smaller than the first pitch P1.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a wiring substrate for flip chip mounting and a semiconductor package using the wiring substrate. [Background technology]

[0002] Flip-chip mounting is a conventional method for mounting semiconductor chips. In flip-chip mounting, electrode pads on a semiconductor chip and pads (FC pads) on a wiring board are bonded with a bonding material such as solder provided on a columnar electrode.

[0003] Here, when the pitch between the electrode pads of the semiconductor chip is small, the pitch between the pads of the wiring board must also be designed to be small. However, if the pad pitch of the wiring board is small, problems such as a decrease in yield may occur.

[0004] Therefore, for example, Patent Document 1 discloses a configuration in which the shape of the pad located at the tip is formed into a pointed shape, thereby ensuring the pitch between pads on a wiring board. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 3623407 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in recent years, with the trend toward higher integration, semiconductor chips are being used in which some of the electrode pads are arranged at a narrower pitch than the other electrode pads.

[0007] In order to accommodate such semiconductor chips, it is necessary to arrange the pads on the wiring board to match the narrow arrangement of the electrode pads. However, even if the pads are made pointed or shaped as in the configuration of Patent Document 1, it is not possible to space the pads the required distance apart from each other in manufacturing, and also, if the area of ​​the pads is reduced, the area over which the solder can wet and spread is reduced, causing the solder to bulge sideways, increasing the risk of short circuits.

[0008] This problem is particularly noticeable in highly integrated semiconductor chips with pad pitches of 45 μm to 85 μm.

[0009] The present disclosure has been made in consideration of the above-mentioned problems, and aims to provide a wiring substrate capable of flip-chip mounting a semiconductor chip in which some of the electrode pads are arranged at a narrower pitch than the other electrode pads, and a semiconductor package using the wiring substrate. [Means for solving the problem]

[0010] The wiring board according to the first aspect of the present disclosure includes: A wiring substrate for flip-chip mounting a semiconductor chip, a plurality of first wirings provided on one main surface of the wiring board; a plurality of second wirings provided on one main surface of the wiring board; the first wiring includes a first connection portion for connection to the semiconductor chip; the second wiring includes a second connection portion for connection to the semiconductor chip; the second connection portion has a planar shape different from that of the first connection portion, and an area of ​​the second connection portion is the same as an area of ​​the first connection portion; The first connection portions are spaced apart from adjacent first connection portions at a first pitch, and the second connection portions are spaced apart from adjacent second connection portions at a second pitch smaller than the first pitch.

[0011] A semiconductor package according to a second aspect of the present disclosure includes: A wiring board according to the first aspect; A semiconductor chip flip-chip mounted on the wiring substrate, The semiconductor chip comprises: a plurality of first electrode pads arranged at the first pitch; a plurality of second electrode pads arranged at the second pitch; The first electrode pad and the first connection portion of the wiring board are electrically connected by a first solder, and the second electrode pad and the second connection portion of the wiring board are electrically connected by a second solder having the same volume as the first solder. Effect of the Invention

[0012] According to the present disclosure, it is possible to provide a wiring substrate capable of flip-chip mounting a semiconductor chip in which some of the electrode pads are arranged at a narrower pitch compared to other electrode pads, and a semiconductor package using the wiring substrate. [Brief description of the drawings]

[0013] [Figure 1] 1 is a top view diagrammatically illustrating a semiconductor package according to a first embodiment. [Diagram 2] 2 is a cross-sectional view taken along line II-II of FIG. 1. [Diagram 3] FIG. 2 is a diagram illustrating an arrangement of first electrode pads and second electrode pads in the semiconductor chip according to the first embodiment. [Figure 4] 3 is a diagram illustrating an arrangement of first wiring and second wiring in a wiring board according to the first embodiment. FIG. [Diagram 5] FIG. 2 is a diagram illustrating a first wiring and a first joint according to the first embodiment. [Figure 6] 5A to 5C are diagrams illustrating a second wiring and a second joint according to the first embodiment. [Figure 7] 10 is a diagram illustrating a second wiring and a second joint according to the second embodiment. FIG. [Figure 8]13 is a diagram illustrating a second wiring and a second joint portion according to the third embodiment. FIG. [Figure 9] 13 is a diagram illustrating a second wiring and a second joint according to the fourth embodiment. FIG. [Figure 10] 11A and 11B are diagrams illustrating modified examples of the semiconductor chip. [Figure 11] 11A and 11B are diagrams illustrating modified examples of the semiconductor chip. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, a wiring board according to an embodiment of the present invention and a semiconductor package using the wiring board will be described with reference to the drawings.

[0015] (Embodiment 1) A semiconductor package 50 according to the first embodiment will be described below with reference to the drawings. In this embodiment, the semiconductor package 50 will be described as a Fan-Out Wafer Level Package (FOWLP) by way of example.

[0016] 1 and 2, the semiconductor package 50 includes a wiring board 10 and a semiconductor chip 20 mounted on the wiring board 10. The wiring board 10 and the semiconductor chip 20 are sealed with a resin mold (not shown).

[0017] 2 and 4, wiring board 10 includes first wiring 11 having first connection portion 11a and second wiring 12 having second connection portion 12a on first main surface 10a of wiring board 10 (top surface of wiring board 10 shown in FIG. 2). Wiring board 10 includes wiring layer 16 for external connection and solder balls 17 on second main surface 10b (bottom surface of wiring board 10 shown in FIG. 2). When wiring board 10 is a multilayer board as shown in FIG. 2, wiring board 10 includes internal wiring layer 15 therein.

[0018] As shown in Fig. 4, a plurality of first wirings 11 are provided, and the plurality of first wirings 11 are arranged at a distance from each other. The number of first wirings 11 provided corresponds to the number of first electrode pads 21 of the semiconductor chip 20 shown in Fig. 3. The first connection portions 11a of the first wirings 11 are arranged at a first pitch P1, and each first connection portion 11a is arranged at a distance D1 from another adjacent first connection portion 11a. The first wirings 11 and the first connection portions 11a are formed of a conductive material, for example, copper.

[0019] As shown in FIG. 4, a plurality of second wirings 12 are provided, three in the example shown in FIG. 4. The number of second wirings 12 also corresponds to the number of second electrode pads 22 of the semiconductor chip 20 shown in FIG. 3. The plurality of second wirings 12 are arranged spaced apart from one another. The second connection portions 12a of the second wirings 12 are arranged at a second pitch P2 narrower than the first pitch, and the second connection portions 12a are arranged spaced apart from adjacent second connection portions 12a by a distance D2. The second wirings 12 and the second connection portions 12a are formed from a conductive material, for example, copper.

[0020] The first pitch P1 and the second pitch P2 have a value of 40 μm or more and 85 μm or less.

[0021] As shown in FIG. 2 and FIG. 3, the semiconductor chip 20 includes a first electrode pad 21 and a second electrode pad 22 on the first main surface 20a side. As shown in FIG. 2, the periphery of the first electrode pad 21 and the second electrode pad 22 is covered with a protective film 27, and each is exposed through an opening 27a provided in the protective film 27. A first columnar electrode 23 is provided on the first electrode pad 21. The first columnar electrode 23 is, for example, a copper pillar formed from copper. A first solder 25 is provided on the first columnar electrode 23, and the first columnar electrode 23 is joined to the first wiring 11 on the wiring board 10 by the first solder 25. In addition, a second columnar electrode 24 is provided on the second electrode pad 22. The second columnar electrode 24 is, for example, a copper pillar formed from copper. A second solder 26 is provided on the second columnar electrode 24, and the second columnar electrode 24 is joined to the second wiring 12 on the wiring board 10 by the second solder 26.

[0022] In this embodiment, the first columnar electrode 23 and the second columnar electrode 24 have the same diameter and height. In addition, the first solder 25 and the second solder 26 have the same volume. The first solder 25 and the second solder 26 are made of an alloy such as a Sn-Ag or Sn-Ag-Cu alloy.

[0023] In this embodiment, the "same" in "same diameter" does not only mean exactly the same, but also allows for an error that occurs during manufacturing. For example, an error of ±5%, preferably ±1% is allowed. The "same" in terms of height, volume, area, etc. also includes similar errors.

[0024] The first electrode pads 21 are spaced apart from each other along each side of the semiconductor chip 20 at a first pitch P1, as shown in Fig. 3. A plurality of second electrode pads 22, for example, three, are provided as shown in Fig. 3, and are spaced apart from each other at a second pitch P2 smaller than the first pitch P1. In this embodiment, the size of the first electrode pads 21 and the size of the second electrode pads are the same. The size of each electrode pad is arbitrary, but is, for example, 50 μm × 50 μm.

[0025] As shown in FIG. 2, the first wirings 11 are provided on the first main surface 10a of the wiring board 10, and as shown in FIG. 4, the first wirings 11 are arranged along each side of the wiring board 10 so as to be spaced apart from each other at a first pitch P1. As shown in FIG. 5, the first wirings 11 are provided with a first connection portion 11a for electrically connecting the semiconductor chip 20 at the tip of the first wirings 11. As shown in FIG. 5, the first connection portion 11a is formed to have a circular shape when the first main surface 10a is viewed in plan. As shown in FIG. 5, the first connection portion 11a is a circle with a radius R1, and the diameter L01 of the first connection portion 11a is 2R1. Here, the area A1 of the first connection portion 11a is given by A1 = R1 × R1 × π In this embodiment, the area A1 of the first connection portion 11a is also the area of ​​the surface to which the first solder 25 is connected. Note that since the first wiring 11 and the first connection portion 11a are formed in the same process by plating or the like, there is no clear boundary between the first wiring 11 and the first connection portion 11a, but the area of ​​the first connection portion 11a is calculated under the assumption that there is a boundary B at the portion where a part of the circle is located.

[0026] The second wirings 12 are provided on the first main surface 10a of the wiring board 10, as shown in Fig. 2. The second wirings 12 are arranged along one side of the wiring board 10 at a second pitch P2, as shown in Fig. 4. In this embodiment, a case is taken as an example in which a plurality of second wirings 12 are grouped together and only one group is arranged on the wiring board 10. The second wirings 12 are provided at the tip of the second wirings 12 with a second connection portion 12a for electrically connecting the semiconductor chip 20, as shown in Fig. 6.

[0027] As shown in FIG. 6, the second connection portion 12a is formed to have a shape different from that of the first connection portion 11a when the first main surface 10a is viewed in plan. In this embodiment, the second connection portion 12a is formed to have a rectangular shape in which, of two pairs of opposing sides, one pair of opposing sides has a length of L11, and the other pair of opposing sides has a length of L12. The area A21 of the second connection portion 12a is formed to be the same as the area A1 of the first connection portion 11a. In this embodiment, the area A21 of the second connection portion 12a is the area of ​​the surface to which the second solder 26 is connected. Specifically, the area A21 of the second connection portion 12a is A21=L11×L12 The values ​​of L11 and L12 are set so that this value is equal to the area A1 of the first connection portion 11a. Note that since the second wiring 12 and the second connection portion 12a are also formed in the same process by plating or the like, there is no clear boundary between the second wiring 12 and the second connection portion 12a, but the area of ​​the second connection portion 12a is calculated assuming that there is a boundary B at the portion where one side of the rectangle is located.

[0028] The values ​​of the first side length L11 and the second side length L12 are determined, for example, as follows.

[0029] First, in the wiring design of the wiring board for flip-chip mounting, it is necessary to design the wiring while considering the risk of occurrence of defects, such as connection failure due to deviation of the bonding position of the semiconductor chip during mounting and occurrence of short circuit due to insufficient distance between adjacent connection parts. When there is a sufficient distance between the electrodes of the semiconductor chip, a standard rule with sufficient tolerance is used in consideration of occurrence of defects, and when there is not enough distance between the electrodes of the semiconductor chip and the standard rule cannot be applied, a special rule is used. As a result, the special rule is more likely to reduce the yield than the standard rule. In this embodiment, the first connection part 11a is designed to satisfy the standard rule, and the second connection part 12a is designed to satisfy the special rule. For example, each design rule requires that the connection part of the wiring board is larger than the diameter of the columnar electrode by a predetermined margin, that the connection part of the wiring board is separated from another adjacent connection part by a predetermined interval (pad space), and the like. As an example, the standard rule in this embodiment is that the connection part of the wiring board is at least 20 μm larger than the diameter of the columnar electrode and the pad space is at least 25 μm, while the special rule is that the connection part of the wiring board is at least 10 μm larger than the diameter of the columnar electrode and the pad space is at least 15 μm.

[0030] In this case, if the second pitch P2 of the second electrode pads 22 is 65 μm and the diameter PD of the second columnar electrode 24 is 40 μm, then if the length L11 is 50 μm, it is 10 μm larger than the diameter of the second columnar electrode 24 and the pad space D2 is 15 μm, which satisfies the special rule. This determines L11.

[0031] In addition, since the standard rule is applied to the first connection portion 11a, the diameter of the first connection portion 11a needs to be 20 μm or more larger than the diameter of the first columnar electrode 23. When the diameter L01 of the first connection portion 11a is set to 60 μm, the pad space D1 is determined to be 25 μm.

[0032] Next, the area A1 of the first connection portion is divided by the length L11 to calculate the length L12 of the second side. Since the diameter L01 of the first connection portion 11a is 60 μm, L12 is calculated using the following formula: L12=A1÷L11 From this, the result is 56.55 μm.

[0033] In this manner, the area A1 of the first connection portion 11a and the area A21 of the second connection portion 12a are made equal to each other.

[0034] According to this embodiment, the following effects can be obtained. Conventionally, when electrode pads are arranged at different pitches on a semiconductor chip and some electrode pads are arranged at a narrower pitch than others, the FC pads to which the columnar electrodes on the electrode pads arranged at the narrower pitch are joined have been addressed by reducing the pad size, reducing the pad pitch, making the pillars of the semiconductor chip thinner, etc.

[0035] However, in the conventional method, the pitch has become narrower to the point where the required dimensions (pad size, distance between pads) specified in the design rules cannot be met, making it difficult to manufacture wiring boards. If the size of some FC pads corresponding to electrode pads with narrow pitches is reduced, if the amount of solder is the same for each pad, the amount of solder will be excessive due to the reduced pad size, and the solder may bulge sideways or protrude outside the pad, resulting in contact with the solder of adjacent FC pads. However, adjusting the amount of solder for only some pads will increase the number of processes and cause problems with poor connection. In addition, if the pillars of the semiconductor chip are made thinner to increase the tolerance for deviation in the bonding position of the semiconductor chip in response to the smaller pads, the bonding area will be reduced, which may reduce the bonding strength between the pillars and the pads.

[0036] In contrast, in the wiring board 10 of the present embodiment, a first connection portion 11a and a second connection portion 12a having a planar shape different from that of the first connection portion 11a are provided, and further, the area A1 of the first connection portion 11a and the area A21 of the second connection portion 12a are made the same, so that the second connection portion 12a can be arranged to satisfy the design rules, and there is no need to make the diameter of the second columnar electrode 24 thinner than that of the first columnar electrode 23 connected to the first connection portion 11a, and there is also no need to change the volume of the solder between the first connection portion 11a and the second connection portion 12a.

[0037] Furthermore, the special rule that is expected to reduce the yield is applied only to the portion of the second connection portion 12a, so the risk of a reduction in the yield can be limited to this range.

[0038] As a result, the wiring board 10 of this embodiment can mount the semiconductor chip 20, in which the second electrode pads 22 are arranged at a pitch narrower than the first electrode pads 21, on the wiring board 10 with a high yield. In particular, this has an excellent effect when the first pitch P1 and the second pitch P2 are fine pitches of 45 μm to 85 μm. Furthermore, the semiconductor package 50 including the wiring board 10 of this embodiment can improve the strength of the joint between the columnar electrode and the FC pad, and can have good reliability.

[0039] (Embodiment 2) A wiring board 10 according to embodiment 2 will be described with reference to the drawings. The wiring board 10 of this embodiment differs from the wiring board according to embodiment 1 in the planar shape of the second connection portion 12b. The same reference numerals are used for the parts common to embodiment 1, and detailed description thereof will be omitted.

[0040] The second connection portion 12b of this embodiment has an oval shape as shown in FIG. 7. The second connection portion 12b includes a square portion 12b1 and semicircular portions 12b2 and 12b3 that contact two opposing sides of the square portion 12b1. The square portion 12b1 has two sides that contact the semicircular portions 12b2 and 12b3 each having a length of L21, and two other sides between the two sides that contact the semicircular portions 12b2 and 12b3 each having a length of L22a. The diameter of each of the semicircular portions 12b2 and 12b3 is L21. The area A22 of the second connection portion 12b of this embodiment is also the same as the area A1 of the first connection portion 11a.

[0041] When the dimensions of the columnar electrodes 23, 24 and the first connecting portion 11a are the same as those in the first embodiment, the dimensions of the second connecting portion 12b are determined as follows. If the second pitch P2 of the second electrode pads 22 is 65 μm and the length L21 is 50 μm, this is 10 μm larger than the diameter PD of the second columnar electrode 24, and the pad space D2 is 15 μm, which satisfies the special rule. As a result, L21 is determined to be 50 μm.

[0042] Next, by determining L21, the combined area of ​​semicircular portions 12b2 and 12b3 can be calculated. The combined area of ​​semicircular portions 12b2 and 12b3 is defined as AC2. The difference between the area A1 of the first connection portion and AC2 is calculated, and the length of the other side L22b of the rectangle is set to the numerical value of this difference. L22a = (A1 - AC2) ÷ L21 Using this formula, the length L22a of the rectangle is calculated. Specifically, L22a is calculated to be 17.28 μm. In this case, the length L22 of the second connection portion 12b in the longitudinal direction is 67.28 μm.

[0043] In this embodiment, by making the second connection portion 12b elliptical, when the length L21 in the short side direction (horizontal direction in FIG. 7) is the same as the length L11 in the short side direction of the second connection portion 12a in embodiment 1, the length L22 in the long side direction (vertical direction in FIG. 7) of the second connection portion 12b can be made larger than the length L12 in the long side direction of the second connection portion 12a in embodiment 1. Therefore, the length in the long side direction can be increased without changing the area of ​​the second connection portion 12b, and the risk of misalignment can be further reduced.

[0044] (Embodiment 3) The wiring board according to the third embodiment will be described with reference to the drawings. The wiring board of this embodiment differs from the wiring board described above in that the planar shape of the second connection portion is a chamfered shape. The same reference numerals are used for the parts common to the above-mentioned embodiments, and detailed description thereof will be omitted.

[0045] The second connection portion 12c of this embodiment has an octagonal planar shape as shown in Fig. 8. The second connection portion 12c has a rectangular shape with four corners chamfered. Specifically, the second connection portion 12c has a length L31 in the short direction (horizontal direction in Fig. 8) and a length L32 in the long direction (vertical direction in Fig. 8), and each of the four corners is chamfered into the same shape. Moreover, the area A23 of the second connection portion 12c of this embodiment is also the same as the area A1 of the first connection portion 11a.

[0046] L31, L32, L32a and L32b are determined, for example, as follows. First, the length of L31 is determined in the same manner as in the first embodiment. Next, in this embodiment, L32 is set to an arbitrary value. At this time, it is preferable to set L32 so as to satisfy the standard rule shown in the first embodiment. After setting L31 and L32, the areas of the triangles to be chamfered are determined from the following formula. L32a and L32b may be the same or different, but it is preferable that they are the same. 1 / 2×L32a×L32b=(L31×L32-A1)×1 / 4 For example, assuming that L31 is 50 μm as in the first embodiment, L32 is 60 μm, and L32a and L32b are the same, L32a is calculated to be 9.29 μm.

[0047] In this embodiment, L32 can be set to any dimension. It is also possible to align it with the standard rule. This allows an appropriate margin to be secured against misalignment. Also, since the area A23 of the second connection portion 12c is the same as that of the first connection portion 11a, it is possible to suppress the spread of the solder during mounting. In addition, by making the second connection portion 12c octagonal, the shape of the fillet can be made more uniform vertically and horizontally in a plan view, and it is also possible to further align it with the shape of the fillet on the first connection portion 11a.

[0048] (Embodiment 4) The wiring board according to the fourth embodiment will be described with reference to the drawings. The wiring board of this embodiment differs from the wiring board described above in that the planar shape of the second connection portion is a curved chamfered shape. The same reference numerals are used for the parts common to the above-mentioned embodiments, and detailed description will be omitted.

[0049] As shown in FIG. 9, the second connection portion 12d of this embodiment has a planar shape in which each corner of a rectangle is chamfered with a curve. Specifically, the second connection portion 12d has a length L41 in the short direction (horizontal direction in FIG. 9) and a length L42 in the long direction (vertical direction in FIG. 9), and each of the four corners is chamfered with a curve. The curves for chamfering the four corners may be different, but are preferably the same. For example, in this embodiment, the chamfering is performed by an arc with a radius L42a and an interior angle of 90°. The interior angle does not have to be 90°. The area A24 of the second connection portion 12d of this embodiment is also the same as the area A1 of the first connection portion 11a.

[0050] L41, L42 and L42a are determined as follows. First, the length of L41 is determined in the same manner as in the first embodiment. Next, in this embodiment, L42 is set to an arbitrary value. At this time, it is preferable to set L42 so as to satisfy the standard rules shown in the first embodiment. After L41 and L42 are set according to the design rules, the areas of the portions to be chamfered are determined according to the following formula. The curve to be chamfered is a circular arc with a radius of L42a and an interior angle of 90°. In this case, the square of L42a is found using the following formula, and L42a is found from the square root of the found value. L42a×L42a=(L41×L42-A1)÷(4-π) For example, if L41 is set to 50 μm as in the first embodiment, and L42 is set to 60 μm, L42a is calculated to be 14.18 μm.

[0051] In this embodiment, like the other embodiments described above, it is possible to suppress the spreading of the solder during mounting, and by using an arc-shaped R chamfer, it is possible to make the curved shape of the solder fillet when mounted even more gentle.

[0052] The present disclosure is not limited to the above-described embodiment, and various modifications and applications are possible.

[0053] In the above-described embodiments, the first electrode pads 21 and the second electrode pads 22 on the semiconductor chip 20 are arranged in one row along each side of the semiconductor chip 20, but the present invention is not limited to this. The arrangement of the electrode pads on the semiconductor chip 20 is arbitrary. For example, as shown in FIG. 10, two rows of electrode pads may be arranged on each side of the semiconductor chip 20. The number of rows arranged on each side may be arbitrary, and as shown in FIG. 11, two rows may be arranged on two sides and three rows may be arranged on one side. Furthermore, the electrode pads may be arranged on the entire main surface 20a of the semiconductor chip 20. The first wiring 11 and the second wiring 12 of the wiring board 10 are formed in accordance with the arrangement of the electrode pads of the semiconductor chip 20.

[0054] 10, the electrode pads arranged on the outside and the electrode pads arranged on the inside may be arranged in a so-called staggered arrangement, in which they are alternately shifted. In addition, the group including the second electrode pads 22 arranged at a fine pitch is not limited to being provided on the semiconductor chip 20 in one case, and multiple groups may be provided, and the arrangement may be arbitrary.

[0055] In the first to fourth embodiments, a configuration in which columnar electrodes are provided on the semiconductor chip 20 has been given as an example, but the method of bonding the semiconductor chip 20 and the wiring board 10 is not limited to this. For example, a configuration in which the columnar electrodes are omitted and bonding is performed using solder bumps having the same volume is also possible. In this case, the volume of the solder at the portion bonding the semiconductor chip 20 and the wiring board 10 increases, so that the bonding strength can be improved. In addition, the bump formation process can be further simplified, and the manufacturing period and / or manufacturing costs can be reduced.

[0056] In the above-mentioned embodiment, a multilayer board is used as an example, but the type of wiring board is not limited to this. The wiring board can be any printed board, such as a single-sided board, a double-sided board, a multilayer board, or a build-up board. The first wiring 11 and the second wiring 12 can be formed by any method, such as plating, or by forming a metal film and then removing a part of it by etching.

[0057] In the above-described embodiment, the first connection portion 11a is disposed at the tip of the first wiring 11, but the present invention is not limited to this. For example, the first connection portion 11a can be provided at any position on the first wiring 11, and the first wiring 11 may be provided so as to extend on both sides of the first connection portion 11a. The same applies to the second connection portion 12a. [Explanation of symbols]

[0058] 10 Wiring board (substrate) 10a,10b,20a Main surface 11 First Wire 11a First connection part 12 Second Wire 12a, 12b, 12c, 12d Second connection part 15 Internal wiring layer 16 wiring layer 17 Solder ball 20. Semiconductor Chips 21 First electrode pad 22 Second electrode pad 23 First columnar electrode 24 Second columnar electrode 25 First Solder 26 Second Solder 27 Protective film 27a aperture 50 Semiconductor Package

Claims

1. A wiring substrate for flip-chip mounting a semiconductor chip, a plurality of first wirings provided on one main surface of the wiring board; a plurality of second wirings provided on one main surface of the wiring board; the first wiring includes a first connection portion for connection to the semiconductor chip; the second wiring includes a second connection portion for connection to the semiconductor chip; the second connection portion has a planar shape different from that of the first connection portion, and an area of ​​the second connection portion is the same as an area of ​​the first connection portion; A wiring board, wherein the first connection portion is spaced apart from an adjacent first connection portion at a first pitch, and the second connection portion is spaced apart from an adjacent second connection portion at a second pitch that is smaller than the first pitch.

2. The wiring board according to claim 1 , wherein the first pitch and the second pitch are in the range of 40 μm to 85 μm.

3. 2. The wiring board according to claim 1, wherein the second connection portion has a planar shape of a rectangle, an oval, a chamfered rectangle, or a polygon.

4. A wiring board according to any one of claims 1 to 3, A semiconductor chip flip-chip mounted on the wiring substrate, The semiconductor chip comprises: a plurality of first electrode pads arranged at the first pitch; a plurality of second electrode pads arranged at the second pitch; a first electrode pad and a first connection portion of the wiring board are electrically connected by a first solder, and a second electrode pad and a second connection portion of the wiring board are electrically connected by a second solder having the same volume as the first solder.

5. The semiconductor chip comprises: a first columnar electrode formed on the first electrode pad; a second columnar electrode formed on the second electrode pad; the first solder and the second solder are provided on the first columnar electrode and the second columnar electrode, respectively; 5. The semiconductor package according to claim 4, wherein a diameter of the first columnar electrode is the same as a diameter of the second columnar electrode.

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