Nitride semiconductor device

Abstract

To suppress a fluctuation of a threshold voltage caused by a gate layer.SOLUTION: A nitride semiconductor device 10 includes an electron transit layer 16, an electron supply layer 18, a gate layer 30, a first gate electrode 51, a source electrode and a drain electrode, and a second gate electrode 52 formed of a material different from that of the first gate electrode 51. The first gate electrode 51 and the second gate electrode 52 are in contact with an upper surface 30a of the gate layer 30. A second contact area S2, which is a contact area between the second gate electrode 52 and the gate layer 30, is smaller than a first contact area S1, which is a contact area between the first gate electrode 51 and the gate layer 30.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter sometimes simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use two-dimensional electron gas (2DEG) formed near the interface of semiconductor heterojunctions as a conductive path (channel). Power devices using HEMTs are recognized as devices that enable lower on-resistance and higher speed / frequency operation compared to typical silicon (Si) power devices.

[0003] For example, the nitride semiconductor device described in Patent Document 1 includes an electron transit layer made of a gallium nitride (GaN) layer and an electron supply layer made of an aluminum gallium nitride (AlGaN) layer. A 2DEG is formed in the electron transit layer near the heterojunction interface between the electron transit layer and the electron supply layer.

[0004] In addition, in the nitride semiconductor device of Patent Document 1, a gate layer (e.g., a p-type GaN layer) containing acceptor-type impurities is provided on an electron supply layer, and a gate electrode is disposed on the gate layer. In this configuration, in the region directly below the gate layer, the gate layer raises the band energy of the conduction band in the vicinity of the heterojunction interface between the electron transit layer and the electron supply layer, thereby eliminating the channel directly below the gate layer, thereby realizing a normally-off state. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2017-73506 A Summary of the Invention [Problem to be solved by the invention]

[0006] As described above, in a nitride semiconductor device including a gate layer and a gate electrode formed on the gate layer, the threshold voltage may vary due to the gate layer. [Means for solving the problem]

[0007] A nitride semiconductor device according to one aspect of the present disclosure includes an electron transit layer made of a nitride semiconductor, an electron supply layer formed on the electron transit layer and made of a nitride semiconductor having a band gap larger than that of the electron transit layer, a gate layer formed on the electron supply layer and made of a nitride semiconductor containing acceptor-type impurities, a first gate electrode in contact with an upper surface of the gate layer, source and drain electrodes arranged to sandwich the gate layer and in contact with an upper surface of the electron supply layer, and a second gate electrode made of a material different from that of the first gate electrode and in contact with an upper surface of the gate layer, wherein a second contact area which is a contact area between the second gate electrode and the gate layer is smaller than a first contact area which is a contact area between the first gate electrode and the gate layer. Effect of the Invention

[0008] According to the nitride semiconductor device of the present disclosure, the variation in threshold voltage caused by the gate layer can be suppressed. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view taken along line 2-2 of FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view taken along line 3-3 in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view taken along line 2-2, showing an example of a method for manufacturing a nitride semiconductor device. [Diagram 5] FIG. 5 is a schematic cross-sectional view taken along line 3-3, showing an example of a method for manufacturing a nitride semiconductor device. [Figure 6] FIG. 6 is a schematic cross-sectional view taken along line 2-2 showing an example of a method for manufacturing a nitride semiconductor device subsequent to FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view taken along line 3-3 of FIG. 5 showing an example of a manufacturing method of a nitride semiconductor device. [Figure 8] FIG. 8 is a schematic cross-sectional view taken along line 2-2 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view taken along line 3-3 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view taken along line 2-2 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view taken along line 3-3 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view taken along line 2-2 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view taken along line 3-3 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Figure 14] FIG. 14 is an equivalent circuit diagram illustrating a nitride semiconductor device. [Figure 15] FIG. 15 is a schematic plan view showing a modification of the nitride semiconductor device of the first embodiment. [Figure 16] FIG. 16 is a schematic end view taken along line 16-16 of FIG. [Figure 17] FIG. 17 is a schematic end view taken along line 17-17 of FIG. [Figure 18] FIG. 18 is a schematic plan view showing a modification of the nitride semiconductor device of the first embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view taken along line 19-19 in FIG. [Figure 20] FIG. 20 is a schematic plan view of an illustrative nitride semiconductor device according to the second embodiment. [Figure 21] FIG. 21 is a schematic cross-sectional view taken along line 21-21 in FIG. [Figure 22] FIG. 22 is a schematic cross-sectional view taken along line 22-22 of FIG. [Diagram 23] FIG. 23 is a schematic cross-sectional view taken along line 21-21, showing one example of a method for manufacturing a nitride semiconductor device. [Figure 24] FIG. 24 is a schematic cross-sectional view taken along line 22-22, showing one example of a method for manufacturing a nitride semiconductor device. [Diagram 25] FIG. 25 is a schematic cross-sectional view taken along line 21-21 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Figure 26] FIG. 26 is a schematic cross-sectional view taken along line 22-22 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Figure 27] FIG. 27 is a schematic cross-sectional view taken along line 21-21 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Figure 28] FIG. 28 is a schematic cross-sectional view taken along line 22-22 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Figure 29] FIG. 29 is a schematic cross-sectional view taken along line 21-21 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Diagram 30] FIG. 30 is a schematic cross-sectional view taken along line 22-22 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Diagram 31] FIG. 31 is a schematic cross-sectional view taken along line 21-21 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Diagram 32] FIG. 32 is a schematic cross-sectional view taken along line 22-22 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Diagram 33] FIG. 33 is a schematic cross-sectional view taken along line 21-21 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Diagram 34] FIG. 34 is a schematic cross-sectional view taken along line 22-22 showing an example of a manufacturing method of a nitride semiconductor device subsequent to FIG. [Diagram 35] FIG. 35 is a schematic plan view showing a modification of the nitride semiconductor device of the second embodiment. [Diagram 36] FIG. 36 is a schematic end view taken along line 36-36 of FIG. [Figure 37] FIG. 37 is a schematic end view taken along line 37-37 of FIG. [Figure 38] FIG. 38 is a schematic cross-sectional view illustrating an example of a modification of the gate layer. [Figure 39] FIG. 39 is a schematic cross-sectional view illustrating an example of a modification of the recess region. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, embodiments of a nitride semiconductor device according to the present disclosure will be described with reference to the accompanying drawings. For simplicity and clarity of description, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0011] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0012] [First embodiment] Fig. 1 is a schematic plan view of an illustrative nitride semiconductor device 10 according to the first embodiment. Fig. 2 is a schematic cross-sectional view taken along line 2-2 in Fig. 1. Fig. 3 is a schematic cross-sectional view taken along line 3-3 in Fig. 1. As an example of the nitride semiconductor device 10, a HEMT using GaN will be described.

[0013] [Schematic Structure of Nitride Semiconductor Device 10] 2, the nitride semiconductor device 10 includes a semiconductor substrate 12, a buffer layer 14 formed on the semiconductor substrate 12, and an electron transit layer 16 formed on the buffer layer 14. The nitride semiconductor device 10 includes an electron supply layer 18 formed on the electron transit layer 16, and a gate layer 30 formed on the electron supply layer 18.

[0014] The semiconductor substrate 12 may be formed of Si (silicon), SiC (silicon carbide), GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 12 may be a conductive Si substrate. The thickness of the semiconductor substrate 12 may be, for example, 200 μm or more and 1500 μm or less. The Z-axis direction of the mutually orthogonal XYZ axes is the thickness direction of the semiconductor substrate 12. Note that the term "planar view" used in this specification refers to viewing the nitride semiconductor device 10 from above along the Z-axis direction, unless explicitly stated otherwise.

[0015] The buffer layer 14 may be located between the semiconductor substrate 12 and the electron transport layer 16. The buffer layer 14 may be formed of any material that can reduce the lattice mismatch between the semiconductor substrate 12 and the electron transport layer 16. In one example, the buffer layer 14 may be composed of any material that can facilitate epitaxial growth of the electron transport layer 16.

[0016] The buffer layer 14 may include one or more nitride semiconductor layers. In one example, the buffer layer 14 may include at least one of an AlN (aluminum nitride) layer, an AlGaN (aluminum gallium nitride) layer, and a graded AlGaN layer having different Al (aluminum) compositions. For example, the buffer layer 14 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, a layer having an AlN / GaN superlattice structure, or a combination of multiple of the five layers described above.

[0017] In one example, buffer layer 14 may include a first buffer layer formed on semiconductor substrate 12 and a second buffer layer formed on the first buffer layer. The first buffer layer may be, for example, an AlN layer having a thickness of 200 nm. The second buffer layer may be, for example, multiple AlGaN layers each having a thickness of 100 nm.

[0018] In order to suppress the leakage current in the buffer layer 14, impurities may be introduced into a part of the buffer layer 14 to make the buffer layer 14 semi-insulating. In that case, the impurities are, for example, carbon (C) or iron (Fe), and the concentration of the impurities is, for example, 4×10 16 cm -3 or more.

[0019] The electron transport layer 16 is composed of a nitride semiconductor. The electron transport layer 16 is, for example, a GaN layer. The thickness of the electron transport layer 16 is, for example, 0.1 μm or more and 2 μm or less. In order to suppress the leakage current in the electron transport layer 16, impurities may be introduced into a part of the electron transport layer 16 to make the region other than the surface layer region of the electron transport layer 16 semi-insulating. In that case, the impurities are, for example, C, and the peak concentration of the impurities in the electron transport layer 16 is, for example, 1×10 19 cm -3 or more.

[0020] The electron supply layer 18 is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 16. The electron supply layer 18 is, for example, an AlGaN layer. In this case, since the larger the Al composition, the larger the bandgap, the electron supply layer 18 which is an AlGaN layer has a larger bandgap than the electron transport layer 16 which is a GaN layer. In one example, the electron supply layer 18 is composed of Al x Ga 1-x N, where x is 0.1 < x < 0.4, and more preferably, 0.2 < x < 0.3. However, it is not necessarily limited to this range. The thickness of the electron supply layer 18 is, for example, 5 nm or more and 20 nm or less.

[0021] The electron transit layer 16 and the electron supply layer 18 are made of nitride semiconductors having different lattice constants. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transit layer 16 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 18 form a lattice-mismatched heterojunction. The energy level of the conduction band of the electron transit layer 16 near the heterojunction interface is lower than the Fermi level due to spontaneous polarization of the electron transit layer 16 and the electron supply layer 18 and piezoelectric polarization caused by stress applied to the electron supply layer 18 near the heterojunction interface. As a result, a two-dimensional electron gas (2DEG) spreads in the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 (for example, within a range of about several nm from the interface).

[0022] As shown in FIGS. 1 to 3, the electron transit layer 16 and the electron supply layer 18 include an active region 21 where 2DEG occurs, and an inactive region 22 that is disposed around the active region 21 and where 2DEG is less likely to occur.

[0023] 1, the active region 21 is formed, for example, in a rectangular shape in a plan view. In detail, the active region 21 is rectangular with one side in the X-axis direction and the other side in the Y-axis direction. However, the planar shape of the active region 21 is not limited to this, and may be a trapezoid, an oval, a circle, or any other shape.

[0024] Impurities that make it difficult for 2DEG to occur are introduced into the inactive region 22. The impurities are different from acceptor-type impurities contained in the gate layer 30, which will be described later. The impurities may be, for example, relatively light elements. Examples of the impurities include He, B, N, O, F, and Ar. The impurities that make it difficult for 2DEG to occur can also be said to be impurities that inhibit the occurrence of 2DEG.

[0025] The resistance value of the inactive region 22 is higher than the resistance value of the active region 21. In this embodiment, the above-mentioned impurities are introduced into the inactive region 22, so that the resistance value of the inactive region 22 is higher than the resistance value of the active region 21. In other words, the inactive region 22 is a region having a higher resistance value than the active region 21.

[0026] The inactive regions 22 are formed so as to surround the active region 21. That is, the inactive regions 22 are arranged on both sides of the active region 21 in the X-axis direction and on both sides of the active region 21 in the Y-axis direction.

[0027] The gate layer 30 is made of a nitride semiconductor having a band gap smaller than that of the electron supply layer 18. For example, when the electron supply layer 18 is an AlGaN layer, the gate layer 30 may be a GaN layer containing acceptor-type impurities. The acceptor-type impurities may contain at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor-type impurities in the gate layer 30 is, for example, 7×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0028] In this embodiment, the acceptor-type impurities contained in the gate layer 30 are different from the impurities introduced into the inactive region 22, specifically, the impurities for making it difficult for the 2DEG to occur.

[0029] As described above, the gate layer 30 contains acceptor-type impurities, which raises the energy levels of the electron transit layer 16 and the electron supply layer 18. Therefore, in the region immediately below the gate layer 30, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. Therefore, at zero bias when no voltage is applied to the gate (specifically, the first gate electrode 51), no 2DEG is formed in the electron transit layer 16 in the region immediately below the gate layer 30. On the other hand, a 2DEG is formed in the electron transit layer 16 in the active region 21 other than the region immediately below the gate layer 30.

[0030] In this manner, the presence of the gate layer 30 doped with acceptor-type impurities causes the 2DEG to disappear in the region directly below the gate layer 30. As a result, a normally-off operation of the transistor is achieved.

[0031] The thickness of the gate layer 30 is not particularly limited, and may be appropriately determined in consideration of the gate breakdown voltage, etc. For example, the thickness of the gate layer 30 may be 50 nm or more and 150 nm or less. In addition, the cross-sectional shape of the gate layer 30 along the ZX plane in FIG. 2 is not particularly limited, and may be, for example, a rectangular shape, a trapezoidal shape, a ridge shape, or any other shape.

[0032] As shown in FIG. 1, in this embodiment, the gate layer 30 is disposed so as to straddle both the active region 21 and the inactive region 22. In detail, the gate layer 30 extends in the Y-axis direction so as to transversely cross the active region 21. The gate layer 30 also has a wide portion having a relatively wide width in the X-axis direction and a narrow portion having a narrower width than the wide portion. The wide portion is located at the end of the gate layer 30 in the Y-axis direction. The wide portion is provided on the inactive region 22. The narrow portions extend from the wide portion in the Y-axis direction and are disposed in the active region 21 and on both sides of the active region 21 in the Y direction. In this case, it can be said that the active region 21 is divided into two regions by the gate layer 30.

[0033] The gate layer 30 comprises a first part 31 formed on the active area 21 and a second part 32 formed on the inactive area 22 . As already described, the first part 31 extends in the Y-axis direction so as to transversely cross the active region 21. In this embodiment, acceptor-type impurities are introduced into the first part 31, but impurities that make it difficult for 2DEG to be generated are not introduced.

[0034] The second part 32 is provided on both sides in the Y-axis direction of the first part 31. In the second part 32 of the present embodiment, both an acceptor-type impurity and an impurity for making it difficult for 2DEG to occur are introduced.

[0035] The nitride semiconductor device 10 includes a source electrode 41 and a drain electrode 42 in contact with the upper surface 18a of the electron supply layer 18. The source electrode 41 and the drain electrode 42 are made of the same material. For example, the source electrode 41 and the drain electrode 42 may be made of one or more metal layers. As an example, the source electrode 41 and the drain electrode 42 may be made of one or a combination of two or more metal layers selected from the group including a Ti layer, a Pd layer, a Ni layer, a TiN layer, an Al layer, an AlSiCu layer, an AlCu layer, and the like.

[0036] The source electrode 41 and the drain electrode 42 may be in ohmic contact with the electron supply layer 18. In other words, the source electrode 41 and the drain electrode 42 may be made of a material that is in ohmic contact with the electron supply layer 18.

[0037] The source electrode 41 and the drain electrode 42 are arranged to sandwich the gate layer 30. In detail, the source electrode 41 and the drain electrode 42 are arranged on both sides in the X-axis direction of the first part 31 in the active region 21. Therefore, the gate layer 30 is interposed between the source electrode 41 and the drain electrode 42 in the active region 21. In other words, the source electrode 41 and the drain electrode 42 are arranged in two regions divided by the gate layer 30.

[0038] The distance in the X-axis direction between the drain electrode 42 and the gate layer 30 may be set to be longer than the distance in the X-axis direction between the source electrode 41 and the gate layer 30. However, both distances are arbitrary and may be the same, for example.

[0039] [First gate electrode and second gate electrode] As shown in FIGS. 1 to 3, the nitride semiconductor device 10 includes a first gate electrode 51 and a second gate electrode 52 in contact with the upper surface 30a of the gate layer 30. As shown in FIG.

[0040] The first gate electrode 51 is configured to form a Schottky junction with, for example, the gate layer 30. In detail, the first gate electrode 51 is made of a material that easily forms a Schottky junction with the gate layer 30. For example, the first gate electrode 51 may be made of TiN, TaN, WN, TiSiN, TaSiN, WSi, WSiN, or the like.

[0041] At least a portion of the first gate electrode 51 is formed on the first part 31. In this embodiment, the first gate electrode 51 is formed on almost the entire area of ​​the gate layer 30. The first gate electrode 51 is formed across both the first part 31 located on the active region 21 and the second part 32 located on the inactive region 22. Therefore, the first gate electrode 51 is formed across both the active region 21 and the inactive region 22. In addition, the first gate electrode 51 extends in the Y-axis direction and cuts across the active region 21 so as to be interposed between the source electrode 41 and the drain electrode 42 in the active region 21.

[0042] According to this configuration, when an appropriate on-voltage is applied to the first gate electrode 51, a channel is formed by the 2DEG in the electron transit layer 16 in the region directly below the first gate electrode 51. This provides electrical continuity between the source and the drain.

[0043] The second gate electrode 52 is made of a material different from that of the first gate electrode 51. For example, the second gate electrode 52 is made of a material having a larger work function than the first gate electrode 51. That is, the second gate electrode 52 may be configured so that the Schottky barrier between the second gate electrode 52 and the gate layer 30 is smaller than the Schottky barrier between the first gate electrode 51 and the gate layer 30. Alternatively, the second gate electrode 52 may be configured of a material that easily makes ohmic contact with the gate layer 30. As an example, the second gate electrode 52 may include any one of Ti, Pd, and Ni.

[0044] In this embodiment, the second gate electrode 52 is made of the same material as the source electrode 41 and the drain electrode 42. For example, the second gate electrode 52, the source electrode 41, and the drain electrode 42 may be made of Ti / Al. However, the present invention is not limited to this, and the second gate electrode 52, the source electrode 41, and the drain electrode 42 may be made of different materials.

[0045] As shown in FIG. 3, the second gate electrode 52 is in contact with the gate layer 30. In detail, an opening 60 that exposes the gate layer 30 is formed in the first gate electrode 51. In this embodiment, the opening 60 is formed in a portion of the first gate electrode 51 that is above the inactive region 22. The opening 60 exposes a part of the gate layer 30, specifically, the second part 32. The second gate electrode 52 is in contact with the gate layer 30 through the opening 60. This electrically connects the second gate electrode 52 and the gate layer 30.

[0046] In this embodiment, the second gate electrode 52 is formed on the second part 32. In detail, the second gate electrode 52 is disposed on the inactive region 22 and is in contact with the second part 32.

[0047] The second gate electrode 52 includes a buried portion 52a buried in the opening 60 and an overlapping portion 52b. The embedded portion 52a is in contact with the gate layer 30 (the second part 32 in this embodiment). The embedded portion 52a is surrounded by the first gate electrode 51 in a plan view. The embedded portion 52a is in contact with a side surface 60a of the opening 60. For example, the embedded portion 52a is in contact with the first gate electrode 51 over the entire periphery in a plan view. In this embodiment, the shape of the opening 60 and the embedded portion 52a in a plan view is square. However, this is not limited thereto, and the planar shape of the opening 60 and the embedded portion 52a is arbitrary, and may be, for example, a rectangular shape having long sides and short sides, or a circular shape.

[0048] The overlapping portion 52b is formed to be slightly larger than the buried portion 52a in a plan view, and protrudes laterally beyond the opening 60. The overlapping portion 52b contacts the upper surface 51a of the first gate electrode 51, more specifically, the peripheral portion of the opening 60 in the first gate electrode 51. This increases the contact area between the first gate electrode 51 and the second gate electrode 52.

[0049] Here, the contact area between the first gate electrode 51 and the gate layer 30 is referred to as a first contact area S1, and the contact area between the second gate electrode 52 and the gate layer 30 is referred to as a second contact area S2. The second contact area S2 is smaller than the first contact area S1. For example, the second contact area S2 may be 1 / 100 or less of the first contact area S1.

[0050] Next, a method for manufacturing the nitride semiconductor device 10 of this embodiment will be described with reference to Figures 4 to 13. Figures 4, 6, 8, 10 and 12 are schematic cross-sectional views of each step taken along line 2-2, and Figures 5, 7, 9, 11 and 13 are schematic cross-sectional views of each step taken along line 3-3.

[0051] 4 and 5, the method for manufacturing the nitride semiconductor device 10 includes a process for forming a buffer layer 14, an electron transit layer 16, an electron supply layer 18, and a gate layer 30 on a semiconductor substrate 12. This process uses epitaxial growth by, for example, MOCVD (Metal Organic Chemical Vapor Deposition). In this process, the gate layer 30 is formed on the entire upper surface 18a of the electron supply layer 18, regardless of the active region 21 and the inactive region 22.

[0052] As shown in FIG. 6 and FIG. 7, the method for manufacturing the nitride semiconductor device 10 next includes a step of forming the inactive region 22. In detail, the step includes a step of forming a resist as a mask only in the active region 21, and a step of ion-implanting an impurity for making it difficult for a 2DEG to occur in both the active region 21 and the inactive region 22. As a result, the impurity is introduced into the inactive region 22 where the resist is not formed. In detail, the impurity is introduced into the gate layer 30 in the inactive region 22. As a result, the second part 32 is formed. The impurity is introduced into the electron supply layer 18 and the electron transit layer 16 through the gate layer 30. The impurity may or may not be introduced into a part of the buffer layer 14. On the other hand, the impurity is not introduced into the gate layer 30, the electron supply layer 18, and the electron transit layer 16 in the active region 21 where the resist is formed.

[0053] 8 and 9, the method for manufacturing the nitride semiconductor device 10 includes a step of etching the gate layer 30. As a result, the gate layer 30 having the shape shown in FIG.

[0054] 10 and 11, the method for manufacturing the nitride semiconductor device 10 includes a step of forming a first gate electrode 51 on the gate layer 30. This step may be a step of forming the first gate electrode 51 over the entire surface by, for example, sputtering, and then etching only the necessary portions using a resist. In this case, it is preferable not to provide a resist at a portion corresponding to the opening 60 so that the opening 60 is formed during etching.

[0055] 12 and 13, the manufacturing method of the nitride semiconductor device 10 includes the steps of forming the source electrode 41, the drain electrode 42, and the second gate electrode 52. In this embodiment, the source electrode 41, the drain electrode 42, and the second gate electrode 52 may be formed simultaneously. In particular, the second gate electrode 52 may be formed on the entire surface, and then etched using a resist to leave only the portions corresponding to the source electrode 41, the drain electrode 42, and the second gate electrode 52. In this case, the source electrode 41, the drain electrode 42, and the second gate electrode 52 are made of the same material (for example, Ti / Al).

[0056] However, the present invention is not limited to this, and the step of forming the source electrode 41 and the drain electrode 42 may be separate steps from the step of forming the second gate electrode 52. In this case, the second gate electrode 52 can be made of a material (e.g., Ni or Pd) different from that of the source electrode 41 and the drain electrode 42.

[0057] Next, the operation of this embodiment will be described with reference to Fig. 14. Fig. 14 is a schematic equivalent circuit diagram of the periphery of the gate layer 30 in the nitride semiconductor device 10 of this embodiment. As shown in FIG. 14, the nitride semiconductor device 10 includes a gate layer resistance R1 which is a resistance component of the gate layer 30, a Schottky barrier diode D1, and a pin diode D2.

[0058] The Schottky barrier diode D1 is formed by the gate layer 30 and the first gate electrode 51. A gate voltage is applied to the gate layer resistance R1 via the Schottky barrier diode D1. The pin diode D2 is formed by a 2DEG of the gate layer 30 / electron supply layer 18 / electron transit layer 16. The pin diode D2 is provided between the gate layer resistance R1 and the source electrode 41 and drain electrode 42.

[0059] That is, the gate layer 30 is electrically sandwiched between the Schottky barrier diode D1 and the pin diode D2. In this case, when a voltage is applied between the gate and source or between the gate and drain, holes are discharged or accumulated in the gate layer 30. Even if the applied voltage is subsequently removed, the gate layer 30 is sandwiched between the barriers of the Schottky barrier diode D1 and the pin diode D2, so that the potential of the gate layer 30 becomes unstable as a floating state. As a result, it takes time for the discharged or accumulated holes to return to their original state, so that the threshold voltage fluctuates with time. If the threshold voltage fluctuates in the negative direction, it becomes easy for the device to be erroneously turned on by noise. On the other hand, if the threshold voltage fluctuates in the positive direction, the on-resistance increases, and power loss may increase.

[0060] In this regard, in the present embodiment, a second gate electrode 52 is provided separately from the first gate electrode 51. The second gate electrode 52 is made of a material having a larger work function than the first gate electrode 51. As an example, the second gate electrode 52 is configured to be in ohmic contact with the gate layer 30. As a result, it can be said that the nitride semiconductor device 10 includes a second gate resistor R2 provided separately from the Schottky barrier diode D1 between the gate layer resistor R1 and the gate. This makes it easier for holes to flow in and out of the gate layer 30 from the second gate electrode 52. Therefore, the potential of the gate layer 30 is stabilized, and the threshold voltage is less likely to fluctuate.

[0061] For example, when a negative voltage is applied to the first gate electrode 51, the Schottky barrier diode D1 is applied in the forward direction, so that holes in the gate layer 30 are emitted from the gate layer 30. On the other hand, holes enter the gate layer 30 via the second gate electrode 52, so that the emitted holes are immediately restored. Therefore, the fluctuation of the threshold voltage caused by the gate layer 30 is suppressed.

[0062] Incidentally, in this embodiment, the Schottky barrier between the second gate electrode 52 and the gate layer 30 is smaller than the Schottky barrier between the first gate electrode 51 and the gate layer 30. In this case, there is a concern that the gate leakage current through the second gate electrode 52 will become large.

[0063] In this regard, in the present embodiment, since the second contact area S2 is smaller than the first contact area S1, the second gate resistance R2 tends to be large, and therefore the gate leakage current through the second gate electrode 52 is small.

[0064] In this embodiment, the second gate electrode 52 is formed on the inactive region 22. In particular, the second gate electrode 52 is formed on the second part 32 on the inactive region 22. As a result, the area directly below the second gate electrode 52 is a high-resistance area. Therefore, it can be said that the second gate electrode 52 is electrically connected to the source and drain via the inactive resistor R3, not the pin diode D2. The inactive resistor R3 reduces the current flowing from the second gate electrode 52 to the source or drain. As a result, the gate leakage current caused by the second gate electrode 52 is reduced.

[0065] According to the present embodiment described above in detail, the following effects are achieved. (1-1) The nitride semiconductor device 10 includes an electron transit layer 16, an electron supply layer 18, a gate layer 30, a first gate electrode 51, a source electrode 41, and a drain electrode 42. The electron transit layer 16 is made of a nitride semiconductor. The electron supply layer 18 is formed on the electron transit layer 16 and is made of a nitride semiconductor having a larger band gap than the electron transit layer 16. The gate layer 30 is formed on the electron supply layer 18 and is made of a nitride semiconductor containing an acceptor-type impurity. The first gate electrode 51 is in contact with an upper surface 30a of the gate layer 30. The source electrode 41 and the drain electrode 42 are disposed to sandwich the gate layer 30, and are in contact with an upper surface 18a of the electron supply layer 18.

[0066] In this configuration, the nitride semiconductor device 10 includes a second gate electrode 52 made of a material different from that of the first gate electrode 51. The second gate electrode 52 is in contact with an upper surface 30a of the gate layer 30. A second contact area S2, which is a contact area between the second gate electrode 52 and the gate layer 30, is smaller than a first contact area S1, which is a contact area between the first gate electrode 51 and the gate layer 30.

[0067] According to this configuration, holes can be accumulated or released in the gate layer 30 via the second gate electrode 52, so that the potential of the gate layer 30 can be stabilized. This makes it possible to suppress the variation in threshold voltage caused by the gate layer 30. In addition, since the second contact area S2 is smaller than the first contact area S1, it is possible to suppress the gate leakage current through the second gate electrode 52. Therefore, it is possible to suppress the variation in threshold voltage caused by the gate layer 30 while suppressing the gate leakage current from increasing.

[0068] (1-2) The second gate electrode 52 may be made of a material having a larger work function than the first gate electrode 51. For example, the second gate electrode 52 may contain any of Ti, Pd, and Ni.

[0069] According to this configuration, the Schottky barrier between the second gate electrode 52 and the gate layer 30 tends to be smaller than the Schottky barrier between the first gate electrode 51 and the gate layer 30. This facilitates the exchange of holes via the second gate electrode 52. Therefore, the effect of (1-1) is achieved.

[0070] (1-3) The second gate electrode 52 may be configured to form an ohmic junction with the gate layer 30. This configuration facilitates smooth exchange of holes between the second gate electrode 52 and the gate layer 30. This makes it possible to more suitably achieve the effect of (1-1).

[0071] (1-4) The second gate electrode 52 may be made of the same material as the source electrode 41 and the drain electrode 42. According to this configuration, the second gate electrode 52 can be formed simultaneously with the source electrode 41 and the drain electrode 42. This makes it possible to suppress an increase in the number of manufacturing steps due to the provision of the second gate electrode 52.

[0072] (1-5) The second contact area S2 may be 1 / 100 or less of the first contact area S1, thereby making it possible to more effectively suppress the gate leakage current. (1-6) The first gate electrode 51 is configured to form a Schottky junction with the gate layer 30.

[0073] According to this configuration, the first gate electrode 51 and the gate layer 30 form a Schottky barrier diode D1. When a forward voltage is applied to the first gate electrode 51, a reverse bias is applied to the Schottky barrier diode D1, and the gate layer 30 is depleted. This allows the diode to operate like an insulated gate, thereby reducing the gate leakage current. Therefore, for example, a gate drive circuit similar to that of a MOSFET may be used as a circuit for driving the nitride semiconductor device 10.

[0074] On the other hand, when the Schottky barrier diode D1 is formed, as described above, unintended accumulation or release of holes becomes more likely, which may cause the potential to become unstable. In this regard, in the present embodiment, as described above, the second gate electrode 52 is provided separately from the first gate electrode 51, so that even if the first gate electrode 51 is Schottky junctioned with the gate layer 30 as described above, the fluctuation in threshold voltage caused by the gate layer 30 can be suppressed.

[0075] (1-7) The first gate electrode 51 includes any one of TiN, TaN, WN, TiSiN, TaSiN, WSi, and WSiN. According to this configuration, by using the above-mentioned material for the first gate electrode 51, a Schottky junction is easily formed between the first gate electrode 51 and the gate layer 30.

[0076] Furthermore, TiN, TaN, WN, TiSiN, TaSiN, WSi, and WSiN are materials that are easy to microfabricate by etching, so that the first gate electrode 51 and the opening 60 can be formed with high precision.

[0077] (1-8) The electron transit layer 16 and the electron supply layer 18 include an active region 21 in which 2DEG occurs, and an inactive region 22 in which 2DEG is less likely to occur than in the active region 21. The gate layer 30 includes a first part 31 formed on the active region 21, and a second part 32 formed on the inactive region 22. At least a portion of the first gate electrode 51 is formed on the first part 31. The second gate electrode 52 is formed on the second part 32.

[0078] According to this configuration, the inactive region 22 exists directly under the second gate electrode 52. The inactive region 22 is a region having a higher resistance value than the active region 21. This makes it possible to suppress the gate current that flows directly from the second gate electrode 52 to the source electrode 41 or the drain electrode 42 without passing through the gate layer 30. Therefore, it is possible to suppress the gate leakage current caused by providing the second gate electrode 52.

[0079] (1-9) The inactive region 22 contains impurities that make it difficult for 2DEG to occur. With this configuration, the inactive region 22 can be realized by ion-implanting the impurities. Moreover, increasing the resistance by introducing such impurities makes it easier to maintain the flatness of the electron supply layer 18 and the like, compared to a method of increasing the resistance by removing the 2DEG occurrence region by mesa-shaped etching. Therefore, it is suitable for integration.

[0080] (1-10) The impurity for making it difficult for 2DEG to occur includes any of He, B, N, O, F, and Ar. According to this configuration, a relatively light element is used as the impurity for making it difficult for 2DEG to occur. As a result, ion implantation from above can reach the depth of the 2DEG, making it possible to form the inactive region 22 by making the 2DEG highly resistive.

[0081] In particular, when O, F, or Ar is used as an impurity to make it difficult for 2DEG to occur, divalent ions of O, F, or Ar may be used. This makes it possible to substantially double the acceleration voltage for ion implantation, and to introduce ions into deep regions.

[0082] (1-11) The first gate electrode 51 has an opening 60 that exposes the gate layer 30. The second gate electrode 52 has a buried portion 52a buried in the opening 60. The buried portion 52a is in contact with the gate layer 30.

[0083] According to this configuration, the buried portion 52a is surrounded by the first gate electrode 51. This makes it easier for the depletion layer from the first gate electrode 51 to extend in the planar direction and to spread to the region directly below the buried portion 52a. This reduces the gate current from the second gate electrode 52. This makes it possible to suppress the gate leakage current.

[0084] (1-12) The buried portion 52a is in contact with a side surface 60a of the opening 60 in the first gate electrode 51. The second gate electrode 52 includes an overlapping portion 52b formed to be wider than the opening 60 in a plan view. The overlapping portion 52b is in contact with an upper surface 51a of the first gate electrode 51.

[0085] According to this configuration, the overlap portion 52b increases the contact area between the first gate electrode 51 and the second gate electrode 52. This makes it possible to reduce the contact resistance between the first gate electrode 51 and the second gate electrode 52 without providing a separate wiring that electrically connects the first gate electrode 51 and the second gate electrode 52.

[0086] In particular, if the opening 60 is enlarged in order to increase the contact area between the gate electrodes 51, 52, the second contact area S2 increases, and there is a concern that the gate leakage current will increase. In this regard, according to the present embodiment, the overlapping portion 52b is provided, so that the contact area between the gate electrodes 51, 52 can be increased without increasing the opening 60. Therefore, the contact area between the gate electrodes 51, 52 can be increased while suppressing an increase in the gate leakage current.

[0087] [Modification of the first embodiment] A modification of the first embodiment will be described with reference to Fig. 15 to Fig. 17. Fig. 15 is a schematic plan view of an illustrative nitride semiconductor device 100 according to a modification of the first embodiment. Fig. 16 is a schematic end view taken along line 16-16 in Fig. 15. Fig. 17 is a schematic end view taken along line 17-17 in Fig. 15.

[0088] As shown in Figures 15 and 16, in this modified example, a nitride semiconductor device 100 includes a source electrode 101 provided in an active region 21, and two drain electrodes 102, 103 provided on both sides of the source electrode 101 in the X-axis direction.

[0089] In this modified example, the gate layer 104 and the first gate electrode 105 are formed in a frame shape surrounding the source electrode 101. Therefore, the source electrode 101 is disposed within the frame of the gate layer 104 and the first gate electrode 105. On the other hand, the drain electrodes 102 and 103 are disposed outside the gate layer 104 and the first gate electrode 105.

[0090] In this modification, it can be said that two transistor cells are configured in the active region 21. That is, the gate layer 104 and the first gate electrode 105 have a first gate portion 106 interposed between the source electrode 101 and the first drain electrode 102, and a second gate portion 107 interposed between the source electrode 101 and the second drain electrode 103. It can also be said that the source electrode 101, the first drain electrode 102, and the first gate portion 106 configure a first transistor cell, and the source electrode 101, the second drain electrode 103, and the second gate portion 107 configure a second transistor cell. This allows the nitride semiconductor device 100 to be highly integrated.

[0091] In this modification, the gate layer 104 and the first gate electrode 105 are formed across both the active region 21 and the inactive region 22. In particular, in this modification, the gate layer 104 and the first gate electrode 105 are formed so as to overlap the boundary between the active region 21 and the inactive region 22. In detail, the gate layer 104 and the first gate electrode 105 include a first connecting portion 108 connecting first ends of both gate portions 106, 107, and a second connecting portion 109 connecting second ends of both gate portions 106, 107. Both connecting portions 108, 109 are disposed at positions so as to overlap the boundary between the active region 21 and the inactive region 22.

[0092] 15 and 17, an opening 60 is formed in the first gate electrode 105. As in the first embodiment, the opening 60 is formed in a position corresponding to the inactive region 22, more specifically, in a portion of the first gate electrode 105 above the inactive region 22. The second gate electrode 52 contacts the upper surface of the gate layer 104 (more specifically, the second part 32) through the opening 60.

[0093] In this modification, one opening 60 and one second gate electrode 52 are provided. That is, one second gate electrode 52 is shared by two transistor cells. This simplifies the configuration compared to a configuration in which a second gate electrode 52 is provided for each transistor cell. Also, the ratio of the second contact area S2 to the first contact area S1 can be made smaller, thereby suppressing the gate leakage current.

[0094] Although the opening 60 and the second gate electrode 52 are provided in the second connecting portion 109, this is not limited to this and they may be provided in the first connecting portion 108, or they may be provided in both connecting portions 108, 109.

[0095] According to the modified example described above in detail, the following effects are achieved. (1-13) The gate layer 104 is formed in a frame shape surrounding the source electrode 101, and the drain electrodes 102 and 103 are disposed outside the gate layer 104. This makes it possible to suppress leakage current from the drain electrodes 102 and 103 to the source electrode 101.

[0096] (1-14) The gate layer 104 is disposed at a position overlapping the boundary between the active region 21 and the inactive region 22. This makes it possible to suppress leakage current flowing from the drain electrodes 102 and 103 to the source electrode 101 via the boundary.

[0097] [Wiring structure in modified example of the first embodiment] 18 and 19, the nitride semiconductor device 100 may include a passivation film 110 covering the first gate electrode 105 and the second gate electrode 52, and wirings 111, 112, and 113 formed on the passivation film 110. The nitride semiconductor device 100 may include vias 121, 122, and 123 that are holes penetrating the passivation film 110, and plugs 131, 132, and 133 embedded in the vias 121, 122, and 123.

[0098] The passivation film 110 has insulating properties and may be made of, for example, SiN or SiO, or an organic material such as polyimide. The wirings 111, 112, and 113 are composed of, for example, a gate wiring 111, a drain wiring 112, and a source wiring 113. The wirings 111, 112, and 113 are arranged at a distance from each other and are insulated from each other. As an example, the wirings 111, 112, and 113 are arranged in the Y-axis direction. For example, the gate wiring 111 is disposed above the second gate electrode 52. The drain wiring 112 is disposed above both drain electrodes 102 and 103. The source wiring 113 is disposed above the source electrode 101. The drain wiring 112 and the source wiring 113 are disposed at positions overlapping the source electrode 101 and both drain electrodes 102 and 103 and shifted from each other in the Y-axis direction.

[0099] The wirings 111, 112, and 113 are made of the same material. For example, the wirings 111, 112, and 113 may be made of Al, AlCu, or Cu. This can reduce the wiring resistance.

[0100] The gate via 121 is disposed on the second gate electrode 52, and is a hole penetrating the passivation film 110 in the thickness direction (in other words, the Z-axis direction) in order to electrically connect the second gate electrode 52 and the gate wiring 111. In other words, the gate via 121 is used to penetrate the passivation film 110 and electrically connect the second gate electrode 52 and the gate wiring 111. The gate via 121 may be formed smaller than the second gate electrode 52 in a plan view, for example, and may be entirely contained within the second gate electrode 52.

[0101] Incidentally, the second gate electrode 52 may be made of Ti, Pd or Ni. In this case, the second gate electrode 52 can be prevented from becoming thin when the gate via 121 is formed. In detail, when the gate via 121 is formed, the passivation film 110 may be dry-etched. In this case, there is a concern that a part of the second gate electrode 52 may also be etched by dry etching. In this regard, when Ti, Pd or Ni is used as the second gate electrode 52, the second gate electrode 52 is relatively less susceptible to dry etching than the first gate electrode 105. Therefore, the second gate electrode 52 can be prevented from becoming thin due to the formation of the gate via 121. Therefore, the contact resistance between the gate wiring 111 and the second gate electrode 52 can be reduced, and the gate resistance can be reduced.

[0102] 19, the gate plug 131 is embedded in the gate via 121. The gate plug 131 may be made of, for example, W (tungsten) or other materials, and may include an adhesion layer such as TiN that improves adhesion with the passivation film 110. The gate plug 131 electrically connects the second gate electrode 52 and the gate wiring 111. That is, the first gate electrode 105 is electrically connected to the gate wiring 111 via the second gate electrode 52 and the gate plug 131. By embedding the gate plug 131, the gate wiring 111 can be flattened. Also, by embedding the gate plug 131, for example, disconnection due to the gate via 121 can be suppressed.

[0103] 18, the drain via 122 is disposed on the drain electrodes 102, 103, and is a hole penetrating the passivation film 110 in the thickness direction (in other words, the Z-axis direction) in order to electrically connect the drain electrodes 102, 103 to the drain wiring 112. The drain plug 132 is embedded in the drain via 122, and electrically connects the drain electrodes 102, 103 to the drain wiring 112. In other words, the drain via 122 is used to penetrate the passivation film 110 and electrically connect the drain electrodes 102, 103 to the drain wiring 112.

[0104] The source via 123 is disposed on the source electrode 101, and is a hole penetrating the passivation film 110 in the thickness direction (in other words, the Z-axis direction) in order to electrically connect the source electrode 101 and the source wiring 113. The source plug 133 is embedded in the source via 123, and electrically connects the source electrode 101 and the source wiring 113. In other words, the source via 123 is used to penetrate the passivation film 110 and electrically connect the source electrode 101 and the source wiring 113.

[0105] The shapes of the vias 121, 122, 123 and the plugs 131, 132, 133 may be circular in a plan view. However, the shapes are not limited to this, and the shapes of the vias 121, 122, 123 and the plugs 131, 132, 133 may be arbitrary, for example, rectangular or oval. Also, instead of the plugs 131, 132, 133, a configuration in which parts of the wirings 111, 112, 113 are embedded in the vias 121, 122, 123 may be used.

[0106] [Second embodiment] The second embodiment will be described with reference to Figs. 20 to 22. Fig. 20 is a schematic plan view of an exemplary nitride semiconductor device 200 according to the second embodiment. Fig. 21 is a schematic cross-sectional view taken along line 21-21 in Fig. 20. Fig. 22 is a schematic cross-sectional view taken along line 22-22 in Fig. 21. As an example of the nitride semiconductor device 200, a HEMT using GaN will be described. Note that the same reference numerals are used for configurations similar to those of the first embodiment, and detailed description thereof will be omitted.

[0107] As shown in FIGS. 20 to 22, the nitride semiconductor device 200 of this embodiment includes a gate layer 210, a first electron supply layer 221, a second electron supply layer 222, and a recess region 230. The nitride semiconductor device 200 includes a gate layer 210, a first electron supply layer 221, a second electron supply layer 222, and a recess region 230.

[0108] The gate layer 210 of this embodiment includes a first part 211 formed on the active region 21 and a second part 212 formed on the inactive region 22, similar to the gate layer 30 of the first embodiment.

[0109] The gate layer 210 of this embodiment is configured to contain acceptor-type impurities but not impurities that make it difficult for 2DEG to occur. That is, the above impurities are not introduced into either the first part 211 or the second part 212 in the gate layer 210 of this embodiment. Therefore, the second gate electrode 52 of this embodiment is joined to the gate layer 210 into which the above impurities are not introduced.

[0110] The first electron supply layer 221 is similar to the electron supply layer 18 of the first embodiment, and is formed on the electron transit layer 16 . 21 , the recess region 230 is formed in a lower portion of the gate layer 210. In detail, the recess region 230 is formed in a region immediately below the first gate electrode 51 in the gate layer 210, but is not formed in a region immediately below the second gate electrode 52 in the gate layer 210. The recess region 230 in this embodiment is a recess that penetrates the first electron supply layer 221 and reaches the electron transit layer 16.

[0111] 20, the recess region 230 is provided between the source electrode 41 and the drain electrode 42, and is formed so as to straddle both the active region 21 and the inactive region 22. In detail, the recess region 230 extends in the Y-axis direction in a region directly below the gate layer 210 and the first gate electrode 51, and cuts across the active region 21. Therefore, the recess region 230 is also formed at a position overlapping the boundary between the active region 21 and the inactive region 22.

[0112] The second electron supply layer 222 is made of a nitride semiconductor having a larger band gap than the electron transit layer 16. For example, the second electron supply layer 222 may be made of the same material as the first electron supply layer 221. As an example, the second electron supply layer 222 may be AlGaN.

[0113] Incidentally, when the first electron supply layer 221 and the second electron supply layer 222 are made of the same material (for example, AlGaN), the composition ratio of both layers may be the same. This allows carriers to be generated between the two electron supply layers 221 and 222 due to polarization, and the leakage current between the gate and source and between the gate and drain can be suppressed. However, this is not limited to the above, and the composition ratio of both electron supply layers 221 and 222 may be different.

[0114] 21, the second electron supply layer 222 is provided across both the recess region 230 and the first electron supply layer 221. In detail, the second electron supply layer 222 is formed on the first electron supply layer 221. The second electron supply layer 222 is formed on the bottom surface and the side surface of the recess region 230. As a result, a space surrounded by the second electron supply layer 222 is formed in the recess region 230. In other words, the second electron supply layer 222 is formed so as to fill a part of the recess region 230.

[0115] A first electron supply layer 221 and a second electron supply layer 222 are disposed between the gate layer 210 and the drain electrode 42. Similarly, a first electron supply layer 221 and a second electron supply layer 222 are disposed between the gate layer 210 and the source electrode 41. That is, compared to the first embodiment, the thickness of the electron supply layer between the gate layer 210 and the drain electrode 42 is thicker by the amount of the second electron supply layer 222, and the thickness of the electron supply layer between the gate layer 210 and the source electrode 41 is thicker.

[0116] In this embodiment, the second electron supply layer 222 formed on the inactive region 22 does not contain impurities that inhibit the generation of 2DEG. However, this is not limited thereto, and the second electron supply layer 222 formed on the inactive region 22 may contain the above-mentioned impurities.

[0117] The gate layer 210 of this embodiment includes a bottom surface 210a in contact with the top surface 222a of the second electron supply layer 222, and a protruding portion 210b protruding from the bottom surface 210a toward the electron transit layer 16. The protruding portion 210b is disposed in the recess region 230 and fills the space surrounded by the second electron supply layer 222 in the recess region 230. The protruding portion 210b is in contact with the second electron supply layer 222 present in the recess region 230.

[0118] Next, a manufacturing method of the nitride semiconductor device 200 of this embodiment will be described with reference to Figures 23 to 34. Figures 23, 25, 27, 29, 31, and 33 are schematic cross-sectional views of each step taken along line 21-21, and Figures 24, 26, 28, 30, 32, and 34 are schematic cross-sectional views of each step taken along line 22-22.

[0119] The method for manufacturing the nitride semiconductor device 200 of this embodiment includes the steps of forming the buffer layer 14, the electron transit layer 16, and the first electron supply layer 221 on the semiconductor substrate 12. This step uses epitaxial growth by, for example, MOCVD.

[0120] 23 and 24, the method for manufacturing the nitride semiconductor device 200 includes a step of forming the inactive region 22 after forming the first electron supply layer 221. That is, in this embodiment, the inactive region 22 is formed before forming the gate layer 210. The specific technique for this step is similar to that of the first embodiment.

[0121] 25, the method for manufacturing the nitride semiconductor device 200 includes a step of forming the recess region 230. This step may be performed by, for example, dry etching. Note that, as shown in FIG. 26, the recess region 230 is not formed in the area where the second gate electrode 52 is to be formed.

[0122] 27 and 28, the method for manufacturing the nitride semiconductor device 200 includes a step of forming the second electron supply layer 222, and a step of forming the gate layer 210 after forming the second electron supply layer 222. The step of forming the second electron supply layer 222 and the gate layer 210 may involve, for example, regrowth by MOCVD. In this case, the second electron supply layer 222 is regrown, and then the gate layer 210 is regrown, so that the second electron supply layer 222 and the gate layer 210 are embedded in the recess region 230. In particular, in the step of forming the second electron supply layer 222, it is preferable to adjust the film thickness of the second electron supply layer 222 so that a desired 2DEG concentration can be achieved.

[0123] Furthermore, in this embodiment, the gate layer 210 is formed after the step of forming the inactive region 22. Therefore, the gate layer 210 does not contain impurities that make it difficult for the 2DEG to occur.

[0124] 29 and 30, the method for manufacturing the nitride semiconductor device 200 includes a step of etching the gate layer 210. As shown in Fig. 31 and 32, the method for manufacturing the nitride semiconductor device 200 includes a step of forming a first gate electrode 51. As shown in Fig. 33 and 34, the method for manufacturing the nitride semiconductor device 200 includes a step of forming a second gate electrode 52, a source electrode 41, and a drain electrode 42. These steps are similar to those in the first embodiment, and therefore detailed description thereof will be omitted.

[0125] According to the present embodiment described above in detail, the following effects are achieved in addition to the effects of the first embodiment. (2-1) The portion of the gate layer 210 that contacts the second gate electrode 52 (in other words, the second part 212) contains acceptor-type impurities, but does not contain the impurities contained in the inactive region 22. This can reduce the Schottky barrier between the second gate electrode 52 and the gate layer 210. Alternatively, an ohmic junction can be formed between the second gate electrode 52 and the gate layer 210. This can prevent the potential of the gate layer 210 from floating, and can stabilize the potential of the gate layer 210. This can further prevent the fluctuation in threshold voltage caused by the gate layer 210.

[0126] (2-2) The nitride semiconductor device 200 includes a recess region 230 provided below the gate layer 210, penetrating the first electron supply layer 221 to reach the electron transit layer 16, and a second electron supply layer 222 provided across both the recess region 230 and the first electron supply layer 221. The gate layer 210 includes a bottom surface 210a in contact with an upper surface 222a of the second electron supply layer 222, and a protruding portion 210b protruding from the bottom surface 210a toward the electron transit layer 16. The protruding portion 210b is disposed within the recess region 230 and in contact with the second electron supply layer 222.

[0127] According to this configuration, the first electron supply layer 221 directly below the gate layer 210 is removed by the recess region 230. This allows the concentration of the 2DEG generated directly below the gate layer 210 to be controlled by controlling the film thickness of the second electron supply layer 222. This makes it easy to control the threshold voltage. In addition, the recess region 230 directly below the gate layer 210 makes it difficult for a leak current to flow between the source and drain. This allows the leak current between the source and drain to be suppressed.

[0128] In addition, since the second electron supply layer 222 is provided, the 2DEG generation regions between the gate layer 210 and the source electrode 41 and between the gate layer 210 and the drain electrode 42 are farther away from the semiconductor surface (the upper surface 222a of the second electron supply layer 222) than in a configuration in which only the first electron supply layer 221 is provided. This reduces the influence of the depletion layer from the semiconductor surface, making it possible to increase the concentration of the 2DEG. Therefore, the on-resistance can be reduced.

[0129] [Modification of the second embodiment] 35 to 37, in a configuration in which a source electrode 101 and both drain electrodes 102, 103 are formed, a gate layer 240 and a first gate electrode 105 may be formed in a frame shape surrounding the source electrode 101. In this case, a recess region 241 may also be formed in a frame shape surrounding the source electrode 101. The gate layer 240, the first gate electrode 105, and the recess region 241 may be disposed at positions overlapping the boundary between the active region 21 and the inactive region 22. This makes it possible to suppress leakage current through the boundary.

[0130] The gate layer 240 may have a bottom surface 240a and a protruding portion 240b protruding from the bottom surface 240a. The protruding portion 240b may be formed in a frame-like protrusion corresponding to the recess region 241.

[0131] <Other changes> The above-described embodiments and modifications can be modified, for example, as follows. The above-described embodiments and modifications can be combined with each other as long as no technical contradiction occurs. In the following modifications, the same reference numerals as those in the above-described embodiments are used for the parts common to the above-described embodiments, and the description thereof will be omitted.

[0132] The shape of the gate layer 30 may be changed. For example, as shown in Fig. 38, the gate layer 30 may include a ridge portion 251, a source side extension portion 252 extending from the ridge portion 251 toward the source electrode 41, and a drain side extension portion 253 extending from the ridge portion 251 toward the drain electrode 42. Both extension portions 252, 253 are thinner than the ridge portion 251. The gate layer 250 may have only one of the extension portions 252, 253.

[0133] As shown in FIG. 39, the nitride semiconductor device 10 may have a recess region 260 recessed from the upper surface 18a of the electron supply layer 18. The recess region 260 may be provided in a portion of the electron supply layer 18 that overlaps with the gate layer 30. The recess region 260 may not penetrate the electron supply layer 18. In other words, the recess region 260 may partially thin the electron supply layer 18. In this case, the electron supply layer 18 has a thin film portion 261 and a thick film portion 262 due to the recess region 260. The thin film portion 261 is formed in a region immediately below the gate layer 30 and the first gate electrode 51. The thick film portion 262 is formed in a region between the gate layer 30 and the source electrode 41 and a region between the gate layer 30 and the drain electrode 42. This makes it possible to suppress the generation of 2DEG immediately below the thin film portion 261, thereby suppressing leakage current. Furthermore, by improving the concentration of the 2DEG in the region between the gate layer 30 and the source electrode 41 and the region between the gate layer 30 and the drain electrode 42, the on-resistance can be reduced.

[0134] The source electrode 41, 101 may include a source field plate portion. The buried portion 52a and the overlapping portion 52b may be made of different materials. It is only necessary that at least the portion of the second gate electrode 52 that is in contact with the gate layer 30 is made of a material having a larger work function than the first gate electrode 51.

[0135] The term "on" as used in this disclosure includes both the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, the expression "component A is formed on component B" is intended to mean that in some embodiments, component A may be directly disposed on component B in contact with component B, while in other embodiments, component A may be disposed above component B without contacting component B. In other words, the term "on" does not exclude a structure in which another component is formed between component A and component B.

[0136] The Z direction used in this disclosure does not necessarily have to be a vertical direction, nor does it have to be perfectly aligned with the vertical direction. Therefore, the various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described herein being "up" and "down" of the vertical direction. For example, the X direction may be a vertical direction, or the Y direction may be a vertical direction.

[0137] The terms "first", "second", "third", etc. in this disclosure are used merely to distinguish objects and do not rank the objects. <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples for the purpose of aiding understanding, and the components described in each appendix should not be limited to the components indicated by the reference symbols.

[0138] [Appendix 1] an electron transit layer (16) made of a nitride semiconductor; an electron supply layer (18, 221) formed on the electron transit layer and made of a nitride semiconductor having a band gap larger than that of the electron transit layer; a gate layer (30, 104, 210, 240, 250) formed on the electron supply layer and made of a nitride semiconductor containing an acceptor-type impurity; a first gate electrode (51, 105) in contact with an upper surface of the gate layer; a source electrode (41, 101) and a drain electrode (42, 102, 103) disposed on either side of the gate layer and in contact with an upper surface of the electron supply layer; a second gate electrode (52) made of a material different from that of the first gate electrode and in contact with an upper surface of the gate layer; Equipped with A nitride semiconductor device, wherein a second contact area (S2) which is a contact area between the second gate electrode and the gate layer is smaller than a first contact area (S1) which is a contact area between the first gate electrode and the gate layer.

[0139] [Appendix 2] 2. The nitride semiconductor device according to claim 1, wherein the second gate electrode is made of a material having a larger work function than the first gate electrode.

[0140] [Appendix 3] 3. The nitride semiconductor device according to claim 1, wherein the second gate electrode is configured to form an ohmic junction with the gate layer.

[0141] [Appendix 4] 4. The nitride semiconductor device according to claim 1, wherein the second gate electrode contains any one of Ti, Pd, and Ni.

[0142] [Appendix 5] 5. The nitride semiconductor device according to claim 1, wherein the second gate electrode is made of the same material as the source electrode and the drain electrode.

[0143] [Appendix 6] 6. The nitride semiconductor device according to claim 1, wherein the second contact area is 1 / 100 or less of the first contact area.

[0144] [Appendix 7] 7. The nitride semiconductor device according to claim 1, wherein the first gate electrode is configured to form a Schottky junction with the gate layer.

[0145] [Appendix 8] 8. The nitride semiconductor device according to claim 1, wherein the first gate electrode includes any one of TiN, TaN, WN, TiSiN, TaSiN, WSi, and WSiN.

[0146] [Appendix 9] The electron transport layer and the electron supply layer are an active region (21) in which a two-dimensional electron gas is generated; an inactive region (22) in which the two-dimensional electron gas is less likely to be generated than in the active region; Including, The gate layer is a first part (31, 211) formed on the active area; a second part (32, 212) formed on the inactive area; Including, At least a portion of the first gate electrode is formed on the first part; 9. The nitride semiconductor device according to claim 1, wherein the second gate electrode is formed on the second part.

[0147] [Appendix 10] 10. The nitride semiconductor device according to claim 9, wherein the inactive region contains an impurity for making it difficult for the two-dimensional electron gas to be generated.

[0148] [Appendix 11] 11. The nitride semiconductor device according to claim 10, wherein the impurity for making it difficult to generate two-dimensional electron gas includes any one of He, B, N, O, F, and Ar.

[0149] [Appendix 12] 12. The nitride semiconductor device according to claim 9, wherein the second part contains an impurity for making it difficult for the two-dimensional electron gas to be generated.

[0150] [Appendix 13] 12. The nitride semiconductor device according to claim 9, wherein the second part does not contain an impurity that makes it difficult for the two-dimensional electron gas to be generated.

[0151] [Appendix 14] The first gate electrode has an opening (60) that exposes the gate layer, 14. The nitride semiconductor device according to claim 1, wherein the second gate electrode has a buried portion (52a) buried in the opening and in contact with the gate layer.

[0152] [Appendix 15] the buried portion is in contact with a side surface (60a) of the opening in the first gate electrode, 15. The nitride semiconductor device according to claim 14, wherein the second gate electrode includes an overlapping portion (52b) that is formed wider than the opening in a plan view and that is in contact with an upper surface of the first gate electrode.

[0153] [Appendix 16] The gate layer is formed in a frame shape surrounding the source electrode, 16. The nitride semiconductor device according to claim 1, wherein the drain electrode is disposed outside the gate layer.

[0154] [Appendix 17] a recessed region (260) recessed from an upper surface of the electron supply layer is formed in a portion of the electron supply layer overlapping with the gate layer; The electron supply layer is a thin film portion (261) that is thinned by the recess region; A thick film portion (262) having a thickness greater than that of the thin film portion; 17. The nitride semiconductor device according to claim 1, further comprising:

[0155] [Appendix 18] the electron supply layer is a first electron supply layer (221), a recess region (230, 241) is formed below the gate layer, the recess region penetrating the first electron supply layer and reaching the electron transit layer; The nitride semiconductor device includes a second electron supply layer (222) made of a nitride semiconductor having a band gap larger than that of the electron transit layer, the second electron supply layer is provided across both the recess region and the first electron supply layer, The gate layer is a bottom surface (210a) in contact with an upper surface of the second electron supply layer; a protruding portion (210b) protruding from the bottom surface toward the electron transport layer; Equipped with 17. The nitride semiconductor device according to claim 1, wherein the protrusion is disposed in the recess region and in contact with the second electron supply layer.

[0156] [Appendix 19] 19. The nitride semiconductor device according to claim 18, wherein the second electron supply layer is made of the same material as the first electron supply layer.

[0157] [Appendix 20] The electron transport layer and the electron supply layer are an active region (21) in which a two-dimensional electron gas is generated; an inactive region (22) in which the two-dimensional electron gas is less likely to be generated than in the active region; Including, the gate layer is formed across both the active region and the inactive region; 20. The nitride semiconductor device according to claim 17, wherein the recess region is provided between the source electrode and the drain electrode, and is formed across both the active region and the inactive region.

[0158] [Appendix 21] an insulating passivation film (110) covering the first gate electrode and the second gate electrode; A gate wiring (111) formed on the passivation film; a gate via (121) that penetrates the passivation film and is used to electrically connect the second gate electrode and the gate wiring; 21. The nitride semiconductor device according to claim 1, comprising:

[0159] [Appendix 22] 22. The nitride semiconductor device of claim 21, further comprising a gate plug (131) embedded in the gate via. [Explanation of symbols]

[0160] 10, 100, 200...Nitride semiconductor device 12...Semiconductor substrate 14…Buffer layer 16...Electron transport layer 18...electron supply layer 18a...Top surface of electron supply layer 21…Active region 22…Inactive area 30,104,210,240,250…Gate layer 31,211…Part 1 32,212…Second part 41,101…Source electrode 42, 102, 103...Drain electrode 51,105...First gate electrode 51a...top surface of first gate electrode 52...Second gate electrode 52a…embedded part 52b…Overlap section 60…Opening 60a…Side of opening 110...passivation film 111…Gate wiring 112…Drain wiring 113…Source wiring 121…Gate via 122…Drain via 123…Sauce via 131…Gate plug 132…Drain plug 133…Source plug 210a...Bottom surface of gate layer 210b...Protruding part 221...first electron supply layer 222…Second electron supply layer 222a...Top surface of second electron supply layer 230, 241, 260…Recess area 261…Thin film section 262…Thick film section S1…1st contact area S2…Second contact area

Claims

1. an electron transit layer made of a nitride semiconductor; an electron supply layer formed on the electron transit layer and made of a nitride semiconductor having a band gap larger than that of the electron transit layer; a gate layer formed on the electron supply layer and made of a nitride semiconductor containing an acceptor-type impurity; a first gate electrode in contact with an upper surface of the gate layer; a source electrode and a drain electrode disposed on either side of the gate layer and in contact with an upper surface of the electron supply layer; a second gate electrode made of a material different from that of the first gate electrode and in contact with an upper surface of the gate layer; Equipped with A nitride semiconductor device, wherein a second contact area, which is a contact area between the second gate electrode and the gate layer, is smaller than a first contact area, which is a contact area between the first gate electrode and the gate layer.

2. The nitride semiconductor device according to claim 1 , wherein said second gate electrode is made of a material having a larger work function than said first gate electrode.

3. The nitride semiconductor device according to claim 2 , wherein said second gate electrode is configured to form an ohmic junction with said gate layer.

4. The nitride semiconductor device according to claim 2 , wherein said second gate electrode contains any one of Ti, Pd and Ni.

5. The nitride semiconductor device according to claim 1 , wherein said second gate electrode is made of the same material as said source electrode and said drain electrode.

6. The nitride semiconductor device according to claim 1 , wherein said second contact area is equal to or smaller than 1 / 100 of said first contact area.

7. The nitride semiconductor device according to claim 1 , wherein said first gate electrode is configured to form a Schottky junction with said gate layer.

8. The nitride semiconductor device according to claim 1 , wherein said first gate electrode includes any one of TiN, TaN, WN, TiSiN, TaSiN, WSi, and WSiN.

9. The electron transport layer and the electron supply layer are an active region in which a two-dimensional electron gas is generated; an inactive region in which the two-dimensional electron gas is less likely to be generated than in the active region; Including, The gate layer is a first part formed on the active area; A second part formed on the inactive area; Including, At least a portion of the first gate electrode is formed on the first part; 9. The nitride semiconductor device according to claim 1, wherein said second gate electrode is formed on said second part.

10. 10. The nitride semiconductor device according to claim 9, wherein said inactive region contains an impurity for making it difficult for said two-dimensional electron gas to be generated.

11. 11. The nitride semiconductor device according to claim 10, wherein said impurity for making it difficult to generate two-dimensional electron gas includes any one of He, B, N, O, F, and Ar.

12. the first gate electrode has an opening formed therein to expose the gate layer; The nitride semiconductor device according to claim 1 , wherein said second gate electrode has a buried portion buried in said opening and in contact with said gate layer.

13. the buried portion is in contact with a side surface of the opening in the first gate electrode, The nitride semiconductor device according to claim 12 , wherein said second gate electrode includes an overlapping portion that is formed wider than said opening in a plan view and that is in contact with an upper surface of said first gate electrode.

14. The gate layer is formed in a frame shape surrounding the source electrode, The nitride semiconductor device according to claim 1 , wherein said drain electrode is disposed outside said gate layer.

15. a recess region recessed from an upper surface of the electron supply layer is formed in a portion of the electron supply layer overlapping with the gate layer, The electron supply layer is a thin film portion that is thinned by the recess region; a thick film portion having a thickness greater than that of the thin film portion; The nitride semiconductor device according to claim 1 ,

16. the electron supply layer is a first electron supply layer, a recess region is formed below the gate layer, the recess region penetrating the first electron supply layer and reaching the electron transit layer; the nitride semiconductor device includes a second electron supply layer made of a nitride semiconductor having a band gap larger than that of the electron transit layer, the second electron supply layer is provided across both the recess region and the first electron supply layer, The gate layer is a bottom surface in contact with an upper surface of the second electron supply layer; a protruding portion protruding from the bottom surface toward the electron transit layer; Equipped with The nitride semiconductor device according to claim 1 , wherein said protrusion is disposed in said recess region and in contact with said second electron supply layer.

17. The nitride semiconductor device according to claim 16 , wherein said second electron supply layer is made of the same material as said first electron supply layer.

18. The electron transport layer and the electron supply layer are an active region in which a two-dimensional electron gas is generated; an inactive region in which the two-dimensional electron gas is less likely to be generated than in the active region; Including, the gate layer is formed across both the active region and the inactive region; 17. The nitride semiconductor device according to claim 15, wherein said recess region is provided between said source electrode and said drain electrode, and is formed across both said active region and said inactive region.

19. an insulating passivation film covering the first gate electrode and the second gate electrode; a gate wiring formed on the passivation film; a gate via that penetrates the passivation film and is used to electrically connect the second gate electrode and the gate wiring; The nitride semiconductor device according to claim 1 , comprising:

20. The nitride semiconductor device of claim 19 further comprising a gate plug embedded in the gate via.

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