Imaging device

Abstract

To provide a highly sensitive imaging device that can perform imaging even under a low illuminance condition.SOLUTION: One electrode of a photoelectric conversion element is electrically connected to one of a source electrode and a drain electrode of a first transistor and one of a source electrode and a drain electrode of a third transistor. The other of the source electrode and the drain electrode of the first transistor is electrically connected to a gate electrode of a second transistor. The other electrode of the photoelectric conversion element is electrically connected to first wiring. A gate electrode of the first transistor is electrically connected to second wiring. When a potential supplied to the first wiring is HVDD, the highest value of a potential supplied to the second wiring is lower than HVDD.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to an imaging device including an oxide semiconductor.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the present invention more specifically disclosed herein The technical field of one embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, driving method thereof, or manufacturing method thereof One example can be mentioned.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] A technology to construct transistors using semiconductor thin films formed on substrates with insulating surfaces The transistor is used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductors are widely used in transistors. are widely known, but oxide semiconductors are attracting attention as another material.

[0005] For example, zinc oxide or In-Ga-Zn oxide semiconductors are used as oxide semiconductors. Techniques for fabricating transistors have been disclosed (see Patent Documents 1 and 2).

[0006] In addition, in Patent Document 3, a transistor having an oxide semiconductor and an extremely low off-state current is used as a pixel Used as part of the circuit, CMOS (Complementary Metal Oxide A transistor with silicon on which circuits can be fabricated. An imaging device configured for road use is disclosed. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2011-119711 A Summary of the Invention [Problem to be solved by the invention]

[0008] To obtain high-definition images, an image sensor with a highly densely integrated pixel array is required. In order to integrate pixels at a high density, the area per pixel must be reduced. stomach.

[0009] When reducing the area of ​​a pixel, the light receiving area of ​​the photoelectric conversion element of the pixel must be reduced. If the light receiving area of ​​the photoelectric conversion element is reduced, the sensitivity to light will decrease. Therefore, imaging under low illumination may be difficult.

[0010] Therefore, one embodiment of the present invention provides an imaging device that can easily capture images under low illuminance. Another object of the present invention is to provide an imaging device with low power consumption. Another object is to provide an imaging device suitable for high speed operation. Another object of the present invention is to provide an imaging device with high integration. Another object of the present invention is to provide an imaging device with a wide dynamic range. Another object of the present invention is to provide an imaging device that can be used in a wide temperature range. Another object of the present invention is to provide an imaging device with a high aperture ratio. Another object of the present invention is to provide a highly reliable imaging device. It is one of the objects to provide an imaging device or the like. Or, to provide a novel semiconductor device or the like. One of the objectives of the Society is to

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention relates to a high-sensitivity imaging device capable of imaging even under low illuminance.

[0013] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. an imaging device having a fourth transistor and a photoelectric conversion element, One electrode of the first transistor is electrically connected to one of the source electrode and the drain electrode of the first transistor. One electrode of the photoelectric conversion element is connected to the source electrode or drain electrode of the third transistor. a source electrode or a drain electrode of the first transistor, The other of the two is electrically connected to the gate electrode of the second transistor. One of the source electrode and the drain electrode is a source electrode or a drain electrode of a fourth transistor. The other electrode of the photoelectric conversion element is electrically connected to the first wiring. The gate electrode of the first transistor is electrically connected to the second wiring, and the gate electrode of the first transistor is electrically connected to the second wiring. When the potential supplied to the wiring is HVDD, the maximum value of the potential supplied to the second wiring is The imaging device is characterized by being smaller than HVDD.

[0014] In the above-mentioned structure, the other of the source electrode and the drain electrode of the second transistor is The potential supplied to the first wiring is HVDD, and the potential supplied to the third wiring is HVDD. When the potential supplied to the second The maximum value of the potential supplied to the wiring can be set to VDD.

[0015] The first transistor and the third transistor each have an oxide semiconductor in an active layer. The oxide semiconductor may be a transistor containing In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf) preferable.

[0016] The second transistor and the fourth transistor each have a silicon active layer or active region. A transistor having a capacitance can be used. Effect of the Invention

[0017] By using one embodiment of the present invention, an imaging device that can easily capture images under low illuminance can be provided. Alternatively, it is possible to provide an imaging device with low power consumption. Alternatively, it is possible to provide an imaging device suitable for high-speed operation. Alternatively, it is possible to provide an imaging device having a high resolution. Alternatively, a highly integrated imaging device can be provided. It is possible to provide an imaging device that can be used in a wide range of temperatures. It is possible to provide an imaging device. Alternatively, it is possible to provide an imaging device with a high aperture ratio. Alternatively, a highly reliable imaging device can be provided. Alternatively, a novel imaging device, etc. Alternatively, a novel semiconductor device or the like can be provided.

[0018] Note that the effects of one embodiment of the present invention are not limited to these. In some cases or depending on the situation, the above effects may be different. Alternatively, for example, one aspect of the present invention may be, in some cases, or depending on the situation, In some cases, these effects may not be present. [Brief description of the drawings]

[0019] [Figure 1] FIG. 2 is a diagram illustrating a pixel circuit. [Diagram 2] FIG. 13 shows Id-Vg characteristics of an OS transistor. [Diagram 3] FIG. 13 shows the withstand voltage characteristics of an OS transistor. [Figure 4] FIG. 13 shows the withstand voltage characteristics of an OS transistor. [Diagram 5] FIG. 13 shows the withstand voltage characteristics of an OS transistor. [Figure 6] 4 is a timing chart illustrating an imaging operation. [Figure 7] FIG. 2 is a circuit diagram illustrating a pixel circuit. [Figure 8] FIG. 2 is a circuit diagram illustrating a pixel circuit. [Figure 9] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 10] 4A and 4B are diagrams for explaining the operations of a global shutter system and a rolling shutter system. [Figure 11] FIG. 3 is a cross-sectional view illustrating a connection form of photoelectric conversion elements. [Figure 12] FIG. 3 is a cross-sectional view illustrating a connection form of photoelectric conversion elements. [Figure 13] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 14] FIG. 3 is a cross-sectional view illustrating a connection form of photoelectric conversion elements. [Figure 15] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 16] 1A and 1B are a cross-sectional view and a circuit diagram illustrating a structure of an imaging device. [Figure 17] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 18] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 19] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 20] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 21] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 22] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 23] 1A and 1B are diagrams illustrating a curved imaging device. [Figure 24] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 25] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 26] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 27] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Figure 28] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Figure 29] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 30] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 31] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Diagram 32] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Diagram 33] FIG. 1 is a top view illustrating a transistor. [Diagram 34] 1A to 1C are diagrams illustrating electronic devices. [Diagram 35] FIG. 2 is a diagram illustrating a pixel circuit. [Diagram 36] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 37] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 38] FIG. 2 is a diagram illustrating a pixel circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0021] For example, in the present specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in the present specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be included in the drawings or text. do.

[0022] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0023] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When a resistor (such as an electrode, display element, light-emitting element, or load) is not connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors, etc.) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0024] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0025] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected and cases where X and Y are functionally connected. and the case where they are electrically connected to each other.

[0026] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) When X and Y are functionally connected (i.e., when X and Y are connected), (When there is a functional connection between X and Y via another circuit in between) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is deemed to be disclosed in the present specification. If it is explicitly stated that it is connected, The same contents are deemed to be disclosed in the present specification and the like.

[0027] For example, the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z 2 (or not), it may be electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0028] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined based on the above.

[0029] Or, as another way of expressing it, for example, "the source (or first terminal, etc.) of a transistor is electrically connected to X through at least a first connection path, and the first connection path is , the second connection path does not have a second connection path, and the second connection path is a transistor The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the transistor The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. The third connection path does not include the second connection path, and the third connection path The connection path is the path through Z2. The source (or the first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and X is electrically connected to the first connection path, and the first connection path does not have a second connection path; The second connection path includes a connection path through a transistor, and the second connection path includes a drain of the transistor. (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or the first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1, and the first electrical path is The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third electrical path is electrically connected to Y through Z2. , the fourth electrical path is not included, and the fourth electrical path is a drain of the transistor (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguish between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0030] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0031] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The electrode functions as both components. The term "electrochemically connected" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0032] The words "membrane" and "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0033] Generally, potential (voltage) is relative, and the magnitude is relative to a reference potential. The size is determined by the distance between the ground and the ground. Even if it is stated, it does not necessarily mean that the potential is 0 volts. For example, "ground" or "GND" may be defined based on the lowest potential in the circuit. Or, define "ground" or "GND" based on the midpoint of the circuit potential. In such cases, positive and negative potentials are defined based on that potential. This results in:

[0034] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0035] FIG. 1 illustrates a pixel circuit that can be used in an imaging device of one embodiment of the present invention. The pixel circuit includes a transistor 51, a transistor 52, a transistor 53, and a transistor The pixel includes a transistor 54 and a photoelectric conversion element 60 .

[0036] One electrode of the photoelectric conversion element 60 is connected to the source electrode or drain electrode of the transistor 51. One electrode of the photoelectric conversion element 60 is electrically connected to the transistor 53. The transistor 51 is electrically connected to one of the source electrode and the drain electrode of the transistor 51. The other of the source electrode and the drain electrode is electrically connected to the gate electrode of the transistor 52. In addition, one of the source electrode and the drain electrode of the transistor 52 is connected to the transistor The transistor 52 is electrically connected to either the source electrode or the drain electrode of the transistor 54 .

[0037] The other electrode of the photoelectric conversion element 60 is electrically connected to the wiring 72 (HVDD). The gate electrode of the transistor 51 is electrically connected to the wiring 75 (TX). The other of the source electrode or the drain electrode of the transistor 52 is electrically connected to the wiring 79 (VDD). The gate electrode of the transistor 53 is electrically connected to the wiring 76 (RS). The other of the source electrode and the drain electrode of the transistor 53 is connected to a wiring 73 ( GND). Also, the source electrode or drain electrode of the transistor 54 The other electrode is electrically connected to the wiring 71 (OUT). The power supply electrode is electrically connected to the wiring 78 (SE). The other terminal of the high voltage power supply 56 is electrically connected to a wire 7 It is electrically connected to 7 (GND).

[0038] The wiring 71 (OUT) can function as an output line for outputting a signal from a pixel. In addition, wires 73 (GND), 77 (GND), and 79 (VDD) are used as power supply lines. For example, the wiring 73 (GND) and the wiring 77 (GND) can have the following functions: The potential power supply line, the wiring 79 (VDD) can function as a high potential power supply line. Wiring 75 (TX), wiring 76 (RS), and wiring 78 (SE) are used to turn on and off each transistor. The signal line can be used to control the

[0039] The wiring 73 (GND) and the wiring 77 (GND) are provided as one wiring. In addition, the potential of the two wirings is not limited to GND, and may be supplied to the wiring 79 (VDD). Any potential may be used as long as it is sufficiently lower than the potential at which the electrode is to be exposed.

[0040] The photoelectric conversion element 60 exhibits photoelectric characteristics when a high voltage potential HVDD is applied to it. In this embodiment, the potential HVDD is the potential VDD supplied to the wiring 79 (VDD). In addition, the photoelectric conversion element 60 has a potential higher than that of the photoelectric conversion element 60, which is designed to enhance the light detection sensitivity at low illuminance. Therefore, it is preferable to use a photoelectric conversion element formed of a material that generates avalanche charge multiplication. A relatively high voltage (HVDD) is required to generate avalanche charge multiplication. Therefore, the high voltage power supply 56 has a function of supplying HVDD, The other electrode of the photoelectric conversion element 60 is supplied with HVDD via a wiring 72 (HVDD). .

[0041] The transistor 51 detects the charge of the charge storage section (NR) which changes in response to the output of the photoelectric conversion element 60. It can function as a transfer transistor to transfer the potential to the charge storage section (ND). In addition, the transistor 53 controls the potentials of the charge storage unit (NR) and the charge storage unit (ND) to Transistor 5 can function as a reset transistor to initialize the 2 functions as an amplifying transistor that outputs a signal according to the potential of the charge storage section (ND). The transistor 54 is a selection transistor for selecting a pixel from which a signal is to be read out. It can function as a transistor.

[0042] When a high voltage is applied to the photoelectric conversion element 60, the transistor connected to the photoelectric conversion element 60 It is necessary to use high-voltage transistors that can withstand high voltages. For example, a transistor using an oxide semiconductor in an active layer (hereafter referred to as an OS transistor) is used as the transistor. Specifically, transistors 51 and 53 can be used. It is preferable to use an OS transistor in the above-mentioned embodiment.

[0043] Here, channel length L / channel width W=0.35μm / 0.8μm, conversion of gate insulating film The static characteristics (drain) of an OS transistor with a film thickness of 20 nm (physical film thickness is 31 nm) are shown in Fig. 2. The gate voltage (Vd) of the transistor is shown in Fig. 3. The drain breakdown voltage when the gate voltage (Vg) = 0V and the source voltage (Vs) = 0V. The characteristics are shown in Fig. 4. The gate breakdown voltage characteristics at Vs=V The gate breakdown voltage characteristics at a negative voltage when d=0V are shown in Figs. As shown, the OS transistor has electrical characteristics that allow for high withstand voltage.

[0044] OS transistors are wide band gap (>3.0 eV) semiconductors, so the drain withstand voltage depends on the thickness of the gate insulating film, not on the junction breakdown voltage. In this case, the short channel effect is unlikely to occur, so the gate insulating film is made thicker to improve the drain resistance. In addition, normally-off transistor characteristics can be easily obtained. It can be seen that the device is tolerant to a bias of over 20 V, which is necessary for charge multiplication. The failure mode of an OS transistor is dielectric breakdown.

[0045] In this specification, a high-voltage transistor is a transistor that can withstand a desired voltage without being electrically destroyed. This means that the transistor can be applied with high voltage. For example, The transistor can be connected to the gate without being destroyed by connecting the source and drain electrodes to GND. A desired high voltage can be applied to the source and gate electrodes. As an ND, a desired high voltage can be applied to the drain electrode without destruction. Or, the source electrode is connected to GND and the gate electrode is connected to VDD, and the drain electrode A desired high voltage can be applied to the

[0046] The transistors 51 and 53 are prioritized for their switching characteristics. Since the amplification characteristic is a priority for the transistor 52, it is preferable that the transistor has a high on-state current. Therefore, transistor 52 is a transistor that uses silicon for the active layer or region. It is preferable to use a silicon transistor.

[0047] The potential of the charge storage section (NR) can be HVDD at most, but the transistor 51 When a -ch type transistor is used, the potential of the charge storage section (ND) is The potential applied to the gate electrode of the charge storage device 1 cannot be greater than the maximum potential. The potential of the integrated circuit (ND) is the maximum potential applied to the gate electrode of the transistor 51. The threshold voltage of resistor 51 (V th ) lower. For example, the charge Even if the potential of the storage section (NR) is HVDD, the maximum potential applied to the wiring 75 (TX) When is VDD, the maximum potential of the charge storage section (ND) is VDD. More precisely, The potential of the charge storage section (ND) is VDD-V th In the following explanation, Transistor 51 V th is considered to be a small value, and the potential of the charge storage section (ND) is The V th The description regarding this is omitted.

[0048] In other words, if the transistor 51 is normally off, a voltage lower than the potential HVDD is applied. Therefore, the gate electrode of the transistor 52 is connected to the power supply voltage VDD. Since no high voltage is applied, the transistor 52 has a thin gate insulating film. No problem occurs even if a Si transistor, which does not have a high breakdown voltage, is used.

[0049] By configuring the transistors 51 to 54 as described above, light To fabricate an imaging device capable of outputting a signal with high detection sensitivity and low noise. In addition, the high light detection sensitivity allows the light capture time to be shortened, Images can be taken at high speed.

[0050] Next, the operation of the pixel will be described with reference to the timing chart of FIG. In one example of operation, the wiring 76 (RS) connected to the gate electrode of the transistor 53 The potential of HVDD is supplied as "H" and the potential of GND is supplied as "L". The wiring 75 (TX) connected to the gate electrode of the transistor 51 is set to “H” and a VDD The source of the transistor 52 is supplied with the GND potential as "L". It is assumed that VDD is supplied to the wiring 79 (VDD) connected to the electrode. A potential other than the above may be supplied to the

[0051] First, the wiring 76 (RS) is set to “H” and the wiring 75 (TX) is set to “H” to Set the potential of the charge storage section (ND) to the reset potential (GND) (Reset In addition, even if VDD is supplied to line 76 (RS) as "H" during reset operation, good.

[0052] Next, the wiring 76 (RS) is set to "L" and the wiring 75 (TX) is set to "L", The potential of the charge storage section (NR) changes (storage operation). Depending on the intensity of the light incident on pin 0, the signal level can range from GND to a maximum of HVDD.

[0053] Following the charge accumulation operation, the line 75 (TX) is set to “H” to charge the charge accumulation unit (NR). is transferred to the charge storage unit (ND) (transfer operation).

[0054] In the accumulation operation, the charge accumulation unit (NR) The potential changes, but since VDD is supplied to the gate electrode of the transistor 51, When the potential of the charge storage section (ND) reaches VDD, the transistor 51 turns off. The potential of the charge storage section (ND) changes from the reset potential (GND) up to VDD. That is, the gate electrode of the transistor 52 is applied with a potential of VDD at maximum. become.

[0055] In FIG. 6, the wiring 75 (TX) is set to "L" during the accumulation operation. TX) may be set to "H". In this case, the charge storage section (NR) changes its potential. The potential of the integrated circuit (ND) also changes, but VDD is supplied to the gate electrode of the transistor 51. Therefore, when the potential of the charge storage section (ND) reaches VDD, the transistor 51 is turned off. Therefore, the potential of the charge storage section (ND) is at most VD In other words, even in this case, the gate electrode of the transistor 52 changes to a maximum The potential of VDD is applied.

[0056] In the accumulation operation, the wiring 75 (TX) is set to “L” to the transistor 51. On the other hand, when the wiring 75 (TX) is set to “H”, the influence of noise caused by the This makes it possible to reduce the effect of noise caused by the switching of the transistor 51. do.

[0057] Following the transfer operation, the wiring 76 (RS) is set to "L", the wiring 75 (TX) is set to "L", and the wiring 78 ( By setting the signal (OUE) to “H”, a signal according to the potential of the charge storage unit (ND) is sent to the wiring 71 (OU That is, the light incident on the photoelectric conversion element 60 during the accumulation operation can be output to the output terminal T. An output signal corresponding to the light intensity can be obtained.

[0058] In the above operation, the maximum voltage applied to the terminals of each transistor is as follows: The source electrode of the transistor 51 is connected to HVDD, and the gate and drain electrodes are connected to VD D may be applied to the gate and drain electrodes of transistor 53. GND may be applied to the source electrode of transistor 52. The drain and gate electrodes may be connected to VDD. VDD may be applied to the source electrode, drain electrode, and gate electrode. Therefore, the transistors 51 and 53 are provided with high voltage resistance capable of withstanding the high voltage HVDD. On the other hand, the transistors 52 and 54 are required to have a resistance capable of withstanding VDD. The pressure is enough.

[0059] Note that a pixel circuit used in the imaging device of one embodiment of the present invention may have a structure shown in FIG. In the pixel circuit shown in FIG. 35, a transistor 5 is added to the charge storage section (ND) in the configuration of FIG. The source electrode or the drain electrode of the transistor 55 is connected. The other of the source electrode and drain electrode is connected to wiring 93 (GND), and the gate electrode is connected to wiring 96 (RS The wiring 93 (GND) is connected to the wiring 73 (GND). The wiring 96 (RS) is a signal line for controlling the transistor 55, and the wiring 7 The same potential as that of the wiring 76 (RS) and the wiring 96 (RS) can be supplied. 6 (RS) is configured to be capable of supplying different potentials to each of them, and Alternatively, the electrodes may be electrically connected.

[0060] In the configuration of the pixel circuit shown in FIG. 1, the reset operation of the charge storage unit (ND) is performed by the transistor 51 This is done by turning on transistors 53 and 54. In the configuration shown in FIG. The charge storage unit (ND) can be reset without operating 1, reducing image noise. It can be reduced.

[0061] In the circuit configuration shown in FIG. 1, the transistor 54 is connected to the transistor 52 via a wiring 71 (OU 36, the transistor 54 is provided between the It may be provided between the transistor 52 and the wiring 79 (VDD).

[0062] In the circuit configuration shown in FIG. 1, in addition to the source electrode or drain electrode of the transistor 52, In the example shown in FIG. 37(A), the high-potential power supply line (wiring 79 (VDD)) is connected to the In this way, the other of the source electrode or the drain electrode of the transistor 52 is connected to a low potential power line (wiring 99 (GND)). Also, as shown in FIG. 37(B), The transistor 52 may be replaced with a p-ch type transistor.

[0063] As another embodiment of the pixel circuit of the present invention, a transistor as shown in FIG. Alternatively, the charge storage unit (N R) may be provided with a capacitance element 57. A capacitance element 58 may be provided in the storage section (ND). As shown in FIG. 7(A), a configuration may be provided with a capacitance element 57 and a capacitance element 58. The configurations shown in FIGS. 35 to 37 can be arbitrarily combined with the configurations shown in FIGS. can.

[0064] The transistors used in the pixel circuits are as shown in FIG. 7(E) or FIG. 7(F). The transistor 51 and the transistor 53 may be provided with a back gate. E) is a structure in which a constant potential is applied to the back gate, and the threshold voltage can be controlled. FIG. 7(F) shows a configuration in which the same potential as that of the front gate is applied to the back gate. As shown in FIG. 7(G) or FIG. 7(H), Alternatively, the transistors 51 to 54 may be provided with back gates. In addition, the structure in which a back gate is provided in a transistor is shown in FIG. The same can be applied to the circuits shown in FIGS. 35 to 37. A structure in which the same potential as that of the front gate is applied to the back gate of the transistor. A structure in which a constant potential is applied to the back gate or a structure without a back gate is used as required. The circuit configuration may be any combination of the above.

[0065] In addition, the pixel circuit includes a plurality of transistors 52 and 54 as shown in FIG. In FIG. 8, the transistor is shared by multiple pixels in the vertical direction. 52 and transistor 54 are shared in common, The transistors 52 and 54 may be shared by multiple pixels in the same direction. By adopting such a configuration, it is possible to reduce the number of transistors per pixel. In addition, as shown in FIG. 38, a reset transistor 55 is provided in the charge storage section (ND). The present invention may be in a form in which the

[0066] In addition, in FIG. 8 and FIG. 38, the transistor 52 and the transistor 54 are shared by four pixels. However, it may be shared by two pixels, three pixels, five pixels or more. In addition, the configuration of FIG. 8 or FIG. 38 and the configurations shown in FIG. 7(A) to FIG. 7(H), FIG. 36, and FIG. The configurations can be combined in any way.

[0067] By adopting the above-mentioned configuration, an imaging device having a highly integrated pixel array is formed. It is also possible to provide an imaging device that can easily capture images under low illuminance conditions.

[0068] Next, a specific configuration example of the imaging device of one embodiment of the present invention will be described with reference to the drawings. FIG. 9A is an example of a cross-sectional view of an imaging device of one embodiment of the present invention. One specific connection form of the photoelectric conversion element 60, the transistor 51, and the transistor 53 is In addition, the transistor 52 and the transistor 54 are not shown in FIG. The imaging device is not provided with a layer in which the transistors 51 to 54 are provided. 1100, and a layer 1200 in which the photoelectric conversion element 60 is provided.

[0069] In the cross-sectional views described in this embodiment, each wiring, each electrode, and each conductor 81 is individually Although shown as separate elements, when they are electrically connected they may be considered to be the same. In some cases, the gate electrode, source electrode, or The embodiment in which the drain electrode is connected to each wiring via the conductor 81 is an example. Each of the gate electrode, source electrode, and drain electrode of the transistor functions as a wiring. In some cases.

[0070] Moreover, on each element, an insulating layer 82 having a function as a protective film, an interlayer insulating film, or a planarizing film is formed. For example, the insulating layer 82 and the insulating layer 83 are made of silicon oxide. An inorganic insulating film such as a silicon oxide nitride film or an acrylic film can be used. Alternatively, an organic insulating film such as a resin or a polyimide resin may be used. The top surface of the 3rd class may be polished by CMP (Chemical Mechanical Polishing) if necessary. It is preferable to perform a flattening process by a flattening method or the like.

[0071] In addition, in some cases, wiring, etc., not shown in the drawings may not be provided, or wiring, etc., not shown in the drawings may not be provided. Each layer may contain transistors, etc. Also, layers not shown in the drawings may be included. Also, some layers shown in the drawings may not be included.

[0072] It is particularly preferable to use OS transistors for the transistors 51 and 53. I wish.

[0073] OS transistors have extremely low off-state current characteristics, expanding the dynamic range of imaging. In the circuit configuration of the pixel shown in FIG. When the light intensity is low, the potential of the charge storage section (ND) becomes small. Since the off-state current is extremely low, even when the gate potential is extremely small, Therefore, the range of illuminance that can be detected is This allows for a wider image quality, i.e., a wider dynamic range.

[0074] In addition, the low off-current characteristics of the transistors 51 and 53 reduce the charge storage The period during which the charge can be held in the charge storage section (NR) and the charge storage section (ND) can be made extremely long. Therefore, the charge accumulation operation can be performed simultaneously in all pixels without complicating the circuit configuration or operation method. A global shutter system that performs this operation can be applied.

[0075] Generally, in an imaging device in which pixels are arranged in a matrix, the following is performed for each row as shown in FIG. A rolling driving method for performing an imaging operation 11, a data holding operation 12, and a read operation 13. When using the rolling shutter method, the simultaneity of imaging is Since this is lost, if the subject moves, the image will be distorted.

[0076] Therefore, in one embodiment of the present invention, the imaging operation 11 is performed simultaneously on all rows as shown in FIG. A global shutter system is used, which can perform a read operation 13 sequentially for each row. By using the global shutter method, it is possible to reduce the number of pixels in the image pickup device. This ensures synchronicity, making it easy to capture images with minimal distortion even when the subject is moving. can be obtained.

[0077] An OS transistor is a transistor that uses silicon in the active region or active layer (hereafter referred to as Because the temperature dependency of the electrical characteristics is smaller than that of silicon transistors, the Therefore, imaging devices and semiconductor devices having OS transistors can be used in a wide range of applications. The conductor device is also suitable for installation in automobiles, aircraft, spacecraft, and the like.

[0078] In addition, the OS transistor has a higher drain withstand voltage than a Si transistor. In photoelectric conversion elements that use selenium-based materials as the photoelectric conversion layer, the avalanche phenomenon is likely to occur. It is preferable to apply a relatively high voltage (e.g., 10 V or more) so that Combining an S transistor with a photoelectric conversion element that uses a selenium-based material as a photoelectric conversion layer This makes it possible to provide a highly reliable imaging device.

[0079] In FIG. 9A, each transistor has a back gate. However, as shown in FIG. 9(B), a configuration without a back gate is also possible. As shown in (C), only some of the transistors, for example, transistor 51, are provided with a back gate. The back gate may be provided on the opposite side of the transistor. In some cases, the back gate may be electrically connected to the front gate of the In some cases, a fixed potential different from that of the back gate may be supplied. This embodiment can also be applied to the other imaging device embodiments described in this embodiment.

[0080] The photoelectric conversion element 60 provided in the layer 1200 can be of various types. FIG. 9A illustrates an embodiment in which a selenium-based material is used for the photoelectric conversion layer 61. The photoelectric conversion element 60 using this material has the characteristic of having a high external quantum efficiency for visible light. In the photoelectric conversion element, the avalanche phenomenon causes a large amplification of electrons relative to the amount of incident light. In addition, since selenium-based materials have a high light absorption coefficient, they can be used as sensors with high sensitivity. This has the advantage that the electric conversion layer 61 can be easily made thin.

[0081] The selenium-based material may be amorphous or crystalline selenium. For example, amorphous selenium can be obtained by forming a film of amorphous selenium and then performing a heat treatment. By making the grain size of the crystalline selenium smaller than the pixel pitch, the characteristic variation between pixels is reduced. Crystalline selenium also has a higher spectral sensitivity to visible light than amorphous selenium. It has the characteristics of high optical absorption coefficient.

[0082] The photoelectric conversion layer 61 is a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, the layer may contain a compound of copper, indium, gallium, and selenium (CIGS). In CIS and CIGS, the avalanche phenomenon can be utilized in the same way as in the case of a single layer of selenium. It is possible to form a photoelectric conversion element capable of

[0083] The photoelectric conversion element 60 using a selenium-based material includes an electrode 66 formed of, for example, a metal material. The photoelectric conversion layer 61 may be disposed between the C IS and CIGS are p-type semiconductors, and require the use of n-type cadmium sulfide to form a junction. Alternatively, zinc sulfide or the like may be provided in contact with the surface of the insulating layer.

[0084] In order to generate the avalanche phenomenon, a relatively high voltage (e.g., 10 It is preferable to apply a voltage of 100 V or more to the OS transistor. Because it has high withstand voltage characteristics, it is easy to apply a relatively high voltage to the photoelectric conversion element. Therefore, we have developed an OS transistor with high drain withstand voltage and a selenium-based material for photoelectric conversion. By combining this with a photoelectric conversion element with a layer of SiO2, a highly sensitive and reliable imaging device can be obtained. It is possible.

[0085] In FIG. 9A, the photoelectric conversion layer 61 and the light-transmitting conductive layer 62 are not separated between the pixel circuits. However, as shown in FIG. 11(A), the circuits may be separated from each other. In addition, a partition 67 made of an insulator is provided in the area between the pixels that does not have the electrode 66, and a photoelectric conversion It is preferable to prevent cracks from occurring in the layer 61 and the transparent conductive layer 62. As shown in FIG. 9B, the partition wall 67 may not be provided. Although the diagram illustrates a configuration in which a wiring 88 and a conductor 81 are interposed between the conductive layer 62 and the wiring 72, As shown in FIGS. 11C and 11D, the transparent conductive layer 62 and the wiring 72 are in direct contact with each other. This is also fine.

[0086] In addition, the electrodes 66 and the wiring 72 may be multi-layered. For example, as shown in FIG. The electrode 66 is made of two layers, a conductive layer 66a and a conductive layer 66b, and the wiring 72 is made of conductive layers 72a and In the configuration of FIG. 12(A), for example, The conductive layer 66a and the conductive layer 72a are formed by selecting a low-resistance metal or the like. The conductive layer 72a is preferably formed by selecting a metal or the like having good contact characteristics with the photoelectric conversion layer 61. With such a structure, the electrical characteristics of the photoelectric conversion element can be improved. In addition, some metals may cause electrolytic corrosion when in contact with the transparent conductive layer 62. Even if such a metal is used for the conductive layer 72a, electrolytic corrosion is prevented by using the conductive layer 72b. It can be prevented.

[0087] The conductive layer 66b and the conductive layer 72b are made of, for example, molybdenum or tungsten. The conductive layer 66a and the conductive layer 72a may be made of, for example, aluminum or titanium. A laminate such as titanium sandwiched between aluminum can be used.

[0088] Also, the insulating layer 82 may have a multi-layer structure. For example, as shown in FIG. The insulating layer 82 has an insulating layer 82a and an insulating layer 82b, and the insulating layer 82a and the insulating layer 8 If the etching rate of the conductor 81 is different from that of the layer 2b, the conductor 81 will have a step. In the case where other insulating layers used for the interlayer insulating film or the planarizing film are multi-layered, the conductor 81 is also In this embodiment, the insulating layer 82 has two layers. The insulating layers 82 and other layers may be made up of three or more layers.

[0089] The partition wall 67 can be formed using an inorganic insulator, an insulating organic resin, or the like. The partition 67 is provided for blocking light from a transistor or the like and / or for reducing the light receiving capacity per pixel. The part may be colored black or the like to define its area.

[0090] The photoelectric conversion element 60 is made of a pin A diode element or the like may also be used.

[0091] For example, FIG. 13 shows an example in which a pin-type thin-film photodiode is used as the photoelectric conversion element 60. The photodiode is made up of a p-type semiconductor layer 65, an i-type semiconductor layer 64, and an n-type semiconductor layer 65. The i-type semiconductor layer 64 is made of amorphous silicon. In addition, it is preferable to use the following for the n-type semiconductor layer 63 and the p-type semiconductor layer 65. Amorphous silicon or microcrystalline silicon containing dopants that impart each conductivity type is used. Photodiodes that use amorphous silicon as a photoelectric conversion layer can detect visible light waves. It has high sensitivity over a long range and is easy to detect weak visible light.

[0092] In the photoelectric conversion element 60 shown in FIG. 13, a p-type semiconductor layer 65 is provided in the transistor 51 and the transistor The n-type semiconductor layer 51 is electrically connected to an electrode 66 which is electrically connected to the n-type semiconductor layer 53. The conductor layer 63 is electrically connected to the wiring 72 via the conductor 81 .

[0093] The configuration of the photoelectric conversion element 60 having the form of a pin-type thin-film photodiode, The photoelectric conversion element 60 and the wiring are connected in the manner shown in FIG. The examples shown in (E) and (F) may also be used. The connection form of 60 and the wiring is not limited to these, and other forms may be used.

[0094] FIG. 14A shows a photoelectric conversion element 60 having an n-type semiconductor layer 63 and a transparent conductive layer 62 in contact therewith. The transparent conductive layer 62 acts as an electrode and transmits the output current of the photoelectric conversion element 60. It can be improved.

[0095] The transparent conductive layer 62 is made of, for example, indium tin oxide or indium tin oxide containing silicon. zinc oxide, zinc oxide, zinc oxide containing gallium, aluminum oxide Zinc oxide, tin oxide, tin oxide containing fluorine, tin oxide containing antimony, or graphene The transparent conductive layer 62 is not limited to a single layer, but may be a laminate of different films. That's fine.

[0096] FIG. 14B shows a case where the n-type semiconductor layer 63 of the photoelectric conversion element 60 and the wiring 88 are directly connected to each other. This is the configuration.

[0097] FIG. 14C shows a photoelectric conversion element 60 having an n-type semiconductor layer 63 and a transparent conductive layer 62 in contact therewith. The wiring 88 and the light-transmitting conductive layer 62 are electrically connected to each other.

[0098] FIG. 14D shows an opening in which the n-type semiconductor layer 63 is exposed in the insulating layer covering the photoelectric conversion element 60. and a transparent conductive layer 62 covering the opening and a wiring 88 are electrically connected to each other. It is.

[0099] FIG. 14E shows a configuration in which a conductor 81 is provided penetrating the photoelectric conversion element 60. In this configuration, the wiring 72 is electrically connected to the n-type semiconductor layer 63 via a conductor 81. In the drawing, the wiring 72 and the electrode 66 are apparently electrically connected via the p-type semiconductor layer 65. However, since the lateral resistance of the p-type semiconductor layer 65 is high, Therefore, if an appropriate distance is provided between the wiring 72 and the electrode 66, the resistance between them will be extremely high. Therefore, the photoelectric conversion element 60 does not function as a diode without the anode and cathode being short-circuited. The conductor 81 electrically connected to the n-type semiconductor layer 63 can have the following characteristics. may be plural.

[0100] FIG. 14F shows a structure in which the n-type semiconductor layer 63 is in contact with the photoelectric conversion element 60 shown in FIG. The light-transmitting conductive layer 62 is provided.

[0101] In the photoelectric conversion element 60 shown in FIG. 14(D), FIG. 14(E), and FIG. 14(F), Since the light receiving region does not overlap with wiring, etc., this has the advantage that a wide light receiving area can be secured.

[0102] As shown in FIG. 15, the photoelectric conversion element 60 has a silicon substrate 30 as a photoelectric conversion layer. A photodiode may also be used.

[0103] The photoelectric conversion element 60 formed using the above-mentioned selenium-based material or amorphous silicon is formed by film formation. It is manufactured using general semiconductor manufacturing processes such as the process of lithography and etching. In addition, selenium-based materials have high resistance, and as shown in FIG. The transfer layer 61 may be configured not to be separated between the circuits. The imaging device can be manufactured at a high yield and low cost. When forming a photodiode with 0 as the photoelectric conversion layer, the polishing process, bonding process, etc. What kind of difficult process is required?

[0104] The imaging device according to one aspect of the present invention has a structure in which silicon substrates 30 on which circuits are formed are stacked. For example, as shown in FIG. 16(A), a silicon substrate 30 having an active region may be formed. A layer 1400 having transistors 31 and 32 overlaps with the pixel circuit. It can be said that:

[0105] The circuit formed on the silicon substrate 30 has a function of reading out the signal output from the pixel circuit and a function of detecting the signal. For example, the circuit shown in FIG. 16B can have a function of converting a signal. The transistor 31 (n- The gate electrodes of transistor 31 (p-ch type) and transistor 32 (p-ch type) are electrically connected. In addition, one of the source electrode or the drain electrode of one transistor is connected to the other transistor. The transistor is electrically connected to either the source electrode or the drain electrode of the transistor. The other of the source electrode and the drain electrode of the transistor is electrically connected to a separate wiring.

[0106] The silicon substrate 30 is not limited to a bulk silicon substrate, but may be a germanium or silicon gel substrate. manium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, Substrates made of gallium nitride or organic semiconductor materials can also be used.

[0107] As shown in FIG. 16C, the transistors 31 and 32 are made of silicon. The active layer 35 may be a polycrystalline silicon thin film transistor. Silicon or SOI (Silicon on Insulator) single crystal silicon It is possible.

[0108] Here, as shown in FIG. 15 and FIG. 16A, a transistor including an oxide semiconductor The area where a Si transistor (a Si photodiode in Fig. 15) is formed. An insulating layer 80 is provided between the regions.

[0109] Hydrogen in the insulating layer provided near the active regions of the transistors 31 and 32 The hydrogen terminates the dangling bonds of silicon. This has the effect of improving the reliability of the transistor 32. Hydrogen in the insulating layer provided in the vicinity of the oxide semiconductor layer, which is a conductive layer, is introduced into the oxide semiconductor layer. Therefore, the hydrogen is one of the factors that cause carrier generation. Therefore, it is necessary to use a silicon-based semiconductor material. When a layer having an OS transistor and a layer having an OS transistor are stacked, It is preferable to provide an insulating layer 80 between the insulating layer 8 and the substrate 10, which has a function of preventing hydrogen diffusion. 0, hydrogen is trapped in one layer, forming transistors 31 and 32. The reliability of the semiconductor device can be improved. In addition, the diffusion of hydrogen from one layer to the other layer is suppressed. This also improves the reliability of the transistor 51 and the like.

[0110] The insulating layer 80 may be made of, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria stabilized zirconia (YSZ), etc. can be used.

[0111] In the configuration shown in FIG. 16(A), a circuit (e.g. , driving circuit), the transistor 51, etc., and the photoelectric conversion element 60 are formed so as to overlap each other. This allows the pixel density to be increased, which means that the resolution of the image pickup device can be improved. For example, imaging devices with a pixel count of 4K2K, 8K4K, or 16K8K can be used. The transistor 52 and the transistor 54 and the like have an overlapping area with the transistors 51 and the photoelectric conversion element 60. Good too.

[0112] In addition, the imaging device shown in FIG. 16A has a structure in which no photoelectric conversion element is provided on the silicon substrate 30. Therefore, the photoelectric conversion element 60 can be formed without being affected by various transistors and wiring. Therefore, a light path for the light source can be secured, and pixels with a high aperture ratio can be formed.

[0113] An imaging device according to one embodiment of the present invention can have a structure shown in FIG.

[0114] The imaging device shown in FIG. 17 is a modified example of the imaging device shown in FIG. 16(A), and includes an OS transistor. The figure shows an example of constructing a CMOS inverter using a silicon transistor and a silicon transistor.

[0115] Here, the transistor 32, which is a Si transistor provided in the layer 1400, is a p-ch type. The OS transistor 31 provided in the layer 1100 is an n-channel transistor. By providing only the −ch type transistor on the silicon substrate 30, well formation and n-type impurity Steps such as layer formation can be omitted.

[0116] In the imaging device shown in FIG. 17, selenium is used for the photoelectric conversion element 60. As in 3, a pin type thin film photodiode may be used.

[0117] In the imaging device shown in FIG. 17, the transistor 31 is a transistor formed in the layer 1100. The transistor 51 and the transistor 53 can be fabricated in the same process. The manufacturing process of the device can be simplified.

[0118] Note that the configuration of the transistor and the photoelectric conversion element included in the imaging device in this embodiment is This is just an example. For example, one or more of the transistors 51 to 54 may be It may also be configured as a transistor having silicon or the like in the active region or active layer. The transistor 31 and / or the transistor 32 are formed of an oxide semiconductor layer as an active layer. The transistor may also have the following structure:

[0119] FIG. 18A is a cross-sectional view of an example of an imaging device with a color filter or the like added thereto. The cross-sectional view shows a part of an area having pixel circuits for three pixels. On the layer 1200 to be formed, an insulating layer 2500 is formed. The insulating layer 2500 is irradiated with visible light. A highly transparent silicon oxide film can be used for the passivation. The anti-reflection film may be a silicon nitride film. A configuration in which a dielectric film such as fluorine is laminated may also be used.

[0120] A light-shielding layer 2510 may be formed on the insulating layer 2500. The light-shielding layer 2510 may include an upper The light shielding layer 2510 has a function of preventing the mixing of colors of light passing through the color filter. A metal layer such as tungsten or aluminum, or a dielectric layer that functions as an anti-reflective coating The film may be laminated.

[0121] An organic resin layer 2520 is provided on the insulating layer 2500 and the light-shielding layer 2510 as a planarizing film. In addition, a color filter 2530 is formed for each pixel. For example, , color filter 2530a, color filter 2530b, and color filter 2530 c: R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), etc. By assigning colors, a color image can be obtained.

[0122] A light-transmitting insulating layer 2560 or the like may be provided on the color filter 2530. do.

[0123] Also, as shown in FIG. 18B, an optical conversion layer 255 is used instead of the color filter 2530. 0 may be used. With this configuration, images in various wavelength regions can be obtained. The imaging device can be configured as follows.

[0124] For example, if a filter that blocks light with wavelengths shorter than visible light is used for the optical conversion layer 2550, infrared The optical conversion layer 2550 can be used as an imaging device. If a filter having such a structure is used, a far-infrared imaging device can be obtained. If a filter that blocks light with wavelengths longer than visible light is used, it can be used as an ultraviolet imaging device. .

[0125] In addition, if a scintillator is used for the optical conversion layer 2550, it is possible to use a radiation detector such as an X-ray imaging device. It is possible to make an imaging device that can obtain an image that visualizes the strength of lines. When radiation strikes a scintillator, it emits a large amount of light due to a phenomenon called photoluminescence. The light is converted into light (fluorescence) such as visible light or ultraviolet light. Image data is obtained by detecting the radiation. A position may also be used.

[0126] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy and These include substances that emit visible light or ultraviolet light. For example, Gd2O2S:Tb, Gd2O2S:P r, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, C eF3, LiF, LiI, and ZnO dispersed in resin or ceramics can be used. Cut.

[0127] In the photoelectric conversion element 60 using a selenium-based material, radiation such as X-rays is directly converted into an electric charge. Since the light can be converted, a configuration can be made in which a scintillator is not required.

[0128] Color filter 2530a, color filter 2530b, and color filter 2530c A microlens array 2540 may be provided on the top. The light passing through each lens passes through the color filter directly below and is irradiated onto the photoelectric conversion element 60. In addition, the area other than the layer 1200 shown in FIGS. Let's say the layer is 1600.

[0129] A specific configuration of the imaging device shown in FIG. 18C is as follows, taking the imaging device shown in FIG. 9A as an example: 19. Taking the image pickup device shown in FIG. 15 as an example, the image pickup device shown in FIG. 20 It becomes like this.

[0130] In addition, the imaging device according to one embodiment of the present invention includes a diffraction grating 1500 and a The image of the object through the diffraction grating 1500 (diffraction image) is captured by the pixel. The input image (image of the subject) can be constructed by performing calculations on the captured image at each pixel. In addition, the cost of the imaging device can be reduced by using a diffraction grating 1500 instead of a lens. It can be done.

[0131] The diffraction grating 1500 can be made of a material having optical transparency. For example, silicon oxide. An inorganic insulating film such as a silicon oxide nitride film or an acrylic resin film can be used. Alternatively, an organic insulating film such as a resin or a polyimide resin may be used. It may be laminated with an organic insulating film.

[0132] The diffraction grating 1500 can be formed by a lithography process using a photosensitive resin or the like. It can also be formed by using a lithography process and an etching process. It can also be formed by using nanoimprint lithography, laser scribing, or the like. do.

[0133] A distance X may be provided between the diffraction grating 1500 and the microlens array 2540. The interval X can be set to 1 mm or less, preferably 100 μm or less. The partition may be a space, or a light-transmitting material may be provided as a sealing layer or an adhesive layer. For example, an inert gas such as nitrogen or a rare gas can be sealed in the gap. Alternatively, a resin such as acrylic resin, epoxy resin, or polyimide resin may be provided in the space. A liquid such as silicone oil may be used. Even when the color filter 2530 and the diffraction grating 1500 are not arranged in the same manner, the distance X is set between the color filter 2530 and the diffraction grating 1500. It is okay.

[0134] The imaging device may also be curved as shown in FIG. 23(A1) and FIG. 23(B1). FIG. 23(A1) shows a state in which the imaging device is bent in the direction of the two-dot chain line X1-X2 in the same figure. FIG. 23(A2) shows the portion indicated by the two-dot chain line X1-X2 in FIG. 23(A1). FIG. 23(A3) is a cross-sectional view of the area indicated by the two-dot chain line Y1-Y2 in FIG. FIG.

[0135] FIG. 23(B1) shows a case where the imaging device is bent in the direction of the two-dot chain line X3-X4 in the same figure, and FIG. 23(B2) shows a state where the wire is bent in the direction of the two-dot chain line Y3-Y4 in the figure. FIG. 23(B3) is a cross-sectional view of a portion indicated by a two-dot chain line X3-X4 in FIG. 23(B1) is a cross-sectional view of a portion indicated by a two-dot chain line Y3-Y4 in FIG. 23(B1).

[0136] By curving the imaging device, it is possible to reduce the field curvature and astigmatism. This makes it easier to design the lenses and other components used in combination with the imaging device. For example, The number of lenses required for aberration correction can be reduced, enabling miniaturization of semiconductor devices using imaging devices. It is possible to easily reduce the size and weight of the camera. In addition, it is possible to improve the quality of the captured image. Cut.

[0137] Note that one embodiment of the present invention has been described in this embodiment. An embodiment of the present invention will be described below. However, the embodiment of the present invention is not limited to these. That is, various inventive aspects are described in this and other embodiments. Therefore, one embodiment of the present invention is not limited to a specific embodiment. However, the present invention is not limited to this embodiment. In some cases or depending on the situation, one aspect of the present invention may be applied to an imaging device. For example, one embodiment of the present invention may be applied to a semiconductor device having another function. For example, in one embodiment of the present invention, a channel formation region, a source / drain region, etc. of a transistor However, one embodiment of the present invention is not limited thereto. In some cases, or depending on the situation, various transistors in one aspect of the present invention may be used. A transistor channel forming region, a transistor source drain region, etc. may comprise a variety of semiconductors. Various transistors, channel formation regions of transistors, or The source and drain regions of the transistor are made of, for example, silicon, germanium, silicon gel, etc. manium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, The semiconductor may have at least one of gallium nitride and organic semiconductors. For example, in some cases or circumstances, various transistors in one aspect of the present invention may be A transistor channel forming region, a transistor source drain region, etc. For example, depending on the circumstances, the oxide semiconductor may not be included. In response, the transistor 51 and / or the transistor 53 may have an oxide layer in the active layer. The semiconductor layer may not be included.

[0138] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0139] (Embodiment 2) In this embodiment, a transistor including an oxide semiconductor that can be used in one embodiment of the present invention will be described. The following description will be given with reference to the drawings. Note that, in the drawings in this embodiment, the For ease of illustration, some elements may be enlarged, reduced, or omitted.

[0140] 24A and 24B are a top view and a cross-sectional view of a transistor 101 of one embodiment of the present invention. FIG. 24(A) is a top view, and FIG. 24(A) is a cross section taken along the dashed line B1-B2 shown in FIG. corresponds to FIG. 24(B). Also, the cross section in the direction of the dashed line B3-B4 shown in FIG. 24(A) is 26(A). The dashed line B1-B2 direction is the channel length direction, and the dashed line B The 3-B4 direction is called the channel width direction.

[0141] The transistor 101 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 140 electrically connected to the oxide semiconductor layer 130; layer 150, the oxide semiconductor layer 130, the conductive layer 140, and the insulating layer 1 60, a conductive layer 170 in contact with the insulating layer 160, a conductive layer 140, a conductive layer 150, an insulating layer 1 60, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. In addition, the insulating layer 180 may have a function as a planarizing film, if necessary. .

[0142] The conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is a gate insulator. The insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0143] In FIG. 24B, a region 231 is a source region, a region 232 is a drain region, and a region 233 is The region 231 and the region 232 can function as a channel forming region. 40 and conductive layer 150, respectively, as conductive layer 140 and conductive layer 150. By using a conductive material that easily bonds with oxygen, the resistance of the regions 231 and 232 can be reduced. can be done.

[0144] Specifically, the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150. Oxygen vacancies occur in the oxide semiconductor layer 130, and the oxygen vacancies and the remaining oxygen in the oxide semiconductor layer 130 Due to interaction with hydrogen that is retained or diffuses from the outside, regions 231 and 232 have low resistance. The n-type of the resistor.

[0145] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. In addition, the term "electrode layer" can be replaced with "wiring." can.

[0146] The conductive layer 170 is illustrated as being formed of two layers, a conductive layer 171 and a conductive layer 172. However, it may be a single layer or a laminate of three or more layers. The same can be applied to transistors.

[0147] Although the conductive layer 140 and the conductive layer 150 are illustrated as being formed as a single layer, they may be formed as a laminate of two or more layers. This structure can be applied to other transistors described in this embodiment. .

[0148] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 24(C) is a top view of the transistor 102, and the dashed line C1-C The cross sections in the two directions correspond to FIG. 24(D). Also, the dashed line C3-C4 shown in FIG. The cross section in the direction corresponds to FIG. 26(B). The direction of the dashed dotted line C3-C4 is referred to as the channel width direction.

[0149] The transistor 102 is formed by connecting the end of the insulating layer 160, which acts as a gate insulating film, and the gate electrode layer 101, except that the ends of the conductive layer 170 acting as a gate electrode are not aligned with each other. The transistor 102 has a structure in which the conductive layer 140 and the conductive layer 150 are insulating layers. Since the edge layer 160 is widely covered, the conductive layer 140, the conductive layer 150, and the conductive layer 170 are The resistance between the gate and the gate electrode is high, and the gate leakage current is low.

[0150] The transistor 101 and the transistor 102 are formed by a conductive layer 170, a conductive layer 140, and a conductive The top gate structure has a region where the gate insulating layer 150 overlaps the gate insulating layer 150. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacitance. In this structure, since no offset region is formed in the oxide semiconductor layer 130, the on-current is high. This makes it easier to form small transistors.

[0151] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 24(E) is a top view of the transistor 103, and the dashed line D1-D1 shown in FIG. The cross sections in the two directions correspond to FIG. 24(F). Also, the dashed line D3-D4 shown in FIG. 24(E) The cross section in the direction corresponds to FIG. 26(A). The direction of the dashed dotted line D1-D2 is the channel rectangular direction. The direction of the dashed dotted line D3-D4 is referred to as the channel width direction.

[0152] The transistor 103 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; an insulating layer 160 in contact with the oxide semiconductor layer 130; and an insulating layer covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170. An edge layer 175, an insulating layer 180 in contact with the insulating layer 175, and a layer including the insulating layer 175 and the insulating layer 180. A conductive layer 140 electrically connected to the oxide semiconductor layer 130 through an opening provided in the and a conductive layer 150. In addition, an insulating layer 180, a conductive layer 140, and a conductive layer An insulating layer (flattening film) or the like may be provided in contact with 150 .

[0153] The conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is a gate insulator. The insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0154] In FIG. 24(F), a region 231 is a source region, a region 232 is a drain region, and a region 233 is The region 231 and the region 232 can function as a channel forming region. 75. For example, if an insulating material containing hydrogen is used as the insulating layer 175, the region 231 And the resistance of the region 232 can be reduced.

[0155] Specifically, the process up to the formation of the insulating layer 175 generates a thin film in the region 231 and the region 232. The oxygen vacancies caused by the oxygen vacancies interact with hydrogen diffusing from the insulating layer 175 into the regions 231 and 232. As a result, the regions 231 and 232 become n-type with low resistance. As the material, for example, silicon nitride or aluminum nitride can be used.

[0156] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 25(A) is a top view of the transistor 104, and the dashed line E1-E The cross sections in the two directions correspond to FIG. 25(B). Also, the dashed line E3-E4 shown in FIG. The cross section in the direction corresponds to FIG. 26(A). The direction of the dashed line E1-E2 is the channel rectangular direction. The direction of the dashed dotted line E3-E4 is referred to as the channel width direction.

[0157] In the transistor 104, the conductive layer 140 and the conductive layer 150 are disposed at the end of the oxide semiconductor layer 130. The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 is in contact with the transistor 103 so as to cover the transistor 103.

[0158] Regions 331 and 334 shown in FIG. 25B are source regions, and regions 332 and 333 are The region 35 can function as a drain region, and the region 333 can function as a channel forming region.

[0159] Regions 331 and 332 correspond to regions 231 and 23 in transistor 101. As with 2, the resistance can be reduced.

[0160] Regions 334 and 335 correspond to regions 231 and 232 in transistor 103. In addition, the resistance of the region 334 and the region 335 in the channel length direction can be reduced in the same manner as in the region 2. When the length of the region 335 is 100 nm or less, preferably 50 nm or less, the gate electric field The on-current does not decrease significantly due to the contribution of the low In some cases, resistance may not be achieved.

[0161] The transistor 103 and the transistor 104 are formed by the conductive layer 170 and the conductive layer 140 and the conductive The self-aligned structure does not have an area where the conductive layer 150 overlaps. The parasitic capacitance between the gate electrode layer and the source and drain electrode layers of the transistor is extremely small. This makes it suitable for high-speed operation.

[0162] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 25(C) is a top view of the transistor 105, and the dashed line F1-F shown in FIG. The cross sections in the two directions correspond to FIG. 25(D). Also, the dashed line F3-F4 shown in FIG. 25(C) The cross section in the direction corresponds to FIG. 26(A). The direction of the dashed line F1-F2 is the channel rectangular direction. The direction of the dashed dotted line F3-F4 is referred to as the channel width direction.

[0163] The transistor 105 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; the oxide semiconductor layer 130, the conductive layer 141, and the insulating layer 160 in contact with the conductive layer 151; The conductive layer 170 in contact with the insulating layer 160, the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, insulating layer 160, and conductive layer 170; insulating layer 175 in contact with insulating layer 175; The insulating layer 175 and the insulating layer 180 are electrically conductive through openings provided in the insulating layer 175 and the insulating layer 180. Conductive layers 142 and 15 are electrically connected to layers 141 and 151, respectively. 2. In addition, if necessary, the insulating layer 180, the conductive layer 142, and the conductive layer 152 are in contact with each other. The insulating layer may be provided.

[0164] The conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and in contact with the side surfaces of the oxide semiconductor layer 130. This is not a structure that can be used in this way.

[0165] The transistor 105 includes a conductive layer 141 and a conductive layer 151, an insulating layer 175, and a and an opening provided in the insulating layer 180, and the conductive layer 14 is formed through the opening. 1 and the conductive layer 151 are electrically connected to the conductive layer 142 and the conductive layer 152, respectively. The conductive layer 140 (conductive layer 141) has a structure similar to that of the transistor 101. and conductive layer 142) can act as a source electrode layer, and conductive layer 150 (conductive Layer 151 and conductive layer 152) may act as a drain electrode layer.

[0166] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 25(E) is a top view of the transistor 106, and the dashed line G1-G The cross sections in the two directions correspond to FIG. 25(F). Also, the dashed line G3-G4 shown in FIG. The cross section in the direction corresponds to FIG. 26(A). The direction of the dashed line G1-G2 is the channel length. The direction of the dashed dotted line G3-G4 is referred to as the channel width direction.

[0167] The transistor 106 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; a conductive layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130, and a conductive layer 162 in contact with the insulating layer 160; layer 170, an insulating layer 120, an oxide semiconductor layer 130, a conductive layer 141, a conductive layer 151, an insulating layer 160, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. The conductive layer 141 and the conductive layer 142 are formed through the openings provided in the insulating layer 175 and the insulating layer 180. The conductive layer 142 and the conductive layer 152 are electrically connected to the layer 151, respectively. If necessary, an insulating layer 180, an insulating layer (planarizing film) in contact with the conductive layer 142 and the conductive layer 152, ) and the like.

[0168] The conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and in contact with the side surfaces of the oxide semiconductor layer 130. This is not a structure that can be used in this way.

[0169] The transistor 106 has the same structure as the transistor 106 except that it has a conductive layer 141 and a conductive layer 151. The conductive layer 140 (conductive layer 141 and conductive layer 142) has a structure similar to that of the capacitor 103. The conductive layer 150 (conductive layer 151 and conductive layer 15 2) can act as a drain electrode layer.

[0170] In the configuration of transistor 105 and transistor 106, conductive layer 140 and conductive layer 1 Since the insulating layer 120 is not in contact with the conductive layer 140, the oxygen in the insulating layer 120 is The oxide semiconductor layer 130 is less likely to be deprived of oxygen by the conductive layer 150. This makes it easier to supply the raw material.

[0171] Regions 231 and 232 in transistor 103, transistors 104 and In the region 334 and the region 335 of the transistor 106, oxygen vacancies are formed to increase the electrical conductivity. As the impurity that forms oxygen vacancies in the oxide semiconductor layer, Examples of these elements include phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, and helix. Um, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, One or more selected from zinc and carbon can be used. The methods of adding the metal oxide include plasma treatment, ion implantation, ion doping, plasma ion implantation, etc. A deposition ion implantation method or the like can be used.

[0172] When the above-mentioned element is added to the oxide semiconductor layer as an impurity element, the metal in the oxide semiconductor layer The bond between the element and oxygen is broken, and oxygen vacancies are formed. The interaction between the electron vacancies and hydrogen remaining in the oxide semiconductor layer or added later causes an oxide The conductivity of the semiconductor layer can be increased.

[0173] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by the addition of an impurity element, the oxygen vacancies Hydrogen enters the loss site and a donor level is formed near the conduction band. As a result, the oxide conductor Here, an oxide semiconductor that has been made into a conductor is referred to as an oxide conductor. Note that an oxide conductor has a light-transmitting property like an oxide semiconductor.

[0174] An oxide conductor is a degenerate semiconductor, and the conduction band edge and the Fermi level are coincident or nearly coincident. Therefore, the oxide conductor layer and the source and drain electrode layers are The contact between the oxide conductor layer and the source electrode layer and the conductive layer that functions as a gate electrode is an ohmic contact. In addition, the contact resistance between the conductive layer functioning as the drain electrode layer and the conductive layer can be reduced.

[0175] The transistor of one embodiment of the present invention is shown in FIG. 26(C) and (D) are cross-sectional views in the channel length direction and the channel width direction, respectively. As shown in the cross-sectional view of the upper side, a conductive layer 173 is provided between the oxide semiconductor layer 130 and the substrate 115. By using the conductive layer 173 as a second gate electrode layer (back gate), It is possible to increase the on-current and control the threshold voltage. In the cross-sectional views shown in (C), (D), (E), and (F), the width of the conductive layer 173 is The conductive layer 173 may be shorter than the semiconductor layer 130. It may be shorter than that.

[0176] In order to increase the on-current, for example, the conductive layer 170 and the conductive layer 173 are set to the same potential, and a double In order to control the threshold voltage, the MOSFET is driven as a gate transistor. A constant potential different from that of the conductive layer 170 may be applied to the conductive layer 173. To make the conductive layers 170 and 173 have the same potential, for example, as shown in FIG. 73 may be electrically connected via a contact hole.

[0177] In the transistors 101 to 106 in FIG. 24 and FIG. 25, an oxide semiconductor Although an example in which the conductor layer 130 is a single layer is illustrated, the oxide semiconductor layer 130 may be a multilayer. The oxide semiconductor layer 130 of the transistors 101 to 106 is 28(D) or 28(E) can be replaced with the oxide semiconductor layer 130 shown in FIG. Cut.

[0178] FIG. 28A is a top view of the oxide semiconductor layer 130, and FIGS. 28B and 28C are top views of the oxide semiconductor layer 130 having a two-layer structure. 28(D) and (E) are cross-sectional views of an oxide semiconductor layer 130 having a three-layer structure. 1 is a cross-sectional view of an oxide semiconductor layer 130 having a structure.

[0179] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are Oxide semiconductor layers having different compositions can be used.

[0180] The transistor of one embodiment of the present invention may have a structure shown in FIGS. 29(A) is a top view of the transistor 107, and the dashed line H1-H The cross sections in the two directions correspond to FIG. 29(B). Also, the dashed line H3-H4 shown in FIG. 31A. The dashed line H1-H2 direction corresponds to the channel length direction. The direction of the dashed dotted line H3-H4 is referred to as the channel width direction.

[0181] The transistor 107 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 140 and the conductive layer 150 connected to each other, 0, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170; and an insulating layer 180 that functions as a flattening film, if necessary. A function may be added.

[0182] The transistor 107 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 140 and the conductive layer 150 are the insulating layer 160. Except for the fact that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between It has a similar configuration to the transistor 101 .

[0183] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 29(C) is a top view of the transistor 108, and the dashed line I1-I The cross sections in the two directions correspond to FIG. 29(D). Also, the dashed line I3-I4 shown in FIG. 31B. The direction of the dashed dotted line I1-I2 corresponds to the channel length direction. The direction of the dashed dotted line I3-I4 is referred to as the channel width direction.

[0184] In the transistor 108, the insulating layer 160 and the end of the oxide semiconductor layer 130c are connected to the conductive layer 17. It differs from transistor 107 in that it does not coincide with the end of 0.

[0185] The transistor of one embodiment of the present invention may have the structure shown in FIGS. 29(E) is a top view of the transistor 109, and the dashed line J1-J shown in FIG. The cross sections in the two directions correspond to FIG. 29(F). Also, the dashed line J3-J4 shown in FIG. 29(E) 31A corresponds to the cross section in the direction of the dashed dotted line J1-J2. The direction of the dashed dotted line J3-J4 is referred to as the channel width direction.

[0186] The transistor 109 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. A stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and an oxide semiconductor layer in contact with the stack. a second insulating layer 160 in contact with the oxide semiconductor layer 130c; 0, the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 An insulating layer 175 covers the conductive layer 170, an insulating layer 180 contacts the insulating layer 175, and the insulating layer 175 is and a conductive layer 14 electrically connected to the stack through an opening in the insulating layer 180. 0 and conductive layer 150. In addition, an insulating layer 180, a conductive layer 140 and An insulating layer (planarizing film) in contact with the conductive layer 150 may be provided.

[0187] The transistor 109 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 has a second insulating layer 130c.

[0188] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 30(A) is a top view of the transistor 110, and the dashed line K1-K The cross sections in the two directions correspond to FIG. 30(B). Also, the dashed line K3-K4 shown in FIG. 31A corresponds to the cross section in the direction of the dashed dotted line K1-K2. The direction of the dashed dotted line K3-K4 is referred to as the channel width direction.

[0189] The transistor 110 has two oxide semiconductor layers 130 in the regions 331 and 332. In the region 333, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 104 has a similar structure to the transistor 104, except that the transistor 104 has a second insulating layer 130c.

[0190] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 30(C) is a top view of the transistor 111, and the dashed line L1-L The cross sections in the two directions correspond to FIG. 30(D). Also, the dashed line L3-L4 shown in FIG. 31(A). The direction of the dashed dotted line L1-L2 corresponds to the channel length direction. The direction of the dashed dotted line L3-L4 is referred to as the channel width direction.

[0191] The transistor 111 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 141 and the conductive layer 151 connected to each other, and the laminate, the conductive layer 141 and the conductive layer 15 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the laminate, the conductive layer 141, the conductive layer 151, the oxide an insulating layer 175 in contact with the semiconductor layer 130c, the insulating layer 160, and the conductive layer 170; The insulating layer 180 in contact with the insulating layer 175 and the openings provided in the insulating layer 175 and the insulating layer 180 are Conductive layer 142 and conductive layer 151 are electrically connected to conductive layer 141 and conductive layer 151, respectively. The conductive layer 152 may also include an insulating layer 180, a conductive layer 142, and a conductive layer 153. An insulating layer (flattening film) or the like may be provided in contact with 52 .

[0192] The transistor 111 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 141 and the conductive layer 151 are the insulating layer 16. 0, except that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between The transistor has a similar structure to that of the transistor 105 .

[0193] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 30(E) is a top view of the transistor 112, and the dashed line M1-M The cross sections in the two directions correspond to FIG. 30(F). Also, the dashed line M3-M4 shown in FIG. 31A corresponds to the cross section in the direction of the dashed dotted line M1-M2. The direction of the dashed dotted line M3-M4 is referred to as the channel width direction.

[0194] The transistor 112 is configured as follows: The oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b). In the region 333, the oxide semiconductor layer 130 is made up of three layers (the oxide semiconductor layer 130a, the oxide 130a and 130b, and an oxide semiconductor layer 130c). They have a similar configuration.

[0195] The transistor according to one embodiment of the present invention is shown in FIG. 31(C) and (D) are cross-sectional views in the channel length direction and the channel width direction, respectively. As shown in the cross-sectional view of the upper side, a conductive layer 173 is provided between the oxide semiconductor layer 130 and the substrate 115. By using the conductive layer as a second gate electrode layer (back gate), It is possible to increase the on-state current and control the threshold voltage. In the cross-sectional views shown in (C), (D), (E), and (F), the width of the conductive layer 173 is set to 0.1 mm. The conductive layer 173 may be shorter than the conductive layer 130. may also be shortened.

[0196] The conductive layer 140 (source electrode layer) and the conductive layer 15 in the transistor according to one embodiment of the present invention 33(A) and 33(B) (the oxide semiconductor layer 130, As shown in FIG. 1, only the conductive layer 140 and the conductive layer 150 are shown. O S ) of the conductive layer 140 and the conductive layer 150. SD ) may be formed long However, it may be formed short. OS ≧W SD (W SD W OS (below) The gate electric field is easily applied to the entire oxide semiconductor layer 130, and the electrical characteristics of the transistor are improved. Also, as shown in FIG. 33(C), the conductive layer 140 and the conductive layer The insulating film 150 may be formed only in the region overlapping with the oxide semiconductor layer 130 .

[0197] In the transistors of one embodiment of the present invention (transistors 101 to 112), In either configuration, the conductive layer 170, which is the gate electrode layer, is connected to the insulating layer 170, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction via the gate insulating film 160, and the on-current Such a transistor structure is called a surrounded channel transistor. This is called the (s-channel) structure.

[0198] A transistor having an oxide semiconductor layer 130a and an oxide semiconductor layer 130b, and The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are included. In the transistor, the material of the two-layer or three-layer that constitutes the oxide semiconductor layer 130 is appropriately By appropriately selecting the oxide semiconductor layer 130b, a current can be passed through the oxide semiconductor layer 130b. By passing current through 130b, the effect of interface scattering is reduced and a high on-current can be obtained. Therefore, the on-current can be improved by thickening the oxide semiconductor layer 130b. There is a match.

[0199] By using a transistor having the above structure, good electrical characteristics are imparted to a semiconductor device. It is possible.

[0200] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0201] (Embodiment 3) In this embodiment, components of the transistor shown in Embodiment 2 will be described in detail. do.

[0202] The substrate 115 may be a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, or a substrate with an insulating surface. A metal substrate with a surface treatment can be used. Alternatively, a transistor or a photodiode can be used. A silicon substrate on which a metal oxide film is formed, and an insulating layer, wiring, contact plug, etc. are formed on the silicon substrate. A conductive material having a function as a guide may be used. When forming a p-ch type transistor on the substrate, n - Silicon substrate having a conductivity type It is preferable to use a plate. - SOI substrate with type or i-type silicon layer In addition, when the transistor provided on the silicon substrate is a p-ch type, The surface orientation of the surface on which the transistor is formed is a (110) silicon substrate. It is preferable to form a p-ch transistor on the (110) surface to increase the mobility. It is possible.

[0203] The insulating layer 120 serves to prevent the diffusion of impurities from the elements contained in the substrate 115. In addition, it can also play a role in supplying oxygen to the oxide semiconductor layer 130. The edge layer 120 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. For example, the surface temperature of the film is 100° C. or more and 700° C. or less. In the TDS method, which is preferably performed by heat treatment at 100°C to 500°C, The converted oxygen release rate is 1.0 x 10 19 atoms / cm 3 The membrane is as above. In the case where the substrate 115 is a substrate on which other devices are formed, the insulating layer 120 is an interlayer insulating film. In that case, planarization processing such as CMP is performed to make the surface flat. It is preferable to do so.

[0204] For example, the insulating layer 120 may be made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or other oxide insulating films. , silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. A laminate of the above materials can be used. It is also possible.

[0205] In this embodiment, the oxide semiconductor layer 130 of the transistor is a) The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are stacked in this order from the insulating layer 120 side. The details will be mainly explained for the three-layer structure.

[0206] Note that in the case where the oxide semiconductor layer 130 is a single layer, Simply use the layer corresponding to 0b.

[0207] In addition, when the oxide semiconductor layer 130 has two layers, the oxide semiconductor layer 13 shown in this embodiment is A layer corresponding to oxide semiconductor layer 130a and a layer corresponding to oxide semiconductor layer 130b are formed in this order from the insulating layer 120 side. In this structure, the oxide semiconductor layer 130a and the oxide semiconductor layer It can also be interchanged with 130b.

[0208] In addition, when the oxide semiconductor layer 130 has four or more layers, for example, A configuration in which another oxide semiconductor layer is added to the oxide semiconductor layer 130 having a three-layer structure. can be done.

[0209] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide layer 130c has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band). The electron affinity is the energy difference between the vacuum level and the top of the valence band (ionic The energy gap between the bottom of the conduction band and the top of the valence band is calculated from the This can be calculated by subtracting the value of

[0210] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. For example, the energy of the conduction band minimum of the oxide semiconductor layer 13 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more than 0b and is close to the vacuum level within the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV. It is preferable that the insulating film be made of a thin oxide semiconductor.

[0211] In such a structure, when an electric field is applied to the conductive layer 170, That is, a channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. do.

[0212] The oxide semiconductor layer 130a contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the insulating layer 120 are in contact with each other, In contrast, an interface state is formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. The interface state may form a channel, which may cause the transistor to malfunction. Therefore, the provision of the oxide semiconductor layer 130a can reduce the threshold voltage. As a result, variations in electrical characteristics such as the threshold voltage of the transistors can be reduced. In addition, the reliability of the transistor can be improved.

[0213] The oxide semiconductor layer 130c contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact with each other, The interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c is Therefore, the oxide semiconductor layer 130c is provided. This makes it possible to increase the field effect mobility of the transistor.

[0214] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c may include, for example, Al, Ti, Ga , Ge, Y, Zr, Sn, La, Ce or Hf is a material having a higher atomic number than the oxide semiconductor layer 130b. Specifically, a material containing the atomic ratio of 1.5 times or more of the atomic ratio can be used. The amount is preferably at least two times, and more preferably at least three times. The above elements bond strongly with oxygen. Therefore, the oxide semiconductor layer has a function of suppressing oxygen vacancies from being generated. The oxide semiconductor layer 130a and the oxide semiconductor layer 130c have a higher oxide content than the oxide semiconductor layer 130b. It can be said that element deficiency is less likely to occur.

[0215] In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The oxide semiconductor that can be used as c contains at least In or Zn. It is preferable that the oxide semiconductor contains both In and Zn. In order to reduce the variation in the electrical characteristics of the transistors, stabilizers were also installed. It is preferred that it includes

[0216] The stabilizer may be Ga, Sn, Hf, Al, or Zr. The stabilizers are the lanthanides La, Ce, Pr, Nd, Sm, Eu, and G. Examples include d, Tb, Dy, Ho, Er, Tm, Yb, Lu, etc.

[0217] For example, oxide semiconductors include indium oxide, tin oxide, gallium oxide, zinc oxide, and I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg Oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In -Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn An oxide can be used.

[0218] Here, for example, In-Ga-Zn oxide is a material having In, Ga, and Zn as main components. It means oxide. Metal elements other than In, Ga, and Zn may also be included. In this specification, a film made of In-Ga-Zn oxide is also called an IGZO film. .

[0219] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It denotes a metal element or elements. Also, In2SnO5(ZnO) n (n>0, and and n is an integer) may be used.

[0220] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are At least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn, La When the oxide semiconductor layer 1 is an In-M-Zn oxide containing a metal such as Ce or Hf, The oxide semiconductor layer 130a is In:M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor layer 130b is I n:M:Zn=x2:y2:z2 [atomic ratio], and the oxide semiconductor layer 130c is In:M:Z If n=x3:y3:z3 [atomic ratio], then y1 / x1 and y3 / x3 are y2 / x2 It is preferable that y1 / x1 and y3 / x3 are 1.0 times greater than y2 / x2. The thickness is set to 5 times or more, preferably 2 times or more, and more preferably 3 times or more. In the conductor layer 130b, when y2 is equal to or larger than x2, the electrical characteristics of the transistor are stabilized. However, if y2 is three times or more larger than x2, the field effect mobility of the transistor Therefore, it is preferable that y2 is less than three times x2.

[0221] When Zn and O are excluded from the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, In this case, the atomic ratio of In and M is preferably less than 50 atomic %. M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is 7 In addition, the oxide semiconductor layer 130b contains Zn and O. The atomic ratio of In and M is preferably 25 atomic % or more of In and 75 atomic % or more of M. More preferably, In is 34 atomic % or more and M is 66 atomic % or less. Less than c%.

[0222] The oxide semiconductor layer 130b is a semiconductor layer including the oxide semiconductor layer 130a and the oxide semiconductor layer 130. It is preferable to have a higher indium content than c. In oxide semiconductors, the s orbital of heavy metals is the The s orbitals contribute to carrier conduction, and by increasing the In content, more s orbitals are formed. Because the paths overlap, oxides with a composition in which In is greater than M have compositions in which In is equal to or less than M. Therefore, the mobility of the oxide semiconductor layer 130b is higher than that of the oxide semiconductor layer 130b. By using oxides with a high content of sodium, a transistor with high field effect mobility can be realized. It is possible.

[0223] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more and 5 The thickness of the oxide semiconductor layer 1 is preferably 0 nm or less, and more preferably 5 nm or more and 25 nm or less. The thickness of 30b is 3 nm or more and 200 nm or less, preferably 5 nm or more and 150 nm or less, more preferably More preferably, the thickness of the oxide semiconductor layer 130c is 10 nm or more and 100 nm or less. The thickness is 1 nm or more and 50 nm or less, preferably 2 nm or more and 30 nm or less, and more preferably The oxide semiconductor layer 130b has a thickness of 3 nm or more and 15 nm or less. Thicker than 0c is preferred.

[0224] In order to provide a transistor having an oxide semiconductor layer as a channel with stable electrical characteristics, The impurity concentration in the oxide semiconductor layer is reduced to make the oxide semiconductor layer intrinsic or substantially intrinsic. Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor layer is 1 ×1015 / cm 3 Preferably less than 1 × 10 13 / cm 3 Being less than More preferably, 8 × 10 11 / cm 3 More preferably, it is less than 1×10 8 / c m 3 Less than 1×10 -9 / cm 3 This is as above.

[0225] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels can become traps and degrade the electrical characteristics of a transistor. Therefore, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer It is preferable to reduce the impurity concentration in layer 130c and at each interface.

[0226] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, a secondary ion beam (SIMS) The hydrogen concentration estimated by ion mass spectrometry (Ion Mass Spectrometry) analysis is 2 ×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 below, More preferably, 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18 a toms / cm 3 Less than or equal to 1×10 17 atoms / cm 3 It has an area where The nitrogen concentration is controlled to be 5×10 19 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 Less than or equal to 5×10 16 atoms / cm 3 The control is performed so as to have a region where the above is satisfied.

[0227] In addition, when silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer is decreased. In order not to deteriorate the crystallinity of the oxide semiconductor layer, the silicon concentration is set to 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1× 10 18 atoms / cm 3 The carbon concentration is controlled to have a region where the carbon concentration is equal to or higher than the range. 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than , and more preferably 1×10 18 atoms / cm 3 Less than 6 × 10 17 ato ms / cm 3 The control is performed so as to have a region where the above is satisfied.

[0228] In addition, a transistor using the purified oxide semiconductor film as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is set to 0.1 V, 5 V or 10V, the off-state current per channel width of the transistor is several It is possible to reduce the resistance to yA / μm to several zA / μm.

[0229] Since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor layer is In this way, it is preferable that the gate insulating film does not contact the semiconductor layer. When a channel is formed at the interface between the oxide semiconductor layer and the silicon oxide semiconductor layer, carrier scattering occurs at the interface. From this viewpoint, the field effect mobility of the transistor may be reduced. It is preferable to separate the region of the semiconductor layer that becomes the channel from the gate insulating film.

[0230] Therefore, the oxide semiconductor layer 130 is divided into an oxide semiconductor layer 130a and an oxide semiconductor layer 130b. By forming a stacked structure of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, a channel is formed in the oxide semiconductor layer 130b. Thus, a transistor having high field effect mobility and stable electrical characteristics can be formed. It is possible to form a

[0231] The band structures of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In this structure, the energy of the conduction band minimum changes continuously. The oxide semiconductor layer 30a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c have similar compositions. This can also be understood from the fact that oxygen easily diffuses between the oxide semiconductor layer 130a. The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are a stack of layers having different compositions. It can also be said that the layers are physically continuous, and in the drawings, the interfaces of the laminate are is represented by a dotted line.

[0232] The oxide semiconductor layer 130, which is laminated with a common main component, is not simply laminated. Continuous junction (here, a U-shaped junction in which the energy of the conduction band edge changes continuously between layers) The layers are fabricated so that a well structure (U Shape Well) is formed. There are no impurities at the interface that would form defect levels such as trap centers or recombination centers. If impurities are mixed between the stacked oxide semiconductor layers, When the interface is in a non-uniform state, the continuity of the energy band is lost, and carriers are trapped or recombined at the interface. It will disappear when combined.

[0233] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed of In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: In-Ga-Zn oxide with an atomic ratio of 9:6 can be used. The compound semiconductor layer 130b has a composition of In:Ga:Zn=1:1:1, 2:1:3, 5:5:6, or Alternatively, an In-Ga-Zn oxide having an atomic ratio of 3:1:2 or the like can be used. When the above oxides are used as sputtering targets for film formation, the oxide semiconductor film formed is The atomic ratio of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c must be They are not necessarily identical.

[0234] The oxide semiconductor layer 130b in the oxide semiconductor layer 130 serves as a well, and The oxide semiconductor layer 130 has an energy level at the bottom of the conduction band. Since the temperature changes continuously, it can also be called a U-shaped well. The channel formed in this configuration may also be referred to as a buried channel.

[0235] In addition, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed by a method of forming a silicon oxide film or the like. In the vicinity of the interface with the insulating layer, trap levels due to impurities or defects may be formed. The presence of the semiconductor layer 130a and the oxide semiconductor layer 130c makes it possible to form the oxide semiconductor layer 13 This makes it possible to keep 0b away from the trap level.

[0236] However, the energy minimum of the conduction band of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is When the difference between the energy of the conduction band minimum of the oxide semiconductor layer 130b and the energy of the oxide semiconductor layer 130c is small, Electrons in the conductor layer 130b may exceed the energy difference and reach the trap level. When the electrons are captured by the trap levels, negative charges are generated at the interface of the insulating layer, causing the transistor to turn off. The threshold voltage of the transistor is shifted in the positive direction.

[0237] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, the transistor It is possible to give stable electrical properties to the crystals. In addition, the crystals oriented along the c-axis are resistant to distortion, The reliability of a semiconductor device using a flexible substrate can be improved.

[0238] A conductive layer 140 acts as a source electrode layer and a conductive layer 141 acts as a drain electrode layer. 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc and alloys of the metallic materials. Representative examples include Ti, which is particularly susceptible to bonding with oxygen, and the fact that the subsequent process temperature can be relatively high. For these reasons, it is more preferable to use W, which has a high melting point. In addition, Cu and Cu-M, which have low resistance, are A stack of an alloy such as n and the above material may be used. 06, transistor 111, and transistor 112, for example, conductive layer 141 and The conductive layer 142 and the conductive layer 152 are made of a laminated film of Ti and Al. There can be.

[0239] The above material has a property of extracting oxygen from the oxide semiconductor film. In some regions of the oxide semiconductor layer, oxygen is released from the oxide semiconductor film, and oxygen vacancies are formed. The oxygen vacancies are combined with the small amount of hydrogen contained in the film, and the area is significantly Therefore, the n-type region becomes the source or drain of the transistor. It can be made to act as such.

[0240] In addition, when W is used for the conductive layer 140 and the conductive layer 150, the conductive layer 140 and the conductive layer 150 may be doped with nitrogen. By doping with nitrogen, the oxygen-pulling property can be moderately weakened, resulting in n-type In addition, the conductive layer 140 and the conductive layer 141 can be prevented from expanding to the channel region. The conductive layer 150 is laminated with an n-type semiconductor layer, and the n-type semiconductor layer and the oxide semiconductor layer are connected. By contacting the n-type region with the For the n-type semiconductor layer, nitrogen-doped In-Ga-Zn oxide, zinc oxide, Indium oxide, tin oxide, indium tin oxide, etc. can be used.

[0241] The insulating layer 160 acting as a gate insulating film may be made of aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing at least one of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. etc. may be contained as impurities.

[0242] Next, an example of a laminated structure of the insulating layer 160 will be described. The insulating layer 160 is, for example, , nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and It preferably contains silicon or silicon oxynitride.

[0243] Hafnium oxide and aluminum oxide are comparatively more effective than silicon oxide and silicon oxynitride. Therefore, compared to the case where silicon oxide is used, the thickness of the insulating layer 160 can be reduced. Since the gate insulating film can be made large, the leakage current due to the tunnel current can be reduced. In addition, it is possible to realize a transistor with a small leakage current. Hafnium has a higher dielectric constant than hafnium oxide, which has an amorphous structure. Therefore, in order to obtain a transistor with a small off-state current, hafnium oxide having a crystalline structure is used. Examples of the crystal structure include monoclinic and cubic crystals. However, one aspect of the present invention is not limited to these.

[0244] The insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130 are made of a nitrogen oxide. It is preferable to use a film with a low emission amount. When the conductor comes into contact with the insulating layer 120, the density of states caused by nitrogen oxides may increase. The insulating layer 160 is made of, for example, a silicon oxynitride film or An oxide insulating layer such as an aluminum oxynitride film can be used.

[0245] The silicon oxynitride film, which emits a small amount of nitrogen oxide, is This is a membrane that releases more ammonia than it outputs, typically releasing 1×10 18 pieces / cm 3 5×10 or more 19 pieces / cm 3 The amount of ammonia released is as follows: Heat treatment at a surface temperature of the film of 50°C or more and 650°C or less, preferably 50°C or more and 550°C or less. The amount of release is considered to be the amount of release by

[0246] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0247] The conductive layer 170 acting as a gate electrode layer may be, for example, Al, Ti, Cr, Co, or Ni. Conductive films of Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W In addition, alloys of the above materials and conductive nitrides of the above materials may be used. In addition, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials are Typically, the material may be a laminate of tungsten or tungsten and titanium nitride. For example, a laminate of tungsten and tantalum nitride can be used. or Cu-Mn alloys, or laminations of the above materials with Cu or Cu-Mn alloys. In this embodiment, the conductive layer 171 may be made of tantalum nitride, and the conductive layer 172 may be made of tungsten. The conductive layer 170 is formed using a fluorine-based compound.

[0248] The insulating layer 175 may be formed using a silicon nitride film or an aluminum nitride film containing hydrogen. The transistor 103, the transistor 104, and the transistor In transistor 106, transistor 109, transistor 110, and transistor 112, By using an insulating film containing hydrogen as the insulating layer 175, part of the oxide semiconductor layer is made n-type. The nitride insulating film also acts as a blocking film against moisture and the like. The reliability of the transistor can be improved.

[0249] Alternatively, an aluminum oxide film may be used as the insulating layer 175. The transistor 101, the transistor 102, the transistor 105, and the transistor In the transistors 107, 108, and 111, the insulating layer 175 is formed of an oxide layer. It is preferable to use an aluminum oxide film. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. Aluminum oxide has a high barrier effect of preventing the permeation of both water and oxygen. The aluminum film is resistant to impurities such as hydrogen and moisture during and after the transistor manufacturing process. Prevents oxygen from being mixed into the oxide semiconductor layer 130, prevents oxygen from being released from the oxide semiconductor layer, and prevents the insulating layer 1 It is suitable for use as a protective film having the effect of preventing unnecessary release of oxygen from 20. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer. do.

[0250] In addition, it is preferable that an insulating layer 180 is formed on the insulating layer 175. are magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride , gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lath oxide The insulating film contains one or more of tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a laminate of the above materials.

[0251] Here, the insulating layer 180, like the insulating layer 120, has more oxygen than the stoichiometric composition. It is preferable that oxygen released from the insulating layer 180 is transported through the insulating layer 160 to the oxide semiconductor Since the layer 130 can be diffused into the channel forming region, The oxygen vacancies can be filled with oxygen, resulting in a stable transistor. The electrical properties can be obtained.

[0252] In order to increase the integration density of semiconductor devices, it is essential to miniaturize transistors. It is known that the electrical characteristics of transistors deteriorate as the channel width decreases. When the gate electrode shrinks, the on-current decreases.

[0253] In the transistors 107 to 112 of one embodiment of the present invention, channels are formed. The oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b. The channel formation layer and the gate insulating film are not in contact with each other. This suppresses the scattering of carriers at the interface with the gate insulating film, and the on-state voltage of the transistor is The flow can be increased.

[0254] In the transistor of one embodiment of the present invention, the channel of the oxide semiconductor layer 130 is The gate electrode layer (conductive layer 170) is formed so as to electrically surround the panel in the width direction. Therefore, the oxide semiconductor layer 130 is subjected to a gate electric field from the side in addition to the gate electric field from the direction perpendicular to the top surface. The gate electric field is applied from a direction perpendicular to the channel formation layer. Since the gate electric field is applied to the MOSFET, the effective channel width is enlarged, and the on-current is further increased. Can be enhanced.

[0255] In one embodiment of the present invention, the oxide semiconductor layer 130 is a two-layer or three-layer transistor. First, an oxide semiconductor layer 130b in which a channel is to be formed is formed on an oxide semiconductor layer 130a. In addition, the oxidation of the oxide film according to one embodiment of the present invention has an effect of making it difficult for an interface state to be formed. In a transistor having a three-layer structure of the oxide semiconductor layer 130, the oxide semiconductor layer 130b is disposed in the middle of the three-layer structure. By placing the layer in the position above the object, it is possible to eliminate the influence of impurities from above and below. Therefore, in addition to the improvement of the on-state current of the transistor, the threshold voltage is stabilized. This allows the gate to be more stable and the S value (subthreshold value) to be reduced. The current when the voltage VG is 0V can be reduced, and power consumption can be reduced. Since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device is improved. In addition, the electrical characteristics of the transistor according to one embodiment of the present invention can be improved with miniaturization. Since deterioration of the semiconductor device can be suppressed, the present invention is suitable for forming a highly integrated semiconductor device.

[0256] The various films such as the metal film, the semiconductor film, and the inorganic insulating film described in this embodiment are typically The thin film can be formed by a deposition method or a plasma CVD method, but other methods, such as thermal CVD, are also possible. An example of the thermal CVD method is MOCVD (Metal Organic Chemical Vapor Deposition). Chemical Vapor Deposition (ALD) and Atom These include the ic Layer Deposition method.

[0257] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0258] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the inside of the chamber is By reacting near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0259] In the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is introduced into the chamber. The film is formed by repeatedly introducing and reacting the raw material gas into the inert gas ( For example, two or more kinds of gases (argon, nitrogen, etc.) may be introduced as a carrier gas. The source gases may be supplied to the chamber in sequence. In this case, multiple source gases are not mixed. In this manner, after the reaction of the first source gas, an inert gas is introduced, and then the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is exhausted by evacuation, and then the second source gas is introduced. The first source gas may be introduced into the substrate so as to adsorb and react with the surface of the substrate to form a first layer. The second source gas is introduced later and adsorbed and reacted with the second layer, which is then formed on the first layer. The gas introduction sequence is controlled to form a thin film of the desired thickness. By repeating this process several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas is injected. This is suitable for fabricating miniaturized FETs.

[0260] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga When forming a -Zn-O film, trimethylindium (In(CH3)3), trime Using dimethylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) The combination is not limited to these, and triethyl gallium may be used instead of trimethyl gallium. Galvanic acid (Ga(C2H5)3) can also be used, and diethyl zinc can be used instead of dimethyl zinc. Zinc (Zn(C2H5)2) can also be used.

[0261] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and Liquids containing hafnium precursors (hafnium alkoxides and tetrakisdimethylamide hafnium Hf (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide The raw material gas is made by vaporizing hafnium (such as hafnium amide) and ozone ( Two types of gases are used:

[0262] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3 Two types of gases are used: the raw material gas made by vaporizing ethanol, etc., and H2O as an oxidizing agent. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, and aluminium. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc. There is.

[0263] For example, when forming a silicon oxide film using a deposition system that uses ALD, The silane is adsorbed on the surface to be coated and the radicals of oxidizing gases (O2, nitrous oxide) are provided. is fed to react with the adsorbate.

[0264] For example, when forming a tungsten film using a deposition system that uses ALD, WF6 gas is used. The initial tungsten film is formed by sequentially introducing WF6 gas and H The tungsten film is formed by sequentially introducing the two gases. Note that SiH4 gas is used instead of B2H6 gas. A gas may also be used.

[0265] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are introduced in sequence to form a GaO layer, and Then, Zn(CH3)2 gas and O3 gas are introduced in sequence to form a ZnO layer. The order of these layers is not limited to this example. It is also possible to form a mixed compound layer such as a Ga-Zn-O layer or a Ga-Zn-O layer. Alternatively, H2O gas obtained by bubbling an inert gas such as Ar may be used. It is preferable to use O3 gas, which does not contain O2.

[0266] A facing target sputtering device can also be used to form the oxide semiconductor layer. The film formation method using this facing target sputtering device is called VDSP (vapor deposition). It can also be called deposition SP).

[0267] An oxide semiconductor layer is formed using a facing target sputtering apparatus, It is possible to reduce plasma damage during the formation of the oxide semiconductor layer. In addition, the oxygen deficiency in the film can be reduced by using a facing target sputtering device. Since this enables deposition at low pressure, the impurity concentration (e.g. For example, hydrogen, rare gases (such as argon), water, etc.) can be reduced.

[0268] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0269] (Embodiment 4) A structure of an oxide semiconductor film that can be used in one embodiment of the present invention will be described below. .

[0270] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0271] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0272] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor). Talline Oxide Semiconductor film, polycrystalline oxide semiconductor film The oxide semiconductor film includes a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0273] First, we will explain the CAAC-OS film.

[0274] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0275] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be confirmed. On the other hand, the high-resolution TEM image also shows clear boundaries between crystals, i.e. grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0276] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction roughly parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is The CAAC-OS film is formed on the surface (also called the surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0277] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction roughly perpendicular to the sample surface. They then confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0278] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0279] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0280] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The impurities are hydrogen, carbon, and The elements are other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that form the oxide semiconductor film, such as arsenic, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius of Since the molecular radius is large, when the cation is included in the oxide semiconductor film, the The impurities in the oxide semiconductor film may cause the atomic arrangement to be disturbed, which may result in a decrease in crystallinity. Objects can act as carrier traps or carrier generation sources.

[0281] The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a carrier source.

[0282] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or The term "substantially high-purity intrinsic" refers to a highly-purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor including the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative ( Also called normally-on.) In addition, high purity intrinsic or substantially high purity The highly intrinsic oxide semiconductor film has few carrier traps. The transistors using the thin film have small fluctuations in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time when the charge is released is long, and it may behave as if it is a fixed charge. A transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. This may be the case.

[0283] In addition, the electrical characteristics of transistors using CAAC-OS films were improved by irradiation with visible light or ultraviolet light. The fluctuation is small.

[0284] Next, a microcrystalline oxide semiconductor film will be described.

[0285] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a region where a crystal part is not clearly observed and a region where a crystal part is not clearly observed. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fineness is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In the nc-OS film, for example, the grain boundaries are clearly identified in high-resolution TEM images. It may not be possible to recognize

[0286] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) is used to measure the nc-OS film using X-rays with a diameter larger than that of the crystals. When structural analysis was performed using the D instrument, the crystal plane In addition, the peaks indicating the probe size were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter (for example, 50 nm or more) When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. Nano-beam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal part. When diffraction is performed, spots are observed. When this is done, a circular (ring-shaped) area of ​​high brightness may be observed. Nanobeam electron diffraction of the nc-OS film revealed multiple spots within the ring-shaped region. It may be observed.

[0287] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher density of defect states than the CAAC-OS film.

[0288] Next, the amorphous oxide semiconductor film will be described.

[0289] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and does not have a crystal part. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0290] In the amorphous oxide semiconductor film, no crystalline parts can be confirmed in a high-resolution TEM image.

[0291] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the lane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0292] Note that the oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may have a structure such as the following. Amorphous-like Ox The resulting film is called an ide semiconductor membrane.

[0293] The amorphous-like OS membrane appears as voids in high-resolution TEM images. In addition, crystals may be clearly observed in high-resolution TEM images. There are areas where crystals can be seen and areas where crystals cannot be seen. The phos-like OS film is formed by irradiating a small amount of electrons, which is the same level as observed by TEM. Crystallization may occur and the growth of crystals may be observed. On the other hand, if the nc-OS film is of good quality, However, crystallization due to minute amounts of electron irradiation, such as that observed by TEM, is hardly observed.

[0294] The size of the crystals in the amorphous-like OS film and the nc-OS film was calculated. Measurements can be performed using high-resolution TEM images. For example, the crystal of InGaZnO4 It has a layered structure, with two Ga-Zn-O layers between In-O layers. InGaZnO4 The unit cell of this crystal has three In-O layers and six Ga-Zn-O layers, for a total of nine layers. The layers are stacked in the c-axis direction. Therefore, the spacing between adjacent layers is is approximately the same as the lattice spacing (also called the d value) of the (009) plane, and crystal structure analysis has revealed that The value is expected to be 0.29 nm. Therefore, we focus on the lattice fringes in the high-resolution TEM image. In the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less, The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0295] The oxide semiconductor film is, for example, an amorphous oxide semiconductor film. e. A stacked film including two or more of an OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film. may be also possible.

[0296] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can. (Embodiment 5)

[0297] The imaging device according to one embodiment of the present invention and a semiconductor device including the imaging device are and image reproducing devices equipped with recording media (typically DVD: Digital A disc that can play recording media such as Versatile Discs and display the images. In addition, the imaging device according to one embodiment of the present invention can be used in a display device. Examples of electronic devices that can use the semiconductor device including the imaging device include a mobile phone, Game consoles including portable ones, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras, goggle-type displays (head-mounted displays), navigation audio systems, audio playback devices (car audio, digital audio players, etc.), Copiers, fax machines, printers, multi-function printers, automated teller machines (ATMs) , vending machines, etc. Specific examples of these electronic devices are shown in Figure 34.

[0298] FIG. 34A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904. 904, microphone 905, speaker 906, operation keys 907, stylus 908, camera 909, etc. The portable game machine shown in FIG. and a display unit 904, the number of display units that the portable game machine has is not limited to this. The imaging device of one embodiment of the present invention can be used as the camera 909.

[0299] FIG. 34B shows a portable data terminal, which includes a first housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows input and output of information. The imaging device of one embodiment of the present invention can be used as the camera 919.

[0300] FIG. 34C shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, and a wristband 9 The display unit 932 may be a touch panel. The imaging device according to one embodiment of the present invention can be used for the laser 939.

[0301] FIG. 34D shows a mobile phone. A housing 951 includes a display unit 952, a microphone 957, and a speaker. The device includes a display 954, a camera 959, an input / output terminal 956, and an operation button 955. The imaging device of one embodiment of the present invention can be used for 959.

[0302] FIG. 34(E) shows a digital camera, which includes a housing 961, a shutter button 962, and a microphone 9 The lens 965 has a focal point of the present invention. The imaging device according to the present invention may include an imaging device according to the present invention.

[0303] FIG. 34(F) shows a video camera, which includes a first housing 971, a second housing 972, a display unit 973, The operation key 974, the lens 975, the connection part 976, etc. 975 is provided in the first housing 971, and the display unit 973 is provided in the second housing 972. The first housing 971 and the second housing 972 are connected by a connection portion 976. The angle between the first housing 971 and the second housing 972 can be changed by the connection part 976. The image on the display unit 973 is transmitted between the first housing 971 and the second housing 97 at the connection unit 976. 2. The focal point of the lens 975 may be set to the position shown in FIG. can be equipped with an imaging device according to one aspect of the present invention.

[0304] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. . [Explanation of symbols]

[0305] 11 Imaging operation 12 Data retention operation 13 Operation 30 Silicon Substrate 31 Transistor 32 Transistor 35 Active layer 51 Transistor 52 Transistor 53 Transistor 54 Transistor 55 Transistor 56 High Voltage Power Supply 57 Capacitive element 58 Capacitive element 60 Photoelectric conversion element 61 Photoelectric conversion layer 62 Transparent conductive layer 63 Semiconductor Layer 64 Semiconductor Layer 65 Semiconductor Layer 66 electrodes 66a conductive layer 66b Conductive layer 67 Bulkhead 71 Wiring 72 Wiring 72a Conductive layer 72b Conductive layer 73 Wiring 75 Wiring 76 Wiring 77 Wiring 78 Wiring 79 Wiring 80 Insulating layer 81 Conductors 82 Insulating layer 82a Insulating layer 82b Insulating layer 83 Insulating Layer 88 Wiring 93 Wiring 96 Wiring 99 Wiring 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 110 Transistor 111 Transistor 112 Transistor 115 Substrate 120 Insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130b Oxide semiconductor layer 130c Oxide semiconductor layer 140 Conductive layer 141 Conductive layer 142 Conductive Layer 150 Conductive layer 151 Conductive layer 152 Conductive layer 160 Insulating layer 170 Conductive Layer 171 Conductive Layer 172 Conductive Layer 173 Conductive Layer 175 Insulating Layer 180 Insulating layer 231 areas 232 areas 233 areas 331 areas 332 areas 333 areas 334 areas 335 areas 901 Case 902 Case 903 Display section 904 Display section 905 Mike 906 Speaker 907 Operation Key 908 Stylus 909 Camera 911 Case 912 Display section 919 Camera 931 Case 932 Display section 933 Wristband 939 Camera 951 Case 952 Display section 954 Speaker 955 Button 956 Input / output terminal 957 Mike 959 Camera 961 Case 962 Shutter button 963 Mike 965 Lens 967 Light emitting part 971 Case 972 Case 973 Display section 974 Operation Key 975 Lens 976 Connection 1100 layers 1200 layers 1400 layers 1500 Diffraction Grating 1600 layers 2500 Insulation Layer 2510 Light blocking layer 2520 Organic resin layer 2530 Color Filter 2530a Color Filter 2530b Color Filter 2530c Color Filter 2540 Microlens Array 2550 Optical conversion layer 2560 Insulation layer

Claims

[Claim 1] An imaging device including a first transistor, a second transistor, a third transistor, a fourth transistor, and a photoelectric conversion element, one electrode of the photoelectric conversion element is electrically connected to one of a source electrode or a drain electrode of the first transistor; one electrode of the photoelectric conversion element is electrically connected to one of a source electrode or a drain electrode of the third transistor; the other of the source electrode and the drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor; one of a source electrode or a drain electrode of the second transistor is electrically connected to one of a source electrode or a drain electrode of the fourth transistor; the other electrode of the photoelectric conversion element is electrically connected to a first wiring; a gate electrode of the first transistor is electrically connected to a second wiring; An imaging device, wherein when a potential supplied to the first wiring is HVDD, a maximum value of a potential supplied to the second wiring is smaller than HVDD.

Images