Signal processing circuit, da converter circuit, ad converter circuit, and audio equipment

Abstract

To provide a signal processing circuit capable of suppressing current consumption or noise caused by a subsequent stage side circuit.SOLUTION: A signal processing circuit (500) includes a pulse selection unit (400) configured to perform pulse selection by selecting a high level selection target period among selection target periods constituting a PWM output signal (Spwm) for a level of an n-value output signal. The pulse selection unit performs pulse selection for each one or more samples of the n-value output signal so that, at changing of the sample, a level of the first selection target period in the PWM output signal corresponding to the current sample matches a level of the last selection target period in the PWM output signal corresponding to the previous sample.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present disclosure relates to a signal processing circuit. [Background technology]

[0002] Conventionally, a ΔΣ modulator is used in a DA converter that converts a digital signal into an analog signal or an AD converter that converts an analog signal into a digital signal (an example of a ΔΣ modulator is disclosed in, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-87876 A

[0004] [overview] In a signal processing circuit using a ΔΣ modulator, it is required to suppress an increase in current consumption or an increase in noise due to a circuit provided in a subsequent stage.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a signal processing circuit that is capable of suppressing current consumption or noise caused by a downstream circuit.

[0006] A signal processing circuit according to an embodiment of the present disclosure includes: a ΔΣ modulator configured to convert an input signal into an n-ary output signal (n is an integer equal to or greater than 2) and output the signal; a PWM conversion unit configured to convert the n-value output signal into a PWM output signal having a duty corresponding to a level of the n-value output signal; a pulse selection unit configured to select a selection period that is to be set to a high level among the selection periods that constitute the PWM output signal, in accordance with a level of the n-value output signal, thereby performing pulse selection; Equipped with The pulse selection unit is configured to select a pulse for each one or more samples of the n-value output signal so that, at the sample switching, the level of the first selection target period in the PWM output signal corresponding to the current sample matches the level of the last selection target period in the PWM output signal corresponding to the previous sample. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a configuration of a DA converter circuit. [Diagram 2] FIG. 2 is a diagram showing an internal configuration of a ΔΣ modulator provided in the DA converter circuit shown in FIG. [Diagram 3] FIG. 3 is a diagram illustrating a two-level ΔΣ modulator. [Figure 4] FIG. 4 is a diagram illustrating a five-level ΔΣ modulator. [Diagram 5] FIG. 5 is a diagram showing an example of improvement in quantization noise. [Figure 6] FIG. 6 is a diagram showing an example of improvement in quantization noise. [Figure 7] FIG. 7 is a diagram illustrating a configuration of an AD converter circuit. [Figure 8] FIG. 8 is a diagram showing an internal configuration of a ΔΣ modulator provided in the AD converter circuit shown in FIG. [Figure 9] FIG. 9 is a diagram illustrating a configuration of a signal processing circuit according to a comparative example. [Figure 10] FIG. 10 is a diagram showing the correspondence relationship between the output level (output amplitude) of the ΔΣ modulator and the waveform of the PWM output signal. [Figure 11] FIG. 11 is a diagram showing a configuration of a signal processing circuit according to the first embodiment of the present disclosure. [Figure 12] FIG. 12 is a diagram showing an example of pulse selection in the comparative example and the first embodiment. [Figure 13] FIG. 13 is a diagram illustrating an example of a PWM output signal in the comparative example and the first embodiment. [Figure 14]FIG. 14 is a diagram showing an example of pulse selection in the comparative example, the first embodiment, and the second embodiment. [Figure 15] FIG. 15 is a diagram showing an example of pulse selection in a comparative example and the third embodiment. [Figure 16] FIG. 16 is a diagram illustrating a configuration of a DA converter circuit and an AD converter circuit according to an embodiment of the present disclosure. [Figure 17] FIG. 17 is a diagram showing a configuration of an audio device according to an embodiment of the present disclosure. [Figure 18] FIG. 18 is a diagram showing a configuration example of a signal processing circuit provided with an insulated communication unit. [Figure 19] FIG. 19 is a diagram illustrating a configuration example of the insulated communication unit.

[0008] [Detailed Description] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0009] <DAコンバータ> 1 is a diagram showing the configuration of a DA converter circuit 5. The DA converter circuit 5 includes a ΔΣ modulator 1, a DAC (DA converter) 2, and an analog LPF (low pass filter) 3.

[0010] The ΔΣ modulator 1 oversamples the input digital input signal Din at a sampling frequency f and converts it into a low-bit digital output signal Dout using ΔΣ modulation. The digital output signal Dout is input to the DAC2, which converts it from a digital signal to an analog signal. The converted analog signal is input to the analog LPF and converted into an analog output signal Aout. By oversampling, the quantization noise can be dispersed over a wide frequency band, so by processing the output of DAC2 with the analog LPF 3, the quantization noise can be removed and an analog output signal Aout with a good S / N ratio can be obtained.

[0011] FIG. 2 is a diagram showing the internal configuration of the ΔΣ modulator 1 provided in the DA converter circuit 5. As shown in FIG. The ΔΣ modulator 1 has an integrator 1A and a quantizer 1B. The difference between a digital input signal Din and an output fed back from the quantizer 1B is accumulated by the integrator 1A, and is converted into a low-bit digital output signal Dout by the quantizer 1B.

[0012] Fig. 3 is a diagram showing a binary ΔΣ modulator 1 as an example of the ΔΣ modulator 1. The binary ΔΣ modulator 1 outputs a 1-bit (0 or 1) digital output signal Dout. As shown in Fig. 3, the digital output signal Dout is composed of pulses indicating 0 or 1, and the pulse width is 1 / f. The binary ΔΣ modulator 1 uses a binary quantizer 1B (Fig. 2) internally.

[0013] 4 is a diagram showing a 5-level ΔΣ modulator 1 as an example of the ΔΣ modulator 1. The 5-level ΔΣ modulator 1 outputs a digital output signal Dout with 5 values ​​(output=0 to 4). The digital output signal Dout is output every 1 / f.

[0014] Methods for improving the accuracy of a ΔΣ modulator include increasing the sampling frequency f or increasing the quantization level of the quantizer.

[0015] When the sampling frequency f is increased, for example, from A1 to A2 in Figure 5, the quantization noise of the ΔΣ modulator is distributed over a wider frequency band, reducing the quantization noise in the signal band S. However, using a high sampling frequency f increases the effect of clock jitter, and an expensive phase locked loop (PLL) circuit is required to generate high frequencies with high precision.

[0016] On the one hand, the quantization level of the quantizer 1B refers to the number of possible values (levels) of the output of the quantizer 1B (for example, 5 values, etc.). When the quantization level is increased, the quantization noise is reduced across the entire frequency band, as shown by A3→A4 in FIG. 6, for example. However, the number of output pins of the quantizer 1B increases, leading to an increase in area and cost. For example, for a 2-value quantizer 1B, there is 1 output pin, and for a 5-value quantizer 1B, there are 4 output pins.

[0017] <AD converter> FIG. 7 is a diagram showing the configuration of the AD converter circuit 50. The AD converter circuit 50 includes a ΔΣ modulator 10, a digital LPF 20, and a decimation filter 30.

[0018] The ΔΣ modulator 10 oversamples the input analog input signal Ain at the sampling frequency f and converts it into a low-bit digital output signal Dout using ΔΣ modulation. The digital output signal Dout is input to the digital LPF 20. The digital output signal Dout has the quantization noise removed by the digital LPF 20, and the sampling frequency is decimated by the subsequent decimation filter 30.

[0019] FIG. 8 is a diagram showing the internal configuration of the ΔΣ modulator 10 provided in the AD converter circuit 50. The ΔΣ modulator 10 has an integrator 10A, a quantizer 10B, and a DAC 10C. The difference between the analog input signal Ain and the output of the DAC 10C is accumulated by the integrator 10A and converted into a low-bit digital output signal Dout by the quantizer 10B. The digital output signal Dout is converted into an analog signal by the DAC 10C and fed back to the input side.

[0020] The method and its problems for improving the accuracy of the ΔΣ modulator 10 used in such an AD converter circuit 50 are the same as described above.

[0021] <PWM output configuration> One possible solution to the above problem is a signal processing circuit 300 as shown in Fig. 9. The signal processing circuit 300 includes a ΔΣ modulator 100 and a PWM (Pulse Width Modulation) conversion unit 200. Here, the ΔΣ modulator 100 is assumed to be a 5-value output ΔΣ modulator as an example of a multi-value output.

[0022] The PWM conversion unit 200 converts the quinary output (output levels = 0 to 4) output from the ΔΣ modulator 100 into a PWM output signal Spwm. Here, Fig. 10 shows the correspondence between the output levels (output amplitudes) of the ΔΣ modulator 100 and the waveforms of the PWM output signals Spwm. The PWM output signal Spwm is formed by arranging four pulses, each having a width of 1 / 4f, where f is the sampling frequency of the ΔΣ modulator 100.

[0023] When the output level of the ΔΣ modulator 100 is 0, all four pulses in the PWM output signal are 0. When the output level of the ΔΣ modulator 100 is 1, the first pulse in the PWM output signal is 1, and the remaining pulses are 0. When the output level of the ΔΣ modulator 100 is 2, the first and second pulses in the PWM output signal are 1, and the remaining pulses are 0. When the output level of the ΔΣ modulator 100 is 3, the first to third pulses in the PWM output signal are 1, and the remaining pulses are 0. When the output level of the ΔΣ modulator 100 is 4, all four pulses in the PWM output signal are 1.

[0024] In this way, the pulse width (duty) of the PWM output signal is changed according to the multi-value output of the ΔΣ modulator 100. This allows the PWM conversion unit 200 to require only one output pin, and the quantization level of the ΔΣ modulator 100 can be increased.

[0025] When configuring a DA converter circuit using the signal processing circuit 300 configured as in Fig. 9, a DAC and an analog LPF are provided downstream of the signal processing circuit 300 as in Fig. 1 (in this case, the input to the ΔΣ modulator 100 is a digital input signal). When configuring an AD converter circuit using the signal processing circuit 300 configured as in Fig. 9, a digital LPF and a decimation filter are provided downstream of the signal processing circuit 300 as in Fig. 7 (in this case, the input to the ΔΣ modulator 100 is an analog input signal).

[0026] However, in the signal processing circuit 300 as described above, the number of change points of the PWM output signal increases. The change points include a change point from a low level to a high level and a change point from a high level to a low level. When the number of change points increases, for example, the number of switching times of a driver circuit provided in a DAC provided in the rear stage of the signal processing circuit 300 increases, the frequency of through current flow increases, and the current consumption increases. In addition, noise is transmitted to the power supply and ground during switching, which may cause deterioration of characteristics. The driver circuit is, for example, a circuit called an H-bridge driver. The H-bridge driver has two half bridges consisting of two switching elements.

[0027] In addition, in the case of an AD converter circuit in which an insulated communication unit as described below is provided downstream of the signal processing circuit 300, the circuit current in the insulated communication unit accounts for a large proportion of the entire circuit, and a large current is generated at each of the above-mentioned change points, so that the insulated communication unit becomes a noise source.

[0028] First Embodiment In order to solve the above problems, the embodiment of the present disclosure described below is implemented. Fig. 11 is a diagram showing a configuration of a signal processing circuit 500 according to the first embodiment of the present disclosure. The signal processing circuit 500 differs from the previously described signal processing circuit 300 (Fig. 9) in that a pulse selection unit 400 is inserted between the ΔΣ modulator 100 and the PWM conversion unit 200.

[0029] In the PWM conversion unit 200 in the signal processing circuit 300 (comparative example) described above, the pulse selected in the PWM output signal was fixed according to the level (output amplitude) of each output sample from the ΔΣ modulator 100. Here, the selection of a pulse means selecting one of the selection target periods (hereinafter, selection target periods) divided every 1 / ((n-1)×f) with quantization level=n, and setting the level to a high level. In the example of FIG. 10, since n=5, the selection target period (four selection target periods) divided every 1 / (4f) is set to a high level, so that the selection target period set to a high level is fixed according to the output amplitude.

[0030] In contrast, the pulse selection unit 400 in the signal processing circuit 500 of this embodiment selects pulses so as to reduce the number of transition points in the PWM output signal Spwm. Specifically, the pulse selection unit 400 sets the number of selection target periods corresponding to the output amplitude for each output sample from the ΔΣ modulator 100 to a high level (this is similar to the signal processing circuit 300 described above). Depending on the output amplitude, all of the selection target periods may be at a low level or a high level.

[0031] Furthermore, when the last selection target period of the PWM output signal corresponding to the previous output sample is at a low level, the pulse selection unit 400 sets the first selection target period of the PWM output signal corresponding to the current output sample to a low level and sets a consecutive period from the last selection target period to a high level. Setting consecutive periods to a high level means that when there is one selection target period to be set to a high level, only the last selection target period is set to a high level, and when there are multiple selection target periods to be set to a high level, the multiple consecutive selection target periods including the last selection target period are set to a high level.

[0032] Furthermore, when the last selection target period of the PWM output signal corresponding to the previous output sample is at high level, the pulse selection unit 400 sets a continuous period from the first selection target period of the PWM output signal corresponding to the current output sample to high level. Setting a continuous period to high level means that when there is one selection target period to be set to high level, only the first selection target period is set to high level, and when there are multiple selection target periods to be set to high level, the multiple continuous selection target periods including the first selection target period are set to high level.

[0033] An example of pulse selection in the PWM output signal Spwm by such a method will be described with reference to Fig. 12. In Fig. 12, the left side shows an example of pulse selection by the signal processing circuit 300 according to a comparative example, and the right side shows an example of pulse selection by the signal processing circuit 500 (pulse selection unit 400) according to this embodiment. In Fig. 12, both the left and right sides show the output amplitude for each output sample from the ΔΣ modulator 100, and the arrangement of the output amplitudes has the same pattern.

[0034] In the left side of Fig. 12 (comparative example), the pulse selection according to the output amplitude is fixed. In contrast, in the right side of Fig. 12 (this embodiment), the pulse selection in the current output sample is changed according to the level of the last selection target period in the previous output sample, even if the output amplitude value is the same. As a result, a pattern in which the front selection target period is at a low level and the rear selection target period is at a high level in the order of the output samples, and a pattern in which the front selection target period is at a high level and the rear selection target period is at a low level are repeated alternately. However, when the output amplitude = 0, all selection target periods are at a low level, and when the output amplitude = 4, all selection target periods are at a high level.

[0035] In Fig. 13, the PWM output signals shown on the left side of Fig. 12 (comparative example) are arranged in time series at the top, and the PWM output signals shown on the right side of Fig. 12 (present embodiment) are arranged in time series at the bottom. In this way, the number of change points in the PWM output signal is reduced from 12 in the comparative example to 6 in this embodiment. By reducing the number of change points in this way, it is possible to suppress the current consumption and noise caused by the subsequent circuit as described above.

[0036] <Second embodiment> In the first embodiment, the pulse selection is performed by the above-mentioned method for each sample output, as shown in the example of Fig. 12. In contrast to this, in the second embodiment, the above-mentioned pulse selection method may be applied to each of a plurality of sample outputs.

[0037] 14, an example of pulse selection by the signal processing circuit 300 according to the comparative example is shown on the left, an example of pulse selection according to the first embodiment is shown in the center, and an example of pulse selection according to the second embodiment is shown on the right. In FIG. 14, the output amplitude patterns of the output samples are the same in all cases.

[0038] 14, in the first embodiment (center), a pattern in which the front is at a low level and the rear is at a high level, and a pattern in which the front is at a high level and the rear is at a low level are repeated for each sample output. In contrast, in the second embodiment (right), a pattern in which the front is at a low level and the rear is at a high level, and a pattern in which the front is at a high level and the rear is at a low level are repeated for every two sample outputs.

[0039] The number of change points of the PWM output signal is 16 in the comparative example, 8 in the first embodiment, and 12 in the second embodiment, so that even in the second embodiment, the number can be reduced compared to the comparative example.

[0040] <Third embodiment> The signal processing circuit according to the third embodiment has the same configuration as that according to the first embodiment (FIG. 11), but the method of pulse selection in the pulse selection section 400 is different from that according to the first embodiment.

[0041] More specifically, in the third embodiment, the pulse selection section 400 performs pulse selection in the following manner. First, a candidate pattern of selection target periods in which the pulse is set to a high level is determined according to the value of the output amplitude of the sample output so that the number of pulse selections, which is the number of times the pulse is set to a high level for each selection target period, is uniform among the selection target periods. However, this does not include cases in which all selection target periods are set to a low level or a high level depending on the value of the output amplitude of the sample output.

[0042] When there is only one candidate pattern, the pulse selection is determined at that time. On the other hand, when there are multiple candidate patterns, the candidate pattern is selected as follows. When the last selection target period of the PWM output signal corresponding to the previous output sample is at low level, the candidate pattern is selected so that the first selection target period of the PWM output signal corresponding to the current output sample is at low level and the consecutive selection target period from the last selection target period is at high level. On the other hand, when the last selection target period of the PWM output signal corresponding to the previous output sample is at high level, the candidate pattern is selected so that the consecutive selection target period from the first selection target period of the PWM output signal corresponding to the current output sample is at high level.

[0043] 15, an example of pulse selection by the signal processing circuit 300 according to the comparative example is shown on the left, and an example of pulse selection according to the third embodiment is shown on the right. In FIG 15, the output amplitude patterns of the output samples are the same on the left and right.

[0044] In the third embodiment, first, when the output amplitude=0 (sample 1), all the selection target periods in the PWM output signal are set to low level, and the pulse selection is confirmed. Next, when the output amplitude=1 (sample 2), a candidate pattern is determined in which one of all the selection target periods is a candidate, and since the last selection target period of the PWM output signal corresponding to the previous output sample is at low level, the first selection target period of the PWM output signal corresponding to the current output sample is set to low level, and only the last selection target period is set to low level. That is, the last selection target period is selected as the candidate pattern.

[0045] Next, when the output amplitude is 1 (sample 3), a candidate pattern is determined in which any one of the selection target periods except the last selection target period is a candidate, and since the last selection target period of the PWM output signal corresponding to the previous output sample is at a high level, only the first selection target period of the PWM output signal corresponding to the current output sample is set to a high level. In other words, the first selection target period is selected as the candidate pattern.

[0046] Next, when the output amplitude is 2 (sample 4), the two selection target periods excluding the first and last selection target periods are determined as candidate target patterns, and since there is only one candidate target pattern, the pulse selection is confirmed. At this point, selection of all selection target periods is completed, and all selection target periods become candidates.

[0047] Next, when the output amplitude is 2 (sample 5), a candidate pattern is determined in which any two of all the selection target periods are candidates, and since the last selection target period of the PWM output signal corresponding to the previous output sample is at a low level, the first selection target period of the PWM output signal corresponding to the current output sample is set to a low level, and the two consecutive selection target periods from the last selection target period are set to a high level. In other words, the last two selection target periods are selected as the candidate pattern.

[0048] Next, when the output amplitude = 3 (Sample 6), in addition to the first two target selection periods, one candidate pattern is determined from the remaining target selection periods as a candidate. Since the last target selection period of the PWM output signal corresponding to the previous output sample is at a high level, three consecutive target selection periods from the first target selection period of the PWM output signal corresponding to this output sample are set to a high level. That is, the first three target selection periods are selected as the candidate pattern.

[0049] Next, when the output amplitude = 3 (Sample 7), a candidate pattern is determined in which the first two target selection periods and the last target selection period are candidates. Since there is only one candidate target pattern, the pulse selection is determined. At this point, all target selection periods are selected.

[0050] When the output amplitude = 4 (Sample 8), all target selection periods in the PWM output signal are set to a high level, and the pulse selection is determined.

[0051] Thereafter, pulse selection is similarly performed for each output sample. Thus, in the example of FIG. 15, in the case of the comparative example (left), the number of change points in the PWM output signal is 24, but in the case of the third embodiment (right), the number of change points can be reduced to 18. As described above, in this embodiment, the number of change points can be reduced and the number of pulse selections can be made uniform. By making the number of pulse selections uniform, when a DA converter circuit or an AD converter circuit is configured using the signal processing circuit 500 according to this embodiment, the S / N ratio can be improved. Such an effect of improving characteristics has been verified by the inventor of the present application.

[0052] <Output pin of the PWM conversion unit> In the above-described embodiment, the output pin of the PWM conversion unit 200 was one pin, but the output pin of the PWM conversion unit may be a plurality of pins. Here, such a modification will be described.

[0053] ​For example, the ΔΣ modulator 100 may be configured to output 17 values, and the number of output pins of the PWM conversion unit 200 may be four. That is, the PWM output signal Spwm is output from the four output pins of the PWM conversion unit 20. In this embodiment, the output of the ΔΣ modulator 110 is n-valued (n is an integer equal to or greater than 2), and (number of output pins of the PWM conversion unit 200) × (number of pulses per output pin) + 1 = n. The number of pulses is the number of periods to be selected.

[0054] As mentioned above, when the delta-sigma modulator 100 outputs five values, the number of pulses per output pin is 4, so the number of output pins is 1, and so the number of values ​​is 1×4+1=5. On the other hand, when the delta-sigma modulator 100 outputs 17 values, the number of pulses per output pin is 4, so the number of output pins is 4, and so the number of values ​​is 4×4+1=17. Therefore, the quantization level of the delta-sigma modulator 100 can be further increased.

[0055] <DAコンバータ、ADコンバータ> When configuring a DA converter circuit using the signal processing circuit 500 according to the first to third embodiments described above, a DAC 2 and an analog LPF 3 are provided downstream of the signal processing circuit 500, as in the DA converter circuit 700 shown in FIG. 16, in the same manner as in FIG. 1 (in this case, the input to the ΔΣ modulator 100 is a digital input signal Din).

[0056] Furthermore, when configuring an AD converter circuit using the signal processing circuit 500, as in the AD converter circuit 750 shown in FIG. 16, a digital LPF 20 and a decimation filter 30 are provided downstream of the signal processing circuit 500, as in FIG. 7 (in this case, the input to the ΔΣ modulator 100 is the analog input signal Ain).

[0057] <Application to audio equipment> The signal processing circuit according to the embodiment of the present disclosure can be applied to various devices, but is preferably applied to an audio device as shown in Fig. 17, for example. An audio device 800 shown in Fig. 17 includes a DA converter circuit 700 (Fig. 16) using the signal processing circuit 500. In this case, a digital audio input signal is used as the digital input signal Din in the signal processing circuit 500. Also, an audio device 850 shown in Fig. 17 includes an AD converter circuit 750 (Fig. 16) using the signal processing circuit 500. In this case, an analog audio input signal is used as the analog input signal Ain in the signal processing circuit 500.

[0058] <Isolated signal processing circuit> The signal processing circuit of the present disclosure may also be preferably configured as an insulated type. Fig. 18 is a diagram showing a signal processing circuit 510 configured by applying an insulated communication unit 900 to the configurations of the first to third embodiments. In the configuration of Fig. 18, the insulated communication unit 900 is disposed on the downstream side of the PWM conversion unit 200. The insulated communication unit 900 transmits the binary output output from the PWM conversion unit 200 to the downstream side while isolating it.

[0059] 19 is a diagram showing a configuration example of an insulated communication unit 900. The insulated communication unit 900 of this configuration example transmits a pulse signal from the primary circuit system 900p to the secondary circuit system 900s while isolating between the primary circuit system 900p (VCC1-GND1 system) and the secondary circuit system 900s (VCC2-GND2 system). The insulated communication unit 900 has a controller chip 910, a driver chip 920, and a transformer chip 930.

[0060] The controller chip 910 is a semiconductor chip that operates by receiving a power supply voltage VCC1. The controller chip 910 includes, for example, a pulse transmission circuit 911 and buffers 912 and 913 integrated therein.

[0061] The pulse transmitting circuit 911 is a pulse generator that generates the transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 911 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputs a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 911 pulse-drives either one of the transmission pulse signals S11 and S21 in response to the logical level of the input pulse signal IN.

[0062] The buffer 912 receives the transmission pulse signal S11 from the pulse transmission circuit 911 and pulse-drives the transformer chip 930 (specifically, the transformer 931).

[0063] The buffer 913 receives the transmission pulse signal S21 from the pulse transmission circuit 911, The transformer chip 930 (specifically, the transformer 932) is pulse-driven.

[0064] The driver chip 920 is a semiconductor chip that operates upon receiving a power supply voltage VCC2. The driver chip 920 has buffers 921 and 922, a pulse receiving circuit 923, and a driver 924 integrated therein.

[0065] The buffer 921 shapes the waveform of a reception pulse signal S12 induced in a transformer chip 930 (specifically, a transformer 931) and outputs the result to a pulse reception circuit 923.

[0066] The buffer 922 shapes the waveform of the received pulse signal S22 induced in the transformer chip 930 (specifically, the transformer 932) and outputs the result to the pulse receiving circuit 923.

[0067] The pulse receiving circuit 923 generates an output pulse signal OUT by driving a driver 924 in response to the received pulse signals S12 and S22 input via buffers 921 and 922. More specifically, the pulse receiving circuit 923 drives the driver 924 so as to raise the output pulse signal OUT to a high level in response to the pulse drive of the received pulse signal S12, and to lower the output pulse signal OUT to a low level in response to the pulse drive of the received pulse signal S22. That is, the pulse receiving circuit 923 switches the logical level of the output pulse signal OUT in response to the logical level of the input pulse signal IN. Note that, for example, an RS flip-flop can be suitably used as the pulse receiving circuit 923.

[0068] The driver 924 outputs the output pulse signal OUT Generate.

[0069] The transformer chip 930 uses transformers 931 and 932 to provide DC insulation between the controller chip 910 and the driver chip 920, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 911 to the pulse reception circuit 923 as reception pulse signals S12 and S22, respectively. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0070] More specifically, the transformer 931 outputs a receiving pulse signal S12 from a secondary coil 931s in response to a transmitting pulse signal S11 input to a primary coil 931p. On the other hand, the transformer 932 outputs a receiving pulse signal S12 from a secondary coil 931s in response to a transmitting pulse signal S21 input to a primary coil 932p. As a result, the secondary coil 932s outputs a reception pulse signal S22.

[0071] Thus, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to a rise signal and a fall signal), and then transmitted from the primary circuit system 900p to the secondary circuit system 900s via two transformers 931 and 932.

[0072] In addition, the isolated communication unit 900 of this configuration example has an independent transformer chip 930 equipped with only transformers 931 and 932, in addition to the controller chip 910 and the driver chip 920, and these three chips are sealed in a single package.

[0073] With this configuration, the controller chip 910 and the driver chip 920 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), making it possible to reduce manufacturing costs.

[0074] <Other> In addition to the above-mentioned embodiment, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-mentioned embodiment, but should be understood to include all modifications that fall within the meaning and scope equivalent to the scope of the claims.

[0075] <Additional Notes> As described above, the signal processing circuit (500) according to one embodiment of the present disclosure includes: A ΔΣ modulator (100) configured to convert an input signal into an n-ary output signal (n is an integer equal to or greater than 2) and output the signal; A PWM conversion unit (200) configured to convert the n-value output signal into a PWM output signal (Spwm) having a duty corresponding to a level (amplitude) of the n-value output signal; A pulse selection unit (400) configured to select a pulse by selecting a selection target period that is to be at a high level among the selection target periods constituting the PWM output signal, for a level of the n-value output signal; Equipped with The pulse selection unit is configured to perform pulse selection for one or more samples of the n-value output signal so that, at the sample switching, the level of the first selection target period in the PWM output signal corresponding to the current sample matches the level of the last selection target period in the PWM output signal corresponding to the previous sample (first configuration).

[0076] Furthermore, in the above first configuration, the pulse selection unit may be configured such that, when the level of the last selection target period in the PWM output signal corresponding to the previous sample is low, the level of the first selection target period in the PWM output signal corresponding to the current sample is low, and the level of the selection target period consecutive to the last selection target period is high (second configuration).

[0077] Furthermore, in the above first or second configuration, the pulse selection unit may be configured such that when the level of the last selection target period in the PWM output signal corresponding to the previous sample is high, the pulse selection unit sets the selection target period consecutive to the first selection target period in the PWM output signal corresponding to the current sample to a high level (third configuration).

[0078] Furthermore, in any of the first to third configurations, the pulse selection unit may be configured to select pulses such that, for one or more samples, a pattern in which the anterior selection target period is at a low level and the posterior selection target period is at a high level is alternated with a pattern in which the anterior selection target period is at a high level and the posterior selection target period is at a low level (fourth configuration).

[0079] In addition, in any one of the first to third configurations, the pulse selection unit determines a candidate pattern for the selection target period in which the pulse is set to a high level according to the level of the sample so that the number of pulse selections, which is the number of times the pulse is set to a high level for each selection target period, is uniform during the selection target period; The candidate pattern may be selected so that the level of the first selection target period in the PWM output signal corresponding to the current sample matches the level of the last selection target period in the PWM output signal corresponding to the previous sample (fifth configuration).

[0080] In addition, in any one of the first to fifth configurations, the number of output pins of the PWM conversion unit is multiple, The number of pulses is the number of the selection target periods, A configuration in which (the number of the output pins)×(the number of the pulses per one of the output pins)+1=n may be used (sixth configuration).

[0081] In addition, in any of the first to sixth configurations, the seventh configuration may further include an insulated communication unit (900) that is arranged downstream of the PWM conversion unit and configured to transmit a pulse signal while isolating it.

[0082] Moreover, a DA converter circuit (700) according to one embodiment of the present disclosure includes a signal processing circuit having any one of the first to seventh configurations described above, a DA converter (2) arranged downstream of the signal processing circuit, and an analog low-pass filter (3) arranged downstream of the DA converter (eighth configuration).

[0083] Moreover, an AD converter circuit (750) according to one embodiment of the present disclosure includes a signal processing circuit having any one of the first to seventh configurations described above, a digital low-pass filter (20) arranged downstream of the signal processing circuit, and a decimation filter (30) arranged downstream of the digital low-pass filter (ninth configuration).

[0084] Moreover, an audio device (800) according to an embodiment of the present disclosure includes the DA converter circuit of the eighth configuration.

[0085] Moreover, an audio device (850) according to an embodiment of the present disclosure includes the AD converter circuit of the ninth configuration. [Industrial Applicability]

[0086] The present disclosure can be used in various devices such as audio devices. [Explanation of symbols]

[0087] 1 Delta-Sigma Modulator 1A integrator 1B Quantizer 2 DAC 3 Analog LPF 5. DA converter circuit 10 Delta-Sigma Modulator 10A integrator 10B Quantizer 10C DAC 20 Digital LPF 30 Decimation Filter 50 AD converter circuit 100 ΔΣ Modulator 200 PWM conversion unit 300 Signal Processing Circuit 400 Pulse selection unit 500,510 Signal processing circuit 700 DA converter circuit 750 AD converter circuit 800 Audio Equipment 850 Audio Equipment 900 Insulated Communication Unit 900p primary circuit system 900s secondary circuit system 910 Controller Chip 911 Pulse transmission circuit 912 Buffer 913 Buffer 920 Driver Chip 921 Buffer 922 Buffer 923 Pulse receiving circuit 924 Driver 930 Transformer Chip 931 Trans 931p Primary coil 931s secondary coil 932 Trans 932p Primary coil 932s secondary coil

Claims

1. a ΔΣ modulator configured to convert an input signal into an n-ary output signal (n is an integer equal to or greater than 2) and output the signal; a PWM conversion unit configured to convert the n-value output signal into a PWM output signal having a duty corresponding to a level of the n-value output signal; a pulse selection unit configured to select a selection period that is to be set to a high level among the selection periods constituting the PWM output signal, in accordance with a level of the n-value output signal, thereby performing pulse selection; Equipped with The pulse selection unit performs pulse selection for each one or more samples of the n-value output signal so that, at the sample change, the level of the first selection target period in the PWM output signal corresponding to the current sample matches the level of the last selection target period in the PWM output signal corresponding to the previous sample.

2. 2. The signal processing circuit according to claim 1, wherein, when the level of the last selection target period in the PWM output signal corresponding to the previous sample is a low level, the pulse selection unit sets the level of the first selection target period in the PWM output signal corresponding to the current sample to a low level and sets the selection target period consecutive to the last selection target period to a high level.

3. 2. The signal processing circuit according to claim 1, wherein when the level of the last selection target period in the PWM output signal corresponding to the previous sample is a high level, the pulse selection unit sets the selection target period continuing from the first selection target period in the PWM output signal corresponding to the current sample to a high level.

4. 2. The signal processing circuit according to claim 1, wherein the pulse selection unit selects pulses for each of the one or more samples by alternating between a pattern in which the front selection target period is at a low level and the rear selection target period is at a high level and a pattern in which the front selection target period is at a high level and the rear selection target period is at a low level.

5. the pulse selection unit determines a candidate pattern of the selection target period in which the pulse is set to a high level according to a level of the sample so that a pulse selection count, which is the number of times the pulse is set to a high level for each selection target period, is uniform during the selection target period; 2. The signal processing circuit according to claim 1, wherein the candidate pattern is selected so that a level of a first selection target period in the PWM output signal corresponding to a current sample matches a level of a last selection target period in the PWM output signal corresponding to a previous sample.

6. The PWM conversion unit has a plurality of output pins, The number of pulses is the number of the selection target periods, 2. The signal processing circuit according to claim 1, wherein (the number of said output pins) x (the number of said pulses per said output pin) + 1 = n.

7. The signal processing circuit according to claim 1 , further comprising an insulating communication unit arranged downstream of the PWM conversion unit and configured to transmit a pulse signal while isolating it.

8. 8. A DA converter circuit comprising: the signal processing circuit according to claim 1; a DA converter arranged in a subsequent stage of the signal processing circuit; and an analog low-pass filter arranged in a subsequent stage of the DA converter.

9. 8. An AD converter circuit comprising: the signal processing circuit according to claim 1; a digital low-pass filter arranged downstream of the signal processing circuit; and a decimation filter arranged downstream of the digital low-pass filter.

10. An audio device comprising the DA converter circuit according to claim 8.

11. An audio device comprising the AD converter circuit according to claim 9.

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