Operation system

Abstract

To suppress occurrence of waste in a system configuration and to detect presence or absence of abnormality in an operation system.SOLUTION: An operation system 100 for executing operation processing utilizing a neural network model includes: multiple processor cores PC1 to PC8; an operation allocation section 11 for determining operation cores and allowing them to execute operation processing according to an operation load of operation processing; and an abnormality detection section 12 for detecting presence or absence of abnormality in the processor cores. The operation allocation section allows at least one portion of the processor cores that are not operation cores to execute abnormality detection operation in parallel to basic operation, and the abnormality detection section determines that the operation cores and the abnormality detection cores are not abnormal when a difference between a first operation result as an operation result of the basic operation and a second operation result as an operation result of an abnormality detection operation satisfies a predetermined permission condition, and determines that at least one portion of the operation cores and the abnormality detection cores is abnormal when the difference does not satisfy the permission condition.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to computing systems. [Background technology]

[0002] Conventionally, in order to ensure the functional safety of a computing system having a processor, a method for detecting an abnormality when the abnormality occurs in the computing system is required. Patent Document 1 discloses a system that includes a processor core for abnormality detection in addition to a processor core used in normal times, and compares the results of calculations by the two processor cores with each other in order to detect abnormalities in the system. Patent Document 2 discloses a system that compares the results of calculations by the processor core at the time of system startup with the results of calculations stored in advance in a memory in order to detect abnormalities in the system. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 6,065,135 [Patent Document 2] US Patent Application Publication No. 2006 / 0062046 Summary of the Invention [Problem to be solved by the invention]

[0004] A similar configuration can also be applied to a computing system equipped with an NPU (Neural network Processing Unit) that executes computational processing using a neural network. However, in Patent Document 1, a processor core for anomaly detection is provided in addition to a processor core used in normal times, which creates a problem of waste in the system configuration. In addition, in Patent Document 2, the computation results previously stored in memory can only be compared at the time of system startup, and anomaly detection cannot be performed for newly output computation results. [Means for solving the problem]

[0005] The present disclosure can be realized in the following forms.

[0006] According to one aspect of the present disclosure, there is provided a computing system (100) that executes computational processing using a neural network model. This arithmetic system comprises a plurality of processor cores (PC1 to PC8) that execute the arithmetic processing, an arithmetic allocation unit (11) that determines an arithmetic core that is a processor core among the plurality of processors to execute the arithmetic processing in accordance with the computational load of the arithmetic processing and causes the arithmetic core to execute the arithmetic processing, and an abnormality detection unit (12) that detects the presence or absence of an abnormality in the processor cores, wherein the arithmetic allocation unit causes at least a portion of the plurality of processor cores that are not the arithmetic cores to execute an abnormality detection calculation, which is an operation obtained based on the basic operation, in parallel with a basic operation that is the arithmetic processing to be executed by the arithmetic core, and the abnormality detection unit determines that there is no abnormality in the arithmetic core and the abnormality detection core that is the processor core that executed the abnormality detection calculation if a difference between a first operation result that is a result of the basic operation and a second operation result that is a result of the abnormality detection calculation satisfies a predetermined tolerance condition, and determines that there is an abnormality in at least a portion of the arithmetic core and the abnormality detection core if the difference does not satisfy the tolerance condition.

[0007] According to this embodiment of the control device, an arithmetic core is selected from among a plurality of processors according to the arithmetic load of the arithmetic processing, and the presence or absence of an abnormality can be detected by determining whether or not the result of the basic arithmetic operation executed in the arithmetic core matches the result of the anomaly detection arithmetic operation executed in the multiple anomaly detection core. Therefore, compared to a configuration that includes a processor core for anomaly detection in addition to a processor core used under normal circumstances, the presence or absence of an abnormality can be detected while suppressing waste in the system configuration. In addition, the presence or absence of an abnormality can be detected by using the newly output arithmetic result. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a schematic configuration of a computing system according to an embodiment of the present invention; [Diagram 2] FIG. 2 is an explanatory diagram illustrating an example of a configuration of a neural network model. [Diagram 3] 5 is a flowchart showing a procedure of an abnormality detection process according to the first embodiment. [Figure 4] 5 is a flowchart showing a procedure of an abnormality detection process according to the first embodiment. [Diagram 5] FIG. 4 is an explanatory diagram showing an example of allocation of arithmetic processing in the first embodiment. [Figure 6] 10 is a flowchart showing the procedure of an abnormality detection process according to a second embodiment. [Figure 7] 10 is a flowchart showing the procedure of an abnormality detection process according to a second embodiment. [Figure 8] FIG. 11 is an explanatory diagram showing an example of allocation of arithmetic processing in the second embodiment. [Figure 9] 13 is a flowchart showing the procedure of an abnormality detection process according to a third embodiment. [Figure 10] FIG. 13 is an explanatory diagram showing an example of allocation of arithmetic processing in the third embodiment. [Figure 11] FIG. 11 is an explanatory diagram showing an example of allocation of arithmetic processing in another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] A. First embodiment: A-1. System configuration: The computing system 100 of this embodiment executes computational processing using a neural network model. In this embodiment, the computing system 100 performs computational processing for identifying pedestrians, structures, and the like included in image data captured by a camera mounted on a vehicle. In this embodiment, the neural network model is configured as a multi-class classifier that outputs the probability that each object included in the image data belongs to each of a plurality of predetermined classes based on the image data. Note that the computing system 100 may execute computational processing not only on image data but also on voice data or text data.

[0010] FIG. 2 shows an example of a neural network model. The neural network model shown in FIG. 2 has a convolution layer L1, a pooling layer L2, a convolution layer L3, a pooling layer L4, and a fully connected layer L5. The calculation system 100 executes calculations in each layer in the above order. The calculation system 100 may execute calculation processing using a neural network model of any configuration, not limited to the neural network model of the configuration shown in FIG. 2. The calculation system 100 may execute calculation processing using a neural network model of a single type, not limited to the calculation processing using a single type of neural network model, but using multiple types of neural network models in sequence.

[0011] 1, the arithmetic system 100 includes processor cores PC1 to PC8, an arithmetic control unit 10, and a semiconductor memory device 20. The processor cores PC1 to PC8, the arithmetic control unit 10, and the semiconductor memory device 20 are communicably connected to each other via a bus BS. The arithmetic system 100 may include a cache memory, a register, and the like in addition to the above configuration.

[0012] In this embodiment, the processor cores PC1 to PC8 are configured as NPUs (Neural network Processing Units) that execute arithmetic processing using a neural network model. The specific configuration of the processor cores PC1 to PC8 is similar to that of a known NPU, and detailed description will be omitted. In this embodiment, the processor cores PC1 to PC8 receive a single image data, and divide different areas of the image data among the multiple processor cores, and execute arithmetic processing in parallel with each other. Note that any one of the processor cores PC1 to PC8 may execute arithmetic processing targeting a single image data.

[0013] The number of processor cores included in the computing system 100 is not limited to eight, and may be any number equal to or greater than two, as long as the computing process with the maximum computation load expected in advance in the computing system 100 can be completed within a predetermined allowable time. The "allowable time" is set, for example, as an upper limit of the time allowed for identifying pedestrians, structures, etc. present around the vehicle. In the following description, the computation load of the computation process that requires all processor cores to operate in parallel in order to complete the computation process within the allowable time is referred to as the "maximum computation load." The "computation load of the computation process" is determined by the type of neural network model used in the computation process, more specifically, the number of layers constituting the neural network model and the type of computation executed in each layer.

[0014] The arithmetic control unit 10 includes an arithmetic allocation unit 11 and an abnormality detection unit 12. The arithmetic allocation unit 11 determines which processor core (hereinafter also referred to as a "arithmetic core") is to execute the arithmetic process among the processor cores PC1 to PC8 in accordance with the arithmetic load of the arithmetic process, and causes the arithmetic core to execute the arithmetic process. In the following description, the arithmetic process executed in the arithmetic core is also referred to as a "basic operation". In this embodiment, the arithmetic allocation unit 11 determines the minimum number of processor cores (hereinafter also referred to as a "minimum number of cores") required to complete the basic operation within an allowable time as the arithmetic cores. The minimum number of cores is set in advance for each type of basic operation to be executed.

[0015] Furthermore, the computation allocation unit 11 causes the processor cores that are not computation cores among the processor cores PC1 to PC8 to execute an anomaly detection computation. The "anomaly detection computation" refers to computation processing executed to detect the presence or absence of an anomaly in a processor core, and is obtained based on basic computation. The computation allocation unit 11 determines the number of processor cores (hereinafter also referred to as "anomaly detection cores") that execute the anomaly detection computation according to the computation load of the basic computation. In this embodiment, the computation allocation unit 11 causes the anomaly detection cores to execute computation processing that is the same as the basic computation as the anomaly detection computation. A specific method of allocation of anomaly detection computation to the anomaly detection cores by the computation allocation unit 11 will be described later.

[0016] The abnormality detection unit 12 detects the presence or absence of an abnormality in the processor core by determining whether or not the difference between the calculation result of the basic calculation and the calculation result of the calculation for abnormality detection satisfies a predetermined allowable condition. The abnormality detection unit 12 may be a functional unit realized on software by executing a program, or may be a functional unit realized on hardware by a logic circuit. Specific processing by the abnormality detection unit 12 will be described later.

[0017] The semiconductor memory device 20 stores various data input / output via the bus BS in the arithmetic processing executed by the processor cores PC1 to PC8, such as image data, coefficients used in the arithmetic processing, arithmetic results, etc. In this embodiment, the semiconductor memory device 20 is configured as a DRAM (Dynamic Random Access Memory).

[0018] A-2. Anomaly detection processing: The operation control unit 10 executes the abnormality detection process shown in Figures 3 and 4, and causes the abnormality detection core to execute an abnormality detection calculation in parallel with the basic calculation by the operation core according to the calculation load of the basic calculation, thereby detecting the presence or absence of an abnormality in the processor core. The abnormality detection process is executed every time a basic calculation is started in the operation system 100. In the following description, it is assumed that the calculation process executed is for image data.

[0019] 3, the computation allocation unit 11 judges whether the computation load of the basic computation is equal to or less than half the maximum computation load. If it is judged that the computation load is greater than half the maximum computation load (step S10: No), the computation allocation unit 11 causes the computation core to execute the basic computation and ends the abnormality detection process. That is, in this case, the abnormality detection unit 12 does not execute the abnormality detection.

[0020] On the other hand, if it is determined that the computational load is equal to or less than 1 / 2 of the maximum computational load (step S10: Yes), the computation allocation unit 11 determines in step S20 shown in FIG. 4 whether the computational load of the basic computation is equal to or less than 1 / 3 of the maximum computational load.

[0021] If it is determined that the computational load is 1 / 3 or less of the maximum computational load (step S20: Yes), in step S30, the computation allocation unit 11 allocates computational processing to the processor core so that, in addition to the basic computation, two computation processes identical to the basic computation are executed in parallel as computations for abnormality detection.

[0022] The allocation of calculation processes in step S30 will be described more specifically with reference to the example shown in Fig. 5. In the example shown in Fig. 5, the minimum number of cores for basic calculations is set to two. In this case, the calculation allocation unit 11 allocates basic calculations to processor cores PC1 and PC2, allocates a first abnormality detection calculation to processor cores PC3 and PC4, and allocates a second abnormality detection calculation to processor cores PC5 and PC6. In the example shown in Fig. 5, processor cores PC1 and PC2 correspond to calculation cores, and processor cores PC3, PC4 and processor cores PC5 and PC6 correspond to abnormality detection cores.

[0023] 5, the arithmetic allocation unit 11 does not allocate arithmetic processing to the processor cores PC7 and PC8. In a configuration in which arithmetic processing is not allocated to the processor cores PC7 and PC8, it is possible to suppress an increase in power consumption and processing load in the arithmetic system 100, compared to a configuration in which arithmetic processing is allocated to the processor cores PC7 and PC8. Note that the arithmetic allocation unit 11 may allocate arithmetic processing to the processor cores PC7 and PC8.

[0024] In step S40 shown in FIG. 4, the anomaly detection unit 12 acquires three intermediate operation results of the basic operation and two anomaly detection operations, which are output in parallel. The "intermediate operation results" refer to the operation results in the intermediate layers among the multiple layers constituting the neural network model. In the example shown in FIG. 2, the convolution layer L1, the pooling layer L2, the convolution layer L3, and the pooling layer L4 correspond to the intermediate layers, and in this embodiment, the operation result in the pooling layer L2 is acquired as the intermediate operation result. Note that the anomaly detection unit 12 may acquire each operation result in two or more intermediate layers, not limited to one of the multiple intermediate layers, as the intermediate operation result. In the example shown in FIG. 5, the basic operation and the two anomaly detection operations are executed by the same number of processor cores, so that the intermediate operation results for the corresponding pixels are output in parallel.

[0025] The anomaly detection unit 12 acquires each intermediate calculation result for each corresponding pixel, each time the intermediate calculation results of the basic calculation and the two anomaly detection calculations are output in parallel. More specifically, the anomaly detection unit 12 directly acquires each intermediate calculation result output from the calculation core and the anomaly detection core. Note that the anomaly detection unit 12 may acquire from the semiconductor memory device 20 each intermediate calculation result output from the calculation core and the anomaly detection core and temporarily stored in the semiconductor memory device 20.

[0026] 4, the anomaly detection unit 12 determines whether or not the three intermediate calculation results of the basic calculation and the two anomaly detection calculations match each other as an allowable condition. Since the anomaly detection unit 12 makes the determination using the intermediate calculation results, it is possible to detect an anomaly in the processor core at an early stage without waiting for the output of the final calculation result described later, and it is possible to suppress an increase in the time required for the anomaly detection process.

[0027] The abnormality detection unit 12 may perform the determination in step S50 on all pixels in the image data, or may perform the determination on a predetermined portion of the pixels in the image data. In a mode in which the determination is performed on all pixels, the presence or absence of an abnormality can be detected with greater accuracy. On the other hand, in a mode in which the determination is performed on a portion of the pixels, the number of times the determination is performed can be reduced, thereby reducing the increase in the processing load and processing time in the abnormality detection unit 12. Which determination method to adopt may be arbitrarily determined in consideration of the length of the allowable time and the required accuracy of abnormality detection, as described above.

[0028] If it is determined that the three intermediate calculation results do not match each other (step S50: No), in step S84, the abnormality detection unit 12 determines that at least a part of the calculation core and the abnormality detection core has an abnormality. "The three intermediate calculation results of the basic calculation and the two abnormality detection calculations do not match each other" means that at least one of the three intermediate calculation results does not match the other intermediate calculation results. Since the abnormality detection unit 12 determines whether the three intermediate calculation results match each other, when the three intermediate calculation results do not match each other, it is possible to identify a processor core in which an abnormality is likely to occur. For example, in the example shown in FIG. 5, when the intermediate calculations of the first abnormality detection calculation and the second abnormality detection calculation match each other and only the intermediate calculation results of the basic calculation are different, it is possible to identify that an abnormality is likely to occur in the processor core PC1 or the processor core PC2. After step S84 is completed, the abnormality detection process is terminated.

[0029] On the other hand, in FIG. 4, if it is determined that the three intermediate calculation results match each other (step S50: Yes), in step S60, the anomaly detection unit 12 acquires three final calculation results of the basic calculation and the two anomaly detection calculations, which are output in parallel. The "final calculation result" means the calculation result in the final layer of the multiple layers constituting the neural network model. In the example shown in FIG. 2, L5 corresponds to the final layer. For the same reason as in the case of the intermediate calculation results described above, the final calculation results for corresponding pixels are output in parallel.

[0030] As in the case of the intermediate calculation results described above, the anomaly detection unit 12 acquires each final calculation result for each corresponding pixel, each time the final calculation results of the basic calculation and the two anomaly detection calculations are output in parallel. More specifically, the anomaly detection unit 12 directly acquires each final calculation result output from the calculation core and the anomaly detection core. Note that the anomaly detection unit 12 may acquire from the semiconductor memory device 20 each final calculation result output from the calculation core and the anomaly detection core and temporarily stored in the semiconductor memory device 20.

[0031] 4, the abnormality detection unit 12 determines whether or not the three final calculation results of the basic calculations and the two abnormality detection calculations match each other as an allowable condition. Since the abnormality detection unit 12 makes the determination using the final calculation results, the reliability of the final calculation results can be guaranteed.

[0032] If it is determined that the three final calculation results match each other (step S70: Yes), in step S80, the abnormality detection unit 12 determines that there is no abnormality in the calculation core and the abnormality detection core. After step S80 is completed, the abnormality detection process ends.

[0033] On the other hand, if it is determined that the three final calculation results do not match each other (step S70: No), in step S84, the abnormality detection unit 12 determines that at least a part of the calculation core and the abnormality detection core has an abnormality. "The three final calculation results of the basic calculation and the two abnormality detection calculations do not match each other" means that at least one of the three final calculation results does not match the other final calculation results. Since the abnormality detection unit 12 determines whether the three final calculation results match each other or not, when the three final calculation results do not match each other, it is possible to identify a processor core that is likely to have an abnormality. The method of identifying a processor core that is likely to have an abnormality is the same as when the determination result in step S50 described above is No. After step S84 is completed, the abnormality detection process ends.

[0034] Returning to the judgment in step S20 described above, if it is judged that the computational load of the basic operation is greater than 1 / 3 of the maximum computational load (step S20: No), in step S32, the computation allocation unit 11 assigns computation processing to the processor core so that, in addition to the basic operation, one computation process that is the same as the basic operation is executed in parallel as a computation for abnormality detection.

[0035] In step S42, the anomaly detection unit 12 acquires two intermediate calculation results, the basic calculation and the calculation for anomaly detection, which are output in parallel. The intermediate layer from which the intermediate calculation results are acquired and the timing for acquiring the intermediate calculation results are the same as those in step S40 described above.

[0036] In step S52, the abnormality detection unit 12 determines whether or not the two intermediate calculation results of the basic calculation and the calculation for abnormality detection match each other as an allowable condition. If it is determined that the two intermediate calculation results do not match each other (step S52: No), in step S84, the abnormality detection unit 12 determines that there is an abnormality in at least a part of the calculation core and the abnormality detection core. After step S84 is completed, the abnormality detection process ends.

[0037] On the other hand, if it is determined that the two intermediate calculation results match each other (step S52: Yes), in step S62, the abnormality detection unit 12 acquires two final calculation results, the basic calculation and the calculation for abnormality detection, which are output in parallel. The timing of acquiring the final calculation results is the same as in step S60 described above.

[0038] In step S72, the abnormality detection unit 12 determines whether or not the two final calculation results of the basic calculation and the calculation for abnormality detection match each other, as an allowable condition. If it is determined that the two final calculation results match each other (step S72: Yes), in step S82, the abnormality detection unit 12 determines that there is no abnormality in the calculation core and the abnormality detection core. After step S82 is completed, the abnormality detection process ends.

[0039] On the other hand, if it is determined that the two final calculation results do not match each other (step S72: No), in step S84, the abnormality detection unit 12 determines that there is an abnormality in at least a part of the calculation core and the abnormality detection core. After step S84 is completed, the abnormality detection process is terminated.

[0040] According to the computing system 100 of the first embodiment described above, a computing core is selected from among a plurality of processors in accordance with the computation load of the computation process, and the presence or absence of an abnormality can be detected by determining whether or not the computation result of the basic computation executed in the computing core matches the computation result of the anomaly detection computation executed in the anomaly detection core. Therefore, compared to a configuration that includes a processor core for anomaly detection in addition to a processor core used under normal circumstances, the presence or absence of an abnormality can be detected while suppressing waste in the system configuration.

[0041] Furthermore, since the abnormality detection unit 12 detects the presence or absence of an abnormality using the calculation results output in parallel with each other, the presence or absence of an abnormality can be detected in real time.

[0042] Furthermore, the calculation allocation unit 11 causes the anomaly detection core to execute calculation processing that is the same as the basic calculation as the anomaly detection calculation, and the anomaly detection unit 12 detects the presence or absence of an anomaly by determining whether or not the calculation result of the basic calculation and the calculation result of the anomaly detection calculation match each other, thereby making it easy to detect an anomaly.

[0043] In addition, since the anomaly detection unit 12 judges the presence or absence of an anomaly using the intermediate calculation result, it is possible to detect an anomaly at an early stage without waiting for the output of the final calculation result, and it is possible to suppress an increase in the time required for anomaly detection.In addition, since the anomaly detection unit 12 judges the presence or absence of an anomaly using the final calculation result, it is possible to ensure the reliability of the final calculation result.

[0044] B. Second embodiment: As shown in Fig. 6, the computing system 100 of the second embodiment differs from the computing system 100 of the first embodiment in that the computing system 100 executes the process shown in Fig. 7 instead of step S12 shown in Fig. 3. The system configuration and other steps in the anomaly detection process of the computing system 100 of the second embodiment are the same as those of the computing system 100 of the first embodiment, so the same configurations and steps are denoted by the same reference numerals and detailed descriptions thereof are omitted.

[0045] If it is determined in step S10 that the computational load of the basic operation is equal to or less than half the maximum computational load (step S10: No), in step S122 shown in FIG. 7, in addition to the basic operation, computation processing is assigned to the processor core so that one computation process identical to the basic operation is executed in parallel as a computation for abnormality detection.

[0046] The allocation of calculation processes in step S122 will be described more specifically with reference to the example shown in Fig. 8. In the example shown in Fig. 8, the minimum number of cores for basic calculations is set to 6. In this case, the calculation allocation unit 11 allocates basic calculations to processor cores PC1 to PC6, and allocates abnormality detection calculations to processor cores PC7 and PC8. In the example shown in Fig. 8, processor cores PC1 to PC6 correspond to calculation cores, and processor cores PC7 and PC8 correspond to abnormality detection cores.

[0047] In step S124 shown in FIG. 7, the anomaly detection unit 12 acquires an intermediate calculation result of the basic calculation and an intermediate calculation result of the calculation for anomaly detection, which is output later than the intermediate calculation result. The intermediate layer from which the intermediate calculation results are acquired is the same as that in step S40 described above. In the example shown in FIG. 8, the number of processor cores executing the calculation for anomaly detection is less than the number of processor cores executing the basic calculation. Therefore, the time required for the calculation in the intermediate layer to be completed in the calculation for anomaly detection is longer than the time required for the calculation in the intermediate layer to be completed in the basic calculation. In this way, the intermediate calculation result of the calculation for anomaly detection is output later than the intermediate calculation result of the basic calculation for the corresponding pixels.

[0048] The anomaly detection unit 12 acquires each intermediate calculation result of the anomaly detection calculation for corresponding pixels each time the intermediate calculation result of the anomaly detection calculation is output after the intermediate calculation result of the basic calculation is output. More specifically, the anomaly detection unit 12 directly acquires the intermediate calculation result of the anomaly detection calculation output from the anomaly detection core, and acquires from the semiconductor memory device 20 the intermediate calculation result of the basic calculation output from the calculation core and temporarily stored in the semiconductor memory device 20. The anomaly detection unit 12 may also acquire from the semiconductor memory device 20 the intermediate calculation result of the anomaly detection calculation output from the anomaly detection core and temporarily stored in the semiconductor memory device 20.

[0049] 7, the abnormality detection unit 12 determines whether or not the two intermediate calculation results of the basic calculation and the calculation for abnormality detection match each other as an allowable condition. If it is determined that the two intermediate calculation results do not match each other (step S126: No), the abnormality detection unit 12 determines in step S134 that there is an abnormality in at least a part of the calculation core and the abnormality detection core. After step S134 is completed, the abnormality detection process ends.

[0050] On the other hand, if it is determined that the two intermediate calculation results match each other (step S126: Yes), in step S128, the abnormality detection unit 12 acquires the final calculation result of the basic calculation and the final calculation result of the calculation for abnormality detection that is output later than the final calculation result. For the same reason as in the case of the intermediate calculation results described above, the final calculation result of the calculation for abnormality detection is output later than the final calculation result of the basic calculation for the corresponding pixels.

[0051] As in the case of the intermediate calculation results described above, the anomaly detection unit 12 acquires each final calculation result for mutually corresponding pixels each time the final calculation result of the anomaly detection calculation is output after the final calculation result of the basic calculation is output. More specifically, the anomaly detection unit 12 directly acquires the final calculation result of the anomaly detection calculation output from the anomaly detection core, and acquires from the semiconductor memory device 20 the final calculation result of the basic calculation output from the calculation core and temporarily stored in the semiconductor memory device 20. The anomaly detection unit 12 may also acquire from the semiconductor memory device 20 the final calculation result of the anomaly detection calculation output from the anomaly detection core and temporarily stored in the semiconductor memory device 20.

[0052] In step S130, the abnormality detection unit 12 determines whether or not the two final calculation results of the basic calculation and the calculation for abnormality detection match each other, as an allowable condition. If it is determined that the two final calculation results match each other (step S130: Yes), in step S132, the abnormality detection unit 12 determines that there is no abnormality in the calculation core and the abnormality detection core. After step S132 is completed, the abnormality detection process ends.

[0053] On the other hand, if it is determined that the two final calculation results do not match each other (step S130: No), in step S134, the abnormality detection unit 12 determines that there is an abnormality in at least a part of the calculation core and the abnormality detection core. After step S134 is completed, the abnormality detection process ends.

[0054] According to the computing system 100 of the second embodiment described above, the presence or absence of an abnormality is detected by using the result of the basic computation and the result of the computation for anomaly detection output after the result of the basic computation. Therefore, even if the computation load of the basic computation is large and the processor core is not able to output the result of the basic computation and the result of the computation for anomaly detection in parallel, the presence or absence of an abnormality can be detected.

[0055] C. Third embodiment: The computing system 100 of the third embodiment differs from the computing system 100 of the second embodiment in that the computing system 100 executes the process shown in Fig. 9 in the anomaly detection process instead of the process shown in Fig. 7. The system configuration of the computing system 100 of the third embodiment and other steps in the anomaly detection process are the same as those of the computing system 100 of the second embodiment, so the same configurations and steps are denoted by the same reference numerals and detailed descriptions thereof are omitted.

[0056] In step S122A, the calculation allocation unit 11 allocates calculation processing to the processor core so that, in addition to the basic calculation, two lightweight calculations are executed in parallel as calculations for anomaly detection. The "lightweight calculation" means a calculation processing that uses a neural network model that has been trained in advance so that the calculation load is reduced compared to the basic calculation. As a method for reducing the calculation load, for example, a known lightweight technology such as pruning or sparsity that reduces the calculation load by replacing the values ​​of some coefficients that have a low contribution to the calculation result with 0 can be applied.

[0057] The allocation of calculation processes in step S122A will be described more specifically with reference to the example shown in FIG. 10. In the example shown in FIG. 10, the minimum number of cores for basic calculations is set to 6. In this case, the calculation allocation unit 11 allocates basic calculations to the processor cores PC1 to PC6. In the example shown in FIG. 10, the calculation allocation unit 11 allocates a first light-weight calculation, the calculation load of which is suppressed to 1 / 6 of the calculation load of the basic calculation, to the processor core PC7 as an abnormality detection calculation, and allocates a second light-weight calculation, which is the same calculation process as the first light-weight calculation, to the processor core PC8. In the example shown in FIG. 10, the processor cores PC1 to PC6 correspond to calculation cores, and the processor cores PC7 and PC8 correspond to abnormality detection cores.

[0058] In step S124A shown in Fig. 9, the abnormality detection unit 12 obtains three intermediate calculation results of the basic calculation and two lightening calculations that are output in parallel. In the example shown in Fig. 10, the number of processor cores that execute each lightening calculation is 1 / 6 of the number of processor cores that execute the basic calculation, but the calculation load of the lightening calculation is also lightened to 1 / 6 of the calculation load of the basic calculation. Therefore, the intermediate calculation results for corresponding pixels are output in parallel.

[0059] In step S126A, in this embodiment, the abnormality detection unit 12 determines whether all of the following conditions (1) to (3) are satisfied as the permissible conditions. The thresholds in the following conditions (2) and (3) may be values ​​previously determined through experiments, such as the difference between the results of intermediate calculations when a basic calculation and a lightweight calculation are respectively executed in a processor core that has been confirmed to be free of abnormalities. (1) The intermediate calculation results of the first weight reduction calculation and the second weight reduction calculation are consistent with each other. (2) The difference between the results of each intermediate calculation between the basic calculation and the first lightening calculation is less than a predetermined threshold. (3) The difference between the results of each intermediate calculation between the basic calculation and the second lightweight calculation is less than a predetermined threshold.

[0060] If it is determined that at least one of the above conditions (1) to (3) is not satisfied (step S128A: No), in step S134, the abnormality detection unit 12 determines that an abnormality exists in at least a part of the calculation core and the abnormality detection core. After step S134 is completed, the abnormality detection process ends.

[0061] On the other hand, if it is determined that all of the above conditions (1) to (3) are satisfied (step S126A: Yes), in step S128A, the abnormality detection unit 12 acquires three final calculation results of the basic calculation and the two lightening calculations, which are output in parallel. For the same reason as in the case of the intermediate calculation results described above, the final calculation results for corresponding pixels are output in parallel.

[0062] In step S130A, in this embodiment, the abnormality detection unit 12 determines whether all of the following conditions (4) to (6) are satisfied as permissible conditions. Furthermore, the thresholds in the following conditions (5) and (6) may be determined in advance in the same manner as the thresholds in the above conditions (2) and (3). (4) The final calculation results of the first weight reduction calculation and the second weight reduction calculation are consistent with each other. (5) The difference between the final calculation results of the basic calculation and the first weighting calculation is less than a predetermined threshold. (6) The difference between the final calculation results of the basic calculation and the second lightweight calculation is less than a predetermined threshold.

[0063] If it is determined that all of the above conditions (4) to (6) are satisfied (step S130A: Yes), in step S132, the abnormality detection unit 12 determines that there is no abnormality in the arithmetic core and the abnormality detection core. After step S132 is completed, the abnormality detection process ends.

[0064] On the other hand, if it is determined that at least one of the above conditions (4) to (6) is not satisfied (step S130A: No), in step S134, the abnormality detection unit 12 determines that an abnormality exists in at least a part of the calculation core and the abnormality detection core. After step S134 is completed, the abnormality detection process ends.

[0065] According to the computing system 100 of the third embodiment described above, the anomaly detection core executes a lightening computation, and it is determined whether or not the difference between the computation result of the basic computation and the computation result of the lightening computation satisfies an allowable condition including that the difference between the computation result of the basic computation and the computation result of the lightening computation is less than a predetermined threshold. Therefore, even if the computation load of the basic computation is large in the computation core and the anomaly detection core, and the same computation process as the basic computation cannot be executed in parallel as the anomaly detection computation, the basic computation and the lightening computation can be executed in parallel to detect the presence or absence of an anomaly, and the presence or absence of an anomaly can be detected in real time using the computation results output in parallel to each other.

[0066] D. Fourth embodiment: The computing system 100 of the fourth embodiment differs from the computing system 100 of the third embodiment in that the allowable conditions in step S130A of the abnormality detection process are different. Since the system configuration of the computing system 100 of the fourth embodiment and other procedures in the abnormality detection process are the same as those of the computing system 100 of the third embodiment, the same configurations and procedures are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0067] In step S130A shown in FIG. 9, the abnormality detection unit 12 determines whether the following condition (7) is satisfied as the permissible condition, and whether at least one of the conditions (8) and (9) is satisfied in this embodiment. (7) In the final calculation results of the first lightening calculation and the second lightening calculation, the top five classes to which the objects included in the image data have a high probability of belonging are identical to each other. (8) In the final calculation results of the basic calculation and the first light weighting calculation, there is at least one class that matches each other among the top five classes to which the object included in the image data has a high probability of belonging. (9) In the final calculation results of the basic calculation and the second lightening calculation, there is at least one class that matches each other among the top five classes to which the object included in the image data has a high probability of belonging.

[0068] In the above conditions (7) to (9), the number of higher order classes to be compared is not limited to 5. In addition, in the above conditions (8) and (9), the lower limit of the number of classes that are required to match each other may be 2 or more.

[0069] According to the calculation system 100 of the fourth embodiment described above, the anomaly detection unit 12 can also detect the presence or absence of an anomaly by determining whether or not at least one of the top five classes to which an object included in the image data has a high probability of belonging in the calculation result of the basic calculation and the top five classes to which an object included in the image data has a high probability of belonging in the calculation result of the anomaly detection calculation satisfies an allowable condition including whether or not the class matches each other.

[0070] E. Fifth embodiment: The computing system 100 of the fifth embodiment differs from the computing system 100 of the fourth embodiment in that the detection core executes a bit number reduction calculation instead of a lightening calculation in step S122A of the abnormality detection process. The system configuration of the computing system 100 of the fifth embodiment and other steps in the abnormality detection process are the same as those of the computing system 100 of the fourth embodiment, so the same configurations and steps are denoted by the same reference numerals and detailed descriptions thereof are omitted.

[0071] The "bit-number reduction calculation" refers to a calculation process that utilizes a neural network model that has been trained in advance using weight coefficients with a smaller number of bits than the weight reduction calculation described above. In this embodiment, the number of bits of the weight coefficients in the weight reduction calculation is 8 bits, whereas the number of bits of the weight coefficients in the bit-number reduction calculation is set to 4 bits. Note that the number of bits in the bit-number reduction calculation is not limited to 4 bits, and may be set to any number of bits smaller than the number of bits of the weight coefficients in the weight reduction calculation.

[0072] In the form in which the lightening calculation is executed as the calculation for anomaly detection, the weighting coefficients used in the basic calculation and the weighting coefficients used in the lightening calculation are different from each other, so that a larger memory capacity is required for storing the weighting coefficients in the semiconductor memory device 20 compared to the form in which the basic calculation is executed as the calculation for anomaly detection. Also, because different weighting coefficients are read out from the semiconductor memory device 20 for the basic calculation and the lightening calculation, the memory bandwidth is compressed compared to the case in which only the weighting coefficients used in the basic calculation are read out.

[0073] In the bit number reduction calculation, weighting coefficients having a smaller number of bits are used compared to the light weight calculation, so that it is possible to suppress an increase in the memory capacity for storing the weighting coefficients in the semiconductor memory device 20. Also, it is possible to suppress pressure on the memory bandwidth when the weighting coefficients are read out from the semiconductor memory device 20.

[0074] According to the calculation system 100 of the fifth embodiment described above, weighting coefficients having a smaller number of bits compared to the light weight calculation are used, so that it is possible to suppress an increase in the memory capacity for storing the weighting coefficients in the semiconductor memory device 20. Also, it is possible to suppress pressure on the memory bandwidth when the weighting coefficients are read out from the semiconductor memory device 20.

[0075] F. Other Embodiments: (F1) In the above embodiment, the anomaly detection unit 12 executes both the judgment using the intermediate calculation result and the judgment using the final calculation result, but the present disclosure is not limited to this. The anomaly detection unit 12 may execute only one of the judgment using the intermediate calculation result and the judgment using the final calculation result.

[0076] (F2) In the above embodiment, the processor cores PC1 to PC8 receive a single image data, and the processor cores share different areas of the image data and execute arithmetic processing in parallel with each other, but the present disclosure is not limited to this. The processor cores PC1 to PC8 may receive a plurality of image data, and the processor cores may each share different image data and execute arithmetic processing in parallel with each other.

[0077] A more detailed description will be given with reference to FIG. 11. As shown in FIG. 11, the processor cores PC1 and PC2 may execute a first basic operation on the first image data, the processor cores PC3 and PC4 may execute a second basic operation on the second image data, and the processor cores PC5 and PC6 may execute a third basic operation on the third image data. In this case, the processor cores PC7 and PC8 may execute the same operation process as the first basic operation on the first image data as the processor cores PC1 and PC2 as an abnormality detection operation. By executing each operation process in this manner, the processor cores PC1 to PC6 can execute each basic operation in parallel on three image data, while detecting the presence or absence of an abnormality in the processor cores PC1, PC2, PC7, and PC8. Furthermore, after the above-mentioned operation process is completed, when the processor cores PC1 to PC6 execute basic operations in parallel on three new image data, the processor cores PC7 and PC8 may execute an abnormality detection operation on the same image data as the image data targeted by the processor cores PC3 and PC4, instead of the processor cores PC1 and PC2. By executing each calculation process in this manner, each time a calculation process is performed on new image data, it is possible to sequentially detect whether or not an abnormality has occurred in a processor core that is different from the previous time, and it is possible to detect whether or not an abnormality has occurred in all processor cores in turn while executing each basic calculation in parallel on three image data.

[0078] (F3) In the third embodiment, the computation allocation unit 11 allocates computation to the processor core so that two lightened computations are executed as computations for anomaly detection in addition to the basic computation in step S122A of the anomaly detection process, but the present disclosure is not limited thereto. The computation allocation unit 11 may allocate computation to the processor core so that one lightened computation is executed as computations for anomaly detection in addition to the basic computation in step S122A. When the computation load of the basic computation is the same as the example shown in FIG. 10, the computation allocation unit 11 may allocate one computation for anomaly detection to the processor cores PC7 and PC8. In this case, the computation load of the lightened computation may be reduced to 1 / 3 of the basic computation. In this configuration, compared to a configuration in which the computation load of the lightened computation is further reduced, it is possible to prevent the difference between the computation results of the basic computation and the lightened computation from becoming large, and to prevent a decrease in the accuracy of anomaly detection.

[0079] (F4) In the third embodiment, the computation allocation unit 11 causes the anomaly detection core to execute, as the lightweight computation, a computation process in which a known lightweight technique is applied to the basic computation, which suppresses the computation load by replacing the values ​​of some coefficients that have a low contribution to the computation result with 0, but the present disclosure is not limited to this. The computation allocation unit 11 may cause the anomaly detection core to execute, as the lightweight computation, a computation process in which the computation load is suppressed by using a neural network model different from the neural network model used in the basic computation. For example, when ResNet is used as the neural network model in the basic computation, MobileNet, which is a neural network model that realizes image recognition similarly to ResNet, may be used in the lightweight computation. Since the layer structure of MobileNet is simpler than that of ResNet, the computation load can be suppressed by using MobileNet in the lightweight computation more than the basic computation using ResNet.

[0080] The computing system 100 and the methods described herein may be implemented by a special-purpose computer provided by configuring a processor and memory programmed to perform one or more functions embodied in a computer program. Alternatively, the computing system 100 and the methods described herein may be implemented by a special-purpose computer provided by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the computing system 100 and the methods described herein may be implemented by one or more special-purpose computers configured by a combination of one or more hardware-programmed processors and memory and a processor configured with one or more hardware logic circuits. The computer program may also be stored on a computer-readable non-transitory tangible recording medium as instructions executed by the computer.

[0081] The present disclosure is not limited to the above-mentioned embodiment, and can be realized in various configurations without departing from the spirit of the present disclosure. For example, the technical features in each embodiment corresponding to the technical features in the form described in the Summary of the Invention column can be appropriately replaced or combined in order to solve some or all of the above-mentioned problems or to achieve some or all of the above-mentioned effects. Furthermore, if the technical feature is not described as essential in this specification, it can be appropriately deleted. (Form 1) A computing system (100) for performing computational processing using a neural network model, A plurality of processor cores (PC1 to PC8) for executing the arithmetic processing; an arithmetic allocation unit (11) that determines an arithmetic core, which is a processor core that is to execute the arithmetic processing, among the plurality of processors in accordance with a calculation load of the arithmetic processing, and causes the arithmetic core to execute the arithmetic processing; an abnormality detection unit (12) for detecting the presence or absence of an abnormality in the processor core; Equipped with the operation allocation unit causes at least a part of the processor cores other than the operation cores among the plurality of processor cores to execute an anomaly detection operation, which is an operation obtained based on the basic operation, in parallel with a basic operation, which is the operation process to be executed by the operation cores; The abnormality detection unit if a difference between a first calculation result which is a calculation result of the basic calculation and a second calculation result which is a calculation result of the abnormality detection calculation satisfies a predetermined allowable condition, it is determined that there is no abnormality in the calculation core and an abnormality detection core which is a processor core that has executed the abnormality detection calculation; if the difference does not satisfy the tolerance condition, it is determined that there is an abnormality in at least a part of the calculation core and the abnormality detection core; Calculation system. (Form 2) 2. The computing system according to claim 1, the abnormality detection unit detects the presence or absence of the abnormality by utilizing the first calculation result and the second calculation result output in parallel with the first calculation result. Calculation system. (Form 3) 2. The computing system according to claim 1, Further comprising a semiconductor memory device that stores the first operation result, the anomaly detection unit detects the presence or absence of the anomaly by utilizing the first calculation result read from the semiconductor memory device and the second calculation result output after the first calculation result. Calculation system. (Form 4) The computing system according to any one of aspects 1 to 3, the anomaly detection unit detects the presence or absence of the anomaly by using at least one of a final operation result, which is an operation result in a final layer of a plurality of layers constituting the neural network model, and an intermediate operation result, which is an operation result in an intermediate layer of the plurality of layers, as the first operation result and the second operation result. Calculation system. (Form 5) The computing system according to any one of aspects 1 to 4, the operation allocation unit causes the anomaly detection core to execute the same operation process as the basic operation as the anomaly detection operation; the permissible condition includes a condition that the first calculation result and the second calculation result are identical to each other; Calculation system. (Form 6) The computing system according to any one of aspects 1 to 4, the calculation allocation unit causes the anomaly detection core to execute, as the anomaly detection calculation, a light-weight calculation that has been learned in advance so as to have a smaller calculation load than the basic calculation; The permissible condition includes a condition that the difference is less than a predetermined threshold. Calculation system. (Form 7) The computing system according to any one of aspects 1 to 4, the neural network model is configured as a multi-class classifier that outputs, for each of a plurality of predetermined classes, a probability that the input data belongs to the class, based on the input data; the calculation allocation unit causes the anomaly detection core to execute, as the anomaly detection calculation, a light-weight calculation that has been learned in advance so as to have a smaller calculation load than the basic calculation; the permissible condition includes a condition that a predetermined number of classes in each of the top N classes with high probabilities in the first calculation result and the top N classes with high probabilities in the second calculation result are identical to each other; Calculation system. (Form 8) The computing system according to any one of aspects 1 to 7, the calculation allocation unit causes the anomaly detection core to execute, as the anomaly detection calculation, a bit number reduction calculation that has been learned in advance using a weighting coefficient having a smaller number of bits than a predetermined weight reduction calculation; Calculation system. [Explanation of symbols]

[0082] 11: operation allocation unit, 12: abnormality detection unit, 100: operation system, PC1 to PC8: processor core

Claims

1. A computing system (100) for performing computational processing using a neural network model, A plurality of processor cores (PC1 to PC8) for executing the arithmetic processing; an arithmetic allocation unit (11) that determines an arithmetic core, which is a processor core that is to execute the arithmetic processing, among the plurality of processors according to a calculation load of the arithmetic processing, and causes the arithmetic core to execute the arithmetic processing; an abnormality detection unit (12) for detecting the presence or absence of an abnormality in the processor core; Equipped with the operation allocation unit causes at least a part of the processor cores other than the operation cores among the plurality of processor cores to execute an anomaly detection operation, which is an operation obtained based on the basic operation, in parallel with a basic operation, which is the operation process to be executed by the operation cores; The abnormality detection unit if a difference between a first calculation result which is a calculation result of the basic calculation and a second calculation result which is a calculation result of the abnormality detection calculation satisfies a predetermined allowable condition, it is determined that there is no abnormality in the calculation core and an abnormality detection core which is a processor core that has executed the abnormality detection calculation; if the difference does not satisfy the tolerance condition, it is determined that there is an abnormality in at least a part of the calculation core and the abnormality detection core; Calculation system.

2. 2. The computing system of claim 1, the abnormality detection unit detects the presence or absence of the abnormality by utilizing the first calculation result and the second calculation result output in parallel with the first calculation result. Calculation system.

3. 2. The computing system of claim 1, Further comprising a semiconductor memory device that stores the first operation result, the abnormality detection unit detects the presence or absence of the abnormality by utilizing the first calculation result read from the semiconductor memory device and the second calculation result output after the first calculation result. Calculation system.

4. 2. The computing system of claim 1, the anomaly detection unit detects the presence or absence of the anomaly by using at least one of a final operation result, which is an operation result in a final layer of a plurality of layers constituting the neural network model, and an intermediate operation result, which is an operation result in an intermediate layer of the plurality of layers, as the first operation result and the second operation result. Calculation system.

5. A computing system according to any one of claims 1 to 4, the operation allocation unit causes the anomaly detection core to execute the same operation process as the basic operation as the anomaly detection operation; the permissible condition includes a condition that the first calculation result and the second calculation result match each other; Calculation system.

6. A computing system according to any one of claims 1 to 4, the calculation allocation unit causes the anomaly detection core to execute, as the anomaly detection calculation, a light-weight calculation that has been learned in advance so as to have a smaller calculation load than the basic calculation; The permissible condition includes a condition that the difference is less than a predetermined threshold. Calculation system.

7. A computing system according to any one of claims 1 to 4, the neural network model is configured as a multi-class classifier that outputs, for each of a plurality of predetermined classes, a probability that the input data belongs to the class, based on the input data; the calculation allocation unit causes the anomaly detection core to execute, as the anomaly detection calculation, a light-weight calculation that has been learned in advance so as to have a smaller calculation load than the basic calculation; the permissible condition includes a condition that a predetermined number of classes in each of the top N classes having the highest probability in the first calculation result and the top N classes having the highest probability in the second calculation result are identical to each other. Calculation system.

8. A computing system according to any one of claims 1 to 4, the calculation allocation unit causes the anomaly detection core to execute, as the anomaly detection calculation, a bit number reduction calculation that has been learned in advance using a weighting coefficient having a smaller number of bits than a predetermined weight reduction calculation; Calculation system.

Images