Transmission device and transmission system

Abstract

To provide a transmission device suitable for long distance transmission between a server and a counter device.SOLUTION: A transmission device transmits signals between a server and a counter device. The transmission device has a memory unit, and a control unit that controls a first queue in the server and a second queue in the server and also controls the memory unit. When the control unit detects issuance of a processing request from the server to the counter device, it queues the processing request in the first queue, acquires data corresponding to the processing request from the server, and stores the acquired data in the memory unit. After requesting transfer of the data and the processing request to the counter device, the control unit queues processing completion of the processing request in the second queue, and releases the processing completion queue before executing the processing request in the counter device.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a transmission device and a transmission system. [Background technology]

[0002] Currently, for example, in data communications within a data center, NVMe (Non-Volatile Memory express) is known as a protocol used when a central processing unit (CPU) in a compute server accesses high-speed SSD (Solid State Drive) storage.

[0003] Also, NVMe-of (over fabric) is known as an extension of NVMe for the purpose of realizing high-speed and efficient data communication between a compute server and a storage server. NVMe-of enables going beyond fabrics such as L2SW by encapsulating with, for example, Ethernet (registered trademark) or Infini-band protocol. For data communication of NVMe-of, for example, NVMe-over RDMA using the RDMA (Remote Direct Memory Access) protocol is known. Also, regarding NVMe-of processing, it is known that the load of network control is offloaded to a smart NIC (Network Interface Card) in order to reduce the network control load of the host CPU on the compute server side.

[0004] In a transmission system that uses NVMe-of, queues are used to manage and control between the host CPU in the compute server and the NVMe controller in the storage server, thereby arbitrating the performance difference between the processing units and ensuring order and reachability. The host CPU has an Admin that is used to control the NVMe controller and an I / O that is used to transfer data, each of which is assigned one or more SQ (Submission Queue) / CQ (Completion Queue). The SQ is a circular buffer that queues requests when the host CPU issues them to the NVMe controller. The CQ is a circular buffer that queues the completion flags of requests that have already been executed. The NVMe controller also has an Admin and an I / O, each of which is assigned one or more SQ / CQ. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2022 / 0197710 [Patent Document 2] JP 2022-122478 A [Patent Document 3] US Patent Application Publication No. 2020 / 0177660 [Patent Document 4] International Publication No. 2016 / 135875 Summary of the Invention [Problem to be solved by the invention]

[0006] In a transmission system using NVMe-of, the distance between the compute server and the storage server is short, for example, about 1 km. However, in the transmission system of a data center, the practical use of optical transmission and CPO (Co-Packaged Optics) is being considered as low latency and low power consumption are required, and in the future, long distance transmission between data centers using L1 frames for optical transmission is also expected to be in demand. Therefore, the reality is that there is a demand for a long distance transmission NVMe-of transmission system between the compute server and the storage server, for example, about 1200 km.

[0007] In one aspect, an object of the present invention is to provide an NVMe-of compatible transmission device, etc., suitable for long distance transmission. [Means for solving the problem]

[0008] A transmission device according to one embodiment transmits a signal between a server and an opposing device. The transmission device includes a storage unit and a control unit that controls a first queue in the server and a second queue in the server, and also controls the storage unit. When the control unit detects an issuance of a processing request from the server to the opposing device, the control unit queues the processing request in the first queue, acquires data corresponding to the processing request from the server, and stores the acquired data in the storage unit. After requesting transfer of the data and the processing request to the opposing device, the control unit queues a processing completion of the processing request in the second queue and releases the processing completion queue before executing the processing request in the opposing device. Effect of the Invention

[0009] According to one aspect, a transmission device or the like suitable for long distance transmission between a server and an opposing device is provided. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is an explanatory diagram illustrating an example of an optical transmission system according to the present embodiment. [Diagram 2]FIG. 2 is an explanatory diagram showing an example of a first smart NIC and a second smart NIC used in the optical transmission system of the present embodiment. [Diagram 3] FIG. 3 is a sequence diagram illustrating an example of a processing operation of the optical transmission system related to a write request process. [Figure 4] FIG. 4 is a sequence diagram illustrating an example of a processing operation of the optical transmission system related to a write request process. [Diagram 5] FIG. 5 is a sequence diagram showing an example of a processing operation of the optical transmission system related to the first data retransmission processing. [Figure 6] FIG. 6 is a sequence diagram illustrating an example of a processing operation of the optical transmission system related to the first data retransmission processing. [Figure 7] FIG. 7 is a sequence diagram illustrating an example of a processing operation of the optical transmission system related to the second data retransmission processing. [Figure 8] FIG. 8 is a sequence diagram illustrating an example of a processing operation of the optical transmission system related to the second data retransmission processing. [Figure 9] FIG. 9 is an explanatory diagram showing an example of a comparison result between the optical transmission system of this embodiment and the optical transmission system of the comparative example. [Figure 10] FIG. 10 is an explanatory diagram illustrating an example of an optical transmission system according to a comparative example. [Figure 11] FIG. 11 is an explanatory diagram showing an example of a third smart NIC and a fourth smart NIC used in an optical transmission system of a comparative example. [Figure 12] FIG. 12 is a sequence diagram showing an example of a processing operation of the optical transmission system of the comparative example related to a write request process. [Figure 13] FIG. 13 is a sequence diagram showing an example of a processing operation of the optical transmission system of the comparative example related to a write request process. [Figure 14] FIG. 14 is an explanatory diagram showing an example of a comparison result between a conventional short-distance transmission system and an optical transmission system of a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] An optical transmission system 100 of a comparative example that realizes long-distance transmission between data centers will be described. Fig. 10 is an explanatory diagram showing an example of the optical transmission system 100 of the comparative example. The optical transmission system 100 shown in Fig. 10 has a compute server 110, a storage server 120, and an optical transmission path 130 that communicatively connects between the compute server 110 and the storage server 120. The compute server 110 is a server having a host CPU (Central Processing Unit) 111, a main memory 112, and a third slot 113.

[0012] The host CPU 111 controls the entire compute server 110. The host CPU 111 has a third control unit 114 that controls the main memory 112, and a third queue 115 used for the NVMe-of protocol. The third queue 115 has a third SQ (Submission Queue) 115A and a third CQ (Completion Queue) 115B. The third SQ 115A is, for example, a circular buffer on the compute server 110 side that queues a processing request of the NVMe-of protocol issued by the host CPU 111 to the controller 123. The third CQ 115B is a circular buffer on the compute server 110 side that queues a processing completion flag indicating the completion of processing of the processing request.

[0013] The main memory 112 is, for example, a double data rate (DDR) memory that stores data. The optical transmission path 130 is, for example, an optical transmission path of wavelength division multiplexing (WDM) of an optical transport network (OTN) that communicatively connects between the compute server 110 and the storage server 120. The third slot 113 is, for example, a peripheral component interconnect express (PCIe) type slot that connects to a third smart network interface card (NIC) 140A. The third smart network interface card (NIC) 140A is a NIC that enables communication of the NVMe-of protocol in an L1 frame for optical transmission.

[0014] The storage server 120 is a counterpart device having a fourth slot 121 and a broadband SSD (Solid State Drive) 122. The broadband SSD 122 controls the entire storage server 120. The broadband SSD 122 has a controller 123 and an NVM (Non-Volatile Memory) 124. The controller 123 controls the entire broadband SSD 122. The controller 123 has a fourth control unit 125 that controls the NVM 124 and a fourth queue 126 used for the NVMe-of protocol. The fourth queue 126 has a fourth SQ 126A and a fourth CQ 126B. The fourth SQ 126A is, for example, a circular buffer on the storage server 120 side that queues processing requests of the NVMe-of protocol transferred from the host CPU 111. Moreover, the fourth CQ 126B is a circular buffer on the storage server 120 side that queues a processing completion flag indicating the completion of processing of a processing request. The NVM 124 is a non-volatile auxiliary storage device that stores data.

[0015] The fourth slot 121 is a PCIe slot connected to the fourth smart NIC 140B. The fourth smart NIC 140B is a NIC that enables communication of the NVMe-of protocol using an L1 frame for optical transmission.

[0016] FIG. 11 is an explanatory diagram showing an example of a third smart NIC 140A and a fourth smart NIC 140B used in the optical transmission system 100 of the comparative example. The third smart NIC 140A has a third optical transceiver 141A and a third FPGA (Field Programmable Gate Array) 142A. The third optical transceiver 141A is an optical transceiver having an optical-electrical conversion function for optical transmission with the optical transmission line 130. The third FPGA 142A has a third communication IF 143A and a third frame control unit 144A. The third communication IF 143A is a communication IF for communication with the third slot 113. The third frame control unit 144A is a signal processing unit that encapsulates (assembles) or decapsulates (disassembles) a signal when communicating with the optical transmission line 130 into an L1 frame for optical transmission.

[0017] The fourth smart NIC 140B has a fourth optical transceiver 141B and a fourth FPGA 142B. The fourth optical transceiver 141B is an optical transceiver having an optical-electrical conversion function for optical transmission with the optical transmission line 130. The fourth FPGA 142B has a fourth communication IF 143B and a fourth frame control unit 144B. The fourth communication IF 143B is a communication IF for communicating with the fourth slot 121. The fourth frame control unit 144B is a signal processing unit that encapsulates or decapsulates a signal when communicating with the optical transmission line 130 into an L1 frame for optical transmission.

[0018] 12 and 13 are sequence diagrams showing an example of a processing operation of the optical transmission system 100 in the comparative example related to a write request processing. The third control unit 114 in the host CPU 111 issues a processing request of the NVMe-of protocol, for example, a processing request to write data to be written stored in the main memory 112 to the NVM 124, and notifies the issued processing request to the third queue 115 (step S111). The third SQ 115A in the third queue 115 queues the notified processing request in the SQ (step S112).

[0019] The third frame control unit 144A in the third smart NIC 140A detects a processing request being queued in the third SQ 115A in response to the doorbell function of the third queue 115 (step S113), and encapsulates the detected processing request (step S114). The third frame control unit 144A optically converts the encapsulated processing request through the third optical transceiver unit 141A, and optically transmits the optically converted processing request to the fourth smart NIC 140B of the storage server 120 via the optical transmission path 130 (step S115).

[0020] The fourth frame control unit 144B in the fourth smart NIC 140B converts the encapsulated processing request into an electrical signal through the fourth optical transceiver 141B, and decapsulates the electrically converted processing request (step S116). Furthermore, the fourth frame control unit 144B notifies the fourth queue 126 in the controller 123 of the decapsulated processing request (step S117). The fourth SQ 126A in the fourth queue 126 queues the notified processing request in the SQ (step S118).

[0021] The fourth control unit 125 in the controller 123 detects a processing request queued in the fourth SQ 126A according to the doorbell function of the fourth queue 126 (step S119). The fourth control unit 125 notifies the fourth frame control unit 144B of a DMA (Direct Memory Access) request according to the detected processing request (step S120). The fourth frame control unit 144B encapsulates the DMA request (step S121). The fourth frame control unit 144B optically converts the DMA request through the fourth optical transceiver unit 141B, and optically transmits the encapsulated DMA request after the optical conversion to the third smart NIC 140A via the optical transmission path 130 (step S122).

[0022] The third frame control unit 144A in the third smart NIC 140A converts the encapsulated DMA request into an electrical signal through the third optical transceiver 141A, and decapsulates the electrically converted DMA request (step S123). Furthermore, the third frame control unit 144A notifies the third control unit 114 in the host CPU 111 of the decapsulated DMA request (step S124). The third control unit 114 issues a read request to the main memory 112 in response to the DMA request (step S125). The main memory 112 reads the data to be written in response to the read request (step S126), and notifies the third control unit 114 of a read response including the read data to be written (step S127).

[0023] When the third control unit 114 detects a read response, it notifies the third frame control unit 144A of a DMA response including the read data to be written (step S128). The third frame control unit 144A encapsulates the DMA response (step S129). The third frame control unit 144A optically converts the encapsulated DMA response through the third optical transceiver unit 141A, and optically transmits the optically converted DMA response to the fourth smart NIC 140B via the optical transmission path 130 (step S130).

[0024] The fourth frame control unit 144B in the fourth smart NIC 140B converts the encapsulated DMA response to electricity through the fourth optical transceiver unit 141B, and decapsulates the electrically converted DMA response (step S131). The fourth frame control unit 144B notifies the fourth control unit 125 of the decapsulated DMA response (step S132). In response to the DMA response, the fourth control unit 125 issues an NVM write request to the NVM 124 to write the data to be written in the DMA response to the NVM 124 (step S133).

[0025] The NVM 124 writes the data to be written in response to the NVM write request (step S134), and notifies the fourth control unit 125 of NVM write completion indicating the completion of writing (step S135). When the fourth control unit 125 detects the completion of the NVM write, it notifies the fourth queue 126 of a processing completion flag indicating the completion of processing of the processing request (step S136). The fourth CQ 126B in the fourth queue 126 queues the notified processing completion flag in the CQ (step S137).

[0026] The fourth frame control unit 144B detects the processing completion flag in the fourth CQ 126B according to the doorbell function of the fourth queue 126 (step S138). The fourth frame control unit 144B encapsulates the processing completion flag (step S139). The fourth frame control unit 144B optically converts the encapsulated processing completion flag through the fourth optical transceiver unit 141B, and optically transmits the optically converted processing completion flag to the third smart NIC 140A via the optical transmission path 130 (step S141).

[0027] The third frame control unit 144A in the third smart NIC 140A converts the encapsulated processing completion flag into an electrical signal through the third optical transceiver 141A, and decapsulates the electrically converted processing completion flag (step S142). Furthermore, the third frame control unit 144A notifies the third queue 115 in the host CPU 111 of the decapsulated processing completion flag (step S143).

[0028] The third CQ 115B in the third queue 115 queues the notified processing completion flag in the CQ (step S144). The third queue 115 releases the information of the target SQ / CQ pair (step S145), and notifies the third frame control unit 144A of a queue release instruction to release the queue of the fourth queue 126 (step S146). The third frame control unit 144A encapsulates the queue release instruction (step S147). The third frame control unit 144A optically converts the encapsulated queue release instruction through the third optical transceiver unit 141A, and optically transmits the optically converted queue release instruction to the fourth smart NIC 140B via the optical transmission path 130 (step S148).

[0029] The fourth frame control unit 144B in the fourth smart NIC 140B converts the encapsulated queue release instruction to electricity through the fourth optical transceiver 141B, and decapsulates the electrically converted queue release instruction (step S149). Furthermore, the fourth frame control unit 144B notifies the fourth CQ 126B in the controller 123 of the decapsulated queue release instruction (step S150). The fourth queue 126 releases the information of the target SQ / CQ pair (step S151), and ends the processing operation shown in FIG. 13.

[0030] In the write request process, a transmission delay occurs due to five handshakes in total: the processing request in step S115, the DMA request in step S122, the DMA response in step S130, the processing completion flag in step S141, and the queue release instruction in step S148. In other words, if the transmission delay of one handshake between the compute server 2 and the storage server 3 is t, the transmission delay due to the handshake from the issuance of one processing request to the completion of execution of the processing request is 5t.

[0031] In other words, when the optical transmission system 100 of the comparative example is applied to long-distance optical transmission, a transmission delay of 5t occurs between the compute server 110 and the storage server 120 for the handshake. Since this transmission delay is included in the processing time and becomes the dominant term, a permanent queue congestion state occurs and the throughput drops significantly. In order to improve the queue congestion state, it is possible to allocate a large number of CPU cores in the host CPU 111 and the controller 123 to share the processing, but this would increase the cost of parts.

[0032] Here, a comparison result of the throughput between a short-distance transmission system using NVMe-of for short distance application and a transmission system using NVMe-of for long distance application will be described. FIG. 14 is an explanatory diagram showing an example of a comparison result between a conventional short-distance transmission system and an optical transmission system 100 as a comparative example. In the short-distance transmission system using NVMe-of for short distance application, the transmission distance between the compute server and the storage server is 1 km, the processing time per entry of a processing request is 300 n seconds, and the processing amount per entry is 4 KB. Furthermore, in this short-distance transmission system, the processing performance per entry is 109 Gbps, the processing time per entry until the queue is released is 25 μs, and the number of CPU cores is 1. In this case, the throughput of the short-distance transmission system is about 109 Gbps.

[0033] In the optical transmission system 100 of the comparative example of NVMe-of for long distance application using a single-core CPU, the transmission distance between the compute server 110 and the storage server 120 is 1200 km, and the processing time per entry is 300 ns. Furthermore, in the optical transmission system 100, the processing amount per entry is 4 KB, the processing performance per entry is 109 Gbps, the processing time per entry until the queue is released is 30 ms, and the number of CPU cores is 1. The throughput of the optical transmission system 100 of this comparative example is about 1 Gbps. It can be seen that the throughput of the optical transmission system 100 of the comparative example is significantly reduced compared to the short distance transmission system due to the occurrence of transmission delays.

[0034] In contrast, in an NVMe-of optical transmission system for long distance use that employs a multi-core CPU, the transmission distance between the compute server 110 and the storage server 120 is set to 1,200 km, and the processing time per entry is set to 300 ns. Furthermore, in this optical transmission system, the processing volume per entry is set to 4 KB, the processing performance per entry is set to 109 Gbps, the processing time per entry until the queue is released is set to 30 ms, and the number of CPU cores is set to 30. The throughput of this optical transmission system is approximately 109 Gbps, as each core shares the processing load.

[0035] That is, in the optical transmission system 100 of the comparative example of NVMe-of for long distance application using a single-core CPU, it can be seen that the throughput is significantly reduced when the long distance transmission is performed because a transmission delay for the handshake occurs. Therefore, it is possible to improve the throughput by increasing the number of CPU cores, but the cost of parts will increase significantly. Therefore, there is a demand for an optical transmission system of NVMe-of suitable for long distance transmission that can improve the throughput without increasing the number of CPU cores. Therefore, the embodiment will be described below as an example. Note that the disclosed technology is not limited by the example. In addition, each example shown below may be appropriately combined within a range that does not cause a contradiction. EXAMPLES

[0036] FIG. 1 is an explanatory diagram showing an example of an optical transmission system 1 of the present embodiment. The optical transmission system 1 shown in FIG. 1 includes a compute server 2, a storage server 3, and an optical transmission path 4 that communicatively connects the compute server 2 and the storage server 3. The compute server 2 is a server that includes a host CPU (Central Processing Unit) 11, a main memory 12, and a first slot 13. The host CPU 11 controls the entire compute server 2. The host CPU 11 includes a first control unit 14 that controls the main memory 12, and a first queue 15 used for the NVMe-of protocol. The first queue 15 includes a first SQ (Submission Queue) 15A and a first CQ (Completion Queue) 15B. The first SQ 15A is, for example, a circular buffer on the compute server 2 side that queues processing requests of the NVMe-of protocol issued by the host CPU 11 to the controller 23. The first CQ 15B is a circular buffer on the compute server 2 side that queues a processing completion flag indicating the completion of processing of a processing request.

[0037] The main memory 12 is, for example, a double data rate (DDR) memory that stores data. The optical transmission path 4 is, for example, an optical transmission path of wavelength division multiplexing (WDM) of an optical transport network (OTN) that connects the compute server 2 and the storage server 3 for communication. The first slot 13 is, for example, a peripheral component interconnect express (PCIe) type slot that connects to a first smart network interface card (NIC) 5A. The first smart NIC 5A is a NIC that enables communication of the NVMe-of protocol in an L1 frame for optical transmission. The first smart NIC 5A is detachably connected to the first slot 13.

[0038] The storage server 3 is a counterpart device having a second slot 21 and a broadband SSD (Solid State Drive) 22. The broadband SSD 22 controls the entire storage server 3. The broadband SSD 22 has a controller 23 and an NVM (Non-Volatile Memory) 24. The controller 23 controls the entire broadband SSD 22. The controller 23 has a second control unit 25 that controls the NVM 24 and a second queue 26 used for the NVMe-of protocol. The second queue 26 has a second SQ 26A and a second CQ 26B. The second SQ 26A is, for example, a circular buffer on the storage server 3 side that queues a processing request of the NVMe-of protocol transferred from the host CPU 11. The second CQ 26B is a circular buffer on the storage server 3 side that queues a processing completion flag indicating the completion of processing of the processing request. The NVM 24 is a non-volatile auxiliary storage device that stores data.

[0039] The second slot 21 is a PCIe slot that is connected to the second smart NIC 5B. The second smart NIC 5B is a NIC that enables communication of the NVMe-of protocol using an L1 frame for optical transmission. The second smart NIC 5B is detachably connected to the second slot 21.

[0040] FIG. 2 is a block diagram showing an example of a first smart NIC 5A and a second smart NIC 5B used in the optical transmission system 1 of the present embodiment. The first smart NIC 5A shown in FIG. 2 has a first optical transceiver 31A and a first FPGA (Field Programmable Gate Array) 32A. The first optical transceiver 31A is an optical transceiver having an optical-electrical conversion function for optical transmission with the optical transmission line 4. The first FPGA 32A has a first communication IF 33A, a first frame control unit 34A, a first offload control unit 35A, and a first HBM (High Bandwidth Memory) 36A. The first communication IF 33A is a communication IF for communicating with the first slot 13. The first frame control unit 34A is a signal processing unit for encapsulating (assembling) or decapsulating (disassembling) a signal when communicating with the optical transmission line 4 into an L1 frame for optical transmission. The first offload control unit 35A executes processing related to NVMe-of to reduce the processing load on the first control unit 14. The first HBM 36A is a large-capacity memory element that stores data.

[0041] The second smart NIC 5B has a second optical transceiver 31B and a second FPGA 32B. The second optical transceiver 31B is an optical transceiver having an optical-electrical conversion function for optical transmission with the optical transmission line 4. The second FPGA 32B has a second communication IF 33B, a second frame control unit 34B, a second offload control unit 35B, and a second HBM 36B. The second communication IF 33B is a communication IF for communicating with the second slot 21. The second frame control unit 34B is a signal processing unit that encapsulates or decapsulates a signal in an L1 frame for optical transmission when communicating with the optical transmission line 4. The second offload control unit 35B reduces the processing load of the second control unit 25 by executing processing related to NVMe-of. The second HBM 36B is a large-capacity memory element that stores data.

[0042] 3 and 4 are sequence diagrams showing an example of a processing operation of the optical transmission system 1 related to a write request processing. The first control unit 14 in the host CPU 11 issues a processing request of the NVMe-of protocol, for example, a processing request to write data to be written stored in the main memory 12 to the NVM 24. Then, the first control unit 14 notifies the issued processing request to the first queue 15 (step S11). The first SQ 15A in the first queue 15 queues the notified processing request in the SQ (step S12).

[0043] The first offload control unit 35A in the first smart NIC 5A detects a processing request queued in the first SQ 15A in response to the doorbell function of the first queue 15 (step S13). The first offload control unit 35A notifies the first control unit 14 of a dummy DMA request in response to the detected processing request (step S14). When the first control unit 14 detects a dummy DMA request, it requests the main memory 12 to make a read request to read data to be written from the main memory 12 in response to the dummy DMA request (step S15). The main memory 12 reads the data to be written in response to the read request (step S16), and notifies the first control unit 14 of a read response including the read data to be written (step S17).

[0044] When the first control unit 14 detects a read response, it notifies the first offload control unit 35A of a dummy DMA response including the read data to be written (step S18). When the first offload control unit 35A detects a dummy DMA response, it requests the first HBM 36A to send an HBM write request including the data to be written in the dummy DMA response (step S19). In response to the HBM write request, the first HBM 36A temporarily stores the data to be written in the HBM write request (step S20), and notifies the first offload control unit 35A of the completion of the HBM write (step S21). That is, the first offload control unit 35A reads the data to be written from the main memory 12 in response to the processing request, and temporarily stores the read data to be written in the first HBM 36A.

[0045] Furthermore, after detecting the completion of the HBM write, the first offload control unit 35A notifies the first frame control unit 34A of the processing request detected in step S13 (step S22). When the first frame control unit 34A detects the processing request, it requests the first HBM 36A to issue an HBM read request to read the data to be written stored in the first HBM 36A (step S27). In response to the HBM read request, the first HBM 36A notifies the first frame control unit 34A of an HBM read response including the data to be written that has been read (step S28). The first frame control unit 34A encapsulates the processing request including the HBM read response (step S29). The first frame control unit 34A optically converts the encapsulated processing request through the first optical transceiver unit 31A, and optically transmits the optically converted processing request to the second smart NIC 5B via the optical transmission path 4 (step S30). In other words, the first offload control unit 35A reads the data to be written that is temporarily stored in the first HBM 36A, and optically transmits a processing request including the read data to be written to the second smart NIC 5B as the first handshake.

[0046] After notifying the first frame control unit 34A of the processing request in step S22, the first offload control unit 35A notifies the first queue 15 of the processing completion flag (step S23). The first CQ 15B in the first queue 15 CQ queues the notified processing completion flag (step S24). The first queue 15 releases the information of the target SQ / CQ pair (step S26). In other words, the first offload control unit 35A releases the queue of the first queue 15 before executing the processing request including the data to be written in the second smart NIC 5B.

[0047] The second frame control unit 34B in the second smart NIC 5B converts the encapsulated processing request into an electrical signal through the second optical transceiver 31B, and decapsulates the electrically converted processing request to separate it into a processing request and data to be written (step S31). The second frame control unit 34B notifies the second queue 26 in the controller 23 of the separated processing request (step S32). The second SQ 26A in the second queue 26 queues the processing request in SQ queueing (step S33). The second frame control unit 34B also requests the second HBM 36B to issue an HBM write request to write the separated data to be written to the second HBM 36B (step S34).

[0048] The second HBM 36B temporarily stores the data to be written in the HBM write request in response to the HBM write request (step S35), and notifies the second offload control unit 35B of the completion of the HBM write (step S36).

[0049] The second control unit 25 detects a processing request queued in the second SQ 26A in response to the doorbell function of the second queue 26 (step S37). The second control unit 25 notifies the second offload control unit 35B of a DMA request in response to the detected processing request (step S38). The second offload control unit 35B requests the second HBM 36B to issue an HBM read request to read data to be written from the second HBM 36B in response to the DMA request (step S39). The second HBM 36B reads the data to be written in response to the HBM read request, and notifies the second offload control unit 35B of an HBM read response including the read data to be written (step S40). When the second offload control unit 35B detects the HBM read response, it notifies the second control unit 25 of a DMA response including the read data to be written (step S41), as shown in FIG. 4. That is, the second control unit 25 can obtain the data to be written from the second HBM 36B in response to a DMA request.

[0050] The second control unit 25 issues an NVM write request to the NVM 24 to write the data to be written in the DMA response to the NVM 24 in response to the DMA response (step S42). The NVM 24 writes the data to be written in response to the NVM write request (step S43), and notifies the second control unit 25 of the completion of the NVM write after the writing is completed (step S44). When the second control unit 25 detects the completion of the NVM write, it notifies the second queue 26 of a processing completion flag (step S45). The second CQ 26B in the second queue 26 queues the data in response to the processing completion flag (step S46).

[0051] The second offload control unit 35B detects the processing completion flag of the second CQ 26B according to the doorbell function of the second queue 26 (step S47). The second offload control unit 35B notifies the second frame control unit 34B of the detected processing completion flag (step S48). When the second frame control unit 34B detects the processing completion flag from the second offload control unit 35B, it encapsulates the processing completion flag (step S49). The second frame control unit 34B optically converts the encapsulated processing completion flag through the second optical transceiver unit 31B, and optically transmits the optically converted processing completion flag to the first smart NIC 5A via the optical transmission path 4 (step S50). The processing completion flag in step S50 is the second handshake. However, since the information of the SQ / CQ pair targeted by the first queue 15 in step S26 has already been released, it does not affect the throughput as seen from the host CPU 11.

[0052] The first frame controller 34A in the first smart NIC 5A converts the encapsulated processing completion flag into an electric signal through the first optical transceiver 31A, and decapsulates the processing completion flag after the electric conversion (step S51). Furthermore, the first frame controller 34A notifies the first offload controller 35A of the decapsulated processing completion flag (step S52). The first offload controller 35A requests the first HBM 36A to issue an HBM release instruction in response to the processing completion flag (step S53). Then, the first HBM 36A executes HBM release to erase the data to be written in response to the HBM release instruction (step S54), and ends the processing operation shown in FIG. 4. As a result, the first HBM 36A can erase the data to be written in response to the HBM release instruction.

[0053] Moreover, the second offload control unit 35B notifies the second frame control unit 34B of the processing completion flag in step S48, and then notifies the second queue 26 of a queue release instruction (step S55). Then, the second queue 26 releases the information of the target SQ / CQ pair (step S56).

[0054] Furthermore, after notifying the second frame control unit 34B of the processing completion flag in step S48, the second offload control unit 35B notifies the second HBM 36B of an HBM release instruction (step S57). The second HBM 36B executes HBM release to erase the data to be written in response to the HBM release instruction (step S58), and ends the processing operation shown in Fig. 4. As a result, the second HBM 36B can erase the data to be written in response to the HBM release instruction.

[0055] When the first smart NIC 5A detects the issuance of a processing request from the first control unit 14, it reads data to be written in response to the processing request from the main memory 12 and stores the data to be written in the first HBM 36A. The first smart NIC 5A optically transmits the processing request including the data to be written stored in the first HBM 36A to the storage server 3 as a first handshake. Before executing the processing request on the storage server 3 side, the first smart NIC 5A CQ queues the processing completion flag of the processing request to the first CQ 15B and releases it.

[0056] When the second smart NIC 5B detects a processing request from the first smart NIC 5A, it SQ queues the processing request in the second SQ 26A and stores the data to be written in the second HBM 36B. The second control unit 25 stores the write data stored in the second HBM 36B in the NVM 24 in response to the processing request in the second SQ 26A. Then, when the second control unit 25 completes storing the data to be written in the NVM 24, it CQ queues the processing completion flag of the processing request in the second CQ 26B and releases it. Furthermore, the second smart NIC 5B optically transmits the processing completion flag to the compute server 2 as a second handshake. Then, the first smart NIC 5A releases the first HBM 36A in response to the processing completion flag.

[0057] That is, in the optical transmission system 1, from SQ queuing to the release of SQ / CQ pair information, a single handshake for the processing request in step S30 is sufficient between the compute server 2 and the storage server 3. As a result, the transmission delay related to the processing request per entry can be shortened. In other words, it is possible to realize an NVMe-of optical transmission system 1 suitable for long-distance transmission that can improve processing delays including transmission delays without increasing the number of CPU cores.

[0058] 5 and 6 are sequence diagrams showing an example of the processing operation of the optical transmission system 1 related to the first data retransmission process. The first data retransmission process is a process executed when the second offload control unit 35B detects a processing completion flag with an error history and the data to be written stored in the second HBM 36B is normal.

[0059] After requesting an NVM write request in step S42, if the second control unit 25 detects an NVM write completion with an error history from the NVM 24 (step S44A), it notifies the second queue 26 of a processing completion flag with an error history (step S45A). The second CQ 26B in the second queue 26 queues the CQ according to the processing completion flag with an error history (step S46A).

[0060] The second offload control unit 35B detects a processing completion flag with an error history from the second CQ 26B in response to the doorbell function of the second queue 26 (step S47A). When the second offload control unit 35B detects a processing completion flag with an error history and determines that the data in the second HBM 36B is normal, it notifies the second frame control unit 34B of a normal processing completion flag (step S48A). The normal processing completion flag is a processing completion flag without an error history that indicates that the execution of the processing request has been completed.

[0061] When the second frame control unit 34B detects the processing completion flag from the second offload control unit 35B, the second frame control unit 34B encapsulates the processing completion flag (step S49A). The second frame control unit 34B optically converts the encapsulated processing completion flag through the second optical transceiver unit 31B, and optically transmits the optically converted processing completion flag to the first smart NIC 5A via the optical transmission path 4 (step S50A).

[0062] The first frame controller 34A in the first smart NIC 5A converts the processing completion flag to electricity through the first optical transceiver 31A, and decapsulates the processing completion flag after the electrical conversion (step S51A). Furthermore, the first frame controller 34A notifies the first offload controller 35A of the decapsulated processing completion flag (step S52A). The first offload controller 35A requests the first HBM 36A to issue an HBM release instruction in response to the processing completion flag (step S53A). Then, the first HBM 36A executes HBM release to erase the data to be written in response to the HBM release instruction (step S54A). That is, the first smart NIC 5A can erase the data to be written stored in the first HBM 36A.

[0063] After notifying the second frame control unit 34B of the processing completion flag in step S48A, the second offload control unit 35B notifies the second queue 26 of a queue release instruction (step S55A). The second CQ 26B in the second queue 26 releases the information of the target SQ / CQ pair (step S56A).

[0064] After notifying the second queue 26 of a queue release instruction in step S55A, the second offload control unit 35B notifies the second queue 26 of a reprocessing request (step S61). The reprocessing request is a processing request to reread the data to be written stored in the second HBM 36B and write the read data to be written to the NVM 24.

[0065] The second SQ 26A in the second queue 26 queues the reprocessing request in SQ queuing in response to the reprocessing request (step S62). The second control unit 25 detects the reprocessing request in the second SQ 26A in response to the doorbell function of the second queue 26 (step S63). The second control unit 25 notifies the second offload control unit 35B of a DMA request in response to the detected reprocessing request (step S64).

[0066] The second offload control unit 35B requests the second HBM 36B to issue an HBM re-read request to re-read the data to be written from the second HBM 36B in response to the DMA request (step S65). The second HBM 36B re-reads the data to be written in response to the HBM re-read request, and notifies the second offload control unit 35B of an HBM re-read response including the read data to be written (step S66). When the second offload control unit 35B detects the HBM re-read response, it notifies the second control unit 25 of a DMA response including the data to be written in the HBM re-read response (step S67).

[0067] 6, the second control unit 25 issues an NVM write request to the NVM 24 in response to the DMA response to write the data to be written in the DMA response to the NVM 24 (step S68). The NVM 24 writes the data to be written in response to the NVM write request (step S69), and notifies the second control unit 25 of the completion of the NVM write after the writing is completed (step S70).

[0068] When the second control unit 25 detects the completion of the NVM write, it notifies the second queue 26 of the processing completion flag of the reprocessing request (step S71). The second CQ 26B in the second queue 26 queues the CQ according to the processing completion flag (step S72).

[0069] The second offload control unit 35B also detects a processing completion flag in the second CQ 26B in response to the doorbell function of the second queue 26 (step S73). The second offload control unit 35B notifies the second queue 26 of a queue release instruction in response to the detected processing completion flag (step S74). Then, the second queue 26 releases the information of the target SQ / CQ pair (step S75).

[0070] After notifying the second queue 26 of a queue release instruction in step S74, the second offload control unit 35B notifies the second HBM 36B of an HBM release instruction (step S76). In response to the HBM release instruction, the second HBM 36B executes HBM release to erase the data to be written (step S77), and ends the processing operation shown in FIG.

[0071] When the second control unit 25 detects a processing completion flag indicating there is an error history, it reads out the data to be written stored in the second HBM 36B again, and writes the read out data to be written to the NVM 24. As a result, it is possible to reacquire the data to be written that was lost due to the error and write it to the NVM 24.

[0072] When the first smart NIC 5A of this embodiment detects the issuance of a processing request from the compute server 2 to the storage server 3, it SQ queues the processing request in the first queue 15. The first smart NIC 5A acquires data corresponding to the processing request from the main memory 12 and stores the acquired data in the first HBM 36A. After requesting the transfer of the data and the processing request to the storage server 3, the first smart NIC 5A CQ queues the processing completion of the processing request in the first queue 15 and releases the queue for the processing completion. As a result, the number of handshakes related to the processing request between the compute server 2 and the storage server 3 is reduced, thereby suppressing transmission delays and improving throughput.

[0073] When the second smart NIC 5B receives a processing request and data transferred from the first smart NIC 5A, it stores the received data in the second HBM 36B. The second smart NIC 5B queues the received processing request in the second queue 26 as an SQ queue, and executes a write operation of the data stored in the second HBM 36B to the NVM 24 in response to the processing request queued in the second queue 26. After executing the write operation, the second smart NIC 5B queues the completion of the processing of the processing request in the second queue 26 as a CQ queue, and releases the queue for the completion of the processing. As a result, the number of handshakes related to the processing request between the compute server 2 and the storage server 3 is reduced, thereby suppressing transmission delays and improving throughput.

[0074] In the optical transmission system 1, the handshake between the first smart NIC 5A and the second smart NIC 5B requires only one processing request in step S30 from SQ queuing to the release of SQ / CQ pair information, so that the number of handshake processes can be reduced by four compared to the comparative example. As a result, in the optical transmission system 1, the number of handshakes related to the DMA request, DMA response, and queue release instruction as in the comparative example is reduced to suppress transmission delays, so that the processing delays related to processing requests can be significantly shortened.

[0075] In the first data retransmission process, when the second control unit 25 detects an error of data loss of the write target, the write target data stored in the second HBM 36B is read again and the write target data is written to the NVM 24. However, when the data stored in the second HBM 36B also has an error, the write target data stored in the first HBM 36A must be acquired again. Therefore, the second data retransmission process shown in Figs. 7 and 8 will be described.

[0076] 7 and 8 are sequence diagrams showing an example of the processing operation of the optical transmission system 1 related to the second data retransmission process. The second data retransmission process is executed when the second offload control unit 35B detects a processing completion flag with an error history and the data to be written stored in the first HBM 36A is normal.

[0077] After requesting an NVM write request in step S42, if the second control unit 25 detects completion of NVM write with error history from the NVM 24 (step S44B), it notifies the second queue 26 of a processing completion flag with error history (step S45B). The second CQ 26B in the second queue 26 queues CQs according to the processing completion flag with error history (step S46B).

[0078] The second offload control unit 35B detects a processing completion flag with an error history from the second CQ 26B in response to the doorbell function of the second queue 26 (step S47B). When the second offload control unit 35B detects a processing completion flag with an error history and determines that the data of the second HBM 36B is also abnormal, it notifies the second frame control unit 34B of a normal processing completion flag (step S48B). At this time, since it is known that the first HBM 36A will be re-read later, a flag for invalidating the release instruction of the first HBM 36A is added.

[0079] When the second frame control unit 34B detects the processing completion flag from the second offload control unit 35B, the second frame control unit 34B encapsulates the processing completion flag (step S49B). The second frame control unit 34B optically converts the encapsulated processing completion flag through the second optical transceiver unit 31B, and optically transmits the optically converted processing completion flag to the first smart NIC 5A via the optical transmission path 4 (step S50B).

[0080] The first frame control unit 34A in the first smart NIC 5A converts the processing completion flag into an electrical signal through the first optical transceiver 31A, and decapsulates the electrically converted processing completion flag (step S51B). Furthermore, the first frame control unit 34A notifies the first offload control unit 35A of the decapsulated processing completion flag (step S52B).

[0081] In addition, the second offload control unit 35B notifies the second frame control unit 34B of the processing completion flag in step S48B, and then notifies the second queue 26 of a queue release instruction (step S55B). The second CQ 26B in the second queue 26 releases the information of the target SQ / CQ pair (step S56B).

[0082] In addition, the second offload control unit 35B notifies the second frame control unit 34B of the processing completion flag in step S48B, and then requests the second HBM 36B to issue an HBM release instruction (step S57B). Then, the second HBM 36B executes HBM release to erase the data to be written in response to the HBM release instruction (step S58B). In other words, the second smart NIC 5B can erase the data to be written stored in the second HBM 36B.

[0083] After notifying the second queue 26 of a queue release instruction in step S55B, the second offload control unit 35B notifies the second queue 26 of a reprocessing request (step S81). The reprocessing request is a processing request to reread the data to be written stored in the first HBM 36A and write the read data to be written to the NVM 24.

[0084] The second SQ 26A in the second queue 26 queues the reprocessing request in SQ queuing (step S82). The second control unit 25 detects the reprocessing request in the second SQ 26A in response to the doorbell function of the second queue 26 (step S83). The second control unit 25 notifies the second offload control unit 35B of a DMA request in response to the detected reprocessing request (step S84).

[0085] The second offload control unit 35B notifies the second frame control unit 34B of an HBM re-read request to re-read the data to be written from the first HBM 36A in response to the DMA request (step S85). When the second frame control unit 34B detects the HBM re-read request from the second offload control unit 35B, it encapsulates the HBM re-read request (step S86). The second frame control unit 34B optically converts the encapsulated HBM re-read request through the second optical transceiver unit 31B, and optically transmits the optically converted HBM re-read request to the first smart NIC 5A via the optical transmission path 4 (step S87).

[0086] The first frame controller 34A in the first smart NIC 5A converts the HBM re-read request to an electrical signal through the first optical transceiver 31A, and decapsulates the electrically converted HBM re-read request (step S88). Furthermore, the first frame controller 34A notifies the first offload controller 35A of the decapsulated HBM re-read request (step S89).

[0087] The first offload control unit 35A requests the first HBM 36A to issue an HBM read request in response to the HBM re-read request (step S90). The first HBM 36A re-reads the data to be written in response to the HBM read request, and notifies the first offload control unit 35A of an HBM read response including the read data to be written (step S91). When the first offload control unit 35A detects an HBM read response, it notifies the first frame control unit 34A of an HBM re-read response including the read data to be written (step S92). After the re-read response, it also notifies the first HBM 36A of an HBM release instruction (step S106). The first HBM 36A executes HBM release to erase the data to be written in response to the HBM release instruction (step S107).

[0088] When the first frame control unit 34A detects the HBM re-read response from the second offload control unit 35B, it encapsulates the HBM re-read response (step S93). The second frame control unit 34B optically converts the encapsulated HBM re-read response through the second optical transceiver unit 31B, and optically transmits the optically converted HBM re-read response to the second smart NIC 5B via the optical transmission path 4 (step S94).

[0089] The second frame control unit 34B in the second smart NIC 5B converts the HBM re-read response to electricity through the first optical transceiver 31A, and decapsulates the electrically converted HBM re-read response (step S95). Furthermore, the second frame control unit 34B notifies the second offload control unit 35B of the decapsulated HBM re-read response (step S96). The second offload control unit 35B notifies the second control unit 25 of a DMA response in response to the HBM re-read response (step S97).

[0090] In response to the DMA response, the second control unit 25 issues an NVM write request to the NVM 24 to write the data to be written in the DMA response to the NVM 24 (step S98). The NVM 24 writes the data to be written in response to the NVM write request (step S99), and notifies the second control unit 25 of the completion of the NVM write after the writing is completed (step S100).

[0091] When the second control unit 25 detects the completion of the NVM write, it notifies the second queue 26 of the processing completion flag of the reprocessing request (step S101). The second CQ 26B in the second queue 26 queues the CQ according to the processing completion flag (step S102).

[0092] The second offload control unit 35B also detects the processing completion flag in the second CQ 26B according to the doorbell function of the second queue 26 (step S103). The second offload control unit 35B notifies the second queue 26 of a queue release instruction according to the detected processing completion flag (step S104). Then, the second queue 26 releases the information of the target SQ / CQ pair (step S105), and ends the processing operation shown in FIG.

[0093] When the second control unit 25 detects a processing completion flag indicating there is an error history, it reacquires the data to be written stored in the first HBM 36A and writes the acquired data to be written to the NVM 24. As a result, it is possible to reacquire the data to be written that was lost due to the error and write it to the NVM 24.

[0094] FIG. 9 is an explanatory diagram showing an example of a comparison result between the optical transmission system 1 of the present embodiment and the optical transmission system 100 of the comparative example. In the optical transmission system 100 of the comparative example of NVMe-of for long distance application using a single-core CPU, the transmission distance between the compute server 110 and the storage server 120 is 1200 km, and the processing time per entry is 300 ns. Furthermore, in the optical transmission system 100, the processing amount per entry is 4 KB, the processing performance per entry is 109 Gbps, the processing time per entry until the queue is released is 30 ms, and the number of CPU cores is 1. The throughput of the optical transmission system 100 of the comparative example is about 1 Gbps. In addition, the data retransmission function is executed at the application layer.

[0095] In a long-distance NVMe-of optical transmission system using a multi-core CPU, the transmission distance between the compute server 110 and the storage server 120 is 1200 km, and the processing time per entry is 300 ns. Furthermore, in this optical transmission system, the processing amount per entry is 4 KB, the processing performance per entry is 109 Gbps, the processing time per entry until the queue is released is 30 ms, and the number of CPU cores is 30. In this case, the throughput is approximately 109 Gbps. Also, the data retransmission function is executed at the application layer.

[0096] In contrast, in the optical transmission system 1 of this embodiment of NVMe-of for long distance use employing a single-core CPU, the transmission distance between the compute server 2 and the storage server 3 is 1200 km, and the processing time per entry is 300 ns. Furthermore, in the optical transmission system 1, the processing amount per entry is 4 KB, the processing performance per entry is 109 Gbps, the processing time per entry until queue release is 6 ms, and the number of CPU cores is 1. The throughput of the optical transmission system 1 of this embodiment is approximately 109 Gbps. Also, the data retransmission function is executed by hardware.

[0097] It can be seen that the optical transmission system 1 of the embodiment has a significantly improved throughput compared to the optical transmission system 100 of the comparative example. Moreover, the throughput can be improved while keeping component costs down compared to optical transmission systems that employ a multi-core CPU.

[0098] For convenience of explanation, the first smart NIC 5A may be built in the compute server 2, and the second smart NIC 5B may be built in the storage server 3, and this can be changed as appropriate.

[0099] Although the processing request has been exemplified as a processing request for writing data to be written that is stored in the main memory 12 to the NVM 24, the processing request is not limited to this and can be changed as appropriate.

[0100] Although an example has been given of optical transmission between the compute server 2 and the storage server 3 using an optical transmission path 4, this is not limited to the optical transmission path 4, and a transmission path for transmitting electrical signals may also be used, and modifications can be made as appropriate.

[0101] An example has been given of encapsulation and decapsulation when transmitting signals between a first smart NIC 5A and a second smart NIC 5B, but this is not limited to this and signals may be transmitted without encapsulation and decapsulation, and modifications can be made as appropriate.

[0102] An example has been given of using the NVMe-of protocol when transmitting signals between the first smart NIC 5A and the second smart NIC 5B, but any communication protocol that manages processing requests in a queue can be used and can be changed as appropriate.

[0103] Furthermore, each component of each unit shown in the figure does not necessarily have to be physically configured as shown in the figure. In other words, the specific form of distribution and integration of each unit is not limited to that shown in the figure, and all or part of them can be functionally or physically distributed and integrated in any unit depending on various loads, usage conditions, etc.

[0104] Furthermore, the various processing functions performed by each device may be executed in whole or in part on a CPU (Central Processing Unit) (or a microcomputer such as an MPU (Micro Processing Unit) or an MCU (Micro Controller Unit)). It goes without saying that the various processing functions may be executed in whole or in part on a program analyzed and executed by a CPU (or a microcomputer such as an MPU or an MCU), or on hardware using wired logic. [Explanation of symbols]

[0105] 1. Optical transmission system 2 Compute Server 3. Storage Server 5A The First Smart NIC 5B Second Smart NIC 14 First control section 15A 1st SQ 15B First CQ 35A First offload control section 36A First HBM 24 NVM 25 Second control section 26A 2nd SQ 26B Second CQ 35B Second offload control section 36B Second HBM

Claims

1. A transmission device that transmits a signal between a server and an opposing device, A storage unit; a control unit that controls a first queue in the server and a second queue in the server and also controls the storage unit; The control unit is When issuance of a processing request from the server to the opposing device is detected, the processing request is queued in the first queue, data corresponding to the processing request is acquired from the server, and the acquired data is stored in the storage unit, After requesting the transfer of the data and the processing request to the opposing device, and before the opposing device executes the processing request, a processing completion of the processing request is queued in the second queue and the processing completion queue is released. A transmission device comprising:

2. The control unit is 2. The transmission device according to claim 1, wherein the data stored in the storage unit is erased in response to completion of processing from the opposite device.

3. A transmission device that transmits a signal between a server and an opposing device, A storage unit; a control unit that controls a first queue in the opposing device and a second queue in the opposing device and also controls the storage unit; The control unit is When a processing request and data transferred from the server are received, the received data are stored in the storage unit, queuing a received processing request in the first queue, executing the processing request using data stored in the storage unit in response to the processing request queued in the first queue, and queuing a processing completion of the processing request in the second queue after the processing request is executed, and releasing the processing completion queue. A transmission device comprising:

4. The control unit is When an error in the data related to the processing request is detected, a reprocessing request is issued and queued in the first queue, and in response to the reprocessing request queued in the first queue, the data is read from the storage unit, the processing request is executed using the read data, and after the processing request is executed, a processing completion of the processing request is queued in the second queue, and the processing completion queue is released.

4. The transmission device according to claim 3.

5. The control unit is When an error in the data related to the processing request is detected, a reprocessing request is issued and queued in the first queue, data stored in the server-side transmission device is received in response to the reprocessing request queued in the first queue, the processing request is executed using the received data, and after the processing request is executed, a completion of the processing of the processing request is queued in the second queue, and the queue for the completion of the processing is released.

4. The transmission device according to claim 3.

6. A transmission system for transmitting signals between a first transmission device connected to a server and a second transmission device connected to an opposing device, The first transmission device A first storage unit; a first control unit that controls a first queue in the server and a second queue in the server and also controls the first storage unit; The first control unit is When issuance of a processing request from the server to the opposing device is detected, the processing request is queued in a first queue in the server, data corresponding to the processing request is acquired from the server, and the acquired data is stored in the first storage unit, After requesting the transfer of the data and the processing request to the second transmission device, before the second transmission device executes the processing request, a processing completion of the processing request is queued in a second queue in the server and the processing completion queue is released. A transmission system comprising:

7. The second transmission device A second storage unit; a second control unit that controls a first queue in the second transmission device and a second queue in the second transmission device and also controls the second storage unit; The second control unit is When a processing request and data transferred from the first transmission device are received, the received data are stored in the second storage unit, and queuing a received processing request in a first queue in the second transmission device, executing the processing request using data stored in the second storage unit in response to the processing request queued in the first queue in the second transmission device, and queuing a processing completion of the processing request in a second queue in the second transmission device after the processing request is executed, and releasing the processing completion queue.

7. A transmission system according to claim 6.

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