Semiconductor device

Abstract

To make wiring connections with a plurality of semiconductor chips in a semiconductor device without using any bonding wire.SOLUTION: A semiconductor device has: a plurality of semiconductor chips including a power semiconductor chip 201L including a switching element and a control semiconductor chip 211L including a control circuit controlling the switching element; a rewiring layer including a first rewiring layer electrically connecting the plurality of semiconductor chips to each other; a first sealing body 101A sealing the plurality of semiconductor chips and the rewiring layer; an insulation substrate 110 which consists of an insulation layer and conductor layers sandwiching the insulation layer, and is arranged at the first sealing body 101A; and a second sealing body 101 which seals the insulation substrate 110, the first sealing body 101A, and external connection terminals.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device suitable for power electronics devices. [Background technology]

[0002] Semiconductor devices for power electronics devices generate a large amount of heat, and therefore require a strong heat dissipation capability. The semiconductor device described in Patent Document 1 includes a substrate having a semiconductor chip (a semiconductor element in Patent Document 1), an insulating base material containing a resin, and two metal bodies arranged on both sides of the insulating base material, and a sealant that seals the semiconductor chip and the substrate. Here, the sealant is formed by transfer molding a mold. In addition, the metal body of the substrate has an exposed surface that is exposed from the sealant. Therefore, in the semiconductor device of Patent Document 1, heat generated by the semiconductor chip is dissipated via the substrate.

[0003] However, in the semiconductor device of Patent Document 1, the external connection terminals and the pads of the semiconductor chip are connected by bonding wires, which causes a problem that the wires are easily displaced by the mold when transfer molding of the encapsulant is performed.

[0004] The semiconductor device described in Patent Document 2 has a heat dissipation member similar to the substrate of Patent Document 1. In Patent Document 2, the main electrodes of the semiconductor chip (semiconductor element in Patent Document 2) are connected to a conductor pattern formed on the metal body of the heat dissipation member, and the signal terminals of the semiconductor chip are connected via a rewiring layer to the conductor pattern formed on the metal body of the heat dissipation member. In Patent Document 2, bonding wires are not used as a means for connecting the semiconductor chip to external connection terminals, and the problem of wire sweep is avoided. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2022-181819 [Patent Document 2] JP 2022-152703 A Summary of the Invention [Problem to be solved by the invention]

[0006] In power electronics devices, miniaturization of semiconductor chips is required due to the demand for miniaturization of devices. However, miniaturization of semiconductor chips makes it difficult to use bonding wires for wiring connections between semiconductor chips and between semiconductor chips and external connection terminals. In the technology disclosed in Patent Document 2, semiconductor chips are connected to external connection terminals via a rewiring layer and a conductor pattern of a heat dissipation member. However, Patent Document 2 does not disclose a technology for realizing wiring connections between multiple semiconductor chips, which is necessary especially in the case of an IPM (Intelligent Power Module). If a rewiring layer is used following the technology of Patent Document 2, wiring of a path of one semiconductor chip → rewiring layer → conductor pattern of a heat dissipation member → rewiring layer → another semiconductor chip is provided. However, wiring of such a path has a problem that the wiring length is long and the wiring inductance is large.

[0007] The present invention has been made in consideration of the above-described circumstances, and has an object to provide a technical means for realizing wiring connections between semiconductor chips in a semiconductor device without using bonding wires. [Means for solving the problem]

[0008] A semiconductor device according to one embodiment of the present invention includes a plurality of semiconductor chips including a power semiconductor chip including a switching element and a control semiconductor chip including a control circuit that controls the switching element, a redistribution layer including a first redistribution layer electrically connecting one semiconductor chip to another semiconductor chip in the plurality of semiconductor chips, a first sealing body that seals the plurality of semiconductor chips and the redistribution layer, an insulating substrate consisting of an insulating layer and a conductor layer sandwiching the insulating layer, and arranged in the first sealing body so as to face the plurality of semiconductor chips and the redistribution layer, and a second sealing body that seals the insulating substrate and the first sealing body.

[0009] The redistribution layer may include a second redistribution layer that electrically connects one of the plurality of semiconductor chips to an external connection terminal protruding to the outside of the second sealing body.

[0010] The external connection terminal may protrude to the outside from a side surface of the second sealing body.

[0011] The second redistribution layer may be exposed from the first sealing body, and the external connection terminal may be connected to this exposed surface.

[0012] A semiconductor device according to another aspect of the present invention comprises a plurality of semiconductor chips including a power semiconductor chip including a switching element and a control semiconductor chip including a control circuit that controls the switching element, a redistribution layer including a first redistribution layer electrically connecting one semiconductor chip to another semiconductor chip in the plurality of semiconductor chips, a first sealing body that seals the plurality of semiconductor chips and the redistribution layer, first and second insulating substrates each consisting of an insulating layer and a conductor layer sandwiching the insulating layer and arranged in the first sealing body so as to sandwich the plurality of semiconductor chips and the redistribution layer between them, and a second sealing body that seals the first insulating substrate, the first sealing body, and the second insulating substrate.

[0013] In a preferred embodiment, the semiconductor device has an external connection terminal protruding outward from a side surface of the semiconductor device surrounding the area sandwiched between the first insulating substrate and the second insulating substrate, and the redistribution layer includes a third redistribution layer electrically connecting one semiconductor chip in the plurality of semiconductor chips to the external connection terminal via a conductor layer of the first insulating substrate or the second insulating substrate. Effect of the Invention

[0014] According to the present invention, in a semiconductor device, wiring connections between semiconductor chips can be realized without using bonding wires. Also, according to the present invention, by using the first redistribution layer, the wiring length of the wiring electrically connecting between the semiconductor chips can be shortened, and the wiring inductance can be reduced. [Brief description of the drawings]

[0015] [Figure 1] 1 is a circuit diagram showing a configuration of an IPM to which the present invention is applied. [Diagram 2] 1 is a plan view showing a configuration of a portion of a semiconductor device according to a first embodiment of the present invention. [Diagram 3] 3 is a cross-sectional view taken along line I1a-I1b in FIG. 2. [Figure 4] 11 is a plan view showing the configuration of another part of the semiconductor device. FIG. [Diagram 5] 5 is a cross-sectional view taken along the line I2a-I2b in FIG. 4. [Figure 6] FIG. 4 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention. [Figure 7] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment of the present invention. [Figure 8] FIG. 2 is a perspective view showing the appearance of the semiconductor device. [Figure 9] FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0017] <Applicable to> Figure 1 is a circuit diagram showing the configuration of an IPM1 to which this invention is applied. This IPM1 is a modularization of switching elements and control circuits that constitute a three-phase inverter. In Figure 1, a positive electrode of a DC power supply (not shown) is connected to terminal P, and a negative electrode of the same DC power supply is connected to terminals N(U), N(V), and N(W).

[0018] The IPM 1 has switching elements Q1 to Q6. The switching elements Q1 to Q6 are wide band gap semiconductor elements such as SiC, and the SiC elements will be described here as an example. The switching elements Q1 to Q6 are SiC elements, and may be configured with MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and parasitic diodes.

[0019] Switching elements Q1, Q3, and Q5 are high-side switching elements for the U phase, V phase, and W phase, respectively, and have their respective drains connected to terminal P. Switching elements Q2, Q4, and Q6 are low-side switching elements for the U phase, V phase, and W phase, respectively, and have their respective sources connected to terminals N(U), N(V), and N(W).

[0020] The sources of switching elements Q1, Q3, and Q5 are connected to the drains of switching elements Q2, Q4, and Q6, respectively. A common connection point between the source of switching element Q1 and the drain of switching element Q2 is connected to terminal U. A common connection point between the source of switching element Q3 and the drain of switching element Q4 is connected to terminal V. A common connection point between the source of switching element Q5 and the drain of switching element Q6 is connected to terminal W. A three-phase load is connected to terminals U, V, and W.

[0021] IPM1 has HVICs (High Voltage Integrated Circuits) 2U, 2V, and 2W, which are Si elements, and LVIC (Low Voltage Integrated Circuit) 3. These have drive control and protection functions for the switching elements in IPM1. More specifically, HVICs 2U, 2V, and 2W each perform turn-on / turn-off drive control for high-side switching elements Q1, Q3, and Q5. LVIC 3 also performs turn-on / turn-off drive control for low-side switching elements Q2, Q4, and Q6, and also plays a role in protecting the elements in IPM1.

[0022] First Embodiment Fig. 2 is a plan view showing a configuration of a portion of a semiconductor device 100A according to a first embodiment of the present invention. Fig. 3 is a cross-sectional view taken along line I1a-I1b in Fig. 2. Fig. 4 is a plan view showing a configuration of a region in the semiconductor device 100A that is shifted in the -X (described later) direction from the region shown in Fig. 2. Fig. 5 is a cross-sectional view taken along line I2a-I2b in Fig. 4.

[0023] The external shape of the semiconductor device 100A may be, for example, a flat plate shape as a whole. Hereinafter, the configuration of this embodiment will be described assuming an orthogonal coordinate system consisting of a Z axis parallel to the plate thickness direction of the semiconductor device 100A, and an X axis and a Y axis that are mutually orthogonal and orthogonal to the Z axis. In the following, for convenience of explanation, for example, a plane orthogonal to the Z axis direction may be referred to as an XY plane. Also, for example, the upward direction in FIG. 3 and FIG. 5 may be referred to as the +Z side, and the downward direction may be referred to as the -Z side. The relationship between these directions and the vertical direction is not particularly limited and is arbitrary.

[0024] 2 to 5, the semiconductor device 100A includes a first sealing body 101A, an insulating substrate 110, and a second sealing body 102A. In the illustrated example, the first sealing body 101A includes power semiconductor chips 201L and 201H, control semiconductor chips 211L and 211H, and redistribution layers 301a, 301b, 304, 314, 302, 312, 303a, 303b, 304, 305, 315, and 316.

[0025] In this embodiment, the switching elements of the power semiconductor chips 201L and 201H are vertical semiconductor elements that pass current in the thickness direction of the semiconductor substrate, and the MOSFETs constituting the control semiconductor chips 211L and 211H are horizontal semiconductor elements that pass current in the surface direction of the semiconductor substrate, i.e., in a direction parallel to the XY plane.

[0026] The insulating substrate 110 is composed of an insulating layer 111, and a first conductor layer 112 and a second conductor layer 113 sandwiching the insulating layer 111. The entire area of ​​the first conductor layer 112 is a conductor layer with no gaps. One or more conductor patterns are formed on the second conductor layer 113. The insulating substrate 110 is disposed in the first sealing body 101A with the second conductor layer 113 facing the semiconductor chip and the rewiring layer in the first sealing body 101A and the first conductor layer 112 facing the opposite side of the first sealing body 101A.

[0027] External connection terminals 451a, 451b, 461a, and 461b are arranged on the flat surface of first sealing body 101A opposite to insulating substrate 110. Second sealing body 102A seals insulating substrate 110, first sealing body 101A, and external connection terminals 451a, 451b, 461a, and 461b. First sealing body 101A and second sealing body 102A are made of, for example, epoxy resin. Note that first conductor layer 112 of insulating substrate 110 may be exposed from the surface of the second sealing body on the side where insulating substrate 110 is located.

[0028] In this embodiment, first, a first sealing body 101A including a semiconductor chip and a rewiring layer is formed. Next, the rewiring layer exposed from the first sealing body 101A and the insulating substrate 110 are bonded with a conductive bonding material such as solder. Next, the external connection terminals 451a, 451b, 461a, and 461b are bonded to the rewiring layer exposed from the first sealing body 101A. Then, the first sealing body 101A to which the external connection terminals are bonded and the insulating substrate 110 are sealed in a second sealing body 102A.

[0029] Next, the rewiring layer in the first sealing body 101A will be described. In this embodiment, one of the semiconductor chips shown in FIG. 2 to FIG. 5 is electrically connected to another semiconductor chip by the rewiring layer. In this embodiment, one of the semiconductor chips is electrically connected to an external connection terminal by the rewiring layer. The rewiring layer is a wiring layer formed of metal plating and an insulating layer. Specifically, the rewiring is formed by, for example, making a pattern mold with photoresist and performing electrolytic plating on it. The metal of the rewiring layer may be selected taking into consideration electrical conductivity, thermal conductivity, bondability in a process described later, cost, and the like. It may be selected from copper, tin, gold, nickel, or an alloy thereof. For example, copper is suitable. A metal layer suitable for solder bonding may be formed on the connection surface (top surface) to the outside. The semiconductor device 100A according to this embodiment has semiconductor chips other than the power semiconductor chips 201L and 201H and the control semiconductor chips 211L and 211H, but these semiconductor chips and the rewiring layers related thereto are omitted from the illustration.

[0030] 2 and 3, in a part of the region in the first sealing body 101A separated from the insulating substrate 110, a power semiconductor chip 201L and a control semiconductor chip 211L are arranged side by side in the Y direction perpendicular to the thickness direction of the semiconductor device 100A. The power semiconductor chip 201L is, for example, a power semiconductor chip including the switching element Q2 in Fig. 1. The control semiconductor chip 211L is, for example, a control semiconductor chip corresponding to the LVIC 3 in Fig. 1.

[0031] In the power semiconductor chip 201L, the source and gate of the MOSFET are formed on the plane (+Z side plane) opposite to the side where the insulating substrate 110 is present, and the drain of the MOSFET is formed on the plane (-Z side plane) on the side where the insulating substrate 110 is present. In the power semiconductor chip 201L, the rewiring layer 301a is present on the plane opposite to the side where the insulating substrate 110 is present, and this rewiring layer 301a is connected to the source of the MOSFET. The rewiring layer 301a is connected to the external connection terminal 451a via the connection pad 401a provided on the side opposite to the side where the insulating substrate 110 is present. That is, the rewiring layer 301a is exposed from the first sealing body 101A, and the external connection terminal 451a is connected to the exposed surface exposed from the first sealing body 101A via the connection pad 401a. The connection pad 401a is a conductive bonding member, for example, solder. The same applies to the other connection pads. The external connection terminal 451a is an external connection terminal that protrudes from the side surface of the second sealing body 102A to the outside of the second sealing body 102A, and is, for example, the terminal N(U) in FIG.

[0032] On the opposite side (+Z side) of the power semiconductor chip 201L and the control semiconductor chip 211L to the side where the insulating substrate 110 is located, there is a redistribution layer 302 extending in the Y direction perpendicular to the thickness direction of the semiconductor device 100A. One end of the redistribution layer 302 is bent toward the insulating substrate 110 and connected to the gate of the power semiconductor chip 201L. The other end of the redistribution layer 302 is bent toward the insulating substrate 110 and connected to a signal terminal of the control semiconductor chip 211L. This signal terminal is, for example, the terminal UOUT of the LVIC 3 shown in FIG. 1. That is, the redistribution layer 302 is a first redistribution layer that electrically connects one semiconductor chip to another semiconductor chip in the plurality of semiconductor chips.

[0033] The control semiconductor chip 211L has rewiring layers 305 and 306 on the insulating substrate 110 side. The rewiring layer 305 is connected to a conductor pattern formed on the second conductor layer 113 of the insulating substrate 110 via a bonding layer not shown. The control semiconductor chip 211L and the rewiring layer 305 are bonded to each other by a conductive bonding member (not shown) such as solder. The rewiring layer 305 is a wiring path that provides a GND potential to the rear surface (plane on the -Z side) of the control semiconductor chip 211L. The rewiring layer 306 is connected to another conductor pattern in the second conductor layer 113 via a bonding layer 423. The rewiring layer 306 does not function as a wiring path, but is a rewiring layer that stabilizes the adhesion between the first sealing body 101A and the insulating substrate 101A, and may be omitted. The bonding layer 423 is a conductive bonding member such as solder. The same applies to the other bonding layers.

[0034] In addition, there are two other signal terminals on the plane opposite to the insulating substrate 110 in the control semiconductor chip 211L. One signal terminal is, for example, the terminal UIN of the LVIC3 shown in FIG. 1. This signal terminal is connected to the external connection terminal 452a via the rewiring layer 303a and the connection pad 402a on the opposite side of the insulating substrate 110 in the control semiconductor chip 211L. The other signal terminal is, for example, the terminal VCC of the LVIC3 shown in FIG. 1. This signal terminal is connected to the external connection terminal 452b via the rewiring layer 303b and the connection pad 402b on the opposite side of the insulating substrate 110 in the control semiconductor chip 211L. That is, the rewiring layers 303a and 303b are exposed from the first sealing body 101A, and the external connection terminals 452a and 452b are connected to the exposed surfaces exposed from the first sealing body 101A via the connection pads 402a and 402b.

[0035] The external connection terminals 452a and 452b, like the external connection terminal 451a, are external connection terminals protruding from the side surface of the second sealing body 102A to the outside of the second sealing body 102A, and correspond to, for example, the terminals IN(LU) and VCCL in Fig. 1. That is, the redistribution layers 303a and 303b and the above-mentioned redistribution layer 301a are a second redistribution layer that electrically connects one of the semiconductor chips to the external connection terminal protruding from the side surface of the second sealing body 102A to the outside. The second redistribution layer is exposed from the first sealing body 101A, and the external connection terminals 451a, 452a, and 452b are connected to this exposed surface.

[0036] A rewiring layer 304 is disposed on the plane on the side of the insulating substrate 110 of the power semiconductor chip 201L. The plane (plane on the +Z side) of the rewiring layer 304 opposite to the side on which the insulating substrate 110 is present is connected to the drain of the power semiconductor chip 201L, and the plane on the insulating substrate 110 side is connected to the conductor pattern of the second conductor layer 113 by a bonding layer 421. The rewiring layer 304 and the power semiconductor chip 201L are bonded by a conductive bonding member (not shown) such as solder. As shown in FIG. 2, the rewiring layer 304 is connected to an external connection terminal 451b via the rewiring layer 301b. The external connection terminal 451b is an external connection terminal protruding from the side surface of the second sealing body 102A to the outside, and is, for example, the terminal U in FIG. 1. The conductor pattern to which the bonding layer 421 is connected is insulated from other conductor patterns formed on the second conductor layer 113.

[0037] 4 and 5, in the first sealing body 101A, in another part of the region separated from the insulating substrate 110 (specifically, the region moved to the -X side), a power semiconductor chip 201H and a control semiconductor chip 211H are arranged side by side in the Y direction perpendicular to the thickness direction of the semiconductor device 100A. The power semiconductor chip 201H is, for example, a power semiconductor chip including the switching element Q1 of FIG. 1. The control semiconductor chip 211H is, for example, a control semiconductor chip corresponding to the HVIC2U of FIG. 1.

[0038] In the power semiconductor chip 201H, the source and gate of the MOSFET are formed on the plane (plane on the +Z side) opposite to the side where the insulating substrate 110 is present, and the drain of the MOSFET is formed on the plane where the insulating substrate 110 is present. In the power semiconductor chip 201H, the rewiring layer 311a is present on the side opposite to the side where the insulating substrate 110 is present, and this rewiring layer 311a is connected to the source of the MOSFET. The rewiring layer 311a is connected to the external connection terminal 461a via the connection pad 411a opposite to the side where the insulating substrate 110 is present. That is, the rewiring layer 311a is exposed from the first sealing body 101A, and the external connection terminal 461a is connected to the exposed surface exposed from the first sealing body 101A via the connection pad 411a. This external connection terminal 461a is an external connection terminal protruding to the outside from the side surface of the second sealing body 102A, and is, for example, the terminal U in FIG. 1.

[0039] On the opposite side (+Z side) of the power semiconductor chip 201H and the control semiconductor chip 211H to the side where the insulating substrate 110 is located, there is a redistribution layer 312 extending in the Y direction perpendicular to the thickness direction of the semiconductor device 100A. One end of the redistribution layer 312 is bent toward the insulating substrate 110 and connected to the gate of the power semiconductor chip 201H. The other end of the redistribution layer 312 is bent toward the insulating substrate 110 and connected to a signal terminal of the control semiconductor chip 211H. This signal terminal is, for example, the terminal OUT of the HVIC2U shown in FIG. 1. That is, the redistribution layer 312 is a first redistribution layer that electrically connects one semiconductor chip and another semiconductor chip among the multiple semiconductor chips.

[0040] The control semiconductor chip 211H has rewiring layers 315 and 316 on the side (-Z side) where the insulating substrate 110 is located. The rewiring layer 315 is connected to a conductor pattern formed on the second conductor layer 113 of the insulating substrate 110 via a bonding layer (not shown). The control semiconductor chip 211H and the rewiring layer 315 are bonded to each other by a conductive bonding member (not shown) such as solder. The rewiring layer 315 is a wiring path that provides a GND potential to the rear surface (plane on the -Z side) of the control semiconductor chip 211L. The rewiring layer 316 is connected to another conductor pattern in the second conductor layer 113 via a bonding layer 424. Like the rewiring layer 306, the rewiring layer 316 does not function as a wiring path, but is a rewiring layer that stabilizes the adhesion between the first sealing body 101A and the insulating substrate 101A.

[0041] In addition, there are two other signal terminals on the plane (+Z plane) opposite to the side where the insulating substrate 110 is present in the control semiconductor chip 211H. One signal terminal is, for example, the terminal IN of the HVIC2U shown in FIG. 1. This signal terminal is connected to the external connection terminal 462a via the rewiring layer 313a and the connection pad 412a on the side opposite to the side where the insulating substrate 110 is present in the control semiconductor chip 211H (+Z side). The other signal terminal is, for example, the terminal VCC of the HVIC2U shown in FIG. 1. This signal terminal is connected to the external connection terminal 462b via the rewiring layer 313b and the connection pad 412b on the side opposite to the side where the insulating substrate 110 is present in the control semiconductor chip 211H (+Z side). That is, the rewiring layers 313a and 313b are exposed from the first sealing body 101A, and external connection terminals 462a and 462b are connected to the exposed surfaces exposed from the first sealing body 101A via connection pads 412a and 412b.

[0042] The external connection terminals 462a and 462b are external connection terminals protruding from the side surface of the second sealing body 102A to the outside, similar to the external connection terminal 451, and correspond to, for example, the terminals IN(HU) and VCCH in Fig. 1. That is, the redistribution layers 313a and 313b and the above-mentioned redistribution layer 311a are a second redistribution layer that electrically connects one of the semiconductor chips to the external connection terminal protruding from the side surface of the second sealing body 102A to the outside. The second redistribution layer is exposed from the first sealing body 101A, and the external connection terminals 461a, 462a, and 462b are connected to this exposed surface.

[0043] In the power semiconductor chip 201H, a redistribution layer 314 is disposed on the insulating substrate 110 side. The redistribution layer 314 has a flat surface on the opposite side (+Z side) to the insulating substrate 110 side connected to the drain of the power semiconductor chip 201H, and the flat surface on the insulating substrate 110 side is electrically connected to the conductor pattern formed on the second conductor layer 113 by a bonding layer 422. The redistribution layer 314 and the power semiconductor chip 201H are bonded by a conductive bonding member (not shown) such as solder. On the other hand, the redistribution layer 314 is connected to an external connection terminal 461b via a redistribution layer 311b as shown in FIG. 4. The external connection terminal 461b is an external connection terminal protruding from the side surface of the second sealing body 102A to the outside, and is, for example, the terminal P in FIG. 1. The above is the configuration of the semiconductor device 100A according to this embodiment.

[0044] According to this embodiment, one semiconductor chip is electrically connected to another semiconductor chip by the first redistribution layer. Also, according to this embodiment, one semiconductor chip is electrically connected to an external connection terminal by the second redistribution layer. Therefore, the wiring length of the wiring to the semiconductor chip can be shortened, thereby reducing the wiring inductance and enabling high-speed switching operation of the power semiconductor chip.

[0045] In particular, when power semiconductor chips are made of SiC, the element is miniaturized and the electrode area is small, making it impossible to connect by wire bonding in high current specifications. Therefore, if connection is made by wire bonding, it becomes difficult to reduce the element size. According to this embodiment, a rewiring layer is connected to the power semiconductor chip instead of a bonding wire, so that the size reduction of the power semiconductor chip is not hindered.

[0046] Furthermore, according to this embodiment, since a rewiring layer is used as the wiring inside the encapsulant instead of a bonding wire, the problem of wire sweep does not occur in the transfer mold structure.

[0047] In addition, in semiconductor devices, the wiring becomes dense as the elements become smaller, which causes noise generation to be an issue. However, according to this embodiment, the use of a redistribution layer increases the degree of freedom of wiring, making it possible to prevent the wiring from becoming dense and to prevent noise generation.

[0048] In addition, in a semiconductor device, when a power semiconductor chip is made of SiC, high-speed operation becomes possible, and di / dt at turn-off becomes large, so suppression of overvoltage at turn-off becomes an issue. According to this embodiment, since no bonding wire is included in the flow path of the output current i of the power semiconductor chip, overvoltage at turn-off can be suppressed.

[0049] <Second embodiment> FIG. 6 is a cross-sectional view showing the configuration of a semiconductor device 100B according to a second embodiment of the present invention. FIG. 6 shows parts corresponding to the parts of the semiconductor device 100A shown in FIG. 3 of the first embodiment. The semiconductor device 100B shown in FIG. 6 has a configuration obtained by roughly inverting the semiconductor device 100A shown in FIG. 3 in the Z-axis direction. The first sealing body 101B includes a plurality of semiconductor chips and a rewiring layer. The insulating substrate 110 is connected to the first sealing body 101B, and the second sealing body 102B seals the first sealing body 101B and the insulating substrate 110. In the illustrated example, the first sealing body 101B is exposed from the second sealing body 102B on the surface opposite to the insulating substrate 110, but the first sealing body 101B may be covered by the second sealing body 102B.

[0050] The difference between this embodiment and the first embodiment is as follows. In the first embodiment (FIG. 3), the redistribution layers 301a and 303b are connected to the external connection terminals 451a and 452b protruding from the side surface of the second sealing body 102A to the outside. In contrast, in this embodiment, the redistribution layers 301a and 303b are exposed to the outside of the first sealing body 101B, and the conductor balls 501 and 502 functioning as external connection terminals are formed on the exposed surfaces. That is, the redistribution layers 301a and 303b (second redistribution layers) are exposed from the first sealing body 101A, and the conductor balls 501 and 502 functioning as external connection terminals are connected to the exposed surfaces exposed from the first sealing body 101A. Furthermore, the wiring layers 301a and 303b are connected to a circuit board (not shown) via the conductor balls 501 and 502.

[0051] The present embodiment also provides the same effects as those of the first embodiment. Moreover, in the present embodiment, since a large number of conductor balls can be arranged over the entire surface of one plane of the first sealing body 101B, an IPM having a large number of external connection terminals can be realized.

[0052] <Third embodiment> Fig. 7 is a cross-sectional view showing the configuration of a semiconductor device 100C according to a third embodiment of the present invention, and Fig. 8 is a perspective view showing the appearance of the semiconductor device 100C. Figs. 7 and 8 show a configuration in which a portion corresponding to one phase (U-phase in this example) of the IPM 1 shown in Fig. 1 is modularized.

[0053] The semiconductor device 100C according to the present embodiment includes a plurality of semiconductor chips including power semiconductor chips 251L and 251H including switching elements and control semiconductor chips 261L and 261H including control circuits for controlling the switching elements, a redistribution layer including a first redistribution layer (in the illustrated example, redistribution layers 351, 352, and 354) that electrically connects one semiconductor chip to another semiconductor chip in the plurality of semiconductor chips, and a semiconductor device including a plurality of semiconductor chips and a redistribution layer. the first sealing body 101C that seals the semiconductor chips, a first insulating substrate 110a and a second insulating substrate 110b that each consist of an insulating layer 111a (111b) and first and second conductor layers 112a and 113a (112b and 113b) that sandwich the insulating layer and are arranged in the first sealing body 101C so as to sandwich a plurality of semiconductor chips and a redistribution layer therebetween, and a second sealing body 102C that seals the first insulating substrate 110a, the first sealing body 101C, and the second insulating substrate 110b.

[0054] Furthermore, semiconductor device 100C has external connection terminals 471-473 protruding outward from the side surfaces of second sealing body 102C. The redistribution layers include a third redistribution layer (redistribution layers 353, 354, 361-364 in the illustrated example) that electrically connects one of the semiconductor chips to the external connection terminals via the conductor layer of first insulating substrate 110a or second insulating substrate 110b.

[0055] As in the first embodiment, in this embodiment, first, a first sealing body 101C including a semiconductor chip and a rewiring layer is formed. Next, the first insulating substrate 110a is connected to the first sealing body 101C by bonding the second conductor layer 113a of the first insulating substrate 110a to the rewiring layer of the first sealing body 101C, and the first insulating substrate 110b is connected to the first sealing body 101C by bonding the second conductor layer 113b of the second insulating substrate 110b to the rewiring layer of the first sealing body 101C. Next, the external connection terminals 471 to 473 are connected to the second conductor layer 113a of the first insulating substrate 110a or the second conductor layer 113b of the second insulating substrate 110b. Next, the first sealing body 101C, the first insulating substrate 110a, the second insulating substrate 110b, and the external connection terminals 471 to 473 are sealed in the second sealing body 102C. In the illustrated example, first conductor layer 112a of first insulating substrate 110a and first conductor layer 112b of second insulating substrate 110b are exposed from second sealing body 102C.

[0056] In the first sealing body 101C, between the first insulating substrate 110a and the second insulating substrate 110b, a power semiconductor chip 251L, a control semiconductor chip 261L, a control semiconductor chip 261H, and a power semiconductor chip 251H are arranged at intervals in the thickness direction (Z-axis direction) of the semiconductor device 100C.

[0057] The power semiconductor chip 251L is a power semiconductor chip including, for example, the switching element Q2 of FIG. 1. The drain of the MOSFET is formed on the plane of the power semiconductor chip 251L on the first insulating substrate 110a side, and the source and gate of the MOSFET are formed on the plane of the power semiconductor chip 251L on the second insulating substrate 110b side. The control semiconductor chip 261L corresponds to, for example, the LVIC3 of FIG. 1. The control semiconductor chip 261L has an element formation surface on the plane of the first insulating substrate 110a side on which elements and signal terminals are formed. The control semiconductor chip 261H corresponds to, for example, the HVIC2U of FIG. 1. The control semiconductor chip 261H has an element formation surface on the plane of the second insulating substrate 110b side on which elements and signal terminals are formed. The power semiconductor chip 251H is a power semiconductor chip including, for example, the switching element Q1 of FIG. 1. The drain of the MOSFET is formed on the plane of the power semiconductor chip 251H on the second insulating substrate 110b side, and the source and gate of the MOSFET are formed on the plane of the first insulating substrate 110a side.

[0058] The redistribution layer 351 is a first redistribution layer that electrically connects a signal terminal (corresponding to the terminal UOUT of the LVIC3 in FIG. 1) of the control semiconductor chip 261L and a gate of the MOSFET of the power semiconductor chip 251L. The redistribution layer 352 is a first redistribution layer that electrically connects a signal terminal (corresponding to the terminal OUT of the HVIC2U in FIG. 1) of the control semiconductor chip 261H and a gate of the MOSFET of the power semiconductor chip 251H.

[0059] The plane of the rewiring layer 353 on the first insulating substrate 110a side is connected to the drain of the power semiconductor chip 251H. The plane of the rewiring layer 353 on the second insulating substrate 110b side is connected to a conductor pattern formed on the second conductor layer 113b of the second insulating substrate 110b via a bonding layer 453, and this conductor pattern is connected to an external connection terminal 472 protruding from a side surface of the second sealing body 102C to the outside. This external connection terminal 472 corresponds to, for example, the terminal P in FIG. 1. That is, the rewiring layer 353 is a third rewiring layer that electrically connects one semiconductor chip in the multiple semiconductor chips to an external connection terminal via the conductor layer of the first insulating substrate or the second insulating substrate.

[0060] The rewiring layer 354 electrically connects the source on the plane of the power semiconductor chip 251H facing the first insulating substrate 110a to the drain on the plane of the power semiconductor chip 251L facing the first insulating substrate 110a. Therefore, the rewiring layer 354 is a first rewiring layer that electrically connects one semiconductor chip to another semiconductor chip. In addition, the power semiconductor chip 251H and the rewiring layer 354 are joined by a conductive joining member (not shown) such as solder.

[0061] On the other hand, the plane of the redistribution layer 354 on the first insulating substrate 110 side is connected to a conductor pattern 113a_3 formed on the second conductor layer 113a of the first insulating substrate 110 via a bonding layer 451, and this conductor pattern 113a_3 is connected to an external connection terminal 473 corresponding to the terminal U in Fig. 1. Therefore, the redistribution layer 354 is not only a first redistribution layer, but also a third redistribution layer that electrically connects one semiconductor chip among the multiple semiconductor chips to an external connection terminal via the conductor layer of the first insulating substrate 110a or the second insulating substrate 110b.

[0062] One end of the redistribution layer 361 is connected to a source on the plane of the power semiconductor chip 251L on the second insulating substrate 110b side. The other end of the redistribution layer 361 is connected to a conductor pattern 113a_1 formed on the second conductor layer 113a of the second insulating substrate 110a via a bonding layer 452, and the conductor pattern 113a_1 is connected to an external connection terminal 471 corresponding to the terminal N(U) in FIG. 1. The redistribution layer 361 is a third redistribution layer that electrically connects one semiconductor chip among the multiple semiconductor chips to an external connection terminal via the conductor layer of the first insulating substrate 110a or the second insulating substrate 110b.

[0063] One end of the rewiring layer 362 is connected to a signal terminal (corresponding to the terminal UIN of the LVIC3 in FIG. 1) on the plane of the control semiconductor chip 261L on the first insulating substrate 110a side. A portion near one end of the rewiring layer 363 is connected to the plane of the control semiconductor chip 261L on the second insulating substrate 110b side and the plane of the control semiconductor chip 261H on the first insulating substrate 110a side. In addition, the control semiconductor chip 261H and the rewiring layer 363 are joined by a conductive joining member (not shown) such as solder. One end of the rewiring layer 364 is connected to a signal terminal (corresponding to the terminal IN of the HVIC2U in FIG. 1) on the plane of the control semiconductor chip 261H on the second insulating substrate 110b side.

[0064] The other ends of the rewiring layers 362, 363, and 364 are connected to separate conductor patterns (not shown) formed on the second conductor layer 113a of the first insulating substrate 110a via separate bonding layers (not shown), and these conductor patterns are connected to separate external connection terminals (not shown). As shown in FIG. 8, the external connection terminal 474 to which the rewiring layer 362 is connected corresponds to, for example, the terminal IN(LU) in FIG. 1. The external connection terminal 475 to which the rewiring layer 363 is connected corresponds to, for example, the terminal COM in FIG. 1. That is, the rewiring layer 363 provides a GND potential to the semiconductor substrates of the control semiconductor chips 261L and 261H. The external connection terminal 476 to which the rewiring layer 364 is connected corresponds to, for example, the terminal IN(HU) in FIG. 1. In this manner, rewiring layers 362 to 364 are third rewiring layers that electrically connect one of the multiple semiconductor chips to an external connection terminal via the conductor layer of first insulating substrate 110a or second insulating substrate 110b.

[0065] The present embodiment also provides the same effects as the first embodiment. Moreover, in this embodiment, the high-side element and the low-side element are stacked vertically, so that the area occupied in the plane of the semiconductor device can be reduced, and the entire device can be made smaller. Moreover, in this embodiment, insulating substrates are provided on both surfaces in the plate thickness direction of the semiconductor device, so that a high heat dissipation effect can be obtained even when the high-side element and the low-side element are stacked vertically.

[0066] <Other embodiments> Although the first to third embodiments of the present invention have been described above, other embodiments of the present invention are also possible. For example, the following embodiments are possible.

[0067] Fig. 9 is a cross-sectional view showing the configuration of a semiconductor device 100D which is a modification of the third embodiment (Fig. 7) described above. In Fig. 9, the same reference numerals are used for parts corresponding to those in Fig. 7, and the description thereof will be omitted.

[0068] In this embodiment, the orientation of the power semiconductor chip 251L is opposite to that of the third embodiment. That is, in this embodiment, the drain of the MOSFET is formed on the plane of the power semiconductor chip 251L facing the second insulating substrate 110b, and the gate and source of the MOSFET are formed on the plane of the power semiconductor chip 251L facing the first insulating substrate 110a.

[0069] In accordance with the change in the orientation of the power semiconductor chip 251L, in this embodiment, the redistribution layer related to the power semiconductor chip 251L is changed.

[0070] The redistribution layer 351b connects the gate of the MOSFET on the plane on the first insulating substrate 110a side of the power semiconductor chip 251L to the conductor pattern 113a_2 formed on the second conductor layer 113a of the first insulating substrate 110a. The redistribution layer 351a connects the conductor pattern 113a_2 to a signal terminal (corresponding to the terminal UOUT of the LVIC 3 in FIG. 1) on the plane on the first insulating substrate 110a side of the control semiconductor chip 261L.

[0071] The rewiring layer 361a connects the source of the MOSFET on the plane on the first insulating substrate 110a side of the power semiconductor chip 251L to a conductor pattern 113a_1 formed on the second conductor layer 113a of the first insulating substrate 110a. An external connection terminal 471 corresponding to the terminal N(U) in FIG. 1 is connected to this conductor pattern 113a_1.

[0072] The redistribution layer 354a electrically connects the source of the MOSFET on the plane on the first insulating substrate 110a side of the power semiconductor chip 251H to the drain of the MOSFET on the plane on the second insulating substrate 110b side of the power semiconductor chip 251L. The redistribution layer 354a is also connected to a conductor pattern 113a_3 formed on the second conductor layer 113a of the first insulating substrate 110a. This conductor pattern 113a_3 is connected to an external connection terminal 473 corresponding to the terminal U in FIG. 1. In this embodiment as well, the same effects as those of the third embodiment can be obtained.

[0073] In the above embodiments, the power semiconductor chip is configured with a MOSFET, but may be configured with other types of elements such as an IGBT (Insulated Gate Bipolar Transistor) and a diode connected in reverse parallel to the IGBT. Also, the power semiconductor chip is configured with a wide band gap semiconductor element such as SiC, but may be a Si element.

[0074] In the above embodiments, the present invention is applied to an IPM including a power semiconductor chip and a control semiconductor chip, but the present invention may be applied to a semiconductor device including only a power semiconductor chip. That is, the HVIC and LVIC may be omitted from the configuration of FIG. 1, and only the switching elements Q1 to Q6 may be connected by a rewiring layer to form a power semiconductor module.

[0075] In each of the above embodiments, the semiconductor device has been described as one element or one phase, but it may be a so-called 6-in-1 package in which three phases are housed in one package. [Explanation of symbols]

[0076] 1: IPM, Q1 to Q6: switching elements, 2U, 2V, 2W: HVIC, 3: LVIC, 100A, 100B, 100C, 100D: semiconductor device, 101A, 101B, 101C: first sealing body, 102A, 102B, 102C: second sealing body, 110: insulating substrate, 110a: first insulating substrate, 110b: second insulating substrate, 111, 111a, 111b: insulating layer, 112, 112a, 112b: first conductor layer, 113, 113a, 113b: second conductor layer, 113a_1, 113a_2, 113a_ 3...conductor pattern, 201L, 231L, 201H, 231H, 251L, 251H...power semiconductor chips, 211L, 211H, 241L, 261L, 261H...control semiconductor chips, 301a, 301b, 302, 303a, 303b, 304, 305, 306, 311a, 311b, 312, 313a, 313b, 314, 315, 316, 351 to 354, 361 to 364...rewiring layer, 401a, 401b...connection pads, 451 to 453, 456, 457...bonding layer, 501, 502...conductor balls.

Claims

1. A plurality of semiconductor chips including a power semiconductor chip including a switching element and a control semiconductor chip including a control circuit for controlling the switching element; a rewiring layer including a first rewiring layer electrically connecting one semiconductor chip and another semiconductor chip among the plurality of semiconductor chips; a first sealing body that seals the semiconductor chips and the rewiring layer; an insulating substrate including an insulating layer and conductive layers sandwiching the insulating layer, the insulating substrate being disposed in the first sealing body so as to face the semiconductor chips and the rewiring layer; a second sealing body sealing the insulating substrate and the first sealing body; A semiconductor device having the above structure.

2. the redistribution layer includes a second redistribution layer that electrically connects one semiconductor chip among the plurality of semiconductor chips to an external connection terminal protruding to the outside of the second sealing body; The semiconductor device according to claim 1 .

3. The external connection terminal protrudes to the outside from a side surface of the second sealing body. The semiconductor device according to claim 2 .

4. the second redistribution layer is exposed from the first sealing body, and the external connection terminal is connected to the exposed surface. The semiconductor device according to claim 2 .

5. A plurality of semiconductor chips including a power semiconductor chip including a switching element and a control semiconductor chip including a control circuit for controlling the switching element; a rewiring layer including a first rewiring layer electrically connecting one semiconductor chip and another semiconductor chip among the plurality of semiconductor chips; a first sealing body that seals the semiconductor chips and the rewiring layer; first and second insulating substrates, each of which includes an insulating layer and a conductor layer sandwiching the insulating layer, and which are disposed in the first sealing body so as to sandwich the plurality of semiconductor chips and the rewiring layer therebetween; a second sealing body that seals the first insulating substrate, the first sealing body, and the second insulating substrate; A semiconductor device having the above structure.

6. an external connection terminal protruding to the outside from a side surface of the second sealing body surrounding a region sandwiched between the first insulating substrate and the second insulating substrate; the redistribution layer includes a third redistribution layer that electrically connects one of the plurality of semiconductor chips to the external connection terminal via a conductor layer of the first insulating substrate or the second insulating substrate; The semiconductor device according to claim 5 .

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