Direct type power conversion circuit

Abstract

To enable an achievement of a continuous mode by controlling a charging period of a capacitor in a charging and discharging circuit.SOLUTION: A rectification circuit includes a first capacitor and a first reactor, and obtains a rectification voltage by executing all-wave rectification and a low-pass filter against a single phase AC voltage. A voltage between a first power supply line and a second power supply line is input into an inverter. A charging and discharging circuit includes: a charging circuit; and a discharging circuit. The discharging circuit contains a second capacitor provided to between the first power supply line and the second power supply line. The charging circuit increases a pressure of the single phase AC voltage or a rectification voltage to which the all-wave rectification is made, and charges the second capacitor in a charging period. The charging period includes a length set independent of an oscillation of an input current input into the rectification circuit and depended onto a phase of the single phase AC voltage. When the voltage of the first reactor is deteriorated, both of a start point and a termination point in the charging period are shifted against the phase to a delay phase side. When the voltage of the first capacitor is increased, both of the start point and the termination point are shifted against the phase to the delay phase side.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to direct power conversion circuits. [Background technology]

[0002] Patent Document 1 discloses a direct power conversion circuit. The direct power conversion circuit includes a converter, a power buffer circuit, an inverter, and a DC link. The converter inputs a single-phase AC voltage and outputs pulsating power to the DC link. The inverter converts the DC voltage in the DC link to an AC voltage. The power buffer circuit includes a discharge circuit having a capacitor and a switch, and a charging circuit that charges the capacitor. Power supplied to the inverter may be supplied from the converter or from the power buffer circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5874800 Summary of the Invention [Problem to be solved by the invention]

[0004] A boost circuit including a reactor, a capacitor, and a switching element is known. The current flowing through the reactor (hereinafter also simply referred to as "reactor current") flows or does not flow through the capacitor, so that the capacitor is charged with a voltage exceeding the voltage applied to the reactor from outside the boost circuit. Such a boost circuit can be used in combination with the charging circuit and capacitor of the above-mentioned direct power conversion circuit. For example, a power buffer circuit is realized by a charging / discharging circuit that charges and discharges the capacitor.

[0005] For example, when a reactor current is passed, a so-called critical mode is adopted. When a reactor current is passed in the critical mode, when the reactor current decreases to zero due to charging of the capacitor, the switching element is turned on and the reactor current starts to pass through the switching element. This point in time does not depend on the phase of the single-phase AC voltage, and can be easily determined only by the presence or absence of the reactor current.

[0006] From the viewpoint of relaxing the current standard required for the elements of the charge / discharge circuit by reducing the peak value of the reactor current, and from the viewpoint of efficiency, it is desirable to adopt a so-called continuous mode for the reactor current. When the continuous mode is adopted for the reactor current, it is necessary to set the timing for passing the reactor current to the switching element without passing it to the capacitor while the reactor current is flowing to the capacitor.

[0007] In view of the necessity for the above-mentioned timing, an object of the present disclosure is to control the charging period of a capacitor in a charge / discharge circuit of a direct power converter, thereby contributing to the realization of a continuous mode. [Means for solving the problem]

[0008] A first aspect of a direct power conversion circuit (100, 100A, 100B, 100C, 100D) in the present disclosure includes a first power supply line (LH), a second power supply line (LL) to which a potential lower than that of the first power supply line is applied, a rectifier circuit (203) having an input side to which a single-phase AC voltage (Vin) is applied from an AC power source (1) and an output side to which the first power supply line and the second power supply line are connected, and outputting a rectified voltage (Vrf) obtained by performing full-wave rectification and low-pass filtering on the single-phase AC voltage (Vin), a charge / discharge circuit (4) provided between the first power supply line and the second power supply line on the output side of the rectifier circuit, and an inverter (5) to which a DC voltage (Vdc) which is the voltage between the first power supply line and the second power supply line is input.

[0009] The rectifier circuit (203) includes a diode rectifier (2; 2a, 2b) used for the full-wave rectification, a first capacitor (C3) connected directly between the first power supply line and the second power supply line or indirectly via the diode rectifier (2; 2a), and a first reactor (L3) that performs the low-pass filtering in cooperation with the first capacitor (C3).

[0010] The charge / discharge circuit (4) includes a second capacitor (C4) provided between the first power supply line and the second power supply line, and has a discharge circuit (4a) that discharges the second capacitor, and a charging circuit (4b) that boosts the full-wave rectified single-phase AC voltage (|Vin|) or the rectified voltage (Vrf) and charges the second capacitor (C4) in a charging period (CH) having a length that is set depending on the phase (θ) of the single-phase AC voltage (Vin) and does not depend on the amplitude (Im) of an input current (Iin) input to the rectifier circuit (203).

[0011] When the voltage (VL) of the first reactor (L3) decreases, both the start point (ts) and the end point (te) of the charging period (CH) are shifted toward the lag phase side with respect to the phase (θ). When the voltage (V3) of the first capacitor (C3) increases, both the start point (ts) and the end point (te) are shifted toward the lag phase side with respect to the phase.

[0012] The polarity of the voltage (VL) of the first reactor (L3) is defined as positive when it is in the opposite direction to the direction of the current supplied from the AC power supply (1) that flows between the diode rectifier (2; 2a) and the first reactor (L3).

[0013] The polarity of the voltage (V3) of the first capacitor (C3) coincides with the polarity of the voltage on the output side or input side of the diode rectifier (2; 2a) to which the first capacitor (C3) is connected.

[0014] A second aspect of the direct power conversion circuit (100, 100A, 100B, 100C, 100D) in the present disclosure is the first aspect of the direct power conversion circuit, and the second capacitor (C4) discharges with a duty (dc) proportional to the product of a cosine value (cos(2θ)) twice the phase (θ) and a command value (Vdc*) of the DC voltage only during a period in which the cosine value (cos(2θ)) is positive.

[0015] In a second aspect, the charging circuit (4b) includes, on the output side of the rectifier circuit (203), a second reactor (L4) connected in series with the second capacitor (C4), a diode (D40) located on the high potential side of the second capacitor (C4) and connected between the second reactor (L4) and the second capacitor (C4) and having a forward direction from the second reactor (L4) to the second capacitor (C4), and a switch (Sl) that switches whether a reactor current (I4) flowing in the second reactor (L4) is to flow to the second capacitor (C4) via the diode (D40) or to the second power supply line (LL).

[0016] In the second mode, the reactor current (I4) flows through the second power line (LL) while increasing from the end point (te) of the first charging period to the start point (ts) of the second charging period immediately after the first charging period. The start point (ts) is the time point at which the reactor current (I4) increases and reaches an upper limit value (il^). The reactor current (I4) flows into the second capacitor (C4) during the charging period (CH).

[0017] In a second aspect, the upper limit (il^) is a product of the amplitude (Im) and a predetermined function (G(θ)) of the phase. The predetermined function (G(θ)) is a square of the sine value of the phase (sin 2 θ) (half the reciprocal of ((2·sin 2 θ) -1 The value obtained by subtracting θ from 1 and multiplying the absolute value of the sine value (|sinθ|) is taken as the product (F(θ)) of the product and adding a correction term (ΔF).

[0018] In the second aspect, the smaller the voltage (VL) of the first reactor (L3), the larger the correction term (ΔF).The larger the voltage (V3) of the first capacitor (C3), the larger the correction term (ΔF).

[0019] A third aspect of the direct power conversion circuit (100, 100A, 100C, 100D) in the present disclosure is the first aspect of the direct power conversion circuit, and the second capacitor (C4) is a square (cos 2 θ) and the DC voltage command value (Vdc*).

[0020] In a third aspect, the charging circuit (4b) includes, on the output side of the rectifier circuit (203), a second reactor (L4) connected in series with the second capacitor (C4), a diode (D40) located on the high potential side of the second capacitor (C4) and connected between the second reactor (L4) and the second capacitor (C4) and having a forward direction from the second reactor (L4) to the second capacitor (C4), and a switch (Sl) that switches whether a reactor current (I4) flowing in the second reactor (L4) is to flow to the second capacitor (C4) via the diode (D40) or to the second power supply line (LL).

[0021] In the third aspect, the reactor current (I4) flows through the second power line (LL) while increasing from the end point (te) of the first charging period to the start point (ts) of the second charging period immediately after the first charging period. The start point (ts) is the time point at which the reactor current (I4) increases and reaches an upper limit value (il^). The reactor current (I4) flows into the second capacitor (C4) during the charging period (CH).

[0022] In a third aspect, the upper limit (il^) is the product of the amplitude (Im) and a predetermined function (G(θ)) of the phase. The predetermined function (G(θ)) is a value obtained by adding a correction term (ΔF) to the product (F(θ)) of the absolute value of the sine value (|sinθ|) and the half-value of the product of the cosine value (cos(2θ)) of twice the phase and a coefficient (1-kb) between 0 and 1, both inclusive, plus 1 / 2.

[0023] In the third aspect, the smaller the voltage (VL) of the first reactor (L3), the larger the correction term (ΔF).The larger the voltage (V3) of the first capacitor (C3), the larger the correction term (ΔF).

[0024] A fourth aspect of the direct power conversion circuit (100, 100A, 100B, 100C, 100D) in the present disclosure is the first aspect of the direct power conversion circuit, and the second capacitor (C4) discharges with a duty (dc) proportional to the product of a cosine value (cos(2θ)) twice the phase (θ) and the amplitude (Vm) of the single-phase AC voltage only during a period in which the cosine value is positive.

[0025] In a fourth aspect, the charging circuit (4b) includes, on the output side of the rectifier circuit (203), a second reactor (L4) connected in series with the second capacitor (C4), a diode (D40) located on the high potential side of the second capacitor (C4) and connected between the second reactor (L4) and the second capacitor (C4) and having a forward direction from the second reactor (L4) to the second capacitor (C4), and a switch (Sl) that switches whether a reactor current (I4) flowing in the second reactor (L4) is to flow to the second capacitor (C4) via the diode (D40) or to the second power supply line (LL).

[0026] In a fourth aspect, the reactor current (I4) flows through the second power line (LL) while increasing from the end point (te) of the first charging period to the start point (ts) of the second charging period immediately after the first charging period. The start point (ts) is the time point at which the reactor current (I4) increases and reaches an upper limit value (il^). The reactor current (I4) flows into the second capacitor (C4) during the charging period (CH).

[0027] In a fourth aspect, the upper limit (il^) is a product of the amplitude (Im) and a predetermined function (G(θ)) of the phase. The predetermined function (G(θ)) is a square of the sine value of the phase (sin 2 (θ)) 2 (θ) -1 ) from 1, a coefficient (kb) between 0 and 1, the coefficient (π / √8), and the absolute value of the sine value (|sinθ|) are multiplied (F(θ)) to add a correction term (ΔF).

[0028] In the fourth aspect, the smaller the voltage (VL) of the first reactor (L3), the larger the correction term (ΔF).The larger the voltage (V3) of the first capacitor (C3), the larger the correction term (ΔF).

[0029] A fifth aspect of the direct power conversion circuit (100, 100A, 100C, 100D) in the present disclosure is the first aspect of the direct power conversion circuit, in which the second capacitor (C4) is discharged with a duty (dc) having a value (1-B) obtained by subtracting a first value (B) from 1.

[0030] In a fifth aspect, the charging circuit (4b) includes, on the output side of the rectifier circuit (203), a second reactor (L4) connected in series with the second capacitor (C4), a diode (D40) located on the high potential side of the second capacitor (C4) and connected between the second reactor (L4) and the second capacitor (C4) and having a forward direction from the second reactor (L4) to the second capacitor (C4), and a switch (Sl) that switches whether a reactor current (I4) flowing in the second reactor (L4) is to flow to the second capacitor (C4) via the diode (D40) or to the second power supply line (LL).

[0031] In the fifth aspect, the reactor current (I4) flows through the second power line (LL) while increasing from the end point (te) of the first charging period to the start point (ts) of the second charging period immediately after the first charging period. The start point (ts) is the time point at which the reactor current (I4) increases and reaches an upper limit value (il^). The reactor current (I4) flows into the second capacitor (C4) during the charging period (CH).

[0032] In a fifth aspect, the upper limit value (il^) is a product of the amplitude (Im) and a predetermined function (G(θ)) of the phase. The predetermined function (G(θ)) is the sum of a correction term (ΔF) and a value (F(θ)) obtained by subtracting the product (B·J) of the first value (B) and the second value (J) from the absolute value (|sinθ|) of the sine value of the phase.

[0033] In a fifth aspect, the first value (B) is a ratio ([Vdc*-Vc] / [Vrec-Vc]) of a value (Vrec-Vc) obtained by subtracting the voltage (Vc) of the second capacitor (C4) from the command value (Vdc*) of the DC voltage to a value (Vrec-Vc) obtained by subtracting the voltage (Vc) of the second capacitor from the command value (Vdc*) of the DC voltage. The second value (J) is a product of a half value obtained by subtracting from 1 the product of a cosine value (cos(2θ)) of twice the value of the phase and a coefficient (1-kb) between 0 and 1, and a ratio (Vm / Vdc*) of the amplitude (Vm) of the single-phase AC voltage to the command value (Vdc*) of the DC voltage.

[0034] In the fifth aspect, the smaller the voltage (VL) of the first reactor (L3), the larger the correction term (ΔF).The larger the voltage (V3) of the first capacitor (C3), the larger the correction term (ΔF).

[0035] A sixth aspect of the direct power conversion circuit (100, 100A, 100B, 100C, 100D) in the present disclosure is any of the second to fifth aspects of the direct power conversion circuit, and the length of the charging period (CH) is proportional to the sum (G(θ)) of a first quantity (F(θ)) that does not depend on either the voltage (VL) of the first reactor (L3) or the voltage (V3) of the first capacitor (C3) but depends on the phase (θ), and a second quantity (ΔF) that depends on either or both of the voltage (VL) of the first reactor (L3) and the voltage (V3) of the first capacitor (C3).

[0036] A seventh aspect of the direct power conversion circuit (100, 100A, 100B, 100C, 100D) in the present disclosure is the first aspect of the direct power conversion circuit, in which the charging circuit (4b) chops a second input current (I4) input to the charging circuit (4b) to charge the second capacitor (C4).

[0037] In the seventh aspect, the smaller the value obtained by dividing the average value of the second input current (I4) in the chopping cycle (Tsw) by the maximum value of the average value, the shorter the charging period (CH).The smaller the voltage (VL) of the first reactor (L3), the longer the charging period (CH).The larger the voltage (V3) of the first capacitor (C3), the longer the charging period (CH).

[0038] For example, the first capacitor (C3) is directly connected between the first power line (LH) and the second power line (LL), and the polarity of the voltage (V3) of the first capacitor (C3) is positive in the direction from the second power line (LL) to the first power line (LH).

[0039] Or, for example, the first capacitor (C3) is located farther from the inverter (5) than the diode rectifier (2; 2a), and the polarity of the voltage (V3) of the first capacitor (C3) is positive in the direction from the low potential to the high potential of the single-phase AC voltage (Vin).

[0040] Alternatively, for example, the first reactor (L3) is provided between the diode rectifier (2; 2a) and the first capacitor (C3), and the polarity of the voltage (VL) of the first reactor (L3) is positive in the direction opposite to the direction of the current (I2) flowing through the first reactor (L3).

[0041] Alternatively, for example, the first reactor (L3) is located farther from the inverter (5) than the diode rectifier (2; 2a), and the polarity of the voltage (VL) of the first reactor (L3) is positive in the direction from a low potential to a high potential of the single-phase AC voltage (Vin).

[0042] Alternatively, for example, the charging circuit (4b) includes a second reactor (L4) connected in series with the second capacitor (C4) between the first power line (LH) and the second power line (LL) on the first power line (LH) side of the second capacitor, a diode (D40) connected between the second reactor (L4) and the second capacitor (C4) and having a forward direction from the second reactor (L4) to the second capacitor (C4), and a switch (Sl) for switching whether the reactor current (I4) flowing from the first power line to the second reactor (L4) is to flow to the second capacitor (C4) via the diode (D40) or to the second power line (LL). The rectified voltage (Vrf) is applied to the series connection of the switch (Sl) and the second reactor (L4).

[0043] Alternatively, for example, the rectifier circuit (203) further includes a second diode rectifier (2b) that performs full-wave rectification on the single-phase AC voltage (Vin) to obtain a second rectified voltage (|Vin|). The charging circuit (4b) includes a second reactor (L4) that is connected in series with the second capacitor (C4) on the output side of the second diode rectifier (2b), a diode (D40) that is located on the high potential side of the second capacitor (C4), that is connected between the second reactor (L4) and the second capacitor (C4), and that has a forward direction from the second reactor (L4) to the second capacitor (C4), and a switch (S1) that switches whether a reactor current (I4) that flows from the second diode rectifier (2b) to the second reactor (L4) flows to the second capacitor (C4) via the diode (D40) or to the second power line (LL).

[0044] Alternatively, for example, the charging circuit (4b) includes a second reactor (L4) connected in series with the second capacitor (C4) on the output side of the diode rectifier (2) without the first reactor (L3) in between, a diode (D40) located on the high potential side of the second capacitor (C4) and connected between the second reactor (L4) and the second capacitor (C4) and having a forward direction from the second reactor (L4) to the second capacitor (C4), and a switch (Sl) that switches whether a reactor current (I4) flowing from the rectifier circuit (203) to the second reactor (L4) is to be passed to the second capacitor (C4) via the diode (D40) or to the second power supply line (LL).

[0045] The direct power conversion circuit according to the present disclosure controls the charging period of the capacitor in the charge / discharge circuit, and contributes to realizing a continuous mode. [Brief description of the drawings]

[0046] [Figure 1] 1 is a circuit diagram illustrating a configuration of a direct power conversion circuit according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a block diagram illustrating a configuration of a control device. [Diagram 3] FIG. 2 is a block diagram illustrating an example of a block configuration. [Figure 4] 6 is a graph illustrating a schematic example of the operation of a charging operation control unit. [Diagram 5] 1 is a graph illustrating a relationship between an input current and a ripple factor; [Figure 6] 1 is a graph illustrating a relationship between an input current and a ripple factor; [Figure 7] 11 is a graph illustrating the relationship between the amplitude of the fluctuation component and the ripple rate. [Figure 8] 11 is a graph illustrating the change over time of a function, an input current, a switching period, an off period, an on period, and a duty. [Figure 9] 11 is a graph illustrating the change over time of a function, an input current, a switching period, an off period, an on period, and a duty. [Figure 10] 1 is a graph illustrating an example of an input current waveform when continuous mode control is adopted in a direct power conversion circuit. [Figure 11] 1 is a graph illustrating an example of an input current waveform when continuous mode control is adopted in a direct power conversion circuit. [Figure 12] 1 is a graph illustrating an example of the relationship between the order of a harmonic component having a fundamental frequency equal to the frequency of a single-phase AC voltage and a harmonic current. [Figure 13] 1 is a graph illustrating an example of the relationship between the order of a harmonic component having a fundamental frequency equal to the frequency of a single-phase AC voltage and a harmonic current. [Figure 14] 4 is a graph illustrating the relationship between the output power from an inverter and the average value of the output voltage from the inverter. [Figure 15] 1 is a graph illustrating the relationship between output power and switching frequency. [Figure 16] 1 is a graph illustrating the relationship between output power and efficiency of a direct power conversion circuit. [Figure 17] 1 is a circuit diagram illustrating a configuration of a direct power conversion circuit according to a first modification of the present disclosure. [Figure 18] 11 is a circuit diagram illustrating a configuration of a direct power conversion circuit according to a second modification of the present disclosure. FIG. [Figure 19] FIG. 13 is a circuit diagram illustrating a configuration of a direct power conversion circuit according to a third modification of the present disclosure. [Figure 20] FIG. 13 is a circuit diagram illustrating a configuration of a direct power conversion circuit according to a fourth modification of the present disclosure. [Figure 21] 13 is a graph showing waveforms of an input current, a current, and a reactor current for comparison with a variation of a variable term of the present disclosure. [Figure 22] 11 is a graph showing waveforms of an input current, a current, and a reactor current according to a modification of a variable term of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047] <Outline of configuration> 1 is a circuit diagram illustrating a configuration of a direct power conversion circuit 100 according to an embodiment of the present disclosure. The direct power conversion circuit 100 includes a diode rectifier 2, an LC filter 3, a charge / discharge circuit 4, and an inverter 5. DC power supply lines LH and LL function as a DC link 7 between the inverter 5 and the charge / discharge circuit 4. A potential lower than that of the DC power supply line LH is applied to the DC power supply line LL.

[0048] The combination of the diode rectifier 2 and the LC filter 3 can be understood as a rectifier circuit 203 having an input side to which the single-phase AC voltage Vin is applied, and an output side to which the DC power supply lines LH and LL are connected.

[0049] An AC current Iin (hereinafter referred to as "input current Iin") flows into the rectifier circuit 203 from the single-phase AC power supply 1. The rectifier circuit 203 performs full-wave rectification and low-pass filtering (hereinafter referred to as "low-pass filtering") on the single-phase AC voltage Vin, and outputs a rectified voltage Vrf. The diode rectifier 2 performs the full-wave rectification. The LC filter 3 performs the low-pass filtering. The LC filter 3, and thus the rectifier circuit 203, perform low-pass filtering on the current flowing to the charge / discharge circuit 4, and can be said to perform filtering that blocks high frequencies of the current flowing to the single-phase AC power supply 1.

[0050] The diode rectifier 2 includes diodes D21, D22, D23, and D24. The diodes D21, D22, D23, and D24 form a bridge circuit. The diode rectifier 2 in the direct power conversion circuit 100 has an input side to which a single-phase AC voltage Vin is applied from the single-phase AC power source 1, and an output side. In the direct power conversion circuit 100, the diode rectifier 2 performs single-phase full-wave rectification on the single-phase AC voltage Vin to obtain a voltage |Vin|, which is output from the output side of the diode rectifier 2 as a voltage Vr.

[0051] The LC filter 3 includes a reactor L3 and a capacitor C3. In the direct power conversion circuit 100, the capacitor C3 is provided directly between the DC power supply lines LH and LL. The capacitor C3 is, for example, a film capacitor. The reactor L3 cooperates with the capacitor C3 to perform the above-mentioned low-pass filtering.

[0052] The reactor L3 is connected in series to the DC power supply line LH or the DC power supply line LL (to the DC power supply line LH on the output side of the diode rectifier 2 in the direct power conversion circuit 100) at a distance from the inverter 5 relative to the capacitor C3.

[0053] In the direct power conversion circuit 100, the voltage Vr (here, Vr=|Vin|) output by the diode rectifier 2 is applied to the series connection of the reactor L3 and the capacitor C3, but depending on the configuration of the rectifier circuit 203, the voltage Vr may be applied to the capacitor C3 without passing through the reactor L3, or may be applied to the input side of the charge / discharge circuit 4 (in these cases, Vr=|Vin| is not necessarily satisfied). These modifications of the rectifier circuit 203 will be described later using the direct power conversion circuits 100A, 100B, 100C, and 100D.

[0054] The diode rectifier 2 outputs a DC current I2 (hereinafter also referred to as "output current I2"). In the direct power conversion circuit 100, the diode rectifier 2 is provided between the single-phase AC power source 1 and the LC filter 3, and the output current I2 coincides with the current flowing through the reactor L3.

[0055] The rectified voltage Vrf obtained by applying the above-mentioned low-pass filtering to the voltage |Vin| appears as the voltage between both ends of the capacitor C3 (hereinafter also referred to as the "voltage between both ends") V3. The polarity of the voltage between both ends V3 coincides with the polarity of the voltage Vr. The rectified voltage Vrf pulsates with the same period as the pulsation period of the voltage |Vin|.

[0056] The charge / discharge circuit 4 has a discharge circuit 4a, a charge circuit 4b, and a current blocking unit 4c. The discharge circuit 4a includes a capacitor C4 provided between the DC power supply lines LH and LL, and has a function of discharging the capacitor C4.

[0057] Specifically, the discharge circuit 4a further includes a switch Sc. The switch Sc and a capacitor C4 are connected in series between the DC power supply lines LH and LL. It can be said that the capacitor C4 is provided between the DC power supply lines LH and LL via the switch Sc. The switch Sc is provided closer to the DC power supply line LH than the capacitor C4.

[0058] When the switch Sc is turned on, the capacitor C4 is discharged to the DC link 7, more specifically, to the DC power supply lines LH and LL. The ratio of the time when the switch Sc is turned on is tentatively called the discharge duty dc. The discharge duty dc is controllable.

[0059] The switch Sc is realized, for example, by using a diode D42 and a transistor (for example, an insulated gate bipolar transistor) Qc connected in anti-parallel to the diode D42. Here, the anti-parallel connection refers to a parallel connection in which the forward directions are opposite to each other. Specifically, the forward direction of the transistor Qc is the direction from the DC power line LL to the DC power line LH, and the forward direction of the diode D42 is the direction from the DC power line LH to the DC power line LL.

[0060] In the following, the voltage across the capacitor C4 is referred to as the capacitor voltage Vc. Since the capacitor voltage Vc is higher than the voltage V3, no current flows through the diode D42. Therefore, the conduction / non-conduction of the switch Sc depends solely on that of the transistor Qc.

[0061] In the direct power conversion circuit 100, the charging circuit 4b boosts the rectified voltage Vrf appearing as a voltage V3 across the capacitor C4 to charge the capacitor C4. For example, the charging circuit 4b includes a diode D40, a reactor L4, and a switch Sl.

[0062] The diode D40 has a cathode and an anode, and the cathode is connected between the switch Sc and the capacitor C4. The reactor L4 is connected between the DC power supply line LH and the anode of the diode D40. The switch Sl is connected between the DC power supply line LL and the anode of the diode D40.

[0063] The switch Sl is realized, for example, by using a diode D41 and a transistor (for example, an insulated gate bipolar transistor) Ql connected in anti-parallel to the diode D41. Specifically, the forward direction of the transistor Ql is the direction from the DC power supply line LH to the DC power supply line LL, and the forward direction of the diode D41 is the direction from the DC power supply line LL to the DC power supply line LH.

[0064] Since the DC power supply line LH has a higher potential than the DC power supply line LL, basically no current flows through the diode D41. Therefore, the conduction / non-conduction of the switch Sl depends solely on that of the transistor Ql.

[0065] The reactor L4 is connected in series with the capacitor C4 on the output side of the rectifier circuit 203. The capacitor C4 is charged by the charging circuit 4b, and the capacitor voltage Vc is higher than the rectified voltage Vrf. It can be said that the diode D40 is located on the high potential side of the capacitor C4 and is connected between the reactor L4 and the capacitor C4. The direction from the reactor L4 to the capacitor C4 is the forward direction of the diode D40.

[0066] The reactor L4 is connected in series with the capacitor C4 via a diode D40 connected in series with the capacitor C4 on the output side of the rectifier circuit 203. The reactor L4 is connected in series with a switch Sl on the output side of the rectifier circuit 203. The switch Sl has a function of switching between flowing the reactor current I4 flowing through the reactor L4 to the capacitor C4 via the diode D40 by turning itself off, or to flow to the DC power supply line LL by turning itself on. Since the reactor current I4 flows from the DC power supply line LH to the DC power supply line LL, its polarity is not reversed and therefore it is a direct current.

[0067] In the following description, a current il flowing through the switch Sl is introduced. The period when the switch Sl is off corresponds to the charging period when the capacitor C4 is charged. The charging circuit 4b and the capacitor C4 form a well-known boost circuit. During the charging period of the capacitor C4, a charging current that decreases with time flows through the capacitor C4, and this charging current is represented by a current (I4-il). During the period when the switch Sl is on, no current flows between the capacitor C4 and the switch Sl due to the function of the diode D40, the capacitor C4 is not charged, and the reactor current I4 and the current il are equal to each other.

[0068] The capacitor voltage Vc is greater than the voltage V3 across the capacitors. The current blocking unit 4c is provided on the DC power supply line LH or the DC power supply line LL between the capacitors C3 and C4 to block the current flowing from the capacitor C4 to the capacitor C3. This prevents the capacitor voltage Vc from being affected by the voltage V3 across the capacitors.

[0069] The current blocking unit 4c is realized by, for example, a diode D43. In the example of FIG. 1, the diode D43 is provided in the DC power supply line LH, and its forward direction is the direction from the diode rectifier 2 to the inverter 5.

[0070] The inverter 5 converts a DC voltage Vdc generated between the DC power supply lines LH and LL on the inverter 5 side relative to the charge / discharge circuit 4 into an AC voltage. The AC voltage is applied to an inductive load 6. For example, the AC voltage is a three-phase AC voltage, and is output to output terminals Pu, Pv, and Pw.

[0071] The inverter 5 constitutes a so-called voltage-source inverter. The inverter 5 includes six switching elements Sup, Svp, Swp, Sun, Svn, and Swn. The switching elements Sup, Svp, and Swp are connected between the output terminals Pu, Pv, and Pw, respectively, and the DC power supply line LH, and the switching elements Sun, Svn, and Swn are connected between the output terminals Pu, Pv, and Pw, respectively, and the DC power supply line LL.

[0072] The inductive load 6 is, for example, a rotating machine. In the case where the inductive load 6 is a three-phase synchronous machine, the control system is exemplified. The speed detector 9 detects three-phase load currents iu, iv, and iw flowing through the inductive load 6, and provides the rotation angular velocity ωm, q-axis current Iq, and d-axis current Id obtained from the currents to the control device 10.

[0073] In addition to the rotational angular velocity ωm, q-axis current Iq, and d-axis current Id, the control device 10 receives as input the amplitude Vm of the single-phase AC voltage Vin, the angular velocity ω (or the phase θ=ωt, which is the product of this and time t), the command value ωm* of the rotational angular velocity, the capacitor voltage Vc and its command value Vc*, the command value Vdc* of the DC voltage Vdc, and the reactor voltage VL.

[0074] The reactor voltage VL is a tentative name for the voltage applied to the reactor L3. As described later, instead of or together with the reactor voltage VL, a voltage V3 across the reactor may be input to the control device 10. The reactor L3 is provided between the diode rectifier 2 and the capacitor C3. An output current I2 flows into the reactor L3 from the diode rectifier 2, and the polarity of the reactor voltage VL is defined as positive in the direction in which the output current I2 flows, more specifically, in the output current I2, the direction opposite to the direction of the component of the input current Iin supplied from the AC power source 1.

[0075] <Control device 10> A distribution ratio kb may be input to the control device 10. The distribution ratio kb is a ratio at which the power given to the inverter 5 is distributed between when it is supplied from the charge / discharge circuit 4 and when it is supplied from the rectifier circuit 203. The distribution ratio kb takes a value between 0 and 1. If the switch Sc is always off, kb=0. If the switch Sc is always on, kb=1. The distribution ratio kb is explained as the distribution ratio k in Patent Document 1, for example, and is publicly known.

[0076] 2 is a block diagram illustrating an example of the configuration of the control device 10. The control device 10 includes an inverter control unit 101, a discharge control unit 102, and a charge control unit 103.

[0077] The inverter control unit 101 outputs inverter control signals SSup, SSvp, SSwp, SSun, SSvn, and SSwn based on the discharge duty dc, the rectification duty drec, and the command values ​​Vu*, Vv*, and Vw* of the voltages output by the inverter 5. The inverter control signals SSup, SSvp, SSwp, SSun, SSvn, and SSwn control the operations of the switching elements Sup, Svp, Swp, Sun, Svn, and Swn, respectively.

[0078] The inverter control unit 101 includes an output voltage command generating unit 1011 , an amplitude modulation command unit 1012 , a product-sum calculation unit 1013 , a comparison unit 1014 , a logical calculation unit 1015 , and a speed control unit 1016 .

[0079] In addition to the command value ωm*, the speed control unit 1016 receives the rotational angular velocity ωm, q-axis current Iq, and d-axis current Id from the speed detection unit 9. The speed control unit 1016 calculates the modulation factor ks of the inverter 5 and the phase φ of the three-phase voltage output by the inverter 5, and outputs these to the output voltage command generation unit 1011. The output voltage command generation unit 1011 calculates the command values ​​Vu*, Vv*, and Vw* of the three-phase voltage using the phases θ and φ and the modulation factor ks. The output voltage command generation unit 1011 and the speed control unit 1016 are described as the output voltage command generation unit 37 and the speed control unit 30, respectively, in, for example, Japanese Patent No. 7206491 and are publicly known.

[0080] The amplitude modulation command unit 1012 controls the operation of the product-sum calculation unit 1013 based on the discharge duty dc and the rectification duty drec. The ratio between the period during which power is input from the rectification circuit 203 to the inverter 5 and the period during which power is input from the charge / discharge circuit 4 to the inverter 5 is equal to the ratio between the rectification duty drec and the discharge duty dc.

[0081] For example, in either a situation in which the switching elements Sup, Svp, and Swp of the inverter 5 are all on and the switching elements Sun, Svn, and Swn are all off, or a situation in which the switching elements Sup, Svp, and Swp of the inverter 5 are all off and the switching elements Sun, Svn, and Swn are all on, no power is input to the inverter 5 from either the rectifier circuit 203 or the charge / discharge circuit 4. If a period in this state is provisionally referred to as a zero period, the duty ratio corresponding to the zero period can be found by subtracting the sum of the rectification duty drec and the discharge duty dc from 1.

[0082] A product-sum calculation unit 1013 (for simplicity, shown by a symbol for only a multiplier) performs product-sum calculations on command values ​​Vu*, Vv*, Vw*, discharge duty dc, and rectification duty drec to generate a signal wave M. A comparison unit 1014 outputs a comparison result between the signal wave M and the value of a carrier CA to a logic calculation unit 1015. The logic calculation unit 1015 performs logic calculations on the comparison result, and outputs inverter control signals SSup, SSvp, SSwp, SSun, SSvn, and SSwn.

[0083] The technology for outputting inverter control signals SSup, SSvp, SSwp, SSun, SSvn, and SSwn using command values ​​Vu*, Vv*, Vw*, rectification duty drec, discharge duty dc, and carrier CA in this manner is itself publicly known, for example from Patent Document 1.

[0084] The discharge control unit 102 has a duty calculation unit 1021 and a comparator 1022. The duty calculation unit 1021 inputs the phase θ (=ωt), the amplitude Vm, the capacitor voltage Vc, and the command value Vdc*, and generates a discharge duty dc and a rectification duty drec. The comparator 1022 compares the discharge duty dc with the carrier CA, and generates a discharge switch signal SSc that turns on the switch Sc. The technology itself for generating the discharge duty dc, the rectification duty drec, and the discharge switch signal SSc in this way using the phase θ (=ωt), the amplitude Vm, the capacitor voltage Vc, and the carrier CA is publicly known, for example from Patent Document 1.

[0085] <Charging capacitor C4> The charging control unit 103 includes an amplitude determination unit 103 a , a charging command generation unit 103 b , a charging operation control unit 103 c , a resonance suppression unit 1035 , and an adder 1037 .

[0086] The amplitude determination unit 103a includes a subtractor 1031 and a proportional-integral controller 1032. The subtractor 1031 obtains the difference between the capacitor voltage Vc and the command value Vc*. The proportional-integral controller 1032 performs integral control or proportional-integral control on the difference to determine the amplitude Im. The operation of the amplitude determination unit 103a itself is also publicly known, for example from Patent Document 1.

[0087] The charging command generating unit 103b includes a charging waveform table 1033 and a multiplier 1034. The charging waveform table 1033 receives the distribution rate kb and the phase θ (=ωt) and outputs a function F(θ) (=F(ωt)) for the phase θ. The adder 1037 adds the function F(θ) and a fluctuation ΔF to output a function G(θ)=F(θ)+ΔF. It can be said that the function G(θ) takes a value obtained by adding the fluctuation ΔF to the function F(θ). The fluctuation ΔF will be described in detail later.

[0088] A multiplier 1034 multiplies the amplitude Im by a function G(θ) to determine an upper limit value il^ of the current il.

[0089] The function F(θ) determines the current il by setting an upper limit value il^ when the resonance of the LC filter 3 is not taken into consideration. The function F(θ) does not depend on either the reactor voltage VL or the voltage V3 across the reactor. For example, the value obtained by multiplying the function F(ωt) variously exemplified in Patent Document 1 by the absolute value |sinθ| of the sine value sinθ of the phase θ is adopted as the function F(θ) in this embodiment.

[0090] Patent Document 1 exemplifies a case in which the period during which switch Sl is on is determined and the reactor current I4 is controlled based on this period. In this embodiment, the reactor current I4 is controlled not by the period during which switch Sl is on but by the upper limit value il^. When switch Sl is on, the voltage Vr applied to reactor L4 is proportional to |sinθ|, so the period during which switch Sl is on introduced in Patent Document 1 is converted into a current il for consideration in this embodiment. From the viewpoint of this conversion, the absolute value |sinθ| times the function F(ωt) exemplified in Patent Document 1 can be adopted as the function F(θ) in this embodiment. Specifically, for example: The discharge duty dc is zero during the period when the cosine value cos(2θ) of 2θ, which is twice the phase θ, is negative or zero; During a period in which the cosine value cos(2θ) is positive, the discharge duty dc is taken as a value proportional to the cosine value cos(2θ), more specifically, as the product (Vdc* / Vc) cos(2θ) of the ratio (Vdc* / Vc) (hereinafter also referred to as the "first voltage ratio") of the command value Vdc* to the capacitor voltage Vc and the cosine value cos(2θ); The function F(θ) is the square of the sine value of the phase θ. 2 Half the reciprocal of θ(2·sin 2 θ) -1 The value obtained by subtracting [1-(2·sin 2 θ) -1 ] and the product of the absolute value |sinθ| [1-(2·sin 2 θ) -1 ]·|sinθ| is taken.

[0091] Or for example: Discharge duty dc is the square of the cosine value cos(θ) of the phase θ 2 A value proportional to θ, more specifically, the square of the first voltage ratio (Vdc* / Vc) and the cosine value cos(θ) 2 Multiply it by θ; The function F(θ) is calculated by multiplying the absolute value |sinθ| to [1+(1-kb)·cos(2θ)]·|sinθ| / 2, which is the product of the cosine value cos(2θ) of 2θ, which is twice the phase θ, and the coefficient (1-kb), (1-kb)·cos(2θ), plus 1 / 2, [1+(1-kb)·cos(2θ)] / 2. Here, the coefficient (1-kb) is the value obtained by subtracting the distribution rate kb from 1, and takes a value between 0 and 1.

[0092] Alternatively, the first voltage ratio can be increased by setting the function F(θ) as follows. Specifically, for example: The discharge duty dc is zero during the period when the cosine value cos(2θ) of 2θ, which is twice the phase θ, is negative or zero; During a period in which the cosine value cos(2θ) is positive, the discharge duty dc is proportional to the cosine value cos(2θ), more specifically, the product (Vm / Vc) cos(2θ) of the ratio (Vm / Vc) of the amplitude Vm to the capacitor voltage Vc (hereinafter also referred to as the "second voltage ratio") and the cosine value cos(2θ); The function F(θ) is the square of the sine value of the phase θ. 2 Half the reciprocal of θ(2·sin 2 θ) -1 The value obtained by subtracting [1-(2·sin 2 θ) -1 ], the product of the distribution rate kb, the coefficient π / √8, and the absolute value |sinθ| (kb π / √8) [1-(2 sin 2 θ) -1 ]·|sinθ| is taken.

[0093] For example, the function F(θ) can be set based on the values ​​disclosed in Japanese Patent No. 6418287, and the DC voltage Vdc can be increased to be higher than the amplitude Vm (hereinafter, also referred to as "boost control"). The discharge duty dc is set to a value (1-B) obtained by subtracting the value B described below from 1; The function F(θ) takes a value (|sinθ|-B·J) obtained by subtracting the product B·J of a value B and a value J (described later) from the absolute value |sinθ| of the sine value of the phase θ.

[0094] Value B is the ratio (Vdc*-Vc) / (Vrec-Vc) of the value (Vdc*-Vc) obtained by subtracting the capacitor voltage Vc from the command value Vdc* to the value (Vrec-Vc) obtained by subtracting the capacitor voltage Vc from the voltage Vrec obtained by full-wave rectifying the single-phase AC voltage Vin (which is calculated as the product Vm |sinθ| of the amplitude Vm and the absolute value |sinθ|).

[0095] The value J is the product of the cosine value cos(2θ) of twice the phase θ (2θ) and the coefficient (1-kb), i.e., (1-kb)·cos(2θ), subtracted from 1, i.e., half the value [1-(1-kb)·cos(2θ)] / 2, and the third voltage ratio (Vm / Vdc*).

[0096] The third voltage ratio (Vm / Vdc*) is the ratio of the amplitude Vm to the command value Vdc*.

[0097] <Fluctuation ΔF> The fluctuation amount ΔF is output from the resonance suppression unit 1035. The fluctuation amount ΔF functions as a correction term for the function F(θ).

[0098] For example, reactor voltage VL is input to resonance suppression unit 1035. Resonance suppression unit 1035 calculates a value proportional to reactor voltage VL (-kL·VL) and outputs this as fluctuation ΔF (kL>0). The technology itself for correcting reactor current I4 using such fluctuation ΔF and reducing the effect of resonance of LC filter 3 is publicly known, for example, from Japanese Patent No. 5920520.

[0099] For example, the voltage V3 across both ends is input to the resonance suppression unit 1035. The resonance suppression unit 1035 calculates a value kc·V3 proportional to the voltage V3 across both ends and outputs this as the fluctuation ΔF (kc>0). The technology itself for correcting the reactor current I4 using such fluctuation ΔF and reducing the effect of the resonance of the LC filter 3 is publicly known, for example, from Japanese Patent No. 6772577.

[0100] In this embodiment, the fluctuation ΔF is generated depending on either or both of the reactor voltage VL and the voltage V3 across the reactor. For example, by introducing coefficients kc0 and kL0, both of which are non-negative, the fluctuation ΔF is calculated as kc0·V3-kL0·VL (where kc0+kL0≠0, kL0=kL when kc0=0, and kc0=kc when kL0=0). The smaller the reactor voltage VL, the larger the fluctuation ΔF. The larger the voltage V3 across the reactor, the larger the fluctuation ΔF.

[0101] The charging operation control unit 103c controls the operation of the charging circuit 4b based on the current il and the upper limit value il^. More specifically, the charging operation control unit 103c generates a charging switch signal SSl that turns on the switch Sl until the current il reaches the upper limit value il^.

[0102] When the switch Sl is turned on, all of the reactor current I4 becomes current il and flows through the switch Sl. When the switch Sl is turned on, the current il rises, and when it reaches the upper limit value il^, the charging switch signal SSl turns off the switch Sl. When the switch Sl is turned off, all of the reactor current I4 is used to charge the capacitor C4. Therefore, the upper limit value il^ is the upper limit of the current il and also the upper limit of the reactor current I4.

[0103] In this embodiment, the charging operation control unit 103c functions as a mode modulation unit that causes the charging circuit 4b to flow the reactor current I4 in a mode including the continuous mode. Specifically, when the current il is positive, the charging switch signal SSl turns on the switch Sl, causing the reactor current I4 to flow in the continuous mode. Patent Document 1 exemplifies a case in which the charging circuit 4b operates in the critical mode.

[0104] Block Z includes an amplitude determination unit 103a, a multiplier 1034, and a charging operation control unit 103c. For example, block Z is realized using a so-called linear IC (linear integrated circuit).

[0105] 3 is a block diagram illustrating the configuration of block Z. The charging operation control unit 103c includes a comparator 1036, a timer 1039, and a flip-flop 1038, for example.

[0106] The flip-flop 1038 has a reset input terminal R, a set input terminal S, and an output terminal Q. After the potential at the set input terminal S rises, the potential at the output terminal Q is maintained at a value corresponding to a first logical value until the potential at the reset input terminal R rises. After the potential at the reset input terminal R rises, the potential at the output terminal Q is maintained at a value corresponding to a second logical value until the potential at the set input terminal S rises. The potential at the output terminal Q functions as a charge switch signal SSl. For example, the potential corresponding to the first logical value is a potential that turns on the transistor Ql, and the potential corresponding to the second logical value is a potential that turns off the transistor Ql.

[0107] The comparator 1036 outputs to the reset input terminal R a potential indicating that the value (il-il^) obtained by subtracting the upper limit value il^ from the current il is non-negative.

[0108] The timer 1039 is, for example, an up-counter that generates a count value that increases with the passage of time. The function G(θ)=F(θ)+ΔF is input to the timer 1039, and the timer 1039 functions as an up-counter that increases the count value to the function G(θ).

[0109] An output terminal Q is connected to the timer 1039. The count value of the timer 1039 is reset by the transition of the potential of the output terminal Q from a value corresponding to the second logical value to a value corresponding to the first logical value.

[0110] 4 is a graph showing a schematic example of the operation of the charging operation control unit 103c. In the graph, the horizontal axis indicates time, and shows a charging period CH during which the capacitor C4 is charged, and a start point ts and an end point te of the charging period CH.

[0111] In the graph shown in FIG. 4, the vertical axis indicates the count value K, the binary logic Xs, the binary logic Xr, the binary logic Xq, the charging switch signal SSl, the current il, (I4-il), and the upper limit value il^.

[0112] The binary logic Xs corresponds to the potential at the set input terminal S. A high state of the potential corresponds to the activation of the binary logic Xs, and a low state of the potential corresponds to the inactivation of the binary logic Xs. The binary logic Xr corresponds to the potential at the reset input terminal R. A high state of the potential corresponds to the activation of the binary logic Xr, and a low state of the potential corresponds to the inactivation of the binary logic Xr. The binary logic Xq corresponds to the potential at the output terminal Q. A high state of the potential corresponds to the activation of the binary logic Xq, and a low state of the potential corresponds to the inactivation of the binary logic Xq. For example, when the charging switch signal SSl takes a high potential, the switch Sl is turned on, and when the charging switch signal SSl takes a low potential, the switch Sl is turned off.

[0113] In this embodiment, the active state of each of the binary logics Xs, Xr, and Xq will be described as corresponding to a logical value "H" and an inactive state as corresponding to a logical value "L". The combinations of the active and inactive states of the binary logic Xs, the potential at the set input terminal S, and the logical values ​​"H" and "L" are not limited to the above examples. The combinations related to the binary logics Xr and Xq are consistent with the combinations related to the binary logic Xs. For example, if the switch Sl is turned off when the charging switch signal SSl has a high potential and the switch Sl is turned on when the charging switch signal SSl has a low potential, the potential of the output terminal Q when the binary logic Xq is active is lower than the potential of the output terminal Q when the binary logic Xq is inactive.

[0114] The count value K is reset when the binary logic Xq transitions from inactive to active. This point corresponds to the end point te. The count value K increases with time from the point when the binary logic Xq transitions from active to inactive. This point corresponds to the start point ts.

[0115] When the count value K reaches a predetermined value, the timer 1039 outputs a potential corresponding to a logical value "H" to the set input terminal S. This can also be considered as the timer 1093 activating the binary logic Xs.

[0116] As the binary logic Xs transitions from inactive to active, the binary logic Xq transitions from inactive to active, and the switch S1 is turned on by the charging switch signal SS1. As the switch S1 is turned on, the reactor current I4 stops flowing to the capacitor C4.

[0117] The binary logic Xq goes from inactive to active, resetting the timer 1039 and stopping the increase in the count value K. This causes the binary logic Xs to go inactive, and the activation of the binary logic Xs occurs in a pulse shape.

[0118] The time when the count value K reaches the predetermined value is the end point te. It can be said that the predetermined value determines the end point te. Considering that the count value K is reset at the end point te and then starts to increase at the start point ts, it can also be said that the predetermined value determines the charging period CH.

[0119] The predetermined value is determined by the function G(θ) and the rate of increase of the count value K. FIG. 4 shows an example in which the predetermined value is the function G(θ). In this case, for example, the increment of the count value K per unit time is 1. If the increment of the count value K per unit time is N, the predetermined value is set to N times the function G(θ), and the charging period CH is determined in the same manner as in the above example. From this, it can be said that the charging period CH is proportional to the function G(θ). Since the fluctuation amount ΔF is set as described above, it can be said that the smaller the reactor voltage VL and the larger the end-to-end voltage V3, the longer the charging period CH.

[0120] The function G(θ) is the sum of the function F(θ) for the phase θ and the fluctuation ΔF. The function F(θ) is a periodic function set as described above, and does not assume that the reactor current I4 is zero. By setting the end point te in this way, the reactor current I4 flows not only in the critical mode but also in the continuous mode.

[0121] The current input to the charging circuit 4b is the reactor current I4, and it can be said that the charging circuit 4b chops the reactor current I4 by switching using the switch S1 to charge the capacitor C4.

[0122] If the effect of the fluctuation ΔF is ignored, the average value of the reactor current I4 in the chopping period Tsw (which can also be said to be the switching period of the switch Sl) is divided by the maximum value of this average value (hereinafter tentatively referred to as the "normal value"), which corresponds to the function F(θ). The predetermined value for the point in time when the count value K is reset is also based on the function F(θ), and the smaller the normal value, the shorter the charging period CH. If the effect of the fluctuation ΔF is taken into consideration, the smaller the reactor voltage VL, the longer the charging period CH, and the larger the voltage V3 across both ends, the longer the charging period CH.

[0123] In the following description, the control that causes the reactor current I4 to flow in accordance with the critical mode is tentatively called "critical mode control," and the control that causes the reactor current I4 to flow in accordance with the continuous mode except near the boundary phase is tentatively called "continuous mode control." Here, "near the boundary phase" is a tentative name for the phase period that includes the phase θ where the function F(θ) is 0 and the phase θ in its vicinity. Near the boundary phase, the reactor current I4 can flow in discontinuous mode.

[0124] While the switch Sl is on, the current il rises at a rate derived from the inductance of the reactor L4. When the current il reaches the upper limit il^, the comparator 1036 outputs a potential corresponding to a logical value "H" to the reset input terminal R. This can also be considered as the comparator 1036 activating the binary logic Xr.

[0125] As the binary logic Xr transitions from inactive to active, the binary logic Xq transitions from active to inactive, and the switch Sl is turned off by the charging switch signal SSl. By turning off the switch Sl, the reactor current I4 flows to the capacitor C4, and the value of the current il becomes zero. This causes the binary logic Xr to become inactive, and the activation of the binary logic Xr occurs in a pulse shape.

[0126] The point in time when the current il reaches the upper limit value il^ is the start point ts. It can be said that the upper limit value il^ determines the start point ts.

[0127] The technology itself of setting a flip-flop by counting up a timer, resetting the timer by the setting, and resetting the flip-flop when a current equivalent to the current il reaches an upper limit value dependent on the phase is known, for example, from U.S. Patent No. 7,279,876, U.S. Patent No. 8,270,190, and the data sheet of STMicroelectronics' product L4984D (see https: / / www.st.com / resource / en / datasheet / l4984d.pdf). The latter two also disclose a technology in which the predetermined value that determines the count-up of the timer depends on the phase of the power supply voltage, but the resonance by the filter that performs low-pass filtering is not taken into account, nor is the amount equivalent to the fluctuation ΔF taken into account.

[0128] In this embodiment, the predetermined value for the count value K is set as described above using the function G(θ). The upper limit value il^ also depends on the fluctuation ΔF, like the predetermined value. In accordance with the above explanation, the smaller the reactor voltage VL and the larger the voltage V3, the larger the predetermined value and the upper limit value il^, and both the start point ts and the end point te become later. In terms of this delay in terms of the phase θ, it can be said that the smaller the reactor voltage VL and the larger the voltage V3, the more the start point ts and the end point te are shifted toward the lagging phase side with respect to the phase θ. The charging period CH is, for example, a period during which the count value K rises from 0 to a value proportional to the function G(θ), and the charging period CH has a length that is set independent of the amplitude Im and dependent on the phase θ.

[0129] In this embodiment, the start point ts and the end point te of the charging period CH are determined in this manner. There is a period during which the reactor current I4 flows in the continuous mode.

[0130] When the function G(θ) exemplified above is employed, it is not a prerequisite that the input current Iin is a sine wave. For example, in Patent Document 1, a description is given taking into consideration a power factor of 1. However, Patent Document 1 exemplifies control in a critical mode, and when continuous mode control is performed as in this embodiment, it is assumed that the reactor current I4 flows in a discontinuous mode near the boundary phase, and therefore it is also assumed that the input current Iin is distorted from a sine wave.

[0131] <Reduction of harmonics> The effect of reflecting the fluctuation ΔF not only at the start point ts but also at the end point te will be described below with reference to Figs. 5, 6, and 7. For ease of explanation, the operation of the charge / discharge circuit 4 in a state where the switch Sc is on will be illustrated. The capacitor voltage Vc is higher than the voltage V3 across the two terminals, and the reactor L4 and the capacitor C4 are not directly connected due to the function of the current blocking unit 4c, so that the charge / discharge circuit 4 can be considered to function as a known power factor improvement circuit. In addition, in order to simplify the effect of the fluctuation ΔF, |sinθ| is adopted as the function F(θ) for convenience, and the absolute value of a sine wave (9th harmonic) having a frequency (9th component) 9 times the frequency of the input current Iin is adopted as the fluctuation ΔF.

[0132] In this way, when a value that is independent of the reactor voltage VL and the capacitor voltage Vc is hypothetically adopted as the fluctuation ΔF, the fluctuation ΔF can be regarded as a disturbance to the function F(θ) that is adopted to determine the current il when the effect of the resonance of the LC filter 3 is not taken into consideration.

[0133] Fig. 5 is a graph illustrating the relationship between the input current Iin and the ripple factor when the fluctuation ΔF is 0.125×|sin(9θ)|. Fig. 6 is a graph illustrating the relationship between the input current Iin and the ripple factor when the fluctuation ΔF is 0.25×|sin(9θ)|. In both Fig. 5 and Fig. 6, the horizontal axis shows the effective value of the input current Iin, which corresponds to 1 / √2 times the amplitude Im. In both Fig. 5 and Fig. 6, the vertical axis shows the ripple factor, which is the percentage of the ninth harmonic in the input current Iin.

[0134] The broken line J11 in Fig. 5 and the broken line J21 in Fig. 6 both show the above relationship in the case where the fluctuation ΔF is reflected only in the setting of the start point ts and the fluctuation ΔF is not reflected in the setting of the end point te. In terms of Fig. 3, this case corresponds to the case where the function F(θ) is input to the timer 1039 instead of the function G(θ).

[0135] The broken line J12 in Fig. 5 and the broken line J22 in Fig. 6 each show the above relationship when the fluctuation ΔF is reflected not only in the setting of the start point ts but also in the setting of the end point te. In terms of Fig. 3, this case corresponds to the case where the function G(θ) is input to the timer 1039 as shown in the figure.

[0136] The ripple rate of the broken line J12 is lower than that of the broken line J11, and the ripple rate of the broken line J22 is lower than that of the broken line J21.

[0137] 7 is a graph illustrating the relationship between the amplitude of the fluctuation ΔF and the above-mentioned ripple rate when the above-mentioned effective value is 16 [Arms]. The broken line J31 shows the above-mentioned relationship when the fluctuation ΔF is reflected only in the setting of the start point ts, and the fluctuation ΔF is not reflected in the setting of the end point te. The broken line J32 shows the above-mentioned relationship when the fluctuation ΔF is reflected not only in the setting of the start point ts but also in the setting of the end point te.

[0138] The plot on the broken line J31 when the amplitude of the fluctuation component ΔF is 0.125 corresponds to the plot on the broken line J11 shown in Fig. 5 when the input current Iin is 16 [Arms]. The plot on the broken line J31 when the amplitude of the fluctuation component ΔF is 0.25 corresponds to the plot on the broken line J21 shown in Fig. 6 when the input current Iin is 16 [Arms].

[0139] The plot on the broken line J32 when the amplitude of the fluctuation component ΔF is 0.125 corresponds to the plot on the broken line J12 shown in Fig. 5 when the input current Iin is 16 [Arms]. The plot on the broken line J32 when the amplitude of the fluctuation component ΔF is 0.25 corresponds to the plot on the broken line J22 shown in Fig. 6 when the input current Iin is 16 [Arms].

[0140] In Fig. 7, the case where the percentage of the amplitude of the fluctuation component ΔF with respect to the amplitude Im is equal to the percentage value of the ripple rate is added with a dashed line. The broken line J32 is below the dashed line, and the average rate of change of the ripple rate with respect to the amplitude of the fluctuation component ΔF (which appears as the slope of the straight line when the broken line J32 is approximated by a straight line in Fig. 7) is about 0.85. The fact that this value 0.85 is smaller than 1 indicates a decrease in the gain for the fluctuation component ΔF. This decrease is due to the sudden change in the fluctuation component ΔF near the boundary phase.

[0141] In the vicinity of the boundary phase, the reactor current I4 is small, and there is a region where the upper limit value il^ is negative in calculation. In that region, the reactor current I4 does not actually flow, and a period occurs in which the reactor current I4 flows in discontinuous mode in the vicinity of the boundary phase, resulting in a decrease in the gain. However, this decrease can be reduced by correcting the coefficients kc and kL in the resonance suppression unit 1035.

[0142] 8 and 9 are graphs illustrating changes over time in the function G(θ), the input current Iin, the period Tsw, the off period Toff, the on period Ton, and the duty ratios Don, Doff.

[0143] The function G(θ) used is the sum of the function F(θ) and the fluctuation ΔF = 0.125 × |sin(9θ)|. The input current Iin contains a ninth harmonic component. The period Tsw is the sum of the off period Toff and the on period Ton. The off period Toff is the period during which the switch Sl is continuously off. The off period Toff corresponds to the charging period CH. The on period Ton is the period during which the switch Sl is continuously on. The reactor current I4 increases during the on period Ton. The duty ratio Don is the ratio of the on period Ton to the period Tsw. The duty ratio Doff is the ratio of the off period Toff to the period Tsw.

[0144] Fig. 8 shows a case where the fluctuation ΔF is reflected only in the setting of the start point ts, and the fluctuation ΔF is not reflected in the setting of the end point te. In terms of Fig. 3, this case corresponds to a case where the function F(θ) is input to the timer 1039 instead of the function G(θ). Therefore, the off time Toff is not affected by the fluctuation ΔF, and is controlled to be constant with respect to the phase θ by the function F(θ).

[0145] The time constant of the proportional-integral controller 1032 is extremely large compared to the period Tsw. Therefore, the on-time Ton is controlled in response to the fluctuation ΔF input to the multiplier 1034 in such a way that it instantaneously corresponds to the upper limit value (il^).

[0146] FIG. 9 shows a case where the fluctuation ΔF is reflected not only in the setting of the start point ts but also in the setting of the end point te. In this case, in terms of FIG. 3, it corresponds to the case where the function G(θ) is input to both the multiplier 1034 and the timer 1039 as shown in the figure. The response corresponding to the fluctuation ΔF input to the multiplier 1034 is the same as that described in FIG. 8. However, the off-time Toff is affected by the fluctuation ΔF and pulsates in proportion to the fluctuation ΔF in addition to the constant value according to the function F(θ). On the other hand, due to the relationship between the single-phase AC voltage Vin and the capacitor voltage Vc, the duty ratios Don and Doff are controlled to be constant with respect to the phase regardless of the fluctuation ΔF. Therefore, the on-time Ton responds quickly to the pulsation of the off-time Toff, and the cycle Tsw fluctuates so as to absorb the pulsation.

[0147] From Figures 8 and 9, it can be seen that the effect of the fluctuation ΔF on the waveform of the input current Iin is the same whether or not the fluctuation ΔF is reflected in the setting of the end point te, as a result of the multiplier 1034 and the charging operation control unit 103c operating using the function G(θ), and that the effect of the resonance of the LC filter 3 is reduced by the command of the resonance suppression unit 1035.

[0148] When the continuous mode control is performed, the input current Iin is distorted from a sine wave as assumed above. The distortion is particularly large near the boundary phase. Compared to when the fluctuation ΔF is reflected only in the setting of the start point ts and not reflected in the setting of the end point te (see FIG. 8), when the fluctuation ΔF is reflected in the settings of both the start point ts and the end point te (see FIG. 9), the switching frequency fsw (the inverse of the period Tsw illustrated in FIG. 8 and FIG. 9) drops near the boundary phase (at the time Time of 0.19 s and its vicinity in FIG. 8 and FIG. 9), and the discontinuous mode has a large effect of distorting the input current Iin. When the fluctuation ΔF is not reflected in the setting of the end point te, the control of the end point te is not delayed, and compared to when the fluctuation ΔF is reflected in the setting of the end point te, the fluctuation of the switching frequency fsw is small and the effect of the discontinuous mode of distorting the input current Iin is also small.

[0149] 10 and 11 are graphs illustrating the waveform of the input current Iin when continuous mode control is adopted in the direct power conversion circuit 100. Fig. 10 illustrates the case where kL=0, and Fig. 11 illustrates the case where kL=0.015. The case illustrated in Fig. 10 and the case illustrated in Fig. 11 have the same conditions except for the coefficient kL. For example, the voltage value (effective value) of the single-phase AC voltage Vin is 200V, its period is 0.02 seconds (=1 / 50Hz), the power input to the direct power conversion circuit 100 is 4kW, the frequency of the carrier CA is 5.9kHz, and the cutoff frequency of the LC filter 3 is 1.75kHz.

[0150] Comparing FIG. 10 with FIG. 11, it can be seen that even when continuous mode control is adopted, the harmonics of the input current Iin are suppressed.

[0151] Fig. 12 and Fig. 13 are graphs illustrating the relationship between the order of the harmonic component of the single-phase AC voltage Vin, which is the fundamental frequency, and the harmonic current (more specifically, the effective value of the amplitude [Arms]). Both Fig. 12 and Fig. 13 illustrate the case where continuous mode control is adopted in the direct power conversion circuit 100. Fig. 13 shows an enlarged view of the region of the graph shown in Fig. 12 where the harmonic current is small.

[0152] 12 and 13, the broken line G10 indicates the limit value of the JIS C61000-3-2 standard (300 V, 20 A / phase or less), the broken line G11 indicates the harmonic components of the input current Iin illustrated in FIG. 10, and the broken line G12 indicates the harmonic components of the input current Iin illustrated in FIG. 11.

[0153] In FIG. 12, the broken lines G11 and G12 look almost the same, and both look to show values ​​lower than the broken line G10. The distortion of the input current Iin when the switch Sc is on, as explained with reference to FIG. 8 and FIG. 9, is also small. By enlarging the display in FIG. 13, it can be seen that the broken line G12 is smaller than the broken line G11 in the 30th order and above. It can be seen that the broken line G12 is largely separated from the broken line G11, especially in the 35th order. From this, it can be seen that when kL=0, that is, when G(θ)=F(θ) is substantially satisfied, the magnitude of the harmonic components of the input current Iin does not satisfy the JISC61000-3-2 standard. On the other hand, by considering the fluctuation ΔF with kL=0.015, the broken line G12 shows a smaller value than the broken line G10, and the JISC61000-3-2 standard is satisfied.

[0154] <Improved efficiency> Fig. 14 is a graph illustrating the relationship between the output power Pmot [W] from the inverter 5 and the average value of the output voltage Vmot [V] from the inverter 5. Fig. 15 is a graph illustrating the relationship between the output power Pmot [W] and the switching frequency fsw of the switch Sl (which can also be said to be the reciprocal of the chopping period Tsw in the charge / discharge circuit 4). Fig. 16 is a graph illustrating the relationship between the output power Pmot [W] and the efficiency of the direct power conversion circuit 100.

[0155] For the sake of simplicity, the case where the switch Sc is kept on is exemplified, in which the charge / discharge circuit 4 functions as a known power factor correction circuit.

[0156] In any of Figures 14 to 16, the white circles and the dashed lines connecting the white circles indicate the above relationship when the critical mode control is adopted. In any of Figures 14 to 16, the black circles and the solid lines connecting the black circles indicate the above relationship when the control in which the start point ts and the end point te of the charging period CH are determined as described above (this corresponds to the above-mentioned "continuous mode control") is adopted.

[0157] The results shown in Figures 14 to 16 are the results when the command value Vdc*, modulation factor ks, and carrier CA frequency in the critical mode control are set equal to the command value Vdc*, modulation factor ks, and carrier CA frequency in the continuous mode control, respectively. The loss of the inverter 5 in the critical mode control is equal to the loss of the inverter 5 in the continuous mode control. In Figures 14 to 16, the effect of the loss of the inverter 5 is eliminated. Here, a static load in which a series-connected circuit of a reactor and a resistor is connected in a three-phase Y-connection is used as the inductive load 6.

[0158] In FIG. 14, no difference between the above relationship in the critical mode control and the above relationship in the continuous mode control is observed.

[0159] In Fig. 15, in the continuous mode control, both the start point ts and the end point te are determined according to the function G(θ), so the switching frequency fsw does not depend on the output power Pmot. In Fig. 15, the value of the switching frequency fsw is about 70 kHz regardless of the output power Pmot. In order to increase the output power Pmot, it is necessary to increase the peak value of the current il, and in the critical mode control, the current il transitions between the peak value and zero, so it is necessary to lengthen the on time and off time of the switch Sl. In the critical mode control, there is an approximately inversely proportional relationship between the switching frequency fsw and the output power Pmot.

[0160] In FIG. 15, when the output power Pmot is about 1150 W or less, the continuous mode control has a lower switching frequency fsw than the critical mode control, and when the output power Pmot is about 1150 W or more, the continuous mode control has a higher switching frequency fsw than the critical mode control.

[0161] In Fig. 16, when the output power Pmot is approximately 1150 [W] or less, the continuous mode control is more efficient than the critical mode control, and when the output power Pmot is approximately 1150 W or less, the continuous mode control is less efficient than the critical mode control. This difference comes from the magnitude relationship between the switching frequency fsw in the critical mode control and the switching frequency fsw in the continuous mode control. In the critical mode, the higher the switching frequency fsw, the larger the iron loss in the reactor L4 and the switching loss in the switch Sl, and the lower the efficiency.

[0162] For example, when the inductive load 6 is an electric motor and the direct power conversion circuit 100 operates it at partial load, the adoption of continuous mode control provides a wider operating region with high efficiency than the adoption of critical mode control.

[0163] <First Modification of Rectifier Circuit 203> 17 is a circuit diagram illustrating a configuration of a direct power conversion circuit 100A according to a first modification of the present disclosure. The configuration of the direct power conversion circuit 100A is different from the configuration of the direct power conversion circuit 100 in the configuration of the rectifier circuit 203, but the other configurations are the same. Like the direct power conversion circuit 100, the direct power conversion circuit 100A also includes a charge / discharge circuit 4 and an inverter 5, and is controlled by the control device 10 in the same manner as the direct power conversion circuit 100.

[0164] In the direct power conversion circuit 100A, the LC filter 3 included in the rectifier circuit 203 is arranged separately on the input side and the output side of the diode rectifier 2. Specifically, the reactor L3 of the LC filter 3 is provided between the single-phase AC power supply 1 and the input side of the diode rectifier 2, and the capacitor C3 is connected to the output side of the diode rectifier 2. It can also be said that the reactor L3 is farther from the inverter 5 than the diode rectifier 2. The configuration of such a rectifier circuit 203 itself is publicly known, for example, in Japanese Patent No. 5920520.

[0165] In the rectifier circuit 203 having such a configuration, the polarity of the reactor voltage VL is positive in the direction from the low potential to the high potential of the single-phase AC voltage Vin. The fact that the value -kL·VL can be handled in the same manner as the direct power conversion circuit 100 by setting the polarity of the reactor voltage VL in this way is publicly known, for example in Japanese Patent No. 5920520, together with a technique for setting the polarity.

[0166] When the input current Iin flows through the reactor L3 and the diodes D21 and D24, the direction of the single-phase AC voltage Vin from low potential to high potential coincides with the direction of the arrow shown next to the single-phase AC voltage Vin in Fig. 17. The direction of the current flowing through the reactor L3 coincides with the direction of the arrow shown next to the input current Iin in Fig. 17. The potential of the reactor L3 on the single-phase AC power supply 1 side is higher than the potential of the reactor L3 on the opposite side to the single-phase AC power supply 1.

[0167] When the input current Iin flows through the reactor L3 and the diodes D22 and D23, the direction of the single-phase AC voltage Vin from low potential to high potential is opposite to the direction of the arrow shown next to the single-phase AC voltage Vin in Fig. 17. The direction of the current flowing through the reactor L3 is opposite to the direction of the arrow shown next to the input current Iin in Fig. 17. The potential of the reactor L3 on the single-phase AC power supply 1 side is lower than the potential of the reactor L3 on the opposite side to the single-phase AC power supply 1.

[0168] Therefore, the polarity of the reactor voltage VL is positive in the direction from the low potential to the high potential of the single-phase AC voltage Vin.

[0169] Whether the input current Iin flows between the diode rectifier 2 and the reactor L3 and passes through the diodes D21 and D24, or whether the input current Iin flows through the diodes D22 and D23, the polarity of the reactor voltage VL is positive in the direction opposite to the direction in which the input current Iin flows.

[0170] Also in the direct power conversion circuit 100, the polarity of the reactor voltage VL is positive in the direction opposite to the direction of the output current I2 flowing between the diode rectifier 2 and the reactor L3, more specifically, the component of the input current Iin of the output current I2 supplied from the AC power source 1. Therefore, in both of the direct power conversion circuits 100 and 100A, the polarity of the reactor voltage VL is positive in the direction opposite to the direction of the current flowing between the reactor L3 and the diode rectifier 2, more specifically, the component of the input current Iin supplied from the AC power source 1.

[0171] In both the direct power conversion circuits 100 and 100A, the capacitor C3 is directly connected between the DC power supply lines LL and LH. In the direct power conversion circuit 100, Vr=|Vin| and V3=Vrf. In the direct power conversion circuit 100A, Vr=V3=Vrf. Considering that the rectified voltage Vrf is obtained by low-pass filtering the full-wave rectified single-phase AC voltage |Vin|, it can be said that the polarity of the voltage V3 across both ends coincides with the polarity of the voltage on the output side of the diode rectifier 2 (this can also be said to be the side to which the capacitor C3 of the diode rectifier 2 is connected) in both the direct power conversion circuits 100 and 100A. More specifically, it can be said that the polarity of the voltage V3 across both ends is positive in the direction from the DC power supply line LL to the DC power supply line LH.

[0172] <Second Modification of Rectifier Circuit 203> FIG. 18 is a circuit diagram illustrating a configuration of a direct power conversion circuit 100B according to a second modification of the present disclosure. The configuration of the direct power conversion circuit 100B is the same as that of the direct power conversion circuit 100, except for the configuration of the rectifier circuit 203. Like the direct power conversion circuit 100, the direct power conversion circuit 100B also includes a charge / discharge circuit 4 and an inverter 5, and is controlled by the control device 10 in the same manner as the direct power conversion circuit 100. However, for reasons described later, the current blocking unit 4c is not necessary in the charge / discharge circuit 4. FIG. 18 illustrates a case where the current blocking unit 4c is removed from the short circuit, specifically, a case where the reactor L4 and the switch Sc are directly connected on the opposite side to the diode D40.

[0173] In the direct power conversion circuit 100B, the LC filter 3 included in the rectifier circuit 203 is disposed on the input side of the diode rectifier 2. Specifically, the reactor L3 of the LC filter 3 is provided between the single-phase AC power supply 1 and the input side of the diode rectifier 2, and the capacitor C3 is connected to the input side of the diode rectifier 2. It can also be said that the reactor L3 and the capacitor C3 are farther from the inverter 5 than the diode rectifier 2. The configuration of such a rectifier circuit 203 itself is publicly known, for example, in Japanese Patent No. 5920520.

[0174] In the rectifier circuit 203 having such a configuration, similarly to the rectifier circuit 203 used in the direct power conversion circuit 100A, the polarity of the reactor voltage VL is positive in the direction from low potential to high potential of the single-phase AC voltage Vin, and the polarity is positive in the opposite direction to the direction in which the input current Iin flows. Therefore, in any of the direct power conversion circuits 100, 100A, and 100B, it can be said that the polarity of the reactor voltage VL is positive in the opposite direction to the direction in which the current flowing between the reactor L3 and the diode rectifier 2, more specifically, the component of the input current Iin supplied from the AC power source 1 flows.

[0175] In the direct power conversion circuit 100B, since the diode rectifier 2 is interposed between the capacitor C3 and the capacitor C4, the function of the current blocking unit 4c is performed by the diode rectifier 2, and the current blocking unit 4c is not necessary.

[0176] Capacitor C3 is connected between the connection point between the anode of diode D21 and the cathode of diode D22 (hereinafter tentatively referred to as the "first connection point") and the connection point between the anode of diode D23 and the cathode of diode D24 (hereinafter tentatively referred to as the "second connection point").

[0177] When the input current Iin flows through the diodes D21 and D24, the direction of the single-phase AC voltage Vin from low potential to high potential coincides with the direction of the arrow shown next to the single-phase AC voltage Vin in Fig. 18. At this time, the potential of the first connection point is higher than the potential of the second connection point, and the positive direction of the voltage V3 across both ends coincides with the direction of the arrow shown next to the voltage V3 across both ends in Fig. 18.

[0178] When the input current Iin flows through the diodes D22 and D23, the direction of the single-phase AC voltage Vin from low potential to high potential is opposite to the direction of the arrow shown next to the single-phase AC voltage Vin in Fig. 18. At this time, the potential of the first connection point is lower than the potential of the second connection point, and the positive direction of the voltage V3 across both ends is opposite to the direction of the arrow shown next to the voltage V3 across both ends in Fig. 18.

[0179] It can be said that the polarity of the voltage V3 across both ends is positive in the direction from the low potential to the high potential of the single-phase AC voltage Vin.

[0180] In the direct power conversion circuit 100B, the first connection point and the second connection point are the sides to which the capacitor C3 of the diode rectifier 2 is connected, and the polarity of the voltage there matches the polarity of the voltage V3 across both ends. In the direct power conversion circuit 100, the capacitor C3 is provided to the diode rectifier 2 via the reactor L3 on the side where the diode rectifier 2 outputs the voltage Vr=|Vin|. The polarity of the voltage Vr matches the polarity of the rectified voltage Vrf.

[0181] Therefore, it can be said that the polarity of the end-to-end voltage V3 coincides with the polarity of the voltage on the output side or the input side of the diode rectifier 2 to which the capacitor C3 is connected in any of the direct power conversion circuits 100, 100A, and 100B.

[0182] <Third Modification of Rectifier Circuit 203> FIG. 19 is a circuit diagram illustrating a configuration of a direct power conversion circuit 100C according to a third modification of the present disclosure. The configuration of the direct power conversion circuit 100C is the same as that of the direct power conversion circuit 100, except for the configuration of the rectifier circuit 203. Like the direct power conversion circuit 100, the direct power conversion circuit 100C also includes a charge / discharge circuit 4 and an inverter 5, and is controlled by the control device 10 in the same manner as the direct power conversion circuit 100. However, for reasons described later, the current blocking unit 4c is not necessary in the charge / discharge circuit 4. FIG. 19 illustrates a case where the current blocking unit 4c is removed and opened, specifically, a case where the reactor L4 and the switch Sc are separated on the opposite side to the diode D40.

[0183] In the direct power conversion circuit 100C, the rectifier circuit 203 includes a diode rectifier 2 that includes a pair of diode rectifiers 2a and 2b.

[0184] The diode rectifier 2 a is provided between the LC filter 3 and the single-phase AC power supply 1, similar to the diode rectifier 2 provided in the direct power conversion circuit 100.

[0185] For example, the diode rectifier 2a includes diodes D21a, D22a, D23a, and D24a. The diodes D21a, D22a, D23a, and D24a form a bridge circuit. The diode rectifier 2a has an input side to which a single-phase AC voltage Vin is applied from the single-phase AC power supply 1, and an output side. The diode rectifier 2a performs single-phase full-wave rectification on the single-phase AC voltage Vin to obtain a voltage |Vin|, which is then output from the output side as a voltage Vr.

[0186] The reactor L3 is provided between the diode rectifier 2a and the capacitor C3. An output current I2 flows from the diode rectifier 2a to the LC filter 3, and the current flowing through the reactor L3 is equal to the output current I2. In the direct power conversion circuit 100C, the capacitor C3 is connected directly between the DC power supply lines LH and LL.

[0187] The diode rectifier 2b is connected to the charge / discharge circuit 4 via the DC power supply lines LHs and LL without via the reactor L3, similar to the diode rectifier 2 included in the direct power conversion circuits 100A and 100B.

[0188] For example, the diode rectifier 2b includes diodes D21b, D22b, D23b, and D24b. The diodes D21b, D22b, D23b, and D24b form a bridge circuit. The diode rectifier 2b has an input side to which a single-phase AC voltage Vin is applied from the single-phase AC power supply 1, and an output side. The diode rectifier 2b performs single-phase full-wave rectification on the single-phase AC voltage Vin to obtain a voltage |Vin|, which is output from the output side as a voltage Vr. The potential of the DC power supply line LL is lower than the potential of the DC power supply line LHs.

[0189] The voltage Vr output by the diode rectifier 2b is applied to the charge / discharge circuit 4, specifically, to the direct connection between the switch Sl and the reactor L4. The current output by the diode rectifier 2b is equal to the reactor current I4. When the switch Sl is on, the reactor current I4 flows from the DC power supply line LHs to the DC power supply line LL via the reactor L4 and the switch Sl. When the switch Sl is off, the reactor current I4 flows to the capacitor C4 via the diode D40, charging the capacitor C4.

[0190] In the charge / discharge circuit 4, the high potential side of the reactor L4 is connected to the high potential side of the output side of the diode rectifier 2b via the DC power supply line LHs, and the high potential side of the switch Sc is connected to the high potential side of the output side of the diode rectifier 2b via the DC power supply line LH and the reactor L3. In the charge / discharge circuit 4, the current blocking unit 4c is removed and opened, and the current flowing from the diode rectifier 2b to the charge / discharge circuit 4 flows independently of the output current I2 flowing from the diode rectifier 2a to the LC filter 3. The configuration of such a rectifier circuit 203 itself and the fact that the direct power conversion circuit 100C can be controlled in the same manner as the direct power conversion circuit 100 are publicly known, for example, in Japanese Patent No. 5381970.

[0191] In the direct power conversion circuit 100C, as in the direct power conversion circuit 100, the polarity of the reactor voltage VL is set to be positive in the direction opposite to the component of the output current I2 flowing between the diode rectifier 2a and the reactor L3, more specifically, of the output current I2 supplied from the AC power supply 1.

[0192] In the direct power conversion circuit 100C, as in the direct power conversion circuit 100, the capacitor C3 is directly connected between the DC power supply lines LL and LH. In both the direct power conversion circuits 100 and 100C, Vr=|Vin| and V3=Vrf. It can be said that the polarity of the voltage V3 across both ends coincides with the polarity of the voltage on the output side of the diode rectifier 2 (this can also be said to be the side of the diode rectifier 2 to which the capacitor C3 is connected) in the direct power conversion circuit 100, and coincides with the polarity of the voltage on the output side of the diode rectifier 2a (this can also be said to be the side of the diode rectifier 2a to which the capacitor C3 is connected) in the direct power conversion circuit 100C. It can be said that the polarity of the voltage V3 across both ends is positive in the direction from the DC power supply line LL to the DC power supply line LH.

[0193] <Fourth Modification of Rectifier Circuit 203> 20 is a circuit diagram illustrating a configuration of a direct power conversion circuit 100D according to a fourth modification of the present disclosure. The configuration of the direct power conversion circuit 100D is the same as the configuration of the direct power conversion circuit 100C except for the configuration of the rectifier circuit 203.

[0194] Specifically, the rectifier circuit 203 in the direct power conversion circuit 100D differs from the rectifier circuit 203 in the direct power conversion circuit 100C in that the arrangement order of the diode rectifier 2a and the LC filter 3 between the single-phase AC power supply 1 and the DC power supply lines LH, LL is switched. Due to this difference, the diode rectifier 2a in the direct power conversion circuit 100D outputs a rectified voltage Vrf, not a voltage |Vin|, like the diode rectifier 2 in the direct power conversion circuit 100B.

[0195] The capacitor C3 is located farther from the inverter 5 than the diode rectifier 2a, and the reactor L3 is located farther from the inverter 5 than the diode rectifier 2a.

[0196] Just as the direct power conversion circuit 100B can be controlled similarly to the direct power conversion circuit 100, the direct power conversion circuit 100D can be controlled similarly to the direct power conversion circuit 100C.

[0197] In the direct power conversion circuit 100D, similarly to the direct power conversion circuit 100B, the polarity of the reactor voltage VL is positive in the direction from a low potential to a high potential of the single-phase AC voltage Vin, and the positive direction is the opposite direction to the direction of the current flowing between the reactor L3 and the diode rectifier 2a, more specifically, the component of the current supplied from the AC power source 1.

[0198] In the direct power conversion circuit 100D, similarly to the direct power conversion circuit 100B, the polarity of the voltage V3 across both ends is positive in the direction from the low potential to the high potential of the single-phase AC voltage Vin. The polarity of the voltage V3 across both ends can also be said to match the polarity of the voltage on the input side of the diode rectifier 2a (which can also be said to be the side to which the capacitor C3 of the diode rectifier 2a is connected).

[0199] <Deformation of fluctuation ΔF> In the direct power conversion circuits 100C and 100D, the LC filter 3 and the charge / discharge circuit 4 are connected in parallel between the AC power source 1 and the DC link 7. In this connection, the current flowing to the charge / discharge circuit 4, specifically the reactor current I4, is corrected based on the fluctuation ΔF, so that at least a part of the current generated by the resonance occurring in the LC filter 3 is cancelled. For example, a value proportional to a value (-I2) obtained by subtracting the output current I2 from zero is adopted as the fluctuation ΔF. The reactor voltage VL is input to the resonance suppression unit 1035, and there is a relationship of VL=Lf·sI2 by introducing the inductance Lf of the reactor L3 and the differential operator s. Since the inductance Lf is known, for example, the output current I2 is obtained by dividing the integral value of the reactor voltage VL by the inductance Lf, and the fluctuation ΔF is set.

[0200] Fig. 21 and Fig. 22 are graphs showing waveforms of the input current Iin, the output current I2, and the reactor current I4 in the direct power conversion circuit 100C. Both graphs illustrate the case where |sinθ| is used as the function F(θ). Fig. 21 illustrates the case where ΔF=0. Fig. 22 illustrates the case where ΔF=-I2. Fig. 22 shows the deformation of the fluctuation ΔF, and Fig. 21 shows a comparison of the deformations.

[0201] The waveform of the reactor current I4 shown in Fig. 22 is affected by the fluctuation ΔF and is significantly distorted from the waveform of the reactor current I4 shown in Fig. 21. The waveform of the input current Iin shown in Fig. 22 is affected by the distortion of the reactor current I4 and has improved distortion compared to the waveform of the input current Iin shown in Fig. 21.

[0202] Although the embodiments and modifications have been described above, it will be understood that various modifications in form and details are possible without departing from the spirit and scope of the claims. The various embodiments and modifications described above can be mutually combined. [Explanation of symbols]

[0203] 2,2a,2b Diode rectifier 4 Charge / discharge circuit 4a discharge circuit 4b charging circuit 5. Inverter 100, 100A, 100B, 100C, 100D Direct power conversion circuit 203 Rectifier circuit C3, C4 capacitors CH charging period D40 Diode I2 current I4 Reactor current Iin Input current Im amplitude F(θ), G(θ) functions J,B value L3, L4 reactor LH,LL DC power line Sl Switch Tsw period V3 Voltage across both ends VL Reactor voltage Vc Capacitor voltage Vdc DC voltage Vdc* command value Vin Single-phase AC voltage Vm amplitude Vrf Rectified voltage DC discharge duty kb distribution rate te end point ts start point ΔF Fluctuation (correction term) θ Phase

Claims

1. A first power line (LH); a second power supply line (LL) to which a potential lower than that of the first power supply line is applied; a rectifier circuit (203) having an input side to which a single-phase AC voltage (Vin) is applied from an AC power source (1) and an output side to which the first power supply line and the second power supply line are connected, and outputting a rectified voltage (Vrf) obtained by performing full-wave rectification and low-pass filtering on the single-phase AC voltage (Vin); a charge / discharge circuit (4) provided between the first power supply line and the second power supply line on the output side of the rectifier circuit; an inverter (5) to which a DC voltage (Vdc) which is a voltage between the first power supply line and the second power supply line is input; Equipped with The rectifier circuit (203) A diode rectifier (2; 2a, 2b) used for the full-wave rectification; a first capacitor (C3) connected between the first power supply line and the second power supply line directly or indirectly via the diode rectifier (2; 2a); a first reactor (L3) for performing the low-pass filtering in cooperation with the first capacitor (C3); having The charge / discharge circuit (4) a discharge circuit (4a) including a second capacitor (C4) provided between the first power supply line and the second power supply line, the discharge circuit discharging the second capacitor; a charging circuit (4b) that boosts the full-wave rectified single-phase AC voltage (|Vin|) or the rectified voltage (Vrf) and charges the second capacitor (C4) in a charging period (CH) having a length that is set depending on the phase (θ) of the single-phase AC voltage (Vin) and not depending on the amplitude (Im) of an input current (Iin) input to the rectifier circuit (203); having When the voltage (VL) of the first reactor (L3) decreases, both the start point (ts) and the end point (te) of the charging period (CH) are shifted to the lagging side with respect to the phase (θ), When the voltage (V3) of the first capacitor (C3) rises, both the start point (ts) and the end point (te) shift toward the delayed phase side with respect to the phase, A direct power conversion circuit (100, 100A, 100B, 100C, 100D) in which the polarity of the voltage (VL) of the first reactor (L3) is positive in the opposite direction to the direction of the current supplied from the AC power source (1) flowing between the diode rectifier (2; 2a) and the first reactor (L3), and the polarity of the voltage (V3) of the first capacitor (C3) matches the polarity of the voltage on the output side or input side of the diode rectifier (2; 2a) to which the first capacitor (C3) is connected.

2. the second capacitor (C4) is discharged with a duty (dc) proportional to the product of a cosine value (cos(2θ)) twice the phase (θ) and a command value (Vdc*) of the DC voltage only during a period in which the cosine value (cos(2θ)) is positive; The charging circuit (4b) a second reactor (L4) connected in series with the second capacitor (C4) on the output side of the rectifier circuit (203); a diode (D40) located on a high potential side of the second capacitor (C4), connected between the second reactor (L4) and the second capacitor (C4), and having a forward direction from the second reactor (L4) to the second capacitor (C4); a switch (S1) for switching whether a reactor current (I4) flowing in the second reactor (L4) is to flow to the second capacitor (C4) via the diode (D40) or to the second power supply line (LL); having From the end point (te) of the first charging period to the start point (ts) of the second charging period immediately after the first charging period, the reactor current (I4) flows through the switch (Sl) while increasing, into the second power supply line (LL); The start point (ts) is the time point at which the reactor current (I4) rises and reaches the upper limit value (il^), The reactor current (I4) flows to the second capacitor (C4) during the charging period (CH), The upper limit value (il^) is a product of the amplitude (Im) and a predetermined function (G(θ)) of the phase, The predetermined function (G(θ)) is the square of the sine value of the phase (sin ２ The half value of the reciprocal of θ ((2 sin ２ θ) －１ ) from 1 and the product (F(θ)) of the absolute value of the sine value (|sinθ|) and a correction term (ΔF) is added to the product (F(θ)), The smaller the voltage (VL) of the first reactor (L3), the larger the correction term (ΔF).

2. The direct power conversion circuit (100, 100A, 100B, 100C, 100D) of claim 1, wherein the correction term (.DELTA.F) is larger as the voltage (V3) of the first capacitor (C3) is larger.

3. The second capacitor (C4) is a square (cos θ) of the cosine value (cos θ) of the phase (θ). ２ θ) and the command value (Vdc*) of the DC voltage, The charging circuit (4b) a second reactor (L4) connected in series with the second capacitor (C4) on the output side of the rectifier circuit (203); a diode (D40) located on a high potential side of the second capacitor (C4), connected between the second reactor (L4) and the second capacitor (C4), and having a forward direction from the second reactor (L4) to the second capacitor (C4); a switch (S1) for switching whether a reactor current (I4) flowing in the second reactor (L4) is to flow to the second capacitor (C4) via the diode (D40) or to the second power supply line (LL); having From the end point (te) of the first charging period to the start point (ts) of the second charging period immediately after the first charging period, the reactor current (I4) flows through the switch (Sl) while increasing, into the second power supply line (LL); The start point (ts) is the time point at which the reactor current (I4) rises and reaches the upper limit value (il^), The reactor current (I4) flows to the second capacitor (C4) during the charging period (CH), The upper limit value (il^) is a product of the amplitude (Im) and a predetermined function (G(θ)) of the phase, The predetermined function (G(θ)) is a value obtained by adding a correction term (ΔF) to the product (F(θ)) of the absolute value of the sine value (|sinθ|) and a half-value of the product of the cosine value (cos(2θ)) of twice the value of the phase and a coefficient (1-kb) between 0 and 1, inclusive, plus ½ of the product, The smaller the voltage (VL) of the first reactor (L3), the larger the correction term (ΔF).

2. The direct power conversion circuit (100, 100A, 100C, 100D) of claim 1, wherein the correction term (.DELTA.F) is larger as the voltage (V3) of the first capacitor (C3) is larger.

4. the second capacitor (C4) is discharged with a duty (dc) proportional to the product of a cosine value (cos(2θ)) twice the value of the phase (θ) and the amplitude (Vm) of the single-phase AC voltage only during a period in which the cosine value (cos(2θ)) is positive; The charging circuit (4b) a second reactor (L4) connected in series with the second capacitor (C4) on the output side of the rectifier circuit (203); a diode (D40) located on a high potential side of the second capacitor (C4), connected between the second reactor (L4) and the second capacitor (C4), and having a forward direction from the second reactor (L4) to the second capacitor (C4); a switch (S1) for switching whether a reactor current (I4) flowing in the second reactor (L4) is to flow to the second capacitor (C4) via the diode (D40) or to the second power supply line (LL); having From the end point (te) of the first charging period to the start point (ts) of the second charging period immediately after the first charging period, the reactor current (I4) flows through the switch (Sl) while increasing, into the second power supply line (LL); The start point (ts) is the time point at which the reactor current (I4) rises and reaches the upper limit value (il^), The reactor current (I4) flows to the second capacitor (C4) during the charging period (CH), The upper limit value (il^) is a product of the amplitude (Im) and a predetermined function (G(θ)) of the phase, The predetermined function (G(θ)) is the square of the sine value of the phase (sin ２ Half the reciprocal of ((2 sin ２ (θ) －１ ) from 1, a coefficient (kb) between 0 and 1, a coefficient (π / √8), and the absolute value of the sine value (|sinθ|) are multiplied (F(θ)) to add a correction term (ΔF), The smaller the voltage (VL) of the first reactor (L3), the larger the correction term (ΔF).

2. The direct power conversion circuit (100, 100A, 100B, 100C, 100D) of claim 1, wherein the correction term (.DELTA.F) is larger as the voltage (V3) of the first capacitor (C3) is larger.

5. The second capacitor (C4) is discharged with a duty (dc) having a value (1-B) obtained by subtracting the first value (B) from 1, The charging circuit (4b) a second reactor (L4) connected in series with the second capacitor (C4) on the output side of the rectifier circuit (203); a diode (D40) located on a high potential side of the second capacitor (C4), connected between the second reactor (L4) and the second capacitor (C4), and having a forward direction from the second reactor (L4) to the second capacitor (C4); a switch (S1) for switching whether a reactor current (I4) flowing in the second reactor (L4) is to flow to the second capacitor (C4) via the diode (D40) or to the second power supply line (LL); having From the end point (te) of the first charging period to the start point (ts) of the second charging period immediately after the first charging period, the reactor current (I4) flows through the switch (Sl) while increasing, into the second power supply line (LL); The start point (ts) is the time point at which the reactor current (I4) rises and reaches the upper limit value (il^), The reactor current (I4) flows to the second capacitor (C4) during the charging period (CH), The upper limit value (il^) is a product of the amplitude (Im) and a predetermined function (G(θ)) of the phase, The predetermined function (G(θ)) is a sum of a value (F(θ)) obtained by subtracting the product (B·J) of the first value (B) and the second value (J) from the absolute value (|sinθ|) of the sine value of the phase, and a correction term (ΔF); the first value (B) is a ratio ([Vdc*-Vc] / [Vrec-Vc]) of a value (Vdc*-Vc) obtained by subtracting the voltage (Vc) of the second capacitor (C4) from a command value (Vdc*) of the DC voltage to a value (Vrec-Vc) obtained by subtracting the voltage (Vc) of the second capacitor (C4) from the product (Vrec) of the amplitude (Vm) of the single-phase AC voltage and the absolute value (|sinθ|); the second value (J) is a product of a half value obtained by subtracting from 1 the product of a cosine value (cos(2θ)) of twice the value of the phase and a coefficient (1-kb) not less than 0 and not more than 1, and a ratio (Vm / Vdc*) of the amplitude (Vm) of the single-phase AC voltage to a command value (Vdc*) of the DC voltage, The smaller the voltage (VL) of the first reactor (L3), the larger the correction term (ΔF).

2. The direct power conversion circuit (100, 100A, 100C, 100D) of claim 1, wherein the correction term (.DELTA.F) is larger as the voltage (V3) of the first capacitor (C3) is larger.

6. The direct power conversion circuit (100, 100A, 100B, 100C, 100D) according to any one of claims 2 to 5, wherein the length of the charging period (CH) is proportional to the sum (G(θ)) of a first quantity (F(θ)) that depends on the phase (θ) but not on either the voltage (VL) of the first reactor (L3) or the voltage (V3) of the first capacitor (C3), and a second quantity (ΔF) that depends on either or both of the voltage (VL) of the first reactor (L3) and the voltage (V3) of the first capacitor (C3).

7. The charging circuit (4b) chops a second input current (I4) input to the charging circuit (4b) to charge the second capacitor (C4); the smaller the value obtained by dividing the average value of the second input current (I4) in the chopping cycle (Tsw) by the maximum value of the average value, the shorter the charging period (CH); The smaller the voltage (VL) of the first reactor (L3), the longer the charging period (CH).

2. The direct power conversion circuit (100, 100A, 100B, 100C, 100D) according to claim 1, wherein the larger the voltage (V3) of the first capacitor (C3), the longer the charging period (CH).

8. 2. The direct power conversion circuit (100, 100A, 100C) according to claim 1, wherein the first capacitor (C3) is directly connected between the first power supply line (LH) and the second power supply line (LL), and the polarity of the voltage (V3) of the first capacitor (C3) is positive in the direction from the second power supply line (LL) to the first power supply line (LH).

9. the first capacitor (C3) is farther from the inverter (5) than the diode rectifier (2; 2a); 2. The direct power conversion circuit according to claim 1, wherein the polarity of the voltage (V3) of the first capacitor (C3) is positive in a direction from a low potential to a high potential of the single-phase AC voltage (Vin).

10. the first reactor (L3) is provided between the diode rectifier (2; 2a) and the first capacitor (C3); 2. The direct power conversion circuit (100, 100C) according to claim 1, wherein the polarity of the voltage (VL) of the first reactor (L3) is positive in a direction opposite to the direction of the current (I2) flowing through the first reactor (L3).

11. the first reactor (L3) is farther from the inverter (5) than the diode rectifier (2; 2a); 2. The direct power conversion circuit according to claim 1, wherein the polarity of the voltage (VL) of the first reactor (L3) is positive in a direction from a low potential to a high potential of the single-phase AC voltage (Vin).

12. The charging circuit (4b) a second reactor (L4) connected in series with the second capacitor (C4) between the first power supply line (LH) and the second power supply line (LL) on the first power supply line (LH) side relative to the second capacitor; a diode (D40) connected between the second reactor (L4) and the second capacitor (C4) and having a forward direction from the second reactor (L4) to the second capacitor (C4); a switch (S1) for switching whether a reactor current (I4) flowing from the first power supply line to the second reactor (L4) is to be flowed to the second capacitor (C4) via the diode (D40) or to the second power supply line (LL); having 2. The direct power conversion circuit (100, 100A, 100B) according to claim 1, wherein the rectified voltage (Vrf) is applied to a series connection of the switch (Sl) and the second reactor (L4).

13. The rectifier circuit (203) a second diode rectifier (2b) for performing full-wave rectification on the single-phase AC voltage (Vin) to obtain a second rectified voltage (|Vin|); Further comprising: The charging circuit (4b) a second reactor (L4) connected in series with the second capacitor (C4) on the output side of the second diode rectifier (2b); a diode (D40) located on a high potential side of the second capacitor (C4), connected between the second reactor (L4) and the second capacitor (C4), and having a forward direction from the second reactor (L4) to the second capacitor (C4); a switch (S1) for switching whether a reactor current (I4) flowing from the second diode rectifier (2b) to the second reactor (L4) is to be flowed to the second capacitor (C4) via the diode (D40) or to the second power supply line (LL); The direct power conversion circuit (100C, 100D) of claim 1, comprising:

14. The charging circuit (4b) a second reactor (L4) connected in series with the second capacitor (C4) on the output side of the diode rectifier (2) without the first reactor (L3) therebetween; a diode (D40) located on a high potential side of the second capacitor (C4), connected between the second reactor (L4) and the second capacitor (C4), and having a forward direction from the second reactor (L4) to the second capacitor (C4); a switch (Sl) for switching whether a reactor current (I4) flowing from the rectifier circuit (203) to the second reactor (L4) is to be flowed to the second capacitor (C4) via the diode (D40) or to the second power supply line (LL); 2. The direct power conversion circuit (100A, 100B, 100C, 100D) of claim 1, comprising:

Images