Energy-efficient ultra-wide band impulse radio system and method

Abstract

To provide ultra-wideband (UWB) technology that uses coded impulses modulated over a wide frequency spectrum at very low power over short distances for digital data transmission.SOLUTION: Such a UWB system needs to operate in the presence of an interfering signal via a receiver and provide robust communication. Therefore, an accurate and sharp filter that operates at low power is needed, and, beneficially, a filter that does not require a high-precision high-power clock is beneficial. Furthermore, since it is necessary to measure the position and / or distance of other elements, it is beneficial for many UWB applications to provide UWB-based distance measurement and / or positioning functions to eliminate the need to add further device complexity and considerable power consumption that is normally required.SELECTED DRAWING: Figure 19

Description

[Technical field]

[0001] The present invention relates to ultra-wideband wireless communications, and more particularly to ultra-low power impulse radio utilizing low energy detectors to provide distance measurements. [Background technology]

[0002] Ultra-Wideband (UWB) technology is a radio technology for transmitting digital data as modulated coded impulses over a very wide frequency spectrum at very low power over short distances. Such pulse-based transmission is an alternative to transmitting information using modulated sine waves, a technology currently employed within today's wireless communication standards and systems, such as IEEE 802.11 (Wi-Fi), IEEE 802.15 wireless personal area networks (PANs), IEEE 802.16 (WiMAX), Universal Mobile Telecommunications System (UMTS), Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), and their access to the Industrial, Scientific, and Medical (ISM) bands, and International Mobile Telecommunications-2000 (IMT-2000).

[0003] UWB transmissions from an antenna are defined by a radiated signal bandwidth exceeding 500 MHz or 20% of the center frequency, whichever is less. Thus, pulse-based systems, e.g., orthogonal frequency division multiplexing (OFDM), in which each transmitted pulse occupies either the full UWB bandwidth or a collection of narrowband carriers of at least 500 MHz, may access the UWB spectrum under the rules. Pulse repetition rates can be low or very high. Pulse-based UWB radar and imaging systems tend to use low to moderate repetition rates (typically in the range of 1 to 100 megapulses per second). On the other hand, communication systems favor high repetition rates (typically in the range of 1 to 2 gigapulses per second), thus enabling short-range gigabit-per-second communication systems. Because each pulse in a pulse-based UWB system occupies a large bandwidth, perhaps even the entire UWB bandwidth, such systems are relatively immune to multipath fading and do not suffer from inter-symbol interference (ISI), unlike carrier modulation-based systems, which suffer from both deep fading and inter-symbol interference (ISI).

[0004] When considering applications such as wireless sensor networks and portable electronics, UWB transceivers must ideally be small in footprint, highly integrated in functionality, support low-cost and high-volume manufacturing, and be energy efficient to run on limited power sources, e.g., batteries, indoor solar cells, small outdoor solar cells, or those developed with evolving technologies such as power by temperature gradients, fluid flow, small fuel cells, piezoelectric energy harvesters, micromachined batteries, and fiber optics. By using discrete pulses as modulation, efficient duty cycle schemes can be implemented when the transmitter is inactive, which can be further improved using On-Off Shift Keying (OOK) modulation.

[0005] Additionally, some UWB operating frequencies, for example 3.1 GHz to 10.6 GHz, have been approved by the Federal Communications Commission for indoor UWB communication systems and may use small antennas that can be easily integrated into reduced overall footprint solutions such as sensors, mobile devices, or portable electronics. Thus, low power UWB systems may support a wide range of applications including, but not limited to, sensor networks, smart buildings, medical devices, remote sensing, remote monitoring, remote control, agriculture, industrial, control, automation, personal monitoring, etc.

[0006] Such UWB systems, through their receivers, may also operate in the presence of interfering signals to provide robust communications in noisy and unregulated radio environments. It would therefore be beneficial to provide circuit designers with accurate, sharp filters that operate at low power. We present such a filtering method that removes the requirement for a precise carrier in the receiver.

[0007] In many applications of UWB devices, it is desirable or necessary to accurately detect the location and / or distance measurement of other elements. It would therefore be beneficial to provide circuit, device, and system designers with UWB-based distance measurement and / or location functionality that removes the additional complexity and power consumption that typically comes with adding Global Positioning System (GPS) receiver(s) or ultrasonic / laser distance measurement circuitry and / or devices. For such UWB-based location and / or distance measurement applications, it would be further beneficial to maintain the overall low power consumption of UWB impulse radio.

[0008] Other aspects and features of the present invention will become apparent to those of ordinary skill in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures. Summary of the Invention [Means for solving the problem]

[0009] The object of the present invention is to provide ultra-wideband wireless communication, and more particularly to an ultra-low power impulse radio utilizing low energy detectors to provide distance measurement.

[0010] According to one embodiment of the present invention, a method for filtering in a UWB receiver is provided by providing an N-path filter that uses a low precision clock source in combination with an energy detector.

[0011] According to an embodiment of the present invention, the present invention provides Synchronizing a first ultra-wideband (UWB) transceiver with a second UWB transceiver; transmitting a first packet from a first UWB transceiver including a plurality of UWB pulse bundles; starting a first timer associated with the first UWB transceiver upon transmission of the last pulse bundle; processing the received bundles of UWB pulses on a second UWB transceiver; synchronizing to a predetermined pulse within a UWB pulse bundle of a first packet using a circuit including at least a first correlator and a first delay locked loop; initiating a second timer associated with the second UWB transceiver upon determining detection of a predetermined pulse within a last pulse bundle of the plurality of pulse bundles; transmitting a second packet from the second UWB transceiver when the second timer reaches a predetermined waiting time; processing the received plurality of UWB pulse bundles associated with a second on the first UWB transceiver; synchronizing to a predetermined pulse within the UWB pulse bundle of the second packet using circuitry including at least a second correlator and a second delay locked loop; stopping the first timer upon determining detection of the predetermined pulse within the last pulse bundle of the plurality of pulse bundles of the second packet; A method for establishing range between a pair of ultra-wideband (UWB) transceivers is provided, the method comprising: calculating a time of flight as a function of an elapsed time of a first timer to determine a range between the first UWB transceiver and the second UWB transceiver.

[0012] According to an embodiment of the present invention, the present invention provides transmitting a UWB impulse with a first UWB transceiver operating at a first clock rate having a first integration window dependent on the first clock rate; receiving a UWB impulse at a second UWB transceiver operating at a second clock rate having a second integration window dependent on the second clock rate; integrating the received UWB signal within a second integration window to determine when the received energy within the second integration window exceeds a predetermined threshold at which a UWB impulse is received; After determining that the UWB impulse has been received, transmitting an echo signal in a second integration window; integrating the received UWB signal within a first integration window to determine when the received energy within the first integration window exceeds a predetermined threshold at which a UWB impulse is received; passing the integrated energy within the first integration window to a digital signal processing (DSP) circuit; A method for establishing range between a pair of ultra-wideband (UWB) transceivers is provided that includes deriving an estimate of elapsed time with a DSP circuit.

[0013] Other aspects and features of the present invention will become apparent to those of ordinary skill in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures. [Brief description of the drawings]

[0014] Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0015] [Figure 1A]FIG. 1 illustrates a wearable technology that supports biometric data acquisition and / or presentation using wireless communication in accordance with an embodiment of the present invention.

[0016] [Figure 1B] FIG. 1 illustrates an example of a wireless technology that supports home automation and location services according to an embodiment of the present invention.

[0017] [Figure 2A] 1 illustrates a prior art single pulse UWB protocol along with a multi-pulse symbol UWB protocol according to an embodiment of the present invention.

[0018] [Figure 2B] FIG. 2 illustrates a symbol, frame, and stream structure of a multi-pulse symbol UWB protocol according to an embodiment of the present invention.

[0019] [Diagram 3] 2 is a schematic diagram of a transmitter circuit of a UWB transmitter / transceiver according to one embodiment of the present invention.

[0020] [Figure 4] 2 is a schematic diagram of a ground-switched power amplifier circuit for a UWB transmitter / transceiver according to one embodiment of the present invention;

[0021] [Diagram 5] 2 is a schematic diagram of a digitally controlled oscillator circuit of a UWB transmitter / transceiver according to one embodiment of the present invention.

[0022] [Figure 6] 2 is a schematic diagram of a pulse generator circuit of a UWB transmitter / transceiver according to one embodiment of the present invention;

[0023] [Figure 7] 2 is a schematic diagram of a receiver circuit of a UWB receiver / transceiver according to one embodiment of the present invention;

[0024] [Figure 8] 2 is a schematic diagram of a low noise amplifier circuit of a UWB receiver / transceiver according to one embodiment of the present invention;

[0025] [Figure 9] 2 is a schematic diagram of a squaring mixer circuit of a UWB receiver / transceiver according to one embodiment of the present invention;

[0026] [Figure 10] 2 is a schematic diagram of a variable gain amplifier circuit of a UWB receiver / transceiver according to one embodiment of the present invention;

[0027] [Figure 11] 2 is a schematic diagram of a clock generator circuit of a UWB transmitter / receiver / transceiver according to one embodiment of the present invention.

[0028] [Figure 12A] 1 shows a schematic diagram of an integrator / analog-digital synchronization circuit for a UWB receiver / transceiver according to an embodiment of the present invention. [Figure 12B] 1 shows a schematic diagram of an integrator / analog-digital synchronization circuit for a UWB receiver / transceiver according to an embodiment of the present invention.

[0029] [Figure 13A] FIG. 1 is a diagram showing a system overview of a UWB receiver according to an embodiment of the present invention that utilizes an N-pass bandpass filter.

[0030] [Figure 13B] FIG. 1 is a diagram showing a system overview of a UWB receiver according to an embodiment of the present invention utilizing an N-pass bandstop filter.

[0031] [Figure 14] 1 shows a simplified block diagram of an N-pass filter utilizing bandpass filtering.

[0032] [Figure 15A] 15 illustrates an embodiment of a generalized circuit representation of an N-path filter utilizing bandpass filtering as shown in FIG. 14.

[0033] [Figure 15B] 15B illustrates a time representation of clock signals for the embodiment of the generalized circuit representation shown in FIG. 15A.

[0034] [Figure 15C] FIG. 15B illustrates a variation of the embodiment of the generalized circuit representation shown in FIG. 15A in which N-1 resistive elements are removed.

[0035] [Figure 16] 15B shows a variation of the embodiment of the generalized circuit representation shown in FIG. 15A, reducing the number of switches by N and making the circuit a single-sided design.

[0036] [Figure 17] 17 illustrates a differential circuit variation of the embodiment of the generalized circuit representation shown in FIG. 16.

[0037] [Figure 18] 15 illustrates an embodiment of a generalized circuit representation of an N-path filter utilizing bandstop filtering as shown in FIG. 14.

[0038] [Figure 19] FIG. 2 illustrates a simplified block circuit receiver representation of a ranging extension to a UWB receiver according to one embodiment of the present invention.

[0039] [Figure 20] 20 shows a simplified timing diagram of a first distance measurement operation mode of a UWB receiver according to an embodiment of the present invention as shown in FIG. 19.

[0040] [Figure 21]FIG. 21 illustrates an exemplary process flow for a first distance measurement mode of operation in accordance with the embodiment of the invention illustrated in FIG. 20.

[0041] [Figure 22] FIG. 4 illustrates an exemplary process flow for a second distance measurement mode of operation in accordance with an embodiment of the present invention.

[0042] [Diagram 23] 23 shows a simplified timing diagram of a second distance measurement operation mode of a UWB receiver according to an embodiment of the present invention as shown in FIG. 22. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0043] The present invention relates to ultra-wideband wireless communications, and more particularly to ultra-low power impulse radio utilizing low energy detectors to provide distance measurements.

[0044] The following description provides only exemplary embodiment(s) and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the following description of exemplary embodiment(s) will provide those skilled in the art with an enabling description for implementing the exemplary embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the spirit and scope as set forth in the appended claims.

[0045] "Ultra-wideband" (UWB), as used herein and throughout this disclosure, refers to a wireless communication system transmitting from an antenna with a radiated signal bandwidth greater than 500 MHz or 20% of the center frequency, whichever is less.

[0046] As used herein and throughout this disclosure, "wireless" refers to the physical implementation of a system that can transmit and receive data wirelessly, including, but not limited to, radio frequency integrated circuits, printed circuit boards, radio modules.

[0047] "Impulse radio" as used herein and throughout this disclosure refers to a radio system that utilizes impulse-like signals for its transmission.

[0048] "Sub-low IF" as used herein and throughout this disclosure refers to an intermediate frequency (IF) generated within an RF signal processor circuit, such as a receiver, where signals in a first frequency range are converted to signals in a second frequency range, and is used by the inventors to distinguish their inventive approach from the prior art; such conversion using different systems and methods is referred to as "zero IF", where a subsequent high pass filter is used to remove a block of frequencies including DC from the second frequency range, i.e., "low IF", where the converted second frequency range includes DC, but the subsequent RF circuitry or RF elements are AC coupled, thereby removing the block of frequencies including DC.

[0049] As used herein and throughout this disclosure, "portable electronic device" (PED) refers to a wireless device used for communications and other applications that require a battery or other independent form of energy for power. This includes, but is not limited to, devices such as mobile phones, smart phones, personal digital assistants (PDAs), portable computers, pagers, portable multimedia players, portable game consoles, laptop computers, tablet computers, sensor nodes, and e-readers.

[0050] As used herein and throughout this disclosure, "Fixed Electronic Device" (FED) refers to wireless and / or wired devices used for communications and other applications that require connection to a fixed interface for power, including, but not limited to, laptop computers, personal computers, computer servers, kiosks, game consoles, digital set-top boxes, analog set-top boxes, Internet-enabled appliances, Internet-enabled televisions, and multimedia players.

[0051] A "user" as used herein may refer to, but is not limited to, an individual or group of individuals, whose biometric data may be monitored, acquired, stored, transmitted, processed, and analyzed locally or remotely to the user, through, but is not limited to, engagement with service providers, third party providers, businesses, social networks, social media, etc., through dashboards, web services, websites, software plug-ins, software applications, graphical user interfaces, for example, to retrieve electronic content. This includes, but is not limited to, individuals, employees of organizations and / or businesses, members of community organizations, members of charities, men, women, children, teenagers, and animals. In its broadest sense, users may further include, but are not limited to, software systems, mechanical systems, robotic systems, android systems, etc., which may be characterized by data related to a subset of conditions, including, but not limited to, their environment, medical condition, biological condition, physiological condition, chemical condition, ambient condition, location condition, neurological condition, drug condition, and one or more specific aspects of one or more of these conditions.

[0052] "Wearable devices" or "wearable sensors" refer to small electronic devices worn by a user, including those worn under, in, on, or on clothing, and are part of the broader general class of wearable technologies, which in contrast include "wearable computers," which are directed to general-purpose or specialized information technology and media developments. Such wearable devices and / or sensors may include, but are not limited to, smartphones, smart watches, e-textiles, smart shirts, activity trackers, smart glasses, environmental sensors, medical sensors, biosensors, physiological sensors, chemical sensors, ambient environment sensors, location sensors, neurosensors, drug delivery systems, medical testing and diagnostic devices, and motion sensors.

[0053] A: Example application scenarios

[0054] Embodiments of the present invention are described and presented within the context of transmitter / receiver / transceiver systems described by the inventors in World Intellectual Property Office application WO / 2016 / 191851, entitled "Systems and Methods for Spectrally Efficient and Energy Efficient Ultra-Wideband Impulse Radios with Scalable Data Rates," filed May 31, 2016, and World Intellectual Property Office application WO / 2015 / 103692, entitled "Systems relating to Ultra-Wideband Broadcasting comprising Dynamic Frequency and Bandwidth Hopping," filed January 1, 2015. However, it will be apparent to one skilled in the art that transmitter / receiver / transceiver designs and systems can be employed utilizing embodiments of the present invention with respect to filtering and ranging.

[0055] However, the increased efficiency of the transmitter / receiver / transceiver system established by the inventors in their earlier patent applications identified above is maintained within the embodiments of the present invention. Such low power transmitter / receiver / transceiver systems improve the feasibility of self-powered wireless sensor networks that operate on energy harvested from the environment, such as the sun, vibration, and temperature, rather than from batteries, which have limited power available, especially for compact, small footprint sensors. Without such low power requirements for UWB devices, the footprint of a UWB transceiver with a footprint of several square millimeters would be completely negated by the requirement of solar cells of tens of square centimeters to provide power. Thus, very low power UWB devices require reduced solar cell footprints to provide power to them or other means that are not otherwise feasible to power them. The embodiments of the present invention are intended to be compatible with sub-micron CMOS design and manufacturing processes provided by commercial foundries.

[0056] The low power UWB transmitter / receiver and transceiver have various applications, including examples shown in the first to third images 100A to 100C of FIG. 1A of a wearable device. In the first image 100A an example of a wearable device is shown, and in the second image 100B an example of a smart garment is shown, where the UWB device may be attached to or enclosed in the fabric of these different smart clothing items. The third image 100C shows an example of a wearable device that presents information to a user, in contrast to the devices / garments of the first and second images 100A and 100B, which typically collect and transmit contextual, environmental, and biometric data to another electronic device. However, the low power UWB receiver in combination with transducers, LEDs, etc. also offers the possibility to provide tactile and / or visual feedback to the user depending on the data received. In other embodiments, the LEDs in the smart garment may light up based on the UWB signal received by the UWB receiver in the smart garment.

[0057] Smart clothing may be made from smart fabrics and used to enable remote physiological monitoring of various vital signs of the wearer, such as heart rate, respiration rate, body temperature, activity, and posture, or it refers to conventional materials with embedded sensors. A smart shirt may, for example, record electrocardiogram (ECG), provide inductance plethysmography, accelerometers, optical pulse oximetry, galvanic skin response (GSR) for skin moisture monitoring, and respiration through blood pressure. Information from such wearable devices may be stored locally or on an associated device, e.g., a smartphone, as well as remotely on a personal server, remote cloud-based storage, etc., typically communicating via wireless networks such as Bluetooth, RF, WLAN, or cellular networks, although wired interfaces may also be provided, e.g., to a user's smartphone, laptop, or dedicated housing, to extract data as well as recharge batteries in the wearable device.

[0058] FIG. 1A also shows fourth and fifth images 100D and 100E, respectively, of sensors and electronic devices providing biometric data related to the user. For example, in the fourth image 100D, the user's smart clothing provides data from sensors including, but not limited to, those providing acoustic environment information via a MEMS microphone 105, the user's breathing analysis via a lung volume sensor 110, global positioning via a GPS sensor 115, their temperature and / or ambient temperature via a thermometer 120, and blood oxygenation via a pulse oximeter 125. These are supplemented by movement data acquired by a muscle activity sensor 130, motion data via a 3D motion sensor (e.g., a 3D acceleration sensor), the user's weight / carrying data from a pressure sensor 140, and walking / running data from a pedometer 145. These may be used alone or in combination with other data including, for example, data acquired from medical devices related to the user as shown in the fifth image 100E of FIG. 1A.

[0059] As shown, these medical devices include, but are not limited to, deep brain nerve stimulators / implants 150, cochlear implants 155, cardiac defibrillators / pacemakers 140, gastric stimulators 145, insulin pumps 170, foot implants 175 and portable data recorders 180. Typically, these devices communicate with a body area aggregator, e.g., a smartphone or a dedicated wearable computer. It will therefore be clear that a user may be associated with one or more sensors, either through a conscious decision, e.g., wearing a blood glucose sensor, an unconscious decision, e.g., putting an accelerometer in a mobile phone, or event-based, e.g., a pacemaker worn to address a cardiac issue. For most of these, data transmission from the wearable device to the PED / FED is generally low, e.g., periodic biometric data, while in some cases, such as smart glasses, continuous and / or larger amounts of data transmission / reception may be required. Even continuous data collection, such as cardiac monitoring, may be transmitted in burst mode, since the amount of data per minute is not large.

[0060] Also shown in FIG. 1A is a sixth image 100F of a high fidelity audio system representing an example of electronic devices connected to UWB wireless impulse radios in a residential, commercial, manufacturing, or retail environment. Thus, speakers, CD / DVD players, preamplifiers, power amplifiers, turntables, etc. may be interconnected to wireless routers, etc. as digital set-top boxes, personal video recorders (PVRs), televisions (TVs), or other configurations such as multiple PEDs / FEDs. Alternatively, Point of Sale (POS) terminals may be networked, electronic displays in a retail environment fed from a central server, autonomous robots in a manufacturing facility updated with activity, etc.

[0061] 1B, a first and second environment 100F and 100G are shown, respectively, for example deployment scenarios of UWB wireless impulse radio according to an embodiment of the present invention for enhancing home automation and wireless interconnection in a first environment 100F, or for providing wireless location services for people, equipment, and medical supplies in a second environment 100G. Considering the first environment 100F, a series of deployment scenarios are shown, including air conditioner 1001, energy saving-efficiency 1002, surveillance 1003, entertainment 1004, timer 1005, lighting 1006, motor control 1007, environment 1008, sprinkler 1009, appliance 1010, and security 1011. In most of these, the requirements for sending / receiving data are very limited and non-periodic. Similarly, in the second environment 100G, a simplified schematic of a hospital's wireless-based location services, inventory tracking services, etc. are shown, ranging from patient tracking, to hospital equipment such as trolleys, diffusion pumps, connectivity of medical equipment such as patient monitors, electrocardiograms (EKG), and medical consumables, etc. Again, data rates are generally low, but in addition there can be a large number of simultaneously operating devices within a small area where interference cannot be tolerated.

[0062] Within such environments, data regarding occupancy of areas within each of the first and second environments 100F and 100G may augment or provide an override to these other UWB-enabled sensors, and so forth. For example, a lighting controller 1006 in a room may determine low light levels and attempt to turn on the lights. However, if the UWB ranging-based occupancy sensor determines that there is no user in the room, the lighting controller 1006 is "over-ruled." However, in other embodiments, the lighting controller 1006 may be associated with a large area with multiple lighting fixtures and virtually established zones. Thus, a UWB ranging device according to an embodiment of the invention may determine whether an individual is presented within a predefined range of the UWB ranging device and thereby associated with that zone. In this way, for example, lights in a hallway may be turned on or off to reflect occupancy, or turned on before, for example, a security guard walks down the hallway at night and turned off afterwards.

[0063] B: Dynamic multi-pulse bundle structure of the bit

[0064] In our earlier patent applications WO / 2016 / 191851 "Systems and Methods for Spectrally Efficient and Energy Efficient Ultra-Wideband Impulse Radios with Scalable Data Rates" and WO / 2015 / 103692 "Systems relating to Ultra-Wideband Broadcasting comprising Dynamic Frequency and Bandwidth Hopping", which are incorporated herein by reference, a design methodology for impulse radios based on pulse bundling was established, and by utilizing multiple pulses per bundle with real-time configurable parameters such as phase, frequency, amplitude, and bandwidth, the inventors established a UWB transmitter design that can dynamically fill the UWB spectrum. UWB communications allows transmission using a wide frequency band, provided that the spectral masks of the appropriate regulatory bodies are adhered to. For example, in the United States, the allocated frequency band is 3.1 GHz≦f≦10.6 GHz, and the Federal Communications Commission (FCC) determines the spectral masks in terms of maximum transmission power in different sub-bands across this allocated frequency band. This allows pulsed operation, which has the advantage of low power consumption, since the transceiver can be duty cycled to consume power only when transmitting or receiving a pulse. Since the spectral mask allows a fixed maximum power spectral density for transmission, it is advantageous to maximize the occupied bandwidth in order to maximize the symbol energy and increase the range achievable by the wireless link. However, the use of a single pulse for communication creates a trade-off between pulse bandwidth and required synchronization accuracy, since an increase in pulse bandwidth corresponds to a decrease in pulse duration, thus increasing the energy required for synchronization and resulting in more difficult and potentially costly circuit implementations.

[0065] The inventors have addressed this trade-off and eliminated it through the conceptual step of applying multiple pulses with different frequency spectra to generate the bits. Referring to FIG. 2A in the first image 200A, a time and frequency domain schematic of a prior art impulse radio is shown, where each bit 210 is a pulse oscillation at a single frequency, so that the frequency spectrum is limited to a frequency range allowed by the regulatory UWB mask 220, below the maximum power in that frequency range. 0 In contrast, as shown in the second image 200B of FIG. 2A, each bit 260 has a frequency f 1 , f 2 , f 3 The multi-pulse spectrum 280 of the symbol (bit 260) is thus conceptually obtained by summing the individual pulse spectra of the sub-pulses 260A to 260C (phase scrambling omitted for clarity), which increases the bandwidth but also the duration of the symbol, allowing to maximize the symbol energy while maintaining maximum power below the UWB mask 220, relaxing the timing requirements and synchronization levels required at the receiver, in contrast to the single-pulse prior art method. Any number of pulses with different sets of parameters may be included in the bundle to tailor the pulse spectrum to specific requirements.

[0066] To provide maximum signal energy without violating the emission mask, the phase of the pulses must be randomized, i.e., the spectrum must be whitened to avoid the generation of "spectral lines" commonly found in periodic signals, and the correlation between the pulses must be reduced so that the multipulse spectrum becomes the sum of the individual pulse spectra. This may be done by applying a pseudorandom noise (PRN) sequence to the phase modulation of the transmitter's power amplifier. No phase synchronization between the transmitter and receiver is required to achieve this, since the receiver is not sensitive to the phase of the signal (due to a non-coherent detection scheme, described below). The exact spectral shape of the transmitted signal may be controlled by generating pulses with different frequencies and durations in each symbol. A symbol or bit is referred to by the inventors as comprising a "pulse bundle". The spectrum of the pulse bundle is easily calculated, since its power is the sum of the individual pulse power spectra. This facilitates dynamic reconfiguration in response to environmental changes or user demands, and also allows operation in different regulatory environments.

[0067] Due to the pulsed nature of the signal, out-of-band spectral side lobes are present. Even if pulse shaping reduces the side lobe level, the maximum value of the side lobes can still be several dB higher than the average out-of-band power spectral density. By applying a PRN sequence to the least significant bit (LSB) of the duty cycle control bits, the width of each pulse can be randomly dithered. This equally dithers the position of the side lobes and nulls in the out-of-band spectrum, effectively whitening the out-of-band spectrum to its average value and increasing the margin against the FCC spectral mask.

[0068] Modulation of the wideband data stream can be achieved by On-Off Keying (OOK) or Pulse Position Modulation (PPM), for example as shown in FIG. 2B. In OOK modulation 2020, the presence of a pulse bundle indicates a "1" and the absence of a bundle indicates a "0". This is a low-power communication method since the transmitter only needs to be active to transmit a "1" and can remain in sleep mode when the data bit is a "0". It also allows for a greater communication range since data is only transmitted approximately half the time (as guaranteed by proper data coding), which means that each pulse bundle can contain more energy and still meet the emission masks imposed by regulatory agencies.

[0069] However, OOK modulation requires a defined threshold to determine whether the received data is a "1" or a "0". This can degrade performance in environments where the channel characteristics or the level of the interfering signal change rapidly. In these situations, for example, PPM modulation 2010 may be preferred as an alternative modulation scheme. In this case, it is the position of the pulse bundle within the symbol period that determines whether a "1" or a "0" is received. The detector essentially compares the energy received in the first half of the symbol period with the energy received in the second half of the symbol period to make the decision, creating a frame-level threshold that can compensate for the rapidly changing environment. According to the inventors' design, the ability to switch between OOK and PPM modulation within the same transmitter-receiver pair is made possible by using a burst-mode communication scheme with a parallel digitization architecture.

[0070] Thus, in Fig. 2B, symbols 200C of the PPM 2010 and OOK 2020 modulation schemes are shown. Furthermore, a frame structure 200D is shown, where each frame 200D is preceded by a synchronization block 2030 to achieve fine synchronization at the receiver and a start bit 2040 to correct the drift of the symbol synchronization before the data 2050 is transmitted / received. Due to the simple synchronization structure, only a short synchronization block 2030 is required, reducing the effective data rate overhead of the system. Between frames 200D, the transmitter and receiver are powered down to reduce power consumption. This produces a stream 200E with the resulting structure of start 2060, frame 200D, and sleep 2080.

[0071] Such transmission protocols are also suitable for reconfigurable data rates. As an example of system operation, assume a data rate of 1 Mbps, a frame size of 1 Kbit, and a burst data rate of 20 Mbps. Within a frame, for example, a symbol is transmitted every 50 ns. In this example, each frame has a duration of 50 μs. To achieve a 1 Mbps data rate, the frame repetition rate would be 1 KHz, i.e., a frame is transmitted every 1 ms. This means that the receiver would only be active for 50 μs every 1 ms, resulting in a 5% duty cycle. To achieve a data rate of 100 kbps with the same frame rate and duration, the only change required would be to reduce the frame repetition rate to 10 ms (i.e., a frame transmitted every 10 ms). Now the receiver would only be active for 50 μs every 10 ms, resulting in a 0.5% duty cycle. Thus, a 10x reduction in data rate would also result in a 10x reduction in power consumption.

[0072] C: Exemplary UWB Transmitter

[0073] Referring to FIG. 3, a schematic diagram of a transmitter 300 according to one embodiment of the present invention is shown. The Pulse Pattern block 310 holds the configuration of the pulse used to represent the current symbol. From the symbol rate clock (i.e. 20 MHz), multiple phases are generated by the Delay Locked Loop (DLL) 330. The rising edge of each clock phase represents the start of one pulse of the symbol pulse bundle. The multiplexer 320 is triggered by the edge of the clock phase to select the current pulse configuration from the Pulse Pattern block 310. The Pulse Generator (Pulse) 350 generates a pulse with a pulse width set by the multiplexer 320 and enables the Digitally Controlled Oscillator (DCO) 340 and the Power Amplifier (PA) 350. When enabled, the DCO 340 generates a Gaussian pulse with a frequency set by the multiplexer 320, which is amplified by the PA 360 and radiated by the antenna 370. Thus, the Pulse Pattern block 310 establishes the pulse of a symbol or a symbol sequence. In this manner, by updating the pulse pattern block 310, the pulse sequence used for each symbol is adjusted, and thus the pulse pattern block 310 may be dynamically updated based on one or more factors including, but not limited to, network environment data, predefined sequences, date, time, geographic location, signal-to-noise ratio (SNR) of the received signal, and regulatory masks.

[0074] C1. Transmitter Pulse Generation and Shaping

[0075] The DCO 340 output may be shaped to provide a predetermined frequency and / or amplitude characteristic, either discretely or in combination with the operation of the pulser 350. For example, in the embodiments of the invention described herein, the use of Gaussian shaping and methods of shaping Gaussian pulses are presented and employed. The embodiment shown in this patent employs shaping the pulse via the PA 360 through adjustment of its ground connection. This allows the transmitter to operate entirely in the digital domain, allowing for a fully digital structure with negligible static current consumption. Additionally, the use of a fully digital transmitter structure allows for very aggressive power cycling, i.e., power cycling at the pulse level. However, in other embodiments, alternative shaping methodologies and shaping profiles may be employed.

[0076] C2. Grounded Switched Power Amplifier

[0077] The pulsed nature of UWB transmissions requires a power amplifier (PA) capable of providing high instantaneous power levels with pulse shaping to reduce side lobes in the pulse spectrum. High power efficiency, efficient power cycling, and fast wake-up / sleep transition times are necessary to achieve low average power consumption. A switching power amplifier (SW-PA) 400 as shown in FIG. 4 was employed within the embodiments of the invention presented herein to transmit UWB pulse bundles. Thus, the SW-PA 400 represents an embodiment of the PA 360 of FIG. 3. As shown, first and second transistors M1 410 and M2 420 function as switches whose inputs are complementary digital clocks generated by the DCO, allowing the implementation of a fully differential SW-PA 400. The frequency of these digital clocks sets the center frequency of each individual pulse in the pulse bundle, and a pulse enable signal applied to a third transistor M3 430 sets the duration of each pulse. Thus, the pulse enable / pulse duration is a pulse signal provided by the pulser 350 coupled to the PULSE 460, while the complementary digital clock is the VCO P440 and VCO N 450, which in turn modifies the ground connection of SW-PA 400 via third transistor M3 430. The output of SW-PA 400 is RF P 470 and RF N 480, SW-PA400 is power rail V DD is combined with

[0078] The functionality can be explained by considering only one side (half circuit) of the differential SW-PA 400, since symmetry ensures that the operation of the other side is identical. The output of the SW-PA 400, in this case the RF P 470 is connected to GND when the first transistor M1 410 is on PA The DC voltage at the SW-PA400 output is connected to the inductor L 1 (via V DD Therefore, when the first transistor M1 410 is off, the SW-PA400 output is V DD +(V DD -GND PA )=2×V DD -GND PA Combining these two cases, we get 2×V DD -GND PA Therefore, the output swing is PA By shaping the voltage of the node, the output of the SW-PA 400 can be a direct shaped version of the clock signal to generate an output pulse. By design, the output pulse is shaped by the third transistor M3 430 and C5 to achieve a Gaussian profile for an optimal balance between pulse duration and bandwidth, and to minimize side lobe power in the pulse spectrum. The SW-PA 400 generates an output pulse when activated by the third transistor M3 430, which acts as an enable switch that ensures that the power amplifier consumes only static power.

[0079] C3. Digitally Controlled Oscillator

[0080] A fully differential ring DCO (FDR-DCO) 500 as shown in Figure 5 is employed within the embodiments of the invention presented herein, and therefore the FDR-DCO 500 represents an embodiment of the DCO 340 of Figure 3. The FDR-DCO 500 provides a digital clock to the first and second transistors M1 510 and M2 520 in the SW-PA 400 of Figure 4, which are fed with the output of the pulser 350 to switch their operation and generate the clock provided to the SW-PA 400. The frequency of this FDR-DCO 500 is set by first and second capacitor banks including first and second capacitors C1 540A and C2 540B and third and fourth capacitors C3 540C and C4 540D, respectively, which are connected to the outputs of the first and second fully differential inverters INV1 510 and INV2 520, respectively. The output from the third fully differential inverter INV3 530 is the VOC P 440 and VCO N Complementary digital clock VOC combined with 450 P and VCO N to provide.

[0081] Thus, in one embodiment of the present invention, the first through fourth capacitors C1 540A through C4 540D are programmable capacitor banks with identical capacitance values, each with 4 bits of programmability, although other levels of programmability, etc., may be used. The third and fourth switches S3 550A and S4 550B are used to turn off the FDR-DCO 500 to save power when no pulses are being transmitted. The fourth inverter INV4 570 in conjunction with the first and second switches S1 560A and S2 560B precharges the oscillator node before oscillation (when the FDR-DCO 500 is off) and controls the polarity of the pulses for phase modulation. This creates an oscillator with a very fast start-up time (on the order of a fraction of a ns) improving the power cycling efficiency of the transmitter. When generating a pulse, the FDR-DCO 500 is enabled by opening the first and second switches S1 560A and S2 560B and closing the third and fourth switches S3 550A and S4 550B, while at all other times the FDR-DCO 500 is in a low power sleep state. DD An additional PMOS transistor may be added between the current branch of SW-PA 400 and SW-PA 400 to turn off SW-PA 400 quickly at the end of the pulse and improve pulse shaping.

[0082] C4. Pulse generator

[0083] The pulse signal from the pulser 350 coupled to the DCO 340, e.g., FDR-DCO 500, and the PA 360, e.g., SW-PA 400, is generated using a pulse generation circuit. Thus, the pulse generator (PULGEN) 600 shown in FIG. 6 is employed within the embodiments of the invention presented herein, and therefore, the PULGEN 600 represents an embodiment of the pulser 350 of FIG. 3. As shown, the input signal is routed directly and indirectly to an AND gate 650 via first and second inverters INV1 610 and INV2 620. The first and second inverters INV1 610 and INV2 620 are part of a variable delay circuit in combination with first and second capacitors C1 630 and C2 640, which are programmable capacitor banks, although other levels of programmability, etc., may be used. Thus, a rising edge on the DATA line causes this circuit to create a pulse on the order of ns. The pulse width is a function of the variable delay created by the first and second capacitors C1 630 and C2 640, which are digitally adjustable, thereby making the pulse width digitally programmable.

[0084] D. Exemplary UWB Receiver

[0085] Referring to FIG. 7, a schematic diagram of a receiver 700 according to an embodiment of the present invention is shown. The RF signal from an antenna 710 is first amplified by a low noise amplifier (LNA) 720 and then passed to a two-stage RF amplifier (AMP1) 730. A first squaring mixer (MIX1) 740 multiplies the signal with itself to convert it to an intermediate frequency (IF). A three-stage variable gain amplifier (VGA) 750 further amplifies the signal and performs a bandpass filter function. The VGA 750 output is then coupled to a second squaring mixer (MIX2) 760 which downconverts the signal to a baseband frequency. Parallel integrators (INT1 and INT2) sum the signal energy and it is digitized by analog-to-digital (A / D) converters (ADC1 and ADC2) in a digital processor (not shown for clarity, but described with respect to the digital processor (DIGIPRO) 1200 below with respect to FIG. 12, for example).

[0086] D1. Receiver detection and interference cancellation

[0087] The receiver IF chain utilizes an instantaneous bandwidth that is on the order of the individual pulse bandwidth, e.g., 500 MHz, while the overall spectrum covers a wider bandwidth, e.g., 3 GHz ≤ f ≤ 6 GHz for BW = 3 GHz via a pulse bundling strategy. This allows for low power consumption of the circuit blocks after pulse downconversion, but still allows for ultra-wideband spectrum to be used for communication. The receiver of UWB signals is challenged because the bandwidth of the signal of interest is wide, requiring a high-bandwidth receiver chain. In addition, narrow in-band interference, DC offsets, and 1 / f noise generation are also problematic for low-power implementations. Therefore, it would be desirable for the IF stage to: · Operates in a sub-low IF architecture to avoid DC offset issues. Reduce 1 / f noise in the RF section. Reject typical narrowband interference (e.g. signals with BW<50MHz) to improve system robustness and interference rejection.

[0088] To achieve this, high-pass decoupling capacitors are specified within the receiver 700 to ensure that a small amount of the desired pulse energy is blocked during this process. This is further combined with a second squaring stage after the IF stage to retain full sensitivity. The double squaring method for enhancing the receiver's energy detection sensitivity / noise rejection and generating a rectified signal is well suited for CMOS integration. This double squaring method takes advantage of the impulse characteristics of the received signal to enhance detection as it is effectively equivalent to a nonlinear processing of each impulse. The first squaring operation downconverts the received pulse to a sub-low IF signal while the second squaring operation uses the entire downconverted pulse energy to increase the probability of detection instead of simply using the detected amplitude / peak as is done in other conventional impulse radio receivers. As previously mentioned, high-pass filtering between the two squaring operations provides DC offset mitigation, 1 / f noise reduction, and narrowband interference rejection.

[0089] It will be apparent to those skilled in the art that the non-coherent receiver architecture presented with respect to FIG. 7 advantageously does not require frequency synchronization or knowledge of the pulse phase / frequency pattern used by the transmitter.

[0090] D2. Low noise amplifier

[0091] A low noise amplifier (LNA) 800 as shown in Figure 8 is employed within the embodiments of the invention presented herein, and therefore the LNA 800 represents an embodiment of the LNA 720 of Figure 7. A differential input signal RF p and RF n are coupled to V through third and fourth capacitors C3 850A and C4 850B, respectively. BIASA first input of the LNA 800 is coupled to the drain of a pair of common-gate transistors M1 810 and M2 820, whose gates are biased by a first input of the LNA 800 and whose bias current is sunk to ground via an inductor L1. At the drains of M1 810 and M2 820, shunt peaking is performed by resistors R1 830 and R2 840 along with an inductor L2 870 to increase the bandwidth of the amplified signal. The signal is coupled from the LNA 800 to the output port OUT P and OUT N is combined with

[0092] D3.Squaring Mixer

[0093] A squaring mixer (SQ-MIX) 900 as shown in Figure 9 is employed within the embodiments of the invention presented herein, and therefore the SQ-MIX 900 represents an embodiment of the first and second squaring mixers MIX1 740 and MIX2 760 of Figure 7. As shown, a differential input signal IN P and I.N. N is coupled to the gates of transistors M7 910 and M8 920, whose transconductance converts the signal into a differential drain current. At the same time, the input signal is also coupled to cross-coupled transistor pairs M3:M4 and M5:M6, which convert their drain currents into the positive (OUT P ) side or negative (OUT N ) side, thereby multiplying the input by itself, i.e., squaring it. Transistors M1 and M2 are biased as current sources 950 to provide maximum voltage gain at the output. Bias circuit 960, which is coupled to the input signal and includes capacitors C1 through C4 and resistors R1 through R4, ensures that the NMOS transistors are biased at the proper bias points.

[0094] D4. Variable Gain Amplifier

[0095] A variable gain amplifier gain stage (VGA-GS) 1000 as shown in Figure 10 is employed within the embodiments of the invention presented herein, and therefore the VGA-GS 1000 represents an embodiment of each gain stage within the VGA 750 of Figure 7. A differential input signal IN P and I.N. N are coupled to the gates of composite transistor pairs M1:M2 and M3:M4, respectively. Each composite transistor M1 to M4, shown in the insert including a transistor array 1070 formed from transistors 1075(1) to 1075(N) with their sources and drains and gates connected, can be connected to either a signal or ground depending on the position of the switch. Thus, the composite transistor pairs M1:M2 and M3:M4 have switchable transconductance. The positive side (OUT P The effective transconductance of the negative side (OUT N ) is equal to the difference in transconductance of M2 and M4. Thus, the gain can be adjusted by the switch position of the composite transistor. Transistors M6 and M7 are biased as a current source 1030 to maximize the output voltage gain. Capacitors C3 and C4 perform low-pass filtering at the output node, while capacitors C1 and C2 and bias resistors R1 and R2 perform high-pass filtering at the input node. Thus, the VGA-GS 1000 operates with an effective band-pass filter response.

[0096] E. Transmitter-Receiver Synchronization and Clocking

[0097] As explained above, the receiver (Rx) and transmitter (Tx) of a UWB communication link are not synchronized with each other via distributed timing information, unlike in other wireless protocols. Thus, the requirement of each circuit is efficient synchronization between Tx and Rx to maintain the highly aggressive duty cycle of the wireless impulse radio according to the embodiments of the present invention, thereby maintaining the energy efficiency inherent to impulse wireless communication. Therefore, the inventors have established a low latency transmitter / receiver synchronization method / algorithm using dedicated synchronization hardware, including a dual clock timer system for ultra-low sleep mode power consumption. This allows efficient synchronization between Tx and Rx to maintain the highly aggressive duty cycle of the radio, thereby maintaining the energy efficiency inherent to impulse wireless communication.

[0098] A multi-phase clock baseband transceiver was designed to reduce the clock frequency (e.g., 20 MHz instead of 200 MHz) and improve power efficiency. In addition, a parallelized ADC / integrator structure, DIGIPRO 1200 in Figure 12A, was employed to enable faster synchronization and enhanced interference detection. This structure allows the complete signal to be observed during the receive time frame. This structure also allows for dynamically changing modulation schemes (OOK, PPM, etc.), improving communication robustness based on the channel or regulatory environment.

[0099] E1. Low-power clock generator

[0100] Referring to FIG. 11, there is shown a first clock generator (CLKGEN1) 1100 that may be employed within the embodiments of the invention presented herein, whereby CLKGEN1 1100 provides a 20 MHz signal to the transmitter 300 and DIGIPRO 1200 in the receiver 700 of FIG. 7. The low-power clock generator CLKGEN1 1100 includes an inverter INV1 1120 that functions as a low-frequency oscillator, i.e., 32 kHz, along with a crystal XTAL 1110, resistor R1, and capacitors C1 and C2. The sinusoidal oscillator signal is amplified by an inverter INV2 1125 to a square wave clock and used as a reference in a Phased Lock Loop (PLL) 1190. PLL 1190 consists of a Voltage Controlled Oscillator (VCO) 1150, whose output is divided in frequency by Divider 1180 and compared to a reference by Phase Detector 1130. Depending on whether the divided clock is lower or higher in frequency than the reference, a DOWN or UP pulse is generated. Charge Pump 1140, along with resistor R2 and capacitors C3 and C4, filters the UP and DOWN signals into the control signal for the VCO. When locked, the loop produces an output clock that is an integer multiple of the reference clock, buffered by inverter INV3 1160.

[0101] As mentioned above, efficient implementation of clock generation and synchronization in UWB transceivers is essential for low power operation. With pulse widths on the order of nanoseconds, traditional simple synthesis digital methods require base clocks of hundreds of MHz or more with high associated dynamic power consumption. Directly generating the base clock with a crystal clock generator results in relatively high power consumption. Since the power of a crystal oscillator is directly proportional to the frequency, running the crystal oscillator at a much lower frequency (e.g., 32 kHz) and multiplying the frequency with a phase-locked loop (PLL) reduces the power consumption significantly. This strategy is utilized by the inventors for low power clock generation in UWB transceivers. The base clock for the digital logic is set to the symbol frequency, e.g., 20 MHz, which is the rate at which symbols are processed by the digital baseband hardware and generated by a clock generator such as CLKGEN1 1100 in FIG. 11 utilizing a low power low frequency oscillator XTAL 1110. 3, the 20 MHz clock is then coupled to a delay locked loop (DLL) 330 which derives multiple phases from this clock with intervals in the nanosecond range, which are used as a timing base to generate the symbol pulses together with a multiplexer 320, a DCO 340, and a pulser 350. The control signal for the pulse generator is generated by a multiplexer which selects a control bit from a memory of pulse patterns 310 on the edges of the DLL's multi-phase clock.

[0102] The start-up time of the PLL 1190 is in the millisecond range and is effectively limited by the number of crystal oscillator cycles required to stabilize the loop. At data rates higher than 50 kbbs, the PLL 1190 and DLL 330 remain on between frames and are optimized for low power consumption. At data rates below 50 kbbs, both the PLL 1190 and DLL 330 may be power cycled between frames and the only power consumption during sleep mode is from the crystal oscillator.

[0103] E2. Synchronization

[0104] Since no clock data is transmitted in the transmission method of the UWB link, it is clear that synchronization of the receiver clock is required. Therefore, as shown with respect to FIG. 12, a synchronization block 1230 is used with the DIGIPRO 1200 of the receiver 700 shown in FIG. 7. As shown in FIG. 12A, the DIGIPRO 1200 includes a pair of double edge triggered integrators and analog-to-digital converter (ADC) blocks. Each of the first and second integrators 1210A and 1210B integrates over half a symbol period, and its output is digitized by one of the first and second ADCs 1220A and 1220B. The first and second integrators 1210A and 1210B are clocked via CLK1 1240A and CLK3 1250A, respectively, while the first and second ADCs 1220A and 1220B are clocked via CLK2 1240B and CLK4 1250B, respectively. Each of the first and second integrators 1210A and 1210B can be, for example, a 3-bit flash ADC. The two integrator ADC blocks are offset by ¼ symbol period so that a total of four overlapping integration windows are available per symbol. This is evident in FIG. 12B.

[0105] Synchronization during the synchronization frame block is achieved by determining the integration window with maximum energy, so that receiver clock synchronization is achieved in principle with one synchronization symbol. In practice, further synchronization symbols are needed to take into account the variable gain loop that tracks the channel changes of the radio link. PPM demodulation is achieved by observing the integration window with maximum energy of each symbol, while OOK modulation is achieved by observing the energy in a fixed integration window.

[0106] F. N-pass filter with energy detector

[0107] As shown in FIG. 7, an exemplary UWB receiver 700 according to an embodiment of the present invention is shown, in which an RF signal from an antenna 710 is first amplified by a low noise amplifier (LNA) 720 before being passed to a two-stage RF amplifier (AMP1) 730. A first squaring mixer (MIX1) 740 multiplies the signal by itself to convert it to an intermediate frequency (IF) before a three-stage variable gain amplifier (VGA) 750 further amplifies the signal. The VGA 750 output is then coupled to a second squaring mixer (MIX2) 760 which downconverts the signal to a baseband frequency, and parallel integrators (INT1 and INT2) sum the signal energy, which is digitized by analog-to-digital converters (ADC1 and ADC2) in a digital processor.

[0108] The squaring mixer (MIX2) 760, hereafter referred to as the squarer, performs squaring of the signal amplitude which, when integrated by a parallel integrator, produces the instantaneous energy of the received signal. Integration over a period of time results in the total energy of the symbols within that period. However, to reduce both the noise and the integrated energy of the interfering signals, the input signal needs to be filtered to restrict it to the band of interest. In the exemplary UWB receiver of FIG. 7, the VGA 750 provided this through a suitable design that provides a bandpass filtering function. However, it would be convenient to separate the amplification and filtering functions to allow for independent optimization of each, without substantial impact on power consumption and allowing for bandstop and bandpass filters.

[0109] Prior art filters usually present circuit designers with high power consumption and low quality factor, especially when intermediate frequency (IF) bandpass filters are required. Therefore, the inventors have established a design methodology based on combining a switched capacitor N-pass filter in front of a squarer. The N-pass filter that emerges is a bandpass or bandstop filter and is based on up / down conversion of a lowpass filter in a passive mixer structure. The quality factor can be high because the lowpass filter is upconverted to a higher frequency and the center frequency can be adjusted by the clock frequency. However, a drawback of N-pass filters is the high power consumption of the clock generator required to generate a high quality clock in a synchronous receiver structure. This makes this technology usually not very suitable for low power applications within the prior art.

[0110] However, the inventors have established a means to avoid the shortcomings of the N-path filter with respect to clock jitter, so that a low power clock generator can be used for the N-path filter rather than the prior art high power high precision (low jitter) clock generator associated with the N-path filter. The effect of clock jitter is to spread the energy of the input signal over a wider bandwidth, which reduces the in-band energy of the synchronous receiver. However, within an exemplary UWB receiver according to an embodiment of the present invention, when the N-path filter is paired with an asynchronous receiver, e.g., an energy detector as shown in FIG. 9, the entire energy of the signal is captured because the energy detector is not affected by the frequency spread of the N-path filter timing clock.

[0111] This technique can also be extended to systems that use the squarer as a self-mixer, for example to downconvert signals around DC. In this scenario, the N-path filter improves the selectivity of the squarer, but the clock generator may exhibit a mitigated amount of jitter and therefore consume less power.

[0112] F.1 Implementation Example

[0113] 13A and 13B, exemplary implementations of the present invention for both bandpass and bandstop variations are shown. Considering FIG. 13A, a receiver front end 1360 includes, for example, an antenna, an LNA, an RF amplifier, a first squaring mixer that multiplies the signal by itself to convert it to an intermediate frequency (IF) before a VGA further amplifies the signal. The output of the VGA is coupled to an N-pass filter 1310 driven by a clock generator (CLK Gen) 1320, the output of which is then coupled to a squarer 1330 and then to subsequent receiver circuitry including, for example, an integrator 1340. In FIG. 13B, the same general receiver circuit configuration is depicted, but the N-pass bandpass filter 1310 is replaced with an N-pass bandstop filter (NP-BS) 1350.

[0114] FIG. 14 shows an exemplary design of the NP-BP 1310 in accordance with one embodiment of the present invention. The filtered received signal, V IN are respectively coupled to N paths 1410A to 1410N. Each path is connected to an input switch S X1 (X=1, 2, . . . , N), filter F X (X=1, 2, . . . , N), and the output switch S X2 (X=1, 2, . . . , N). The outputs from N paths 1410A through 1410N are respectively combined to produce a filtered output V OUT , to provide a filter F X is a low-pass or band-pass filter.

[0115] The NP-BP shown in Figure 14 is illustrated in Figure 15A, showing the clock signals applied to each electrical switch and an exemplary RC filter design for each filter Fx. As shown, the input and output electrical switches are driven within each NP-BP 1510A to NP-BP 1510N, respectively, and are each driven by the same clock signal, e.g., CLK 0 Includes NP-BP 1510A, CLK 1 Including NP-BP 1510B, CLK N-1 Between each pair of switches, there is a resistor R connected in series between the pair of switches and a capacitor C connected in parallel to ground. x (X=1, 2, . . . , N). The clock signal is shown in FIG. 15B, while FIG. 15C shows a simplification of the first implementation where a single resistor R is placed before the split into N paths. FIG. 16 shows a further implementation simplification where the NP-BP is implemented as a single-sided design. Thus, the input is the clock signal CLK Y (Y=0, 1, . . . , N-1) and associated capacitor C x (X=1, 2, . . . , N). The output is now the common point between all the paths and the input.

[0116] An exemplary implementation of a squarer 1330 with a squaring mixer (SQ-MIX) 900 is shown in Figure 9. Since this is a differential squarer implementation, it can be coupled to a differential N-path filter as shown in Figure 17. Thus, a pair of NP-BP one-sided filters as shown in Figure 16 is shown, each including an input resistor R with N switches and a capacitor. In Figure 17N=4, the capacitor C 1 ;C 2 ;C 3 ;C 417, four parallel paths 1710A to 1710D with differential inputs 1710A to 1710D are shown, where the differential circuit uses a single capacitor coupled to each differential input by a switch. These switches are driven by the appropriate phases of clock signals shown as CLK(θ=0°); CLK(θ=90°); CLK(θ=180°); CLK(θ=270°). These clocks are generated by a four-stage clock generator 1720 from a differential clock coupled to it from a clock generator circuit.

[0117] FIG. 18 shows an equivalent bandstop filter design to that shown in FIG. 16, which now includes a capacitor Cx (X=1, 2, . . . , N) in series with a resistor R.

[0118] G.UWB Impulse Radio Ranging and Positioning

[0119] As mentioned above, distance measurement and location / localization are one aspect of many applications of devices / subsystems / systems / components that use UWB transceivers. Without utilizing UWB-based technology within such devices / subsystems / systems / components, additional hardware features must be provided, along with associated power consumption, to achieve the desired distance measurement and location / localization using another wireless technology, e.g., optical / RF / microwave based locally for internal applications, or global positioning system (GPS) / radio triangulation, covering both internal / external environments, and external environments with microwave / RF wireless systems such as Bluetooth, Wi-Fi, WiMAX, etc.

[0120] The inventors have therefore established two techniques utilizing the low power pulse based UWB transmitter / receiver / transceiver they developed in this patent application together with those described and illustrated in WO / 2016 / 191851 "Systems and Methods for Spectrally Efficient and Energy Efficient Ultra-Wideband Impulse Radios with Scalable Data Rates" and WO / 2015 / 103692 "Systems relating to Ultra-Wideband Broadcasting comprising Dynamic Frequency and Bandwidth Hopping", both of which are incorporated herein by reference.

[0121] F.1 Time of flight distance measurement (synchronous UWB transceiver pair)

[0122] The ranging system is described for a UWB communications link, leveraging an innovative energy detection scheme in combination with an exemplary 20 Mbps over-the-air data rate. It leverages the capabilities of the UWB transceiver's advanced synchronization scheme to ensure robust communication and tracking of pulse bundles, and uses a ranging scheme to "zoom in" on arrival.

[0123] In addition to the UWB transceiver / receiver, an integrated circuit (IC) implementation or hybrid implementation requires a ranging circuit as described and illustrated according to Figure 19. Depending on the desired ranging estimation tolerance / accuracy, a higher precision timing reference may be required to enable ranging estimation in the centimeter range.

[0124] A simplified version of the system block diagram and simplified pulse train is shown in FIG. 19. The incoming pulse train passes through a post antenna 1910 and through a low noise amplifier (LNA) 1920. A portion of the amplified received signal is coupled to a correlator circuit 1940 and the remainder propagates to the remainder of the receiver front end circuitry 1930. The correlator circuit 1940 correlates the received signal with a reference pulse provided by a reference pulse generator 1960 driven by a pulse generator 1970. The pulse generator 1970 is itself driven through a delay locked loop (DLL) 1990 that has approximately 50 taps spaced 0.5 ns apart for a nominal 20 Mb / s UWB system according to an embodiment of the invention established by the inventors. The DLL 1980 is driven by a precision reference clock 1990. The output from the correlator circuit 1940 is sent to a timer circuit.

[0125] Due to the construction of the pulse bundle, all pulses in the pulse train have different center frequencies, so only one pulse in the input pulse train will match the reference (or template) pulse. This means that a UWB energy detector receiver, such as that shown and described above with respect to embodiments of the present invention, can still derive the benefit of integrating the energy of a complete pulse train to increase communication range, while the ranging portion can "zoom in" on a single pulse to improve timing resolution.

[0126] An exemplary process according to an embodiment of the present invention would start with tap #1 and after each pulse bundle, the taps would be advanced until a correlation peak is established. The search space is greatly reduced because the energy detection receiver already knows the "location" of the pulse bundle to within 25 ns. This greatly reduces hardware complexity, search time, etc.

[0127] F1.1 Flight Algorithm Time

[0128] It is important to note that this exemplary algorithm according to an embodiment of the present invention assumes that the pair of UWB transceivers are already synchronized. For reference, a simplified timing diagram is shown in FIG. 20, and an exemplary process flow of the algorithm according to an embodiment of the present invention is shown in FIG. 21. It will be clear to one skilled in the art that many variations of this exemplary algorithm are possible. The basic accuracy depends on the accuracy of the reference available at the transceiver, and sub-nanosecond level accuracy / drift is recommended.

[0129] 21, the process includes steps 2105 to 2150. Steps 2105 to 2150 show the following: · Step 2105: Synchronize the UWB transceiver pair (UWB#1 and UWB#2). · Step 2110: UWB chip #1 transmits a packet consisting of a UWB pulse bundle. · Step 2115: The UWB chip #1 timer (TC1) is started during the transmission of the last pulse bundle. · Step 2120: UWB#2 receives the packet and the correlator circuit 1940 / DLL circuit 1990 locks onto the appropriate pulse. · Step 2125: UWB#2 starts a timer when the synchronization pulse in the last bundle is received.

[0130] Then steps 2130 through 2150 are performed, including the following: Step 2130: UWB#2 waits for a precise time known to both transceivers. (Note: Chip#2 knows when the last bundle occurs because it knows the packet length.) · Step 2135: After the correct waiting time, Chip #2 sends the same type of packet back to Chip #1. · Step 2140: Now chip #1 performs the same synchronization process. Step 2145: Chip #1 determines that the last bundle of packets has arrived and stops its TC1 timer to count the elapsed time, TC1 ELAPSEGenerate. · Step 2150: Chip #1 determines the time of flight (TOF) based on the following equation (1) and the ranging distance: TC1 ELAPSE = TOF + known wait time + TOF + packet length (1)

[0131] Optionally, chip #1 can stop the timer as soon as the correlator detects the appropriate pulse, and instead of using the "packet length" in the TOF calculation, it can use the "number of bundles before correlation", which reduces timing errors and the number of bundles is known from the transceiver's bit counter.

[0132] Steps 2110 to 2150 may be repeated to improve accuracy and provide an averaged result. Optionally, however, the length of the packets may be shortened since the pair of transceivers knows approximately which DLL taps to use. Thus, shorter packets mean less clock drift between the UWB transceivers.

[0133] F.2 Integrated Time Window Distance Measurement (Asynchronous UWB Transceiver Pair)

[0134] According to an embodiment of the present invention, a pair of UWB circuits, chip #1 and chip #2, may each transmit a UWB impulse that may be repeated based on the internal clock of each chip. Both chip #1 and chip #2 may receive UWB impulses from the transmitter of the other UWB circuit. The UWB circuits according to the method according to an embodiment of the present invention recognize the arrival of a UWB impulse by integrating the incoming signal energy within integration time windows defined as PW1 and PW2 of chip #1 and chip #2, respectively. These integration windows are based on the internal clock of each chip, and PW2 is a bit longer than PW1 because chip #1 has a slightly different internal clock than chip #2. Therefore, the two chips must not be synchronized.

[0135] Referring to FIG. 22, there is shown an exemplary process flow for the integral time window method of distance measurement with a timing diagram shown in FIG.

[0136] The algorithm comprises the following steps 2210 to 2280: · Step 2210: Chip #1 transmits a UWB impulse (the first timing 2300A in FIG. 23 shows this impulse energy versus time). · Step 2220: After a time, ΔT (proportional to the distance between the two chips), the impulse reaches chip #2 (second timing 2300B in Figure 23). · Step 2230: To detect this impulse, Chip#2 integrates the energy of the input signal within an integration time window (third timing 2300C in FIG. 23). · Step 2240: If the energy within the integration time window is greater than the threshold, it is assumed that an impulse arrives at chip #2 and at the start of the next integration window, chip #2 sends an echo signal back to chip #1 (fourth timing 2300D in FIG. 23). Step 2250: After a time ΔT has elapsed, this echo impulse reaches chip #1 (fifth timing 2300E in FIG. 23). · Step 2260: Chip #1 integrates the energy of the input signal within its own integration window (sixth timing 2300F). · Step 2270: This integrated energy is passed to a digital signal processor (DSP) and combined with chip #1 to estimate ΔT. · Step 2280: Steps 2210 to 2270 may be repeated multiple times and the estimated ΔT is averaged to reduce its uncertainty.

[0137] Flight Time with F2.1 Digital Signal Processing:

[0138] Within many ranging algorithms, the time difference (ΔT) between the transmitted signal and the received echo is used to measure the time of flight (TOF) of the signal. This time of flight is proportional to the distance between the transmitter and the echo generator. However, within the proposed algorithm presented below, the time difference is not measured directly, but is derived via a digital signal processing algorithm. This algorithm exploits the fact that when an echo signal is received, its energy is distributed into two consecutive integration time windows, as shown in the sixth graph 2300F of FIG. 23. The exact arrival time of the echo signal can be estimated by processing the proportion of the energy integrated in each of these two time slots, which are called E1 and E2, respectively. For example, if the energies are equal, i.e., E1=E2, this means that the signal arrived exactly in the middle of the first time slot. Using a linear approximation, it can be shown that the estimated arrival time is given by equation (2), where PW1 is the width of the time slot.

number

[0139] Therefore, the time difference ΔTOA must be measured accurately and this time must be related to ΔT. As shown in Figure 23, this time difference ΔTOA consists of two time slots: the time between the transmitted signal and the echo signal (ΔT12) and the echo signal at chip #2 and the received signal at chip #1 (ΔT).

[0140] Calculation of ΔT12: If the received signal of chip #2 (third graph 2300C of FIG. 23) arrives exactly at the beginning of the integration time window, ΔT12 is equal to ΔT+PW2, otherwise it is a random variable with a uniform distribution between ΔT+0.5PW2 and ΔT+1.5PW2 due to the lack of synchronization between chip #1 and chip #2. Therefore, ΔTOA has a mean value of 2×ΔT+PW2. Therefore, by repeating the algorithm and measuring and averaging ΔTOA for many samples, ΔT can be estimated.

[0141] Specific details are given in the above description to provide a thorough understanding of the embodiments. However, it is understood that the embodiments can be practiced without these specific details. For example, circuits may be shown in block diagrams in order to avoid obscuring the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments.

[0142] The implementation of the above techniques, blocks, steps, and means may be performed in various ways. For example, these techniques, blocks, steps, and means may be implemented in hardware, software, or a combination thereof. In the case of hardware implementation, the processing unit may be implemented in one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, other electronic units designed to perform the above functions, and / or combinations thereof.

[0143] Also, it is noted that the embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process is terminated when its operations are completed, but may have additional steps not included in the diagram.

[0144] The foregoing disclosure of exemplary embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many variations and modifications of the embodiments described herein will be apparent to those skilled in the art in light of the above disclosure. The scope of the present invention is defined only by the claims appended hereto and their equivalents.

[0145] Furthermore, in describing representative embodiments of the present invention, the specification may present the method and / or process of the present invention as a particular sequence of steps. However, unless the method or process relies on the particular order of steps described herein, the method or process should not be limited to the particular order of steps described. As one of ordinary skill in the art will appreciate, other orders of steps may be possible. Thus, the particular order of steps described herein should not be construed as a limitation of the claims. In addition, claims regarding the method and / or process of the present invention should not be limited to performing those steps in the order described, as one of ordinary skill in the art may readily appreciate that the order may be changed and still be within the spirit and scope of the invention.

Claims

1. 1. A method comprising: establishing range between a pair of ultra-wideband (UWB) transceivers, the pair including a first UWB transceiver and a second UWB transceiver, using a process performed on the first UWB transceiver and a second UWB transceiver, the method comprising: the process having one of a first configuration, a second configuration, and a third configuration; In the first configuration, the process is performed by a digital signal processor (DSP) of the first transceiver, the DSP being coupled to a synchronization circuit including a detector circuit and a correlator circuit; The DSP executes other processes, including: transmitting a first packet including a plurality of UWB pulse bundles; starting a first timer associated with a transmission of a last pulse bundle of the plurality of UWB pulse bundles; processing a plurality of other UWB pulse bundles forming a second packet received from the second UWB transceiver; synchronizing to a predetermined pulse within a last pulse bundle of the plurality of other UWB pulse bundles of the second packet using the synchronization circuitry; stopping the first timer upon determining detection of the predetermined pulse; and Calculating a flight time according to an elapsed time of the first timer; In the second configuration, the process includes establishing a timing reference process on the first UWB transceiver using a correlator circuit forming part of the first UWB transceiver in response to processing UWB pulse bundles received from the second UWB transceiver; the correlator circuit comprises a reference pulse generator driven by a signal from a pulse generator to correlate a portion of the UWB pulse bundle received by the first UWB transceiver with a reference pulse sequence to generate a reference pulse sequence, the pulse generator being driven through a delay locked loop (DLL) including a plurality of taps spaced at a predetermined time offset from one another, the DLL being driven by a precision reference clock; At least one of the following: the predetermined time offset of the plurality of taps from one another and the number of taps within the plurality of taps are established depending on at least one of a nominal data rate for communication between the first UWB transceiver and the second UWB transceiver and a duration of the UWB pulse bundle. And the timing reference process advances which of the plurality of taps from the DLL are used by the pulse generator in driving the reference pulse generator to generate the reference pulse sequence until a correlation peak is established in the correlator. In the third configuration, the process includes establishing a timing reference process on the first UWB transceiver using a correlator circuit forming part of the first UWB transceiver in response to processing UWB pulse bundles received from the second UWB transceiver; the first UWB transceiver comprises a tap including an input port for receiving the UWB pulse bundle received from the second UWB transceiver, a first output port connected to the correlator circuit, and a second output port connected to an energy detector circuit for converting the received UWB pulse bundle into data; the timing reference circuit and said energy detector circuit operate simultaneously; A method, wherein an output of the timing reference circuit is used in establishing timing information for establishing range between the pair of Ultra-Wideband (UWB) transceivers.

2. In the first configuration, the second UWB transceiver comprises another digital signal processor (DSP) coupled to another detector circuit and to another synchronization circuit including another correlator circuit and another delay locked loop; The other DSP executes other processes, including: processing the plurality of UWB pulse bundles of the first packet; synchronizing to another predetermined pulse within a last pulse bundle of the plurality of UWB pulse bundles of the first packet using a second synchronization circuit; starting a second timer upon determining detection of the other predetermined pulse; and transmitting the second packet when the second timer reaches a predetermined waiting time; The method of claim 1.

3. In each of the first, second and third configurations, each UWB pulse bundle represents a single symbol of a data signal and includes a plurality of N pulses; each pulse of the N pulses is at a predetermined frequency among a plurality of M frequencies, has a predetermined amplitude, and has a predetermined pulse length; The method of claim 1 , wherein N and M are each a positive integer greater than or equal to 2.

4. In each of the first, second and third configurations, each UWB pulse bundle of the UWB pulse bundles transmitted by a first UWB transmitter represents a single symbol of a data signal and includes a plurality of N pulses, and each UWB pulse bundle of the UWB pulse bundles received by the first UWB transmitter represents a single symbol of another data signal and includes a plurality of R pulses; each pulse of the N pulses is at a predetermined frequency among a plurality of M frequencies and has a predetermined amplitude and a predetermined pulse length; each pulse of the R pulses is at a predetermined frequency from a plurality of S frequencies and has a predetermined amplitude and a predetermined pulse length; The method of claim 1 , wherein N, M, R, and S are positive integers greater than or equal to 2.

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