Phased array antenna device

Abstract

To provide a phased array antenna device that achieves high spatial resolution even with a small number of antenna elements.SOLUTION: A phased array antenna device includes: a plurality of real elements 101r and 201r; a signal processing unit 20 that is provided for each of the real elements and converts an analog signal received by the real element into data of a digital signal; a data processing unit 30 that is provided for each of the real elements for performing delay processing based on the positions of the real element and a virtual element and an orientation direction relative to data output from the signal processing unit 20 for each of virtual elements 101a to 101c, 201a to 201c that are assumed to be located within a predetermined range of the real elements; and an addition unit 40 for performing addition processing of data after the delay processing of the plurality of real elements and data after the delay processing of the plurality of virtual elements.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a phased array antenna device mainly for receiving microwaves. [Background technology]

[0002] Conventionally, the technology of narrowing the directional range (beam width) of an antenna receiving radio waves and continuously changing the directional direction is essential for obtaining the distribution of observation quantities with high spatial resolution, for example in microwave remote sensing. Specific methods of this technology include (1) rotating the reflector on which the antenna is attached, and (2) forming a phased array antenna with multiple antenna elements and combining the received signals from each antenna element with a time lag according to the directional direction.

[0003] In the case of satellite observations, a high spatial resolution is desirable in order to obtain a highly detailed distribution of observed quantities. Visible light or infrared rays, which have a much higher frequency (shorter wavelength) than radio waves, can obtain the intensity distribution of observed signals with a maximum spatial resolution of several meters even with conventional technology. However, even if visible light or infrared rays are used, it is not possible to obtain the intensity distribution of observed signals for information on objects below clouds, or for information on objects at night in the case of visible light.

[0004] On the other hand, compared to visible light or infrared rays, radio waves have a longer wavelength, so it is possible to obtain the intensity distribution of objects under clouds or at night, depending on the spatial resolution of the antenna. However, conventional technologies using radio waves have a problem with low spatial resolution. For this reason, there has been a demand to improve the spatial resolution and solve the problems of conventional technologies.

[0005] As the phased array antenna device of (2) above, the applicant has proposed a phased array antenna device described in Patent Document 1. Patent Document 1 states that "The phased array antenna device performs A / D conversion directly on the analog signal of the antenna amplified by the amplifier via a BPF. Then, after converting it into complex frequency data by FFT, it performs cross-spectrum calculation. In order to detect weak electromagnetic waves, the FFT is repeatedly executed over a long period of time, and finally, it is integrated." [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication No. 2021-93679 Summary of the Invention [Problem to be solved by the invention]

[0007] To observe the strength of radio waves with high spatial resolution, (1) requires a large rotating reflector, and (2) requires many antenna elements. In either case, the system becomes bulky and long, which not only increases manufacturing costs but also limits the environment in which the system can be installed.

[0008] The present invention has been made in consideration of the above circumstances, and has an object to provide a phased array antenna device that can achieve high spatial resolution even with a small number of antenna elements. [Means for solving the problem]

[0009] In order to solve the above problems, a phased array antenna apparatus according to one aspect of the present invention includes a plurality of actual antenna elements, a signal processing unit, a data processing unit, and an adder. The signal processing unit is provided for each real antenna element and converts an analog signal received by the real antenna element into a digital signal (digital data). The data processing unit performs delay processing on the digital data output from the signal processing unit for each virtual antenna element and real antenna element that is assumed to be located within a predetermined range of the real antenna element provided for each real antenna element, based on the positions and directivity of the real antenna element and virtual antenna element. The adder performs addition processing of the digital data after delay processing of the multiple real antenna elements and the digital data after delay processing of the multiple virtual antenna elements. Effect of the Invention

[0010] According to at least one aspect of the present invention, it is possible to provide a phased array antenna device capable of achieving high spatial resolution even with a small number of antenna elements. Problems, configurations and effects other than those described above will become apparent from the following description of the embodiments. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram for explaining the technical concept of the present invention. [Diagram 2] FIG. 1 is a diagram illustrating an example of a phased array antenna device having an A / D conversion function. [Diagram 3] 1A and 1B are diagrams for explaining the path difference and delay time of signals arriving from the directivity directions between two antenna elements. [Figure 4] 1 is a diagram illustrating an example of the configuration of a phased array antenna apparatus according to a first embodiment of the present invention. [Diagram 5] 2 is a block diagram showing an example of a hardware configuration of a controller included in the phased array antenna apparatus according to the first embodiment of the present invention. FIG. [Figure 6] FIG. 11 is a diagram illustrating an example of the configuration of a phased array antenna apparatus according to a second embodiment of the present invention. [Figure 7] FIG. 11 is a diagram illustrating an example of the configuration of a phased array antenna apparatus according to a third embodiment of the present invention. [Figure 8] Fig. 8A is a diagram showing an example of an array antenna using a plurality of actual antenna elements, and Fig. 8B is a diagram showing an example of a beam pattern using the array antenna of Fig. 8A. [Figure 9] Fig. 9A is a diagram showing an example of an array antenna in which multiple virtual antenna elements are introduced around one real antenna element, and Fig. 9B is a diagram showing an example of a beam pattern by the array antenna of Fig. 9A. [Figure 10] Fig. 10A is a diagram showing an example of an array antenna in which a plurality of virtual antenna elements are introduced around each of a plurality of real antenna elements, and Fig. 10B is a diagram showing an example of a beam pattern by the array antenna of Fig. 10A. [Figure 11] Fig. 11A is a diagram showing an example of an array antenna using multiple real antenna elements and a simulation result of a beam pattern using the array antenna. Fig. 11B is a diagram showing an example of an array antenna using multiple real antenna elements and a simulation result of a beam pattern using the array antenna. [Figure 12] Fig. 12A is a diagram showing an example of an array antenna using multiple real antenna elements, and the results of actual measurement of power count values ​​using the array antenna. Fig. 12B is a diagram showing an example of an array antenna using multiple virtual antenna elements around each of multiple real antenna elements, and the results of actual measurement of power count values ​​using the array antenna. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, examples of modes for carrying out the present invention (hereinafter referred to as "embodiments") will be described with reference to the accompanying drawings. In this specification and the accompanying drawings, identical components or components having substantially the same functions are given the same reference numerals, and duplicated explanations will be omitted. Furthermore, when there are multiple components having the same or similar functions, they may be described with the same reference numerals given different suffixes. Note that when it is not necessary to distinguish between these multiple components, the suffixes may be omitted in the description.

[0013] <First embodiment> A phased array antenna device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 5. FIG.

[0014] [Technical idea of ​​the present invention] First, the technical concept of the present invention will be described with reference to FIG. As shown in Figure 1, the actual antenna element E i On the other hand, a virtual antenna element E i,j Define the antenna element E as follows: i and antenna element E i,j The path difference δ is expressed by the following equation (1): Hereinafter, an antenna element that actually exists will be referred to as a "real element," and a virtual antenna element that does not actually exist will be referred to as a "virtual element."

[0015]

number

[0016] In the present invention, the real element E i The received signal is delayed by δ / c and the signal is i,j The signal is processed assuming that it was received by the signal generator. In order to accurately delay and synthesize the received signals, the digital signals obtained by analog-to-digital (A / D) conversion of the received signals are processed. Here, the limit of the magnitude of the baseline vector a can be expressed as the following equation (2).

[0017]

number

[0018] If the sampling speed (SPS: Samples Per Second) of the A / D converter can be made faster, that is, if the sampling interval T can be made shorter, it is possible to obtain the limit of the delay time δ / c (the circle indicated by the dashed line in FIG. 1) with high accuracy. For example, in the phased array antenna apparatus according to this embodiment, the sampling speed and sampling interval of the A / D conversion have the following values.

[0019] A / D conversion sampling rate: F=27.648×10 9 [SPS](27.648[GSPS]) A / D conversion sampling interval: T=1 / F=1 / (27.648×10 9 )

[0020] [Phased array antenna device with A / D conversion function] Next, a phased array antenna device having an A / D conversion function will be described with reference to FIG.

[0021] FIG. 2 is a diagram illustrating an example of a phased array antenna device equipped with an A / D conversion function. As shown in Figure 2, the group of antenna elements (▽ symbols) that make up the array antenna are arranged with reference to the antenna element at the origin O. Here, an example is shown of four antenna elements, but the number of antenna elements is not limited to this example.

[0022] In the example of Fig. 2, the distances from this reference antenna element to the other antenna elements are b1 to b3, respectively. It can also be said that the distances b1 to b3 represent the positional relationship between the reference antenna element and the other antenna elements. In addition, in the directional direction R(θ,φ), the path difference between the reference antenna element and an antenna element located at a distance b2 is d2, and the path difference between the reference antenna element and an antenna element located at a distance b3 is d3. θ is the azimuth angle, and φ is the elevation angle.

[0023] In a phased array antenna device, after A / D conversion of the received signal by each antenna element, the path difference d according to the directivity direction R (θ, φ) is calculated for the digital data of each received signal (hereinafter, received data). n The delay-added (direction-controlled) received data is subjected to a fast Fourier transform (FFT) as a frequency analysis process (g0 to g3).

[0024] After that, the phased array antenna device performs voltage addition using output data (spectral component data) obtained by performing a fast Fourier transform on each received data. Although not shown in the figure, for two FFT output data (e.g., g0, g1), for each of the same complex frequency components, one of the data is converted to a complex conjugate number and then multiplied.

[0025] Then, the phased array antenna device performs an addition process (correlation process) of each output data (cross-spectrum component data) obtained by the multiplication process. This corresponds to adding (correlation process) the received signal voltages of the antennas. Note that a method of voltage addition process in such a phased array antenna device is well known, as described in Patent Document 1.

[0026] The phased array antenna device performs power conversion (integration processing) on ​​each output data (voltage spectrum component data) obtained by the addition processing. Here, autocorrelation processing of the voltage spectrum component data is performed. "Autocorrelation" is a process that finds the correlation between a certain waveform (data) and the same corresponding waveform (data), and is a process that multiplies the value of a certain waveform by the value of the same waveform (if it is a complex number, its conjugate complex number) at all times.

[0027] When an antenna element receives power (energy), a voltage corresponding to the power is applied to the antenna element. Therefore, a voltage is also applied to the receiving circuit located after the antenna element, and a corresponding current flows, so Current x Voltage = (Voltage 2 / resistance) to get the power.

[0028] As described above, the Fourier transform is applied to the time series signal that is the digitalized version of the voltage flowing through the receiving circuit. As a result of the Fourier transform, complex Fourier coefficients corresponding to each frequency component of the voltage are obtained. At this time, the tangent of the complex Fourier coefficients corresponding to each frequency component of the voltage is -1 (Imaginary part / Real part) represents the phase at the moment when the Fourier transform is performed. Note that the power of each frequency component of the voltage is constant at the moment when the Fourier transform is performed. This is because, among the characteristics of complex numbers (phase, norm), norm = (real part 2 +imaginary part 2 This corresponds to the fact that σ = (real part + imaginary part) × (real part - imaginary part) is invariant regardless of phase.

[0029] From the above, obtaining the autocorrelation of the complex Fourier coefficients (=complex voltage spectrum component data) related to all frequency components of the voltage of the received signal is equivalent to obtaining power spectrum component data (all frequency components of power). Moreover, the power spectrum component data can be obtained by obtaining the norm of the complex voltage spectrum component data, that is, "(real part+imaginary part)×(real part−imaginary part)" of the complex voltage spectrum component data. Here, the power spectrum component data is also called the antenna reception power spectrum. Such a method of power conversion processing in a phased array antenna device is well known, as described in Patent Document 1.

[0030] After power conversion, the phased array antenna device performs time integration of the antenna reception power spectrum and performs brightness temperature calibration processing to obtain a brightness temperature spectrum for each pointing direction R(θ,φ). In general, thermal temperature (T) is expressed as the brightness temperature (T B ) is different from

[0031] Time integration is the process of sequentially adding up the power spectrum obtained from one Fourier transform. This weakens the drastic changes in power due to time changes, leaving only the gradual changes in power due to time changes. For example, it takes about 3.6 ns to A / D convert the received signal at 27.648 GSPS to obtain 1024 points of data. From here, it takes several ns (6.4 ns here) to perform a Fourier transform on that data, calculate the autocorrelation, turn it into power spectrum component data, and store it in a register (memory). In other words, if the time required for one Fourier transform is 10 ns, and the integration time is 1 second, the power spectrum will be added up 10 million times.

[0032] In a phased array antenna device, the voltage received by the antenna elements is actually amplified by an amplifier (e.g., an LNA (Low Noise Amplifier)) several times before being A / D converted, so the resulting power spectrum contains the characteristics of the amplifier. This is called the "power count value spectrum" and is different from the "power spectrum" received by the antenna elements. This power count value spectrum corresponds to the power count value in Fig. 12, which will be described later.

[0033] To obtain the power spectrum received by the antenna element, a procedure is required to convert the power count value spectrum, which is called the calibration process. B ) is T B =P / kB (k: Boltzmann constant, B: bandwidth). For example, if the received signal is A / D converted at 27.648 GSPS to obtain 1024 points of data, and then Fourier transformed, the spacing between adjacent spectra is 27.648×10 9 / 1024=27×10 6 Hz = 27MHz. Therefore, the brightness temperature (T B ) is 300K, the power received by the antenna element (P) is kB·T B =1.1 10 -11 W. This is different from the power count value, which includes amplifier characteristics.

[0034] As such, since the power received by an antenna element is an extremely small value and difficult to handle, brightness temperature is used instead. To find the power received by an antenna element (=brightness temperature spectrum) from the power count value, two known "brightness temperature - power count value" relationships are prepared, and this relationship is interpolated and / or extrapolated to convert any power count value into the corresponding brightness temperature. An absorber with a known thermal temperature also has a known brightness temperature. For example, the brightness temperature of an absorber (terminator on the receiving circuit) with a thermal temperature of 100K is 100K, and if the thermal temperature is 400K, the brightness temperature is 400K.

[0035] Unlike general wireless communication, microwave radiometers, and the like, a phased array antenna device equipped with such an A / D conversion function is capable of detecting weak electromagnetic waves in an extremely wide frequency range for each frequency component. In addition, since a phased array antenna device equipped with an A / D conversion function does not use any mechanically moving parts, it has a longer life than an antenna device that uses mechanically moving parts. In addition, since a phased array antenna device equipped with an A / D conversion function does not need to be rotated, the size of the device can be made larger more easily than an antenna device that uses mechanically moving parts. This is advantageous in terms of the spatial resolution of the antenna device.

[0036] As described above, a phased array antenna device equipped with an A / D conversion function is also disclosed in Patent Document 1.

[0037] [Path difference of signals arriving from the direction of direction between antenna elements] Next, the path difference and delay time of signals arriving from the directivity directions between two antenna elements will be described with reference to Fig. 3. For simplicity, the description will be given using two antenna elements.

[0038] FIG. 3 is a diagram for explaining the path difference and delay time of a signal arriving from the direction of directivity between two antenna elements. In the figure, the first element corresponds to a real element, and the second element corresponds to a virtual element. If the path difference of a signal from the direction of directivity between two antenna elements is δ, and the time (delay time) required for a received signal to travel the path difference δ is t=δ / c, then the sampling interval T=1 / F=1 / (27.648×10 9 According to [SPS], the delay time t can be expressed by the following equation (3), where n is the number of samples of the sampling clock, and nT is the sample delay (also called bit delay).

[0039]

number

[0040] The signal received by the second element is delayed by a delay time t and combined with the signal received by the first element. The signal of frequency f advances in phase by 2πfτ over time τ. Therefore, the signal of the second element delayed by n samples is decomposed into a spectrum by FFT, and each frequency component is assigned e j2πfτ By multiplying this by the phase slope, the signal (each frequency component) of the second element delayed by the delay time t can be obtained. The time τ is set to be shorter than the sampling interval T. The time τ makes it possible to adjust the fractional time of the delay time t that cannot be adjusted by the sample delay nT.

[0041] [Configuration of phased array antenna device] Next, a configuration of a phased array antenna device according to a first embodiment of the present invention, in which the technical idea shown in FIGS. 1 to 3 is implemented, will be described with reference to FIG.

[0042] Fig. 4 is a diagram showing a configuration example of a phased array antenna apparatus according to the first embodiment of the present invention. The phased array antenna apparatus 400 shown in Fig. 4 includes an antenna element group 10, a signal processing unit 20, a data processing unit 30, a clock control unit 107, delay pattern data 108, a voltage addition unit 40, and a power conversion unit 50. The data processing unit 30, the clock control unit 107, and the delay pattern data 108 are included in a controller 500. The hardware configuration of the controller 500 will be described later with reference to Fig. 5.

[0043] The antenna element group 10 includes a plurality of real antenna elements (hereinafter, real elements) and a plurality of virtual antenna elements (hereinafter, virtual elements) arranged around them, and is divided into groups for each real element. If there are 14 real elements, 14 groups are formed. In Fig. 4, group G1 of real element 1 includes real element 101r (real element 1) and virtual elements 101a to 101c (virtual elements 1 to 3 of real element 1).

[0044] Moreover, group G2 of real element 2 includes real element 201r (real element 2) and virtual elements 201a-201c (virtual elements 1-3 of real element 2). In Fig. 4, the virtual elements, as well as virtual circuits and processing units, are indicated by dashed lines. In the following, group G1 of real element 1 will be described, since group G1 of real element 1 and group G2 of real element 2 have the same configurations of signal processing unit 20 and data processing unit 30.

[0045] The signal processing unit 20 includes a receiving circuit (RC in the figure) 102r and an A / D converter 103r, and converts the signal received through the real element 101r into digital data. A signal processing unit 20 is provided for each real element. In the group G1 of the real element 1, the signal processing unit 20 includes a receiving circuit 102r that receives the radio waves that reach the real element 101r, and an A / D converter 103r. The signal processing unit 20 also includes virtual receiving circuits 102a to 102c that receive the radio waves that reach the virtual elements 101a to 101c, and virtual A / D converters 103a to 103c.

[0046] The virtual elements 101a to 101c, the virtual receiving circuits 102a to 102c, and the virtual A / D converters 103a to 103c do not actually exist. Software processing in the data processing unit 30, which will be described later, is performed as if the virtual elements 101a to 101c, the virtual receiving circuits 102a to 102c, and the virtual A / D converters 103a to 103c existed.

[0047] The receiving circuit 102r (RC in the figure) is composed of, for example, a preamplifier such as an LNA and a BPF (Band-Pass Filter). The A / D converter 103r (A / D in the figure) digitizes an analog input signal and outputs it to the subsequent data processing unit 30. Note that in the signal processing unit 20, a register or memory may be provided subsequent to the A / D converter 103.

[0048] The data processing unit 30 applies frequency analysis processing and delay processing to the digital data of the received signal of each antenna element output from the signal processing unit 20, and outputs the result to the voltage adding unit 40. A data processing unit 30 is provided for each real element. In the group G1 of the real element 1, the data processing unit 30 includes sample delay units 104r, 104a to 104c to which data of the signal received by the real element 101r is input, FFTs 105r, 105a to 105c, and slope adding units 106r, 106a to 106c. The processing of the data processing unit 30 is controlled by a clock control unit 107. The data processing unit 30 performs "sample delay" and "slope addition" on the data corresponding to the signal of the virtual element.

[0049] The data processing unit 30 performs delay processing for each real element and virtual element by applying a delay time corresponding to the path difference (FIG. 2) between the signal arriving at the reference real element and the signal arriving at the real element and virtual element.

[0050] The clock control unit 107 provides a time shift (delay) to the timing of supplying the sampling clock to the data processing unit 30 according to the target direction (direction) in which the phased array antenna device 400 receives radio waves.

[0051] When scanning a target area that is preset or manually specified, the clock control unit 107 reads a delay time t(n, τ) from the delay pattern data 108 for each directivity direction (θ, φ). Then, the clock control unit 107 notifies the sample delay units 104r, 104a to 104c of the number of samples n to be delayed, and the slope adding units 106r, 106a to 106c of the time τ. In this embodiment, the time τ is shorter than the sampling interval T. In the same manner, the clock control unit 107 also performs clock control for group G2 of the real element 2 and other groups.

[0052] The delay pattern data 108 is map information (table) that defines the correspondence between the directivity direction (azimuth angle θ, elevation angle φ) and delay time t(n, τ) for each real element and virtual element of the antenna element group 10. When the distance from a reference real element to other real elements and surrounding virtual elements is different, the delay time t of the received signal of the other real elements and surrounding virtual elements from the reference real element changes, and when the distance from the reference real element to the other real elements and surrounding virtual elements is the same, the delay time t does not change.

[0053] The sample delay units 104r, 104a to 104c perform sample delay processing based on the positions and directivity directions (θ, φ) of the real elements 101r and the virtual elements 101a to 101c, which are assumed to be arranged within a predetermined range of the real element 101r, for the data of the real elements output from the signal processing unit 20 for each of the virtual elements 101a to 101c and the real element 101r. In the sample delay unit 104, the signal of each virtual element is considered to be the same as the signal received by the real element. In this embodiment, the sample delay unit 104 performs delay processing on the digital data before the fast Fourier transform of the signal received by the real element 101r, based on the sample delay nT notified from the clock control unit 107.

[0054] The above-mentioned predetermined range of real elements is a range in which the output of the grating lobe is equal to or less than a predetermined threshold value (such as 10%) relative to the output of the main lobe in a beam pattern obtained by adding together data obtained from a real element and virtual elements arranged around it. In general, when the output of the grating lobe is equal to or less than 10% relative to the main lobe, a certain level of quality can be expected for the beam pattern. By virtually arranging each virtual element around the real element under such conditions, the signal of each virtual element can be regarded as the same as the signal received by the real element. Therefore, the signal received by the real element can be used to perform signal processing on the virtual element as if it actually exists.

[0055] The FFT 105r, 105a to 105c performs frequency analysis by applying a fast Fourier transform to the delayed data output from each of the sample delay units 104r, 104a to 104c. The FFT may be realized by hardware, for example, by designing an integrated circuit. For example, a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) may be used as the hardware.

[0056] The slope adding units 106r, 106a to 106c perform a slope adding process to add a phase slope to the spectral component data output from the FFTs 105r, 105a to 105c. The slope adding units 106r, 106a to 106c add a phase slope e to each spectral component data after the fast Fourier transform based on the time τ notified by the clock control unit 107. j2πfτ Add.

[0057] Group G2 of real elements 2 also includes an antenna element group 10, a signal processing unit 20, and a data processing unit 30. In group G2 of real elements 2, antenna element group 10 includes, for example, real element 201r (real element 2) arranged adjacent to real element 101r, and virtual elements 201a to 201c (virtual elements 1 to 3 of real element 2).

[0058] In the group G2 of the real element 2, the signal processing unit 20 includes a receiving circuit (RC in the figure) 202r and an A / D converter 203r. In the group G2 of the real element 2, the data processing unit 30 includes sample delay units 204r, 204a to 204c to which the data of the signal received by the real element 201r is input, FFTs 205r, 205a to 205c, and slope adding units 206r, 206c to 206c.

[0059] 4, the data processing unit 30, the clock control unit 107, and the delay pattern data 108 are included in the controller 500. On the other hand, the data processing unit 30, the clock control unit 107, and the delay pattern data 108 may be configured separately from each other, or the data processing unit 30 may include the clock control unit 107 and the delay pattern data 108. That is, the clock control function of the clock control unit 107 and the data processing function of the data processing unit 30 are implemented in the controller 500.

[0060] [Controller hardware configuration] Here, the hardware configuration of the controller 500 included in the phased array antenna device 400 will be described with reference to FIG.

[0061] Fig. 5 is a block diagram showing an example of a hardware configuration of the controller 500. The controller 500 can be configured using an FPGA, for example. As shown in Fig. 5, the controller 500 includes, for example, a processor 501, a memory 502, a non-volatile storage 503, and an input / output interface 504. Each block can transmit and receive data to and from each other via a system bus. The configuration of the controller 500 is an example of hardware used as a computer.

[0062] The processor 501 reads out program code of software for realizing each function according to this embodiment from the non-volatile storage 503, loads it into the memory 502, and executes it. Variables, parameters, etc. generated during the arithmetic processing of the processor 501 are temporarily written into the memory 502, and these variables, parameters, etc. are read out as appropriate by the processor 501. The processor 501 executes the program code read into the memory 502, thereby realizing the clock control function and data processing function of the controller 500.

[0063] The nonvolatile storage 503 is an example of a non-transient recording medium, and is capable of storing data used by a program, data obtained by executing a program, etc. The delay pattern data 108 is configured using the nonvolatile storage 503. As the nonvolatile storage 503, a hard disk drive (HDD), a solid state drive (SSD), a disk medium using light or magnetism, a semiconductor memory card, etc. are used.

[0064] A communication device such as a network interface card (NIC) is used as the input / output interface 504. The input / output interface 504 is configured to be capable of transmitting and receiving various data between the signal processing unit 20 and an external device via a communication network such as the Internet. The hardware configuration of the controller 500 included in the phased array antenna device 400 has been described above.

[0065] Returning to Fig. 4, the explanation will be continued. The data processing unit 30 shown in Fig. 4 delays the data of a signal received at a certain real element by n samples with a sampling interval of T in consideration of the delay time relative to the data of the signal received at a reference real element using the sample delay unit 104, and then performs a Fourier transform using the FFT 105. The data processing unit 30 then uses the spectral component data obtained by subjecting the signal data of the real element to a Fourier transform using the FFT 105 as the spectral component data of the virtual element.

[0066] Then, the data processing unit 30 adds the output data obtained by performing the Fourier transform in the FFT 105 by the voltage adder unit 40 to obtain a complex voltage spectrum for each frequency component. The voltage adder unit 40 adds the data after delay processing of the multiple real elements and the data after delay processing of the multiple virtual elements in each group output from the data processing unit 30.

[0067] Furthermore, the data processing unit 30 obtains a power spectrum by adding up the complex voltage spectra and taking the autocorrelation using the power conversion unit 50. This power spectrum represents the sum of the power received from all the directing directions where the path difference between the reference real element and the other real elements is the sample delay nT.

[0068] In this embodiment, for a group of virtual elements belonging to a certain group of real elements, the same number of samples n as that of the real element is used during sample delay processing. In other words, for the delay time t defined as t = nT + τ, the same sample delay nT is applied to the real element and the group of virtual elements around it, and an appropriate delay time t is given to the data of each element according to the time τ within the range not exceeding the limit of the size of the vector a (Figure 1).

[0069] In this way, multiple virtual elements are placed around one real element at positions where the path difference between each element is different within the range of the delay time limit, thereby realizing a phased array antenna device with high spatial resolution.

[0070] According to this embodiment having such a configuration, it is possible to reduce the area in which the antenna elements constituting the phased array antenna device can be installed, and therefore it is possible to install the phased array antenna device of this embodiment even on a small satellite that has restrictions on mass and the upper limit of the power supply.

[0071] For example, the phased array antenna device 400 can achieve a sharp beam width similar to that of a conventional phased array antenna device that requires many antenna elements. Therefore, when the phased array antenna device of this embodiment is used for satellite observation, high spatial resolution observation is achieved.

[0072] As described above, the phased array antenna apparatus according to the first embodiment includes a plurality of real antenna elements, a signal processing unit (signal processing unit 20) provided for each real antenna element, which converts an analog signal received through the real antenna element into a digital signal and outputs data of the signal, a data processing unit (data processing unit 30) provided for each real antenna element, which is assumed to be located within a predetermined range of the real antenna element, and a data processing unit (data processing unit 30) which performs delay processing on data output from the signal processing unit based on the position and directivity of the real antenna element or the virtual antenna element, and an adder (voltage adder 40) which adds the data after the delay processing of the plurality of real antenna elements and the data after the delay processing of the plurality of virtual antenna elements.

[0073] More specifically, the data processing unit (data processing unit 30) according to this embodiment includes a first delay unit (sample delay units 104r, 104a to 104c, 204r, 204a to 204c) that performs sample delay processing using a sampling interval T and a sample number n on the data of the signal received by the real antenna element and output from the signal processing unit, and a second delay unit (sample delay unit ... The antenna element further includes a fast Fourier transform unit (FFT 105r, 105a to 105c, 205r, 205a to 205c) that performs a fast Fourier transform on the data after the pull delay process, and a plurality of second delay units (slope adding units 106r, 106a to 106c, 206r, 206a to 206c) that are provided for each real antenna element and virtual antenna element and that perform delay processing by adding a phase slope using time τ to the data output from the fast Fourier transform unit and output the data to an adder unit.

[0074] According to the above-described embodiment, even if the number of actual antenna elements is small, a phased array antenna device composed of a virtually large number of antenna elements can be realized. This means that a high spatial resolution and a directivity control function comparable to those of a phased array antenna device composed of many actual antenna elements can be realized with a small number of antenna elements.

[0075] Furthermore, according to the present embodiment, the number of antenna elements is reduced, thereby reducing the manufacturing cost required to achieve the same performance. Furthermore, the reduced number of antenna elements makes it possible to install a phased array antenna device in a place where it was previously impossible due to the installation area, mass, or upper limit of power supply, thereby expanding the range of application of the phased array antenna device.

[0076] Regardless of whether it is satellite or terrestrial, microwave transmitting and receiving systems using phased array antenna devices are used in a wide range of applications, such as interferometers, synthetic aperture radar, etc. Therefore, by applying the phased array antenna device of the present invention to microwave transmitting and receiving systems, it is expected that the range in which the benefits of miniaturization and weight reduction can be enjoyed will be expanded.

[0077] <Second embodiment> The second embodiment is an example in which the configuration of the data processing unit 30 of the phased array antenna device 400 (FIG. 4) according to the first embodiment is simplified.

[0078] Fig. 6 is a diagram showing a configuration example of a phased array antenna apparatus according to a second embodiment of the present invention. In a phased array antenna apparatus 600 shown in Fig. 6, a controller 500 includes a data processing unit 30A instead of the data processing unit 30 (Fig. 4) according to the first embodiment.

[0079] The data processing unit 30A is configured to perform only "slope addition" on the data corresponding to the signals of the virtual elements. In the group G1 of the real element 1, the data processing unit 30A does not include the sample delay units 104a to 104c and the FFTs 105a to 105c for the data corresponding to the signals of the virtual elements 101a to 101c.

[0080] Similarly, in group G2 of real element 2, sample delay units 204a to 204c and FFTs 205a to 205c are not present in data processing unit 30A for data corresponding to the signals of virtual elements 201a to 201c.

[0081] In this embodiment, as in the first embodiment, for a group of virtual elements belonging to a certain group of real elements, a sample delay nT with the same number of samples n as that of the real element is considered during sample delay processing. Here, the sample delay nT is reflected only in the data of the real elements, and the data reflecting the sample delay nT is input to the slope adding unit of each of the real elements and the group of virtual elements. Then, in each slope adding unit, an appropriate delay time t is finally given to the data of each element according to the time τ within a range that does not exceed the limit of the magnitude of the vector a (FIG. 1).

[0082] In this way, a calculation is performed by arranging multiple virtual elements at positions around one real element, each with a different path difference within a range not exceeding the delay time limit, with a configuration simpler than that of the first embodiment. Even with this configuration, a phased array antenna device with high spatial resolution is realized.

[0083] In addition, there is a limit to the program capacity that can be written into the controller 500 (for example, configured with an FPGA) that processes the signals of the real elements and virtual elements. However, in this embodiment, since the sample delay unit and FFT for the virtual elements are not required, the program capacity can be reduced and the number of virtual elements can be increased. This makes it possible to realize a phased array antenna device with even higher spatial resolution.

[0084] As described above, in the phased array antenna apparatus according to the second embodiment, the data processing unit (data processing unit 30A) includes a first delay unit (sample delay unit 104r, 204r) provided for each real antenna element, which performs sample delay processing using a sampling interval T and a sample number n on data of a signal received by the real antenna element and output from the signal processing unit, a fast Fourier transform unit (FFT 105r, 205r) provided for each real antenna element, which performs fast Fourier transform on data after the sample delay processing and output from the first delay unit, and a plurality of second delay units (slope adding units 106r, 106a to 106c, 206r, 206a to 206c) provided for each real antenna element and virtual antenna element, which perform delay processing by adding a phase slope using time τ to data output from the fast Fourier transform unit, and output the data to an adder.

[0085] <Third embodiment> The third embodiment is an example in which the configuration of the data processing unit 30A of the phased array antenna apparatus 600 (see FIG. 6) according to the second embodiment is further simplified.

[0086] Fig. 7 is a diagram showing a configuration example of a phased array antenna apparatus according to a third embodiment of the present invention. In a phased array antenna apparatus 700 shown in Fig. 7, a controller 500 includes a data processing unit 30B instead of the data processing unit 30A (Fig. 6) according to the second embodiment.

[0087] The data processing unit 30B is configured to perform only "slope addition" on data corresponding to the signals of the real elements and virtual elements. The data processing unit 30B performs e based on the delay time t in the slope adding unit without sample delay for both the real elements and the virtual elements. j2πft can be multiplied as the phase slope.

[0088] In group G1 of real element 1, sample delay units 104r, 104a-104c, and FFTs 105r, 105a-105c are not present in data processing unit 30A for data corresponding to signals of real element 101r and virtual elements 101a-101c. Similarly, in group G2 of real element 2, sample delay units 204r, 204a-204c, and FFTs 205r, 205a-205c are not present in data processing unit 30A for data corresponding to signals of real element 201r and virtual elements 201a-201c.

[0089] In this embodiment, for real elements and virtual element groups belonging to a certain group, a sample delay nT with the same number of samples n as the real element is taken into consideration during slope addition processing. That is, for delay time t defined as t=nT+τ, the same sample delay nT is reflected in the slope addition to the data of the real element and the virtual element group around it for the delay time t. Each slope addition unit gives an appropriate delay time t to the data of each element according to the time τ including the sample delay nT, within the range not exceeding the limit of the magnitude of vector a (FIG. 1).

[0090] In this way, a calculation is performed by arranging multiple virtual elements at positions where the path difference between each of the virtual elements is different within the range that does not exceed the delay time limit, with a configuration simpler than that of the second embodiment. Even with this configuration, a phased array antenna device with high spatial resolution can be realized.

[0091] As described above, in the phased array antenna apparatus according to the third embodiment, the data processing unit (data processing unit 30B) includes a fast Fourier transform unit (FFT 105r, 205r) provided for each real antenna element, which performs a fast Fourier transform on data of a signal received by the real antenna element and output from the signal processing unit, and a plurality of delay units (slope adding units 106r, 106a to 106c, 206r, 206a to 206c) provided for each real antenna element and virtual antenna element, which perform delay processing by adding a phase slope using a delay time t to the data output from the fast Fourier transform unit, and output the data to an adder unit.

[0092] <Antenna element arrangement and beam pattern> Here, the arrangement of antenna elements and the beam pattern (brightness temperature spectrum) will be described with reference to FIGS. 8A, 8B to 10A and 10B.

[0093] [In the case of only real antenna elements] 8A and 8B are diagrams showing examples of an array antenna with multiple real antenna elements and its beam pattern. FIG. 8A shows an example of an array antenna composed of 14 real antenna elements, and FIG. 8B shows an example of a beam pattern obtained by the array antenna. "Z [m]" written under the antenna element arrangement 810 in FIG. 8A means an axis perpendicular to the XY plane and represents the height of the antenna elements. In the example of FIG. 8A, all the real antenna elements are installed at the same height (for example, Z=0).

[0094] Beam pattern 820 in FIG. 8B is the result of a simulation in which delays are applied to each element and synthesized based on the path difference when 10 GHz signals arrive at the array antenna from all directions (azimuth angle θ, elevation angle φ).

[0095] "Gain" shown at the bottom of Fig. 8B is an index related to the sensitivity of the antenna element after power conversion. In the example of Fig. 8B, the sensitivity in the directional direction (θ,φ) = (0,0) is set to 0 dB, and the ratio of the sensitivity in each directional direction to this is shown by color. For example, if the ratio is 0.1, it is -10 dB, and if it is 0.01, it is -20 dB. As shown in beam pattern 820, with 14 elements, countless sensitivities (grating lobes) occur in unwanted directions.

[0096] [When virtual antenna elements are introduced] 9A and 9B are diagrams showing examples of an array antenna in which multiple virtual antenna elements are introduced around a real antenna element and its beam pattern. Fig. 9A shows an example of an array antenna in which 15 virtual antenna elements are arranged around one real antenna element, and Fig. 9B shows an example of a simulation result of a beam pattern obtained by the array antenna.

[0097] As shown in antenna element arrangement 910 in Fig. 9A, 15 virtual element groups are deployed with respect to the real elements, with the position of the real elements as the origin. There is a maximum difference of 14 between the signals of the virtual element group and the real elements. In beam pattern 920 in Fig. 9B, the sensitivity at origin 921 of the directivity direction (θ,φ)=(0,0) is higher than the other directivity directions, but many sensitivities (grating lobes) in unwanted directions also occur.

[0098] [When virtual antenna elements are used for multiple real antenna elements] 10A and 10B are diagrams showing examples of an array antenna in which multiple virtual antenna elements are introduced around each of multiple real antenna elements, and its beam pattern. Fig. 10A shows an example of an array antenna in which 15 virtual antenna elements are arranged around each of 14 real antenna elements, and Fig. 10B shows an example of a simulation result of a beam pattern obtained by the array antenna.

[0099] As shown in antenna element arrangement 1010 in Fig. 10A, for each real element, a group of 15 virtual elements is deployed with the position of each real element as the origin. That is, in antenna element arrangement 1010, (1 real element + 15 virtual elements) x 14 sets = 224 elements are arranged.

[0100] As shown in a beam pattern 1020 in Fig. 10B, the sensitivity (Gain) is significantly increased at a position 1021 where the azimuth angle and elevation angle are 0 degrees, and the sensitivity is decreased at other positions. Note that the examples in Fig. 8B, Fig. 9B, and Fig. 10B are simulation results assuming the configuration of the phased array antenna device 400 (Fig. 4) according to the first embodiment.

[0101] <Simulation results and actual measurement results> In order to verify the effects of the invention, the inventors performed the signal processing and data processing shown in Figure 4 when receiving microwaves from multiple directional directions using an array antenna made up of multiple real antenna elements and an array antenna in which multiple virtual antenna elements are introduced around each of the multiple real antenna elements.

[0102] [Simulation results] First, the results of simulations of beam patterns for each array antenna will be described with reference to FIGS. 11A and 11B.

[0103] FIG. 11A is a diagram showing an example of an array antenna using a plurality of actual antenna elements and a simulation result of a beam pattern produced by the array antenna. FIG. 11B is a diagram showing an example of an array antenna in which a plurality of virtual antenna elements are introduced around each of a plurality of real antenna elements, and a simulation result of a beam pattern produced by the array antenna. These simulation results were obtained using the phased array antenna apparatus 600 (FIG. 6) according to the second embodiment.

[0104] As shown in beam pattern 1110 of Fig. 11A, when there are only 14 real elements, the grating lobe is 40% or less of the main lobe. On the other hand, as shown in beam pattern 1120 of Fig. 11B, when virtual elements (15 each) are introduced for each of the 14 real elements, the grating lobe is 10% or less of the main lobe. From the results of this simulation, it is recognized that the introduction of virtual elements has the effect of suppressing grating lobes in the array antenna.

[0105] [Actual measurement results] Next, the results of actual measurements of the power count values ​​for each array antenna will be described with reference to FIGS. 12A and 12B.

[0106] FIG. 12A is a diagram showing an example of an array antenna made up of a plurality of actual antenna elements and the results of actual measurement of power count values ​​using the array antenna. FIG. 12B shows an example of an array antenna in which multiple virtual antenna elements are introduced around each of multiple real antenna elements, and the results of actual measurement of the power count value of the array antenna. 14 means.

[0107] In the antenna element arrangement 810 of Fig. 12A, an array antenna was fabricated using 14 real elements, and radio waves were received by this array antenna. In the antenna element arrangement 1010 of Fig. 12B, 15 virtual elements were arranged around each of the 14 real elements. The actual measurement results were obtained by actual measurement using the phased array antenna device 600 (Fig. 6) according to the second embodiment.

[0108] As shown in power count value data 1210 in Fig. 12A, when there are only 14 real elements, the power count value of the grating lobe is 40% or less of the main lobe, but frequently exceeds 10% of the main lobe. On the other hand, as shown in power count value data 1220 in Fig. 12B, the power count value of the grating lobe decreases outside the main lobe, and also frequently exceeds 10% of the main lobe. These actual measurement results show that the introduction of virtual elements is effective in suppressing grating lobes in an array antenna.

[0109] The power count values ​​were obtained by actual measurements and are therefore larger than those when the Gain (brightness temperature spectrum) shown in Figures 8B, 9B, 10B, and 11B was used. However, it was confirmed that the grating lobes were suppressed to the same extent as in the simulation results.

[0110] It should be noted that the results shown in Figures 11 and 12 were obtained using the configuration of the phased array antenna device 600 (Figure 6) according to the second embodiment, but similar results can be obtained when the phased array antenna device 400, 700 according to the first and third embodiments are used.

[0111] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various other application examples and modifications are possible without departing from the gist of the present invention described in the claims. For example, the above-described embodiments are detailed and specific descriptions of the configuration of a phased array antenna device in order to easily explain the present invention, and are not necessarily limited to those including all of the components described. In addition, it is also possible to add, replace, or delete other components to a part of the configuration of each embodiment.

[0112] In the above-described embodiment, the control lines and information lines are those that are considered necessary for the explanation, and not all control lines and information lines in the product are necessarily shown. In reality, it may be considered that almost all components are connected to each other. [Explanation of symbols]

[0113] 10...antenna element group, 20...signal processing unit, 30, 30A, 30B...data processing unit, 40...voltage addition unit, 50...power conversion unit, 101r, 201r...real elements, 101a to 101c, 201a to 201c...virtual elements, 102r, 102a to 102c, 202r, 202a to 202c...receiving circuit, 103r, 103a to 103c, 203r, 203a to 202c...A / D converter, 104r, 104a to 104c, 204r, 204a to 204c...sample delay unit, 105r, 105a to 105c, 205r, 205a to 205c...FFT, 106r, 106a to 106c, 206r, 206a to 206c...slope adding unit, 107...clock control unit, 108...delay pattern data, 400, 600, 700...phased array antenna device, 500...controller, G1, G2...group

Claims

1. A plurality of real antenna elements; a signal processing unit provided for each of the real antenna elements, which converts an analog signal received by the real antenna element into a digital signal and outputs data of the signal; a data processing unit that performs delay processing on data output from the signal processing unit for each of the real antenna elements and for each of the real antenna elements, the delay processing being based on the positions and directivity of the real antenna elements and the virtual antenna elements, the data processing unit being provided for each of the real antenna elements and the real antenna elements and the virtual antenna elements; an adder that adds the delayed data of the plurality of real antenna elements and the delayed data of the plurality of virtual antenna elements. Phased array antenna device.

2. The predetermined range of the real antenna element is a range in which the output of the grating lobe is equal to or smaller than a predetermined threshold value with respect to the output of the main lobe, with respect to a beam pattern obtained by adding together data obtained from the real antenna element and the virtual antenna elements arranged around the real antenna element.

2. The phased array antenna apparatus according to claim 1.

3. The data processing unit performs delay processing by applying a delay time corresponding to a path difference between a signal arriving at a reference real antenna element and a signal arriving at the real antenna element and the virtual antenna element for each of the real antenna elements and the virtual antenna elements. The phased array antenna apparatus according to claim 2 .

4. The delay time t is expressed by the following equation, where t is the delay interval when the analog signal received through the real antenna element is converted into a digital signal, T is the sampling interval, n is the number of samples of the sampling clock, and τ is the time. t = nT + τ The same number of samples n is used for the real antenna element and the virtual antenna element within a predetermined range of the real antenna element. The phased array antenna apparatus according to claim 3 .

5. The data processing unit includes: a plurality of first delay units provided for the real antenna elements and the virtual antenna elements, which perform a sample delay process using a sampling interval T and the number of samples n on data of a signal received by the real antenna elements output from the signal processing unit; a plurality of fast Fourier transform units each provided for each of the real antenna element and the virtual antenna element, each performing a fast Fourier transform on data after sample delay processing output from a corresponding one of the plurality of first delay units; and a plurality of second delay units provided for each of the real antenna elements and the virtual antenna elements, which perform delay processing by adding a phase slope using time τ to data output from a corresponding one of the plurality of fast Fourier transform units, and output the data to the adder. The phased array antenna apparatus according to claim 4.

6. The data processing unit includes: a first delay unit provided for each of the real antenna elements, the first delay unit performing a sample delay process using a sampling interval T and the number of samples n on the data of the signal received by the real antenna element output from the signal processing unit; a fast Fourier transform unit provided for each of the real antenna elements, the fast Fourier transform unit performing a fast Fourier transform on the sample-delayed data output from the first delay unit; a plurality of second delay units provided for each of the real antenna elements and the virtual antenna elements, which perform delay processing by adding a phase slope using time τ to the data output from the fast Fourier transform unit and output the data to the adder unit; The phased array antenna apparatus according to claim 4.

7. The data processing unit includes: a fast Fourier transform unit provided for each of the real antenna elements, the fast Fourier transform unit performing a fast Fourier transform on data of a signal received by the real antenna element and output from the signal processing unit; a plurality of delay units provided for each of the real antenna elements and the virtual antenna elements, which perform delay processing by adding a phase slope using the delay time t to the data output from the fast Fourier transform unit, and output the data to the adder unit; The phased array antenna apparatus according to claim 4.

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