Semiconductor chip and manufacturing method for semiconductor chip

Abstract

To provide a semiconductor chip in which a columnar electrode has excellent adhesion strength, and a manufacturing method for the semiconductor chip.SOLUTION: A semiconductor chip 10 includes an electrode pad 12 provided on a first main surface of a base material 11, a passivation film 13 provided on the first main surface of the base material 11 and including a first opening part 13a for exposing a part of the electrode pad 12, a seed layer 14 provided to cover a part of the electrode pad 12 that is exposed by the first opening part 13a, an inner peripheral surface of the first opening part 13a, and a peripheral part of the first opening part 13a on an upper surface of the passivation film 13, and a columnar electrode 20 including a pedestal part 21 provided on the seed layer 14 and a columnar part 22 provided in an upper surface of the pedestal part 21. The seed layer 14 and the pedestal part 21 are formed to have the same shape when the first main surface is viewed from above. The pedestal part 21 and the columnar part 22 are formed of the same material.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to semiconductor chips and methods for manufacturing semiconductor chips. [Background technology]

[0002] Flip-chip mounting is a conventional method for mounting semiconductor chips. In flip-chip mounting, electrode pads on a semiconductor chip and pads (FC pads) on a wiring board are joined by columnar electrodes, solder, or the like.

[0003] Recently, with the increasing performance and integration of semiconductor chips, the arrangement pitch of electrode pads is becoming narrower (fine pitch). As the pad pitch becomes narrower, it becomes necessary to form the columnar electrodes on the semiconductor chips thinner. As the columnar electrodes become thinner, the bonding area between the columnar electrodes and the electrode pads decreases, and this may cause defects due to peeling or tilting of the columnar electrodes during the manufacturing process, when mounting the mounting board, after mounting on the board, etc.

[0004] Therefore, Patent Document 1 discloses a configuration for improving the adhesion of electrode pads and bumps. In Patent Document 1, electrode pads and a protective film are arranged on a semiconductor chip, and an opening is provided in the protective film for exposing the electrode pads. In addition, one metal film and another metal layer are laminated on the protective film, and a columnar electrode is formed on the other metal layer. In addition, a bump is formed on the columnar electrode. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2004-235420 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, when the arrangement pitch of the electrode pads becomes narrower and it becomes necessary to make the columnar electrodes even thinner, the configuration of Patent Document 1 has the problem that the diameter of the columnar electrodes cannot be made smaller than the opening in the protective film for exposing the electrode pads.

[0007] In addition, when forming a columnar electrode by electrolytic plating using a conductive film as a seed layer for electrolytic plating as in the configuration of Patent Document 1, it is necessary to remove the conductive film by etching after forming the columnar electrode. The corrosive effect of the etching makes the conductive film narrower in an inverted cone shape, and the bottom area of ​​the conductive film becomes smaller than that of the columnar electrode. The reduction in the bonding area of ​​the conductive film, which is the base part of the columnar electrode, may reduce the bonding strength of the columnar electrode.

[0008] This problem becomes particularly noticeable in highly integrated semiconductor chips where the pitch of electrode pads is 45 μm to 85 μm.

[0009] Therefore, when it becomes necessary to form thin pillar electrodes as the pad arrangement pitch becomes finer due to the high performance and high integration of semiconductor chips, it is required to prevent a decrease in adhesion strength due to a reduction in the bonding area of ​​the pillar electrodes and to suppress problems such as the occurrence of defects.

[0010] The present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a semiconductor chip in which columnar electrodes have good adhesion strength, and a method for manufacturing the semiconductor chip. [Means for solving the problem]

[0011] The semiconductor chip according to the first aspect of the present disclosure includes: An electrode pad provided on a first main surface of the substrate; a passivation film provided on the first main surface of the base material, the passivation film having an opening for partially exposing the electrode pad; a pedestal portion provided on a portion of the electrode pad exposed by the opening, an inner circumferential surface of the opening, and a peripheral portion of the opening on an upper surface of the passivation film; a column portion provided within an upper surface of the base portion, the column portion having an outer shape smaller than an outer shape of the base portion when the first main surface is viewed in plan; A columnar electrode having Equipped with The base and the post are formed from the same material.

[0012] A semiconductor chip according to a second aspect of the present disclosure includes: An electrode pad provided on a first main surface of the substrate; a passivation film provided on the first main surface of the base material, the passivation film having a first opening for partially exposing the electrode pad; an insulating film provided on the passivation film and the electrode pad, the insulating film having a second opening for partially exposing the electrode pad; a pedestal portion provided on a portion of the electrode pad exposed by the second opening, an inner circumferential surface of the second opening of the insulating film, and a peripheral portion of the second opening on an upper surface of the insulating film; and a column portion provided within an upper surface of the base portion, the column portion having an outer shape smaller than an outer shape of the base portion when the first main surface is viewed in plan; A columnar electrode having Equipped with The base and the post are formed from the same material.

[0013] A method for manufacturing a semiconductor chip according to a third aspect of the present disclosure includes: preparing a base material having an electrode pad provided on a first main surface and a passivation film provided on the first main surface, the passivation film having an opening formed therein for partially exposing the electrode pad; forming a seed layer on a portion of the electrode pad exposed by the opening and on the passivation film; forming a pedestal portion on the seed layer by plating; forming a column portion within an upper surface of the base portion by plating; removing a portion of the seed layer that is not covered by the pedestal by etching; having The outer shape of the column portion is formed smaller than the outer shape of the base portion when the first main surface is viewed in plan, The base portion and the column portion are formed using the same material.

[0014] A method for producing a semiconductor chip according to a fourth aspect of the present disclosure includes: A step of preparing a base material having an electrode pad provided on a first main surface and a passivation film provided on the first main surface, the passivation film having a first opening for partially exposing the electrode pad; forming an insulating film on the passivation film and the electrode pad, the insulating film having a second opening for partially exposing the electrode pad; forming a seed layer on a portion of the electrode pad exposed by the second opening and on the insulating film; forming a pedestal portion on the seed layer by plating; forming a column portion on the base portion by plating; removing a portion of the seed layer that is not covered by the pedestal by etching; having The outer shape of the column portion is formed smaller than the outer shape of the base portion when the first main surface is viewed in plan, The base portion and the column portion are formed using the same material. Effect of the Invention

[0015] According to the present disclosure, it is possible to provide a semiconductor chip in which columnar electrodes have good adhesion strength, and a method for manufacturing the semiconductor chip. [Brief description of the drawings]

[0016] [Figure 1] 1 is a top view diagrammatically illustrating a portion of a semiconductor chip according to a first embodiment. [Diagram 2] 2 is a cross-sectional view taken along line II-II in FIG. [Diagram 3] 1(a) to 1(c) are diagrams illustrating a method for manufacturing a semiconductor chip according to the first embodiment. [Figure 4] 1(a) and 1(b) are diagrams illustrating a method for manufacturing a semiconductor chip according to the first embodiment. [Diagram 5] 1(a) and 1(b) are diagrams illustrating a method for manufacturing a semiconductor chip according to the first embodiment. [Figure 6] 1(a) and 1(b) are diagrams illustrating a method for manufacturing a semiconductor chip according to the first embodiment. [Figure 7] FIG. 11 is a top view diagrammatically illustrating a portion of a semiconductor chip according to a second embodiment. [Figure 8] 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7. [Figure 9] 10(a) to 10(c) are diagrams illustrating a method for manufacturing a semiconductor chip according to a second embodiment. [Figure 10] 10(a) and 10(b) are diagrams illustrating a method for manufacturing a semiconductor chip according to a second embodiment. [Figure 11] 10(a) and 10(b) are diagrams illustrating a method for manufacturing a semiconductor chip according to a second embodiment. [Figure 12] 10(a) and 10(b) are diagrams illustrating a method for manufacturing a semiconductor chip according to a second embodiment. [Figure 13] FIG. 1A is a diagram illustrating the structure of a conventional semiconductor chip, and FIG. 1B is an enlarged view of a joint between an electrode pad and a pillar. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, a semiconductor chip and a method for manufacturing the semiconductor chip according to the present embodiment will be described with reference to the drawings.

[0018] (Embodiment 1) A semiconductor chip 10 according to a first embodiment is shown in Figures 1 and 2. As shown in Figures 1 and 2, the semiconductor chip 10 includes a substrate 11, an electrode pad 12, a passivation film 13, a seed layer 14, a columnar electrode 20, and a solder 17. The columnar electrode 20 includes a pedestal portion 21 and a column portion 22 provided on the pedestal portion 21.

[0019] Inside the substrate 11, circuits and the like (not shown) are formed.

[0020] The electrode pads 12 are provided on a first main surface (the upper surface shown in FIG. 2) of the base material 11. The electrode pads 12 are arranged at a pitch of 45 μm to 85 μm, for example, at a pitch of 50 μm.

[0021] The passivation film 13 is provided on the first main surface of the substrate 11. The passivation film 13 is provided with a first opening 13a for partially exposing the electrode pad 12. The first opening 13a has, for example, a square planar shape. As an example, the first opening 13a is a square with each side measuring 35 μm.

[0022] The seed layer 14 is made of, for example, Ti or W, and is used when forming the columnar electrode 20 by electrolytic plating as described later. The seed layer 14 has a thickness of 0.5 μm to 1 μm. The seed layer 14 may have a single-layer structure, or may have a two-layer structure in which a layer made of Cu is provided on a layer made of Ti or W. The seed layer 14 is formed to be slightly larger than the first opening 13a as shown in FIG. 2. Specifically, the seed layer 14 is provided so as to cover the portion of the electrode pad 12 exposed by the first opening 13a of the passivation film 13, the inner peripheral surface of the first opening 13a, and the peripheral portion of the first opening 13a on the upper surface of the passivation film 13 as shown in FIG. 2.

[0023] The columnar electrode 20 includes a pedestal portion 21 and a column portion 22 provided on the pedestal portion 21. The pedestal portion 21 is provided on the seed layer 14, and is provided on the portion of the electrode pad 12 exposed by the first opening 13a, the inner peripheral surface of the first opening 13a, and the peripheral portion of the first opening 13a on the upper surface of the passivation film 13. The pedestal portion 21 is formed of a conductive material, for example, copper. As will be described in detail later, the seed layer 14 is formed by etching using the pedestal portion 21 as a mask. For this reason, the outer shape of the pedestal portion 21 is the same as the outer shape of the seed layer 14, that is, as shown in FIG. 1 and FIG. 2, when the first main surface of the substrate 11 is viewed in plan, the outline of the pedestal portion 21 and the outline of the seed layer 14 have the same shape. As an example, the pedestal portion 21 is formed into a square having a side of 45 μm as shown in FIG. 1. The seed layer 14 has the same outer shape as the base 21, and is therefore formed into a square with one side measuring 45 μm. The thickness of the base 21 is preferably 5 μm or less to accommodate fine pitch. In this specification, the term "same shape" includes errors that occur during manufacturing.

[0024] The column portion 22 has a cylindrical shape. The column portion 22 is formed from the same material as the base portion 21, for example, copper. In FIG. 2, a boundary is shown between the base portion 21 and the column portion 22 for the purpose of explanation, but the base portion 21 and the column portion 22 are formed from the same material and are further formed by continuous plating, so that there is no actual boundary. Therefore, the base portion 21 and the column portion 22 have good bonding strength. In addition, when the first main surface of the column portion 22 is viewed in plan, the outer shape of the column portion 22 is formed to be smaller than the outer shape of the base portion 21, and the column portion 22 is arranged so as to be located within the upper surface of the base portion 21. For example, the diameter of the column portion 22 is smaller than the width and length of the base portion 21 when the first main surface of the substrate 11 is viewed in plan, and the column portion 22 is located within the region of the upper surface of the base portion 21. The diameter of the column portion 22 is 5 to 30 μm. The height of pillar portion 22 is 10 to 30 μm, for example 25 μm. It is preferable that one side of pedestal portion 21 is larger by 5 μm to 20 μm than the diameter of pillar portion 22. As an example, when pillar portion 22 has a diameter of 25 μm, pedestal portion 21 is preferably formed into a square with one side of 45 μm.

[0025] 1, the pillar portion 22 is disposed directly above the first opening 13a. In other words, the pillar portion 22 is provided so as to be located within the region of the electrode pad 12 exposed by the first opening 13a. The diameter of the pillar portion 22 is smaller than the length of one side of the first opening 13a. It is preferable that one side of the first opening 13a is 5 to 20 μm larger than the diameter of the pillar portion 22. As an example, when the diameter of the pillar portion 22 is 25 μm, it is preferable that one side of the first opening 13a is 35 μm.

[0026] The solder 17 is provided on the column portion 22. The solder 17 is made of, for example, SnAg. The height of the solder 17 is, for example, 10 μm.

[0027] (Method of manufacturing semiconductor chips) A method for manufacturing the semiconductor chip 10 will be described below with reference to the drawings.

[0028] As shown in Fig. 3(a), a base material 11 is prepared having electrode pads 12 and a passivation film 13 formed on a first main surface. Circuits and the like (not shown) are formed within the base material 11. The base material 11 is in a state before being divided into individual pieces, and has a plurality of semiconductor chips connected together. Therefore, Figs. 3 to 6 show an area in which one semiconductor chip is formed.

[0029] As shown in FIG. 3(b), a seed layer 51 is formed on the first main surface side of the base material 11. The seed layer 51 is formed by a sputtering method. The seed layer 51 is, for example, a thin metal film having a thickness of 0.5 μm to 1 μm, and is formed on the entire surface of the base material 11. The seed layer 51 is formed by using, for example, Ti or W. The seed layer 51 may be composed of a single layer, or may have a two-layer structure including a layer made of Cu on a layer made of Ti or W.

[0030] A first resist layer 52 for forming the pedestal portion 21 is formed on the seed layer 51. A photosensitive material is used as the first resist layer 52. The first resist layer 52 is formed by applying a liquid resist material using a coating method such as spin coating.

[0031] Next, the first resist layer 52 is patterned to form a resist opening 52a as shown in Fig. 3(c). Specifically, a photomask is used, and the first resist layer 52 is exposed to light by an exposure device, developed, and hardened, thereby patterning the first resist layer 52. Here, the shape of the resist opening 52a corresponds to the shape of the pedestal portion 21.

[0032] 4(a), Cu plating is performed to form the base portion 21. The Cu plating is performed by electrolytic plating. Specifically, power is supplied from the seed layer 51, and plating is performed to a predetermined thickness.

[0033] Next, as shown in FIG. 4(b), the first resist layer 52 is dissolved and removed using a stripping solution.

[0034] A second resist layer 53 for plating is formed to form the columnar section 22. A photosensitive material is used as the second resist layer 53. The second resist layer 53 is formed by applying a liquid resist material using a coating method such as spin coating. Alternatively, instead of using a liquid resist material, the second resist layer 53 may be formed by laminating a dry film using a lamination method.

[0035] The second resist layer 53 is patterned to form resist openings 53a as shown in FIG. 5(a). Specifically, the resist layer 53 is exposed to light by an exposure device using a photomask, developed, and cured, thereby performing patterning. The shape of the resist openings 53a corresponds to the shape of the pillars 22. The position of the resist openings 53a is determined so that the pillars 22 are located within the first openings 13a of the passivation film 13 when the first main surface of the substrate 11 is viewed in plan as shown in FIG. 1.

[0036] 5(b), Cu plating is performed to form the columnar portion 22. The Cu plating is performed using an electrolytic plating method. Specifically, power is supplied from the seed layer 51, and plating is performed to a predetermined thickness.

[0037] 6(a), plating is performed to form a solder layer 54. As with Cu plating, electrolytic plating is used. Specifically, power is supplied from the seed layer 51, and a solder alloy such as SnAg is plated to a predetermined thickness.

[0038] The second resist layer 53 is dissolved and removed using a stripping solution.

[0039] Next, the portion of the seed layer 51 that is not covered by the pedestal portion 21 is removed by etching. As a result, as shown in FIG. 6(b), only the portion of the seed layer 51 that is located under the pedestal portion 21 remains, and the seed layer 14 is formed. When the seed layer 51 is etched, the pedestal portion 21 functions as an etching mask, so that when the first main surface is viewed in plan, the outer shape of the seed layer 14 is formed to be the same as the outer shape of the pedestal portion 21. Here, there is a possibility that a part of the outer periphery of the seed layer 14 will be removed during etching. Therefore, the "same shape" in this specification includes such manufacturing-induced errors.

[0040] Subsequently, the solder layer 54 is melted by a reflow process, shaped and fixed to form the solder 17. Next, the resultant product is diced into individual pieces, thereby manufacturing the semiconductor chips 10.

[0041] According to the present embodiment, a semiconductor chip in which the columnar electrodes have good adhesion strength and a method for manufacturing the semiconductor chip are provided.

[0042] First, for comparison, a conventional example of a semiconductor chip is shown in FIG. 13(a). In this example, the pillars are provided directly on the electrode pads via the seed layer. In this example, when the pillars must be thinned to meet the high performance and high integration of semiconductor chips, the bonding area between the pillars and the electrode pads is reduced, resulting in a problem of reduced adhesion strength. If the bonding strength is reduced, defects such as peeling, tilting, or falling of the pillars may occur during the manufacture or after mounting of the semiconductor chip. In addition, as shown in FIG. 13(b), if the outer periphery of the seed layer located between the pillars and the electrode pads is thinned into an inverted cone shape by etching, the bonding area of ​​the pillar bottoms may be reduced, which may cause a further decrease in strength.

[0043] In contrast, in the semiconductor chip 10 of the first embodiment, the pedestal 21 and the column 22 are formed from the same material and further formed by continuous plating, so there is no boundary. Therefore, the pedestal 21 and the column 22 have good bonding strength. Even if the seed layer 14 is thinned by etching, the bonding between the pedestal 21 and the column 22 is not affected. Furthermore, compared to the case where the pedestal and the column are formed using different materials, the manufacturing process is simplified and the material cost and manufacturing price can be reduced. In addition, in the semiconductor chip 10 of the present embodiment, the pedestal 21 is formed wider than the column 22, so that the bonding area between the seed layer 14 formed from different materials and the pedestal 21 can be made wider compared to the case where the column is provided directly on the electrode pad via the seed layer, and the bonding strength between the columnar electrode 20 and the electrode pad 12 can be increased.

[0044] (Embodiment 2) A semiconductor chip 30 according to embodiment 2 and a manufacturing method thereof will be described with reference to the drawings. The semiconductor chip 30 of this embodiment differs from the semiconductor chip 10 according to embodiment 1 in that it has an insulating film 31 on a passivation film 13. The parts common to embodiment 1 are given the same reference numerals and detailed description will be omitted.

[0045] 7 and 8 show a semiconductor chip 30 according to the second embodiment. Fig. 8 is a cross-sectional view taken along line VIII-VIII shown in Fig. 7.

[0046] 7 and 8, the semiconductor chip 30 includes a substrate 11, an electrode pad 12, a passivation film 13, an insulating film 31, a seed layer 14, a columnar electrode 20, and a solder 17. The columnar electrode 20 includes a pedestal portion 21 and a column portion 22 provided on the pedestal portion 21.

[0047] The electrode pads 12 are provided on a first main surface (the upper surface shown in FIG. 8) of the substrate 11, similarly to the first embodiment. The electrode pads 12 are arranged at a pitch of 45 μm to 85 μm, for example, at a pitch of 50 μm.

[0048] The passivation film 13 is provided on the first main surface of the substrate 11. The passivation film 13 is provided with a first opening 13a for partially exposing the electrode pad 12. The first opening 13a has, for example, a square planar shape. As an example, the first opening 13a is a square with each side measuring 35 μm.

[0049] The insulating film 31 is made of an insulating material, for example, polyimide. In addition, a second opening 31a for exposing the electrode pad 12 is formed in the insulating film 31. The second opening 31a is formed to have a circular planar shape when viewed from the first main surface side of the base material 11, and the inner peripheral surface of the second opening 31a is inclined as shown in FIG. 8, and the inner diameter of the second opening 31a gradually decreases from the top surface to the bottom surface of the insulating film 31. In addition, the second opening 31a is formed so as to expose the electrode pad 12 in a circular shape with a diameter of, for example, 15 μm. Here, the second opening 31a shown in FIG. 7 shows the shape of the boundary portion between the insulating film 31 and the electrode pad 12, and shows the portion where the electrode pad 12 is exposed from the insulating film 31.

[0050] The seed layer 14 is made of, for example, Ti or W, and is used when forming the columnar electrode 20 by electrolytic plating as described later. The seed layer 14 has a thickness of 0.5 μm to 1 μm. The seed layer 14 may have a one-layer structure or a two-layer structure. As shown in FIG. 8, the seed layer 14 is formed to be larger than the second opening 31a. Specifically, as shown in FIG. 8, the seed layer 14 is provided so as to cover a portion of the electrode pad 12 exposed by the second opening 31a of the insulating film 31, the inner peripheral surface of the second opening 31a, and the peripheral portion of the second opening 31a on the upper surface of the insulating film 31.

[0051] The columnar electrode 20 includes a pedestal portion 21 and a column portion 22 provided on the pedestal portion 21. The pedestal portion 21 is provided on the seed layer 14, and is provided on the portion of the electrode pad 12 exposed by the second opening 31a, the inner peripheral surface of the second opening 31a of the insulating film 31, and the peripheral portion of the second opening 31a on the upper surface of the insulating film 31a. In this embodiment, the outer shape of the pedestal portion 21 is the same as the outer shape of the seed layer 14, that is, as shown in Figs. 7 and 8, when the first main surface of the substrate 11 is viewed in plan, the outline of the pedestal portion 21 and the outline of the seed layer 14 are the same shape. As an example, the pedestal portion 21 is formed in a square with one side being 45 μm as shown in Fig. 7. The outer shape of the seed layer 14 is also the same as the outer shape of the pedestal portion 21, so it is formed in a square with one side being 45 μm. In addition, the thickness of the pedestal portion 21 is preferably 5 μm or less.

[0052] The pillar portion 22 has a cylindrical shape. The pillar portion 22 is formed from the same material as the base portion 21, for example, copper. The base portion 21 and the pillar portion 22 are formed from the same material and are further formed by continuous plating, so that there is actually no boundary as shown in FIG. 8. The pillar portion 22 is provided within the upper surface of the base portion 21. When the first main surface of the pillar portion 22 is viewed in plan, the outer shape of the pillar portion 22 is formed to be smaller than the outer shape of the base portion 21, and the pillar portion 22 is arranged so as to be located within the upper surface of the base portion 21. For example, the diameter of the pillar portion 22 is smaller than the width and length of the base portion 21 when viewed in plan from the first main surface side of the substrate 11, and the pillar portion 22 is arranged within the upper surface of the base portion 21. The diameter of the pillar portion 22 is 5 to 30 μm, and the height is 25 μm. It is preferable that one side of base portion 21 is larger by 5 μm to 20 μm than the diameter of column portion 22. As an example, one side of base portion 21 is 45 μm, and the diameter of column portion 22 is 25 μm.

[0053] 7, the pillar portion 22 is disposed directly above the first opening 13a of the passivation film 13, as in the first embodiment. The diameter of the pillar portion 22 is smaller than the length of one side of the first opening 13a. It is preferable that one side of the first opening 13a is 5 to 20 μm larger than the diameter of the pillar portion 22. As an example, when the diameter of the pillar portion 22 is 25 μm, it is preferable that one side of the first opening 13a is 35 μm.

[0054] The solder 17 is provided on the column portion 22. The solder 17 is made of, for example, SnAg. The height of the solder 17 is, for example, 10 μm.

[0055] (Method of manufacturing semiconductor chips) A method for manufacturing the semiconductor chip 30 will be described below with reference to the drawings.

[0056] First, a base material 11 is prepared, on whose first main surface the electrode pads 12 and the passivation film 13 are formed. In this embodiment as well, the base material 11 is in a state prior to being divided into individual pieces.

[0057] An insulating material, for example, photosensitive polyimide, is applied onto the electrode pads 12 and the passivation 13 on the base material 11. Then, a photomask is used, and the insulating film 31 having the second openings 31a formed therein is formed on the electrode pads 12 by performing a development process after exposure with an exposure device.

[0058] 9(b), a seed layer 51 is formed on the first main surface side of the base material 11. The seed layer 51 is formed by using a sputtering method.

[0059] A first resist layer 52 for forming the pedestal portion 21 is formed on the seed layer 51. The first resist layer 52 is formed using a photosensitive material. Next, the first resist layer 52 is patterned to form a resist opening 52a as shown in FIG. 9(c). Here, the shape of the resist opening 52a becomes the shape of the pedestal portion 21.

[0060] Cu plating is performed to form the base portion 21 as shown in Fig. 10(a). The Cu plating is performed using an electrolytic plating method. Specifically, power is supplied from the seed layer 51, and plating is performed to a predetermined thickness.

[0061] Next, as shown in FIG. 10(b), the first resist layer 52 is dissolved and removed using a stripping solution.

[0062] A second resist layer 53 for plating to form the columnar portion 22 is formed, and then the second resist layer 53 is patterned to form a resist opening 53a as shown in Fig. 11(a). The shape of the resist opening 53a becomes the shape of the columnar portion 22. The position of the resist opening 53a is determined so that the columnar portion 22 is located within the first opening 13a of the passivation film 13 when viewed in plan from the first main surface side of the substrate 11.

[0063] 11(b), the columnar portion 22 is formed by Cu plating. The Cu plating is performed by electrolytic plating. Specifically, power is supplied from the seed layer 51, and plating is performed to a predetermined thickness.

[0064] 11(b), plating is performed to form a solder layer 54. As with Cu plating, electrolytic plating is used. Specifically, power is supplied from the seed layer 51, and a solder alloy such as SnAg is plated to a predetermined thickness.

[0065] As shown in FIG. 12(a), the second resist layer 53 is dissolved and removed using a stripping solution.

[0066] 12(b), the portion of the seed layer 51 that is not covered by the pedestal portion 21 is removed by etching. As a result, only the portion of the seed layer 51 that is located under the pedestal portion 21 remains, and the seed layer 14 is formed. When the seed layer 51 is etched, the pedestal portion 21 functions as an etching mask, so that the outer shape of the seed layer 14 is formed to be the same as the outer shape of the pedestal portion 21.

[0067] Subsequently, the solder layer 54 is melted by a reflow process, shaped and fixed to form the solder 17. Next, the resultant product is divided into individual pieces by dicing, thereby manufacturing the semiconductor chip 30 shown in FIG.

[0068] In the semiconductor chip 30 of this embodiment, an insulating film 31 is further provided on the passivation film 13, but as in the first embodiment, the pedestal 21 and the column 22 are formed by continuous plating, and therefore have no boundary. Therefore, the pedestal 21 and the column 22 have good connection strength. As a result, even if the inner circumferential surface of the second opening 31a of the insulating film 31 is inclined, since the pedestal 21 is formed on the insulating film 31 along the inclination, good bonding strength can be obtained even if the column 22 is located on the inclined surface of the insulating film 31.

[0069] The present disclosure is not limited to the above-described embodiment, and various modifications and applications are possible.

[0070] In the above-mentioned embodiments, the configuration in which the solder 17 is formed on the column portion 22 of the columnar electrode 20 has been described as an example, but the present invention is not limited thereto. For example, a metal layer having a low diffusion coefficient such as Ni can be provided between the column portion 22 and the solder 17. By providing such a metal layer, when the column portion is made of Cu, diffusion and alloying between the solder and the column portion can be suppressed, thereby suppressing electromigration or improving the bulk strength of the solder joint.

[0071] The planar shape of the pedestal 21 is not limited to a square shape, but may be a circle, a rectangle, or the like. If the pedestal 21 is a circle, the diameter of the pedestal 21 is preferably 5 μm to 20 μm larger than the diameter of the columnar portion 22, and if the pedestal 21 is a rectangle, the shorter side of the pedestal 21 is preferably 5 μm to 20 μm larger than the diameter of the columnar portion 22. Similarly, the planar shape of the first opening 13a of the passivation film 13 is not limited to a square shape, but may be a circle, a rectangle, or the like. If the first opening 13a is a circle, the diameter of the first opening 13a is preferably 5 μm to 20 μm larger than the diameter of the columnar portion 22, and if the first opening 13a is a rectangle, the shorter side of the first opening 13a is preferably 5 μm to 20 μm larger than the diameter of the columnar portion 22. [Explanation of symbols]

[0072] 10,30 Semiconductor chips 11 Base material 12 Electrode pads 13 Passivation film 13a First opening 14,51 Seed layer 17 Solder 20 columnar electrode 21 Pedestal 22 Pillar section 31 Insulating film 31a Second opening 52 First resist layer 53 Second resist layer 52a, 53a Resist opening 54 Solder layer

Claims

1. An electrode pad provided on a first main surface of a substrate; a passivation film provided on the first main surface of the base material, the passivation film having an opening for partially exposing the electrode pad; a pedestal portion provided on a portion of the electrode pad exposed by the opening, an inner circumferential surface of the opening, and a peripheral portion of the opening on an upper surface of the passivation film; a column portion provided within an upper surface of the base portion, the column portion having an outer shape smaller than an outer shape of the base portion when the first main surface is viewed in plan; A columnar electrode having A solder portion provided on an upper portion of the column portion; Equipped with the base portion and the column portion are formed from the same material, A semiconductor chip, wherein, when the first main surface is viewed in plan, the pedestal portion is formed to the outside of the electrode pad, and the column portion is formed inside the electrode pad.

2. a seed layer provided to cover a portion of the electrode pad exposed by the opening, an inner circumferential surface of the opening, and a peripheral portion of the opening on an upper surface of the passivation film; the pedestal portion is provided on the seed layer, and the seed layer and the pedestal portion are formed to have the same shape when the first main surface is viewed in plan; The semiconductor chip according to claim 1 .

3. The pillar portion is provided so that the electrode pad is located only above the area exposed by the opening. The semiconductor chip according to claim 1 .

4. The thickness of the base is 5 μm or less. The semiconductor chip according to claim 1 .

5. The diameter of the column is in the range of 5 to 30 μm. The semiconductor chip according to claim 1 .

6. An electrode pad provided on a first main surface of a substrate; a passivation film provided on the first main surface of the base material, the passivation film having a first opening for partially exposing the electrode pad; an insulating film provided on the passivation film and the electrode pad, the insulating film having a second opening for partially exposing the electrode pad; a pedestal portion provided on a portion of the electrode pad exposed by the second opening, an inner circumferential surface of the second opening of the insulating film, and a peripheral portion of the second opening on an upper surface of the insulating film; and a column portion provided within an upper surface of the base portion, the column portion having an outer shape smaller than an outer shape of the base portion when the first main surface is viewed in plan; A columnar electrode having A solder portion provided on an upper portion of the column portion; Equipped with the base portion and the column portion are formed from the same material, A semiconductor chip, wherein, when the first main surface is viewed in plan, the pedestal portion is formed to the outside of the electrode pad, and the column portion is formed inside the electrode pad.

7. preparing a base material having an electrode pad provided on a first main surface and a passivation film provided on the first main surface, the passivation film having an opening formed therein for partially exposing the electrode pad; forming a seed layer on a portion of the electrode pad exposed by the opening and on the passivation film; forming a pedestal portion on the seed layer by plating; forming a column portion within an upper surface of the base portion by plating; forming a solder layer on the top of the column; removing a portion of the seed layer that is not covered by the pedestal by etching; having The base portion is formed to an outer side of the electrode pad when the first main surface is viewed in a plan view, The outer shape of the column portion is formed on the inner side of the electrode pad when the first main surface is viewed in plan, A method for manufacturing a semiconductor chip, wherein the base portion and the column portion are formed using the same material.

8. forming the pillars such that the electrode pads are located only above the areas exposed by the openings; The method for manufacturing a semiconductor chip according to claim 7 .

9. The thickness of the pedestal portion is formed to be 5 μm or less. The method for manufacturing a semiconductor chip according to claim 7 .

10. The column portion is formed so that the diameter of the column portion is in the range of 5 to 30 μm. The method for manufacturing a semiconductor chip according to claim 7 .

11. A step of preparing a base material having an electrode pad provided on a first main surface and a passivation film provided on the first main surface, the passivation film having a first opening for partially exposing the electrode pad; forming an insulating film on the passivation film and the electrode pad, the insulating film having a second opening for partially exposing the electrode pad; forming a seed layer on a portion of the electrode pad exposed by the second opening and on the insulating film; forming a pedestal portion on the seed layer by plating; forming a column portion on the base portion by plating; forming a solder layer on the column; removing a portion of the seed layer that is not covered by the pedestal by etching; having The base portion is formed to an outer side of the electrode pad when the first main surface is viewed in a plan view, The outer shape of the column portion is formed on the inner side of the electrode pad when the first main surface is viewed in plan, A method for manufacturing a semiconductor chip, wherein the base portion and the column portion are formed using the same material.

12. The base portion has a rectangular shape when the first main surface is viewed in a plan view. The semiconductor chip according to claim 1 or 6.

13. In the step of forming the pedestal portion, the pedestal portion is formed into a square shape when the first main surface is viewed in a plane. The method for manufacturing a semiconductor chip according to claim 7 or 11.

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