Game machine

Abstract

To provide a game machine for increasing environmental performance and cost effectiveness.SOLUTION: A game machine includes a performance control CPU 71, a first storage area (FeRAM 77), and a second storage area (integral data ROM 92). The performance control CPU 71 transfers an activation program FRAM(R)_BOOT from the FeRAM 77, and can execute the transferred activation program, can transfer setting information from the integral data ROM 92, and performs a setting pertaining control, such as PLL control performed by the performance control CPU 71 on the basis of the transferred setting information.SELECTED DRAWING: Figure 44

Description

[Technical field]

[0001] The present invention relates to a gaming machine using a gaming medium. [Background technology]

[0002] In gaming machines such as pachinko machines, various effects are provided using image display devices with liquid crystal screens, audio output devices (speakers), motorized gimmicks, etc., in order to increase the interest of players. For example, a presentation pattern is determined based on the result of a lottery for a symbol held when a gaming ball enters a starting hole, and a presentation image is displayed on an image display device according to this presentation pattern (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP2015-062748A Summary of the Invention [Problem to be solved by the invention]

[0004] The performance control CPU, which controls the performance, starts up by executing a startup program stored in the boot ROM on the performance control board. Some recent performance control CPUs have integrated the functions of the VDP, which controls image display. When such a performance control CPU starts up, it also starts up the VDP section, and at that time performs PLL control to generate a drive clock that depends on the resolution of the liquid crystal display device installed in the gaming machine. To do this, it is necessary to store setting information such as the drive clock of the liquid crystal display device in the boot ROM. If the size of the LCD display changes in a new model, the setting information will also change. In that case, it is necessary to rewrite the setting information on the boot ROM, making it difficult to completely reuse the performance control board. This goes against the trend toward reuse of performance control boards, including the performance control CPU, from an environmental and economical perspective. The present invention has been made in consideration of the above-mentioned problems, and aims to provide a gaming machine that can be started without storing setting information on the performance control board, making it easy to reuse, and improving environmental friendliness and cost-effectiveness. [Means for solving the problem]

[0005] The present invention has been made to solve the above-mentioned problems, and can be realized in the following forms. A first form according to the present invention is characterized by a gaming machine comprising a control unit, a first memory area, and a second memory area different from the first memory area, wherein the control unit is capable of transferring a startup program from the first memory area and executing the transferred startup program, and by executing the startup program, is capable of transferring setting information from the second memory area, and performs settings related to control by the control unit based on the transferred setting information. Effect of the Invention

[0006] As configured as described above, the present invention makes it possible to realize a gaming machine that is environmentally friendly and economical. [Brief description of the drawings]

[0007] [Figure 1] 1 is a front view of a gaming machine according to an embodiment of the present invention. [Diagram 2] 2 is an oblique view showing an example of the back side of the gaming machine according to the present embodiment. FIG. [Diagram 3] A block diagram showing the configuration of a game control device provided in the gaming machine of this embodiment. [Figure 4] FIG. 1 is a block diagram of the performance control CPU. [Diagram 5]FIG. 4 is a rear view showing the state in which each unit is assembled to the base frame. [Figure 6] FIG. 6 is a partially exploded perspective view of FIG. 5. [Figure 7] 1 is a diagram illustrating a performance control board (first performance board) stored in the performance board case of this embodiment. FIG. [Figure 8] 13 is a diagram illustrating the performance control board (second performance board) stored in the performance board case of this embodiment. FIG. [Figure 9] FIG. 1 is a schematic front view illustrating a performance board case according to an embodiment of the present invention; [Figure 10] 1 is a schematic oblique view illustrating the performance board case of this embodiment. FIG. [Figure 11] This is an exploded oblique view of the performance board case. [Figure 12] This is an exploded oblique view of the performance board case. [Figure 13] 13 is a diagram illustrating the components attached to the performance board case. FIG. [Figure 14] FIG. 1 shows a ROM board equipped with an integrated data ROM. [Figure 15] FIG. 2 is a schematic diagram of a ROM cassette. [Figure 16] FIG. [Figure 17] FIG. [Figure 18] FIG. 2 is a schematic diagram illustrating a basic configuration of a first liquid crystal module. [Figure 19] 4 is a schematic diagram showing a layered structure of elements constituting the first liquid crystal module. FIG. [Figure 20] FIG. 1 is a diagram for explaining the basic operation of a TN type liquid crystal module. [Figure 21] FIG. 2 is a diagram explaining in more detail the operation of a TN type liquid crystal module. [Figure 22] FIG. 1 is a diagram for explaining drive control of a liquid crystal module according to the VA method. [Figure 23] 4 is a timing chart illustrating display control of the first liquid crystal module. [Figure 24]4 is a schematic diagram showing a layered structure of elements constituting the second liquid crystal module. FIG. [Diagram 25] 4 is a schematic diagram illustrating a basic configuration of a second liquid crystal module. FIG. [Figure 26] 10A and 10B are diagrams illustrating the concept of color display in the second liquid crystal module. [Figure 27] 13 is a timing chart illustrating display control of the second liquid crystal module. [Figure 28] 10 is a timing chart illustrating display control focusing on one pixel of the second liquid crystal module. [Figure 29] FIG. 2 is a diagram showing a configuration of an image display unit according to the present embodiment. [Diagram 30] 5 is a timing chart illustrating display control in the image display unit of the present embodiment. [Diagram 31] 10 is a timing chart (part 1) illustrating a control signal for each pixel of a first liquid crystal module in the image display unit of the present embodiment. [Diagram 32] 13 is a timing chart (part 2) illustrating a control signal for each pixel of a first liquid crystal module in the image display unit of the present embodiment. [Diagram 33] 3A to 3C are diagrams illustrating an example of an image display mode of the image display unit of the present embodiment. [Diagram 34] FIG. 13 is a diagram showing a modified example of the image display unit of the present embodiment. [Diagram 35] 22 is a schematic cross-sectional view illustrating an image display by the image display unit of FIG. 21. [Diagram 36] FIG. 2 is a diagram illustrating a basic configuration of a liquid crystal screen. [Figure 37] FIG. 4 is a diagram showing a synchronization signal of a liquid crystal module. [Figure 38] FIG. 1 is a diagram (part 1) for explaining a synchronization signal for adjusting the vertical synchronization timing of two liquid crystal screens provided in the image display unit of this embodiment. [Figure 39] FIG. 2 is a diagram (part 2) for explaining a synchronization signal for adjusting the vertical synchronization timing of two liquid crystal screens provided in the image display unit of this embodiment. [Diagram 40] FIG. 2 is a diagram illustrating an LED module provided in the gaming machine. [Diagram 41] 1A and 1B are diagrams illustrating display modes using light emission by DC drive and light emission by PWM drive of an LED module. [Diagram 42] 13A and 13B are diagrams for explaining a display mode when dual liquid crystal display is not performed. [Diagram 43] FIG. 34 is a diagram for explaining a display mode conforming to the configuration shown in FIG. 33. [Diagram 44] A diagram explaining the configuration of the control program of the performance control board in the gaming machine of this embodiment. [Diagram 45] A diagram explaining the startup sequence of the performance control CPU. [Figure 46] 11 is a conceptual diagram illustrating the volume balance for each range according to a change in the master volume value. FIG. [Figure 47] 2 is a schematic diagram illustrating a voice control circuit provided in the gaming machine. FIG. [Figure 48] FIG. 13 is a diagram illustrating changes in volume for each range at each master volume value. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the drawings. <Basic configuration of gaming machine> FIG. 1 is a front view showing an example of a gaming machine according to this embodiment, FIG. 2 is an oblique view showing an example of the back side of the gaming machine according to this embodiment, and FIG. 3 is a block diagram showing the configuration of a gaming control device provided in the gaming machine according to this embodiment.

[0009] In the gaming machine 1 shown in Figure 1, an inner frame (opening / closing frame) 3 is attached so as to be openable and closable to an outer frame 2 which is attached to the island structure of a gaming hall, and a glass frame 4 is attached so as to be openable and closable to this inner frame 3. A window 4a is formed in the glass frame 4, and a transparent plate (glass plate) 4b is attached to the window 4a. A game board 10 having a board surface from which game balls are shot out is attached to the inner frame 3, and a game area 10a in which game balls can roll and flow down is formed between the board surface of the game board 10 and the transparent plate in front of it. The transparent plate 4b is, for example, a glass plate, and is fixed to the glass frame 4 in a detachable manner.

[0010] The glass frame 4 is connected to the outer frame 2 via a hinge mechanism 5 at one end in the left-right direction (for example, the left side when facing the gaming machine), and can be rotated in a direction to open the other end in the left-right direction (for example, the right side when facing the gaming machine) from the outer frame 2 with the hinge mechanism 5 as a fulcrum. The glass frame 4 covers the gaming board 10 together with a transparent plate, and can open the inner part of the outer frame 2 including the gaming board 10 by rotating like a door with the hinge mechanism 5 as a fulcrum. A lock mechanism is provided at the other end of the glass frame 4 to fix the other end of the glass frame 4 to the outer frame 2. The fixation by the lock mechanism can be released by a dedicated key. The glass frame 4 is also provided with an open detection switch 252 that detects whether the glass frame 4 is released from the outer frame 2 or not.

[0011] A tray unit 7 having storage trays 6 (upper tray 6a and lower tray 6b) for storing game balls is provided at the bottom of the glass frame 4 (the lower part of the window 4a). The tray unit 7 is equipped with a performance button 8 (Figure 1) that the player can press, a cross key 78 with which the player can perform various selection operations, and an ejection button 9 for ejecting the game balls stored in the lower tray 6b outside the gaming machine. The effect button 8 is only enabled when, for example, a message to operate the effect button 8 is displayed on the image display unit 31 described later. The effect button 8 is provided with an effect button detection switch 8a (see FIG. 3), and when this effect button detection switch 8a detects an operation by the player, a further effect is executed in response to this operation. The cross key 78 is provided with cross key detection switches 78a to 78d (an up key detection switch, a down key detection switch, a left key detection switch, and a right key detection switch).

[0012] An operating handle 11 is provided on the lower right side of the glass frame 4. When a player touches the operating handle 11, a touch sensor 11a (see FIG. 3) in the operating handle 11 detects that the player has touched the operating handle 11 and transmits a touch signal to the launch control board 75. When the launch control board 75 receives the touch signal from the touch sensor 11a, it allows the launch solenoid 12a to be energized. Then, the knob of the launch volume 11b rotates by changing the rotation angle of the operating handle 11. A voltage corresponding to the detected angle of the launch volume 11b is applied to the launch solenoid 12a provided in the game ball launching mechanism. Then, when a voltage is applied to the launch solenoid 12a, the launch solenoid 12a operates according to the applied voltage, and the game ball is launched into the game area 10a of the game board 10 with a strength corresponding to the rotation angle of the operating handle 11.

[0013] An outer rail R1 and an inner rail R2 are provided around the play area 10a of the play board 10. These outer rail R1 and inner rail R2 guide the play ball launched from the play ball launching mechanism to the upper part of the play area 10a when the operating handle 11 is operated. The play ball guided to the upper part of the play area 10a falls within the play area 10a. At this time, the game ball falls unpredictably due to multiple nails and windmills provided in the play area 10a. A center member 12 is disposed approximately in the center of the game board 10. The center member 12 is provided with an image display unit 31 made of a liquid crystal display device or the like, and a performance prop device 32 shaped like a "sword."

[0014] In addition, a first starting hole 13 through which a game ball can enter is provided in the game area 10a at the center lower side of the center member 12. A second starting hole 14 is provided below the first starting hole 13. The second starting hole 14 has an opening and closing door 14b, and is controlled to move between a first state in which the opening and closing door 14b is kept closed and a second state in which the opening and closing door 14b is open. Therefore, when the second starting hole 14 is in the first state, there is no chance of a game ball entering, and when it is in the second state, there is an increased chance of a game ball entering. In this embodiment, when the second starting hole 14 is controlled to the first mode, the game ball is prevented from entering the second starting hole 14. However, if there are fewer opportunities for the game ball to enter when the first mode is controlled than when the second mode is controlled, the game ball may enter the second starting hole 14 when the first mode is controlled. In other words, the first mode includes a state in which it is impossible or difficult for the game ball to enter the second starting hole 14.

[0015] The first start hole 13 and the second start hole 14 are provided with a first start hole detection switch 13a (see FIG. 3) and a second start hole detection switch 14a, respectively, which detect the entrance of a game ball, and when these detection switches detect the entrance of a game ball, a lottery for the right to play a jackpot game, which will be described later (hereinafter, referred to as a "jackpot lottery") is held. Also, when the first start hole detection switch 13a and the second start hole detection switch 14a detect the entrance of a game ball, a predetermined prize ball (for example, three game balls) is paid out. In the gaming machine 1 of this embodiment, when a gaming ball enters the first start hole 13 and the second start hole 14, for example, three gaming balls are paid out, but it is not necessary to pay out the gaming balls when they enter. Also, the number of payouts may be different for each start hole, for example, three for the first start hole 13 and one for the second start hole 14.

[0016] Gates 15 through which game balls can pass are provided in the game areas 10a on both sides of the center member 12. The gates 15 are provided with gate detection switches 15a (see FIG. 3) that detect the passage of game balls, and when the gate detection switches 15a detect the passage of game balls, a lottery for normal symbols, which will be described later, is held. Furthermore, a first large prize opening 16 and a second large prize opening 17 into which game balls can enter are provided in the game area 10a on the right side of the center member 12. For this reason, the game balls are configured not to enter the first large prize opening 16 and the second large prize opening 17 unless the game balls are shot out with great force by rotating the operating handle 11 greatly.

[0017] The first large prize opening 16 is normally kept closed by the opening / closing door 16b, making it impossible for game balls to enter. In contrast, when a big win game, which will be described later, starts, the opening / closing door 16b opens and functions as a tray that guides game balls into the first large prize opening 16, making it possible for the game balls to enter the first large prize opening 16. The first large prize opening 16 is provided with a first large prize opening detection switch 16a, and when the first large prize opening detection switch 16a detects the entry of a game ball, a preset number of prize balls (for example, 15 game balls) are paid out.

[0018] The second large prize opening 17 is normally kept in a closed state by the movable piece 17b, making it impossible for game balls to enter. In contrast, when a big win game, which will be described later, starts, the movable piece 17b is actuated and opened, and this movable piece 17b functions as a guide path that guides the game ball into the second large prize opening 17, making it possible for the game ball to enter the second large prize opening 17. The second large prize opening 17 is provided with a second large prize opening detection switch 17a, and when this second large prize opening detection switch 17a detects the entry of a game ball, a preset prize ball (for example, 15 game balls) is paid out. Furthermore, the game area 10a is provided with a plurality of general winning holes 18. When a game ball enters each of these general winning holes 18, a predetermined number of prize balls (for example, 10 game balls) are paid out.

[0019] At the bottom of the game area 10a, there is an outlet 19 for discharging game balls that do not enter any of the general winning opening 18, the first starting opening 13, the second starting opening 14, the first large winning opening 16, and the second large winning opening 17. The image display unit 31 displays images during standby when no game is being played, and displays images according to the progress of the game. In particular, when a game ball enters the first start hole 13 or the second start hole 14, a performance pattern 35 that notifies the player of the lottery result is displayed in a variable manner. The performance symbols 35 scroll three symbols (numbers), for example, a first symbol (left symbol), a second symbol (right symbol), and a third symbol (center symbol), and stop the scrolling after a predetermined time has elapsed to display a specific symbol (number). The performance symbols are displayed variably during the period when the special symbols are displayed variably, and are displayed stationary during the period when the special symbols are displayed stationary.

[0020] This gives the player the impression that a lottery is currently being drawn while the symbols are scrolling, and the player is notified of the lottery results by the symbols displayed when the scrolling stops. By displaying various images and characters during the varying display of the performance symbols 35, the player is given a high sense of expectation that he or she may win a jackpot. Although not shown, a fourth symbol is displayed on the image display unit 31 in addition to the effect symbol 35. The fourth symbol is a symbol that indicates a change state of the effect symbol 35 used to notify the lottery result by the big win lottery process. It should be noted that the fourth symbol does not necessarily have to be displayed on the image display unit 31, and may be displayed by a separate fourth symbol display lamp.

[0021] In addition to the performance pattern 35, the image display unit 31 displays a small performance pattern (small pattern) 35A smaller than the performance pattern 35. The small pattern 35A is composed of three patterns (left pattern, middle pattern, right pattern) like the performance pattern 35. The small pattern 35A is displayed variably during the period when the special pattern is displayed variably, and is displayed stationary during the period when the special pattern is displayed stationary. Depending on the effect being executed, the effect symbol 35 may be temporarily hidden, but the small symbol 35A is always displayed so that the player can always grasp the changing status of the symbol. In this embodiment, the small symbol 35A is displayed on the second display module 32b on the front side, which will be described later.

[0022] A pair of performance lighting devices 33, one on each side, are installed on the upper part of the glass frame 4. Each performance lighting device 33 is equipped with multiple lights, and various performances can be created by changing the irradiation direction and emission color of each light. Each of the performance lighting devices 33 is equipped with a plurality of lights, and various performances can be performed by changing the direction of light irradiation and the color of light emitted by each light. Furthermore, although not shown in FIG. 1, the gaming machine 1 is provided with an audio output device 34 (see FIG. 3) consisting of a speaker, which, in addition to the above-mentioned performance devices, outputs BGM (background music), SE (sound effects), etc., so as to provide sound-based performance. The audio output device 34 includes an upper left speaker SL0, an upper right speaker SR0, a lower left speaker SL1, a lower right speaker SR1, a subwoofer SSUB0, and a subwoofer SSUB1.

[0023] At the lower left side of the game area 10a, there are provided display areas including a first special pattern display device 20, a second special pattern display device 21, a normal pattern display device 22, a first special pattern reserved display device 23, a second special pattern reserved display device 24, a normal pattern reserved display device 25, and a round number display device 26, which will be described later. The first special symbol display device 20 notifies the player of the result of the lottery for the big win, which is triggered by the entry of a game ball into the first starting hole 13, and is composed of multiple LEDs. In other words, multiple special symbols corresponding to the lottery results for the big win are provided, and the lottery results are notified to the player by displaying special symbols (lighting patterns) corresponding to the lottery results for the big win on the first special symbol display device 20. The special symbols displayed in this way are not displayed immediately, but are displayed in a variable manner (blinking) for a predetermined period of time and then displayed stationary. More specifically, when a game ball enters the first starting hole 13, a lottery for a big win is held, but the result of this lottery is not immediately notified to the player, but is notified to the player after a predetermined time has passed. Then, after the predetermined time has passed, a special symbol corresponding to the lottery result for the big win is stopped and displayed, so that the lottery result is notified to the player.

[0024] The second special pattern display device 21 is intended to notify the result of the jackpot lottery that is triggered when a gaming ball enters the second starting hole 14, and its display mode is the same as the display mode of the special pattern in the first special pattern display device 20. The normal symbol display device 22 is for notifying the result of a lottery for normal symbols, which is conducted when the game ball passes through the gate 15. As will be described in detail later, when a predetermined winning is won in the lottery for this normal symbol, the normal symbol display device 22 lights up, and then the second starting hole 14 is controlled to the second mode for a predetermined time. Note that the lottery result for this normal symbol is not immediately notified when the game ball passes through the gate 15, but the normal symbol is displayed in a variable manner, such as by flashing the normal symbol display device 22, until the predetermined time has passed. Furthermore, when a game ball enters the first start hole 13 or the second start hole 14 and a lottery for a jackpot cannot be held immediately, such as during the variable display of special symbols or during a special game described below, the right to a lottery for a jackpot is reserved under certain conditions. More specifically, the right to a lottery for a jackpot reserved when a game ball enters the first start hole 13 is reserved as a first reservation, and the right to a lottery for a jackpot reserved when a game ball enters the second start hole 14 is reserved as a second reservation.

[0025] The upper limit of the number of reserved balls for each of these two reserves is set to four, and the number of reserved balls is displayed on the first special symbol reserved indicator 23 and the second special symbol reserved indicator 24, respectively. The maximum number of reserved ordinary symbols is also set to four, and the reserved number is displayed on the ordinary symbol reserved indicator 25 in the same manner as the first special symbol reserved indicator 23 and the second special symbol reserved indicator 24. The round number display 26 is for notifying the number of rounds of a round game performed during a special game, which will be described later.

[0026] 3, the rear surface of the gaming machine 1 is provided with a main control board 50, a performance control board 95, a payout control board 60, a launch control board 75, a power supply board PS, a game information output terminal board 27, etc. In addition, the power supply board PS is provided with a power plug P for supplying power to the gaming machine, and a power switch (not shown). As described later, the performance control board 95 is formed, for example, by combining a first performance board 55 and a second performance board 70.

[0027] A game control device that controls the progress of a game in the gaming machine 1 of this embodiment will be described with reference to FIG. 3, a main control board 50 controls the basic operations of a game. This main control board 50 is equipped with at least a one-chip microcomputer consisting of a main CPU 50a, a main ROM 50b, and a main RAM 50c, and input and output ports for main control (not shown). The main CPU 50a reads out the programs stored in the main ROM 50b and performs arithmetic processing based on the input signals from each detection switch, and also directly controls each device and display, or transmits commands to other boards according to the results of the arithmetic processing. The main RAM 50c functions as a data work area during the arithmetic processing of the main CPU 50a. Furthermore, when the power is turned on, the main CPU 50a starts up (boots up) by executing a startup program stored in the main ROM 50 or a startup ROM (boot ROM) provided separately.

[0028] The input side of the main control board 50 is connected to the first start hole detection switch 13a, the second start hole detection switch 14a, the gate detection switch 15a, the first large prize hole detection switch 16a, the second large prize hole detection switch 17a, and the general prize hole detection switch 18a, so that the detection signal of the game ball is input to the main control board 50. In addition, connected to the output side of the main control board 50 are a start opening / closing solenoid 14c which opens and closes the opening / closing door 14b of the second start opening 14, a first large prize opening opening / closing solenoid 16c which opens and closes the opening / closing door 16b of the first large prize opening 16, and a second large prize opening opening / closing solenoid 17c which opens and closes the movable piece 17b of the second large prize opening 17. Furthermore, the output side of the main control board 50 is connected to the first special pattern display device 20, the second special pattern display device 21, the normal pattern display device 22, the first special pattern reserved indicator 23, the second special pattern reserved indicator 24, the normal pattern reserved indicator 25, and the round count indicator 26, and various signals are output via the output ports. In addition, the main control board 50 outputs to the game information output terminal board 27 external information signals required for managing the gaming machines in the hall computer of the gaming establishment or the like.

[0029] The main ROM 50b of the main control board 50 stores a game control program (to be described later) and data and tables necessary for various games. Furthermore, the main RAM 50c of the main control board 50 has a plurality of storage areas. For example, the main RAM 50c includes a normal symbol reserved number (G) memory area, a normal symbol reserved memory area, a first special symbol reserved number (U1) memory area, a second special symbol reserved number (U2) memory area, a judgment memory area, a first special symbol memory area, a second special symbol memory area, a high probability game count (X) memory area, a time-saving game count (J) memory area, a round game count (R) memory area, an opening count (K) memory area, a first large prize entry ball count (C1) memory area, a second large prize entry ball count (C2) memory area, a game status memory area, a game status buffer, a stop symbol data memory area, a performance transmission data storage area, etc. The game status memory area includes a time-saving game flag memory area, a high probability game flag memory area, a special symbol special telephone processing data memory area, and a normal symbol normal telephone processing data memory area. Note that the above-mentioned memory areas are merely examples, and many other memory areas are provided.

[0030] The game information output terminal board 27 is a board for outputting external information signals generated in the main control board 50 to a hall computer or the like of an amusement facility. The game information output terminal board 27 is connected to the main control board 50 by wiring, and is provided with a connector for connecting to a hall computer or the like of an amusement facility. The power supply board PS converts the power supply voltage supplied from the power plug P to a predetermined voltage and supplies it to each control board. The power supply board PS also has a backup power supply consisting of a capacitor, which monitors the power supply voltage supplied to the gaming machine and outputs a power interruption detection signal to the main control board 50 when the power supply voltage falls below a predetermined value. More specifically, when the power interruption detection signal becomes high level, the main CPU 50a becomes operable, and when the power interruption detection signal becomes low level, the main CPU 50a becomes inoperative. The backup power supply is not limited to a capacitor, and may be, for example, a battery, or a combination of a capacitor and a battery.

[0031] The performance control board 95 mainly controls each performance during play, standby, etc. This performance control board 95 is equipped with a performance control CPU 71, and is connected to the main control board 50 so as to be able to communicate in one direction from the main control board 50 to the performance control board 95. The performance control board 95 further includes a performance control ROM 73 and a performance control RAM 74. The performance control CPU 71 is equipped with an integrated performance control ROM 73 and a performance control RAM 74. The performance control CPU 71 includes a general control CPU 76 (FIG. 4), an image control CPU (host CPU) 151, and an image processor (VDP) 157. The overall control CPU 76 reads out a program stored in the performance control ROM 73 and performs arithmetic processing based on commands transmitted from the main control board 50 or an input signal from the performance button detection switch 8a, and transmits corresponding data to the performance control board 95 based on the processing. The performance control RAM 74 functions as a work area for data during calculation processing by the performance control CPU 71 (overall control CPU 76).

[0032] The performance control ROM 73 stores programs for performance control, data required for various games, and tables. For example, a variable presentation pattern determination table (not shown) for determining a presentation pattern based on a variable pattern designation command received from the main control board 50, a presentation symbol pattern determination table (not shown) for determining a combination of presentation symbols 35 to be stopped and displayed, and the like are stored in the presentation control ROM 73. Note that the above-mentioned tables are merely examples of characteristic tables among the tables in this embodiment, and many other tables and programs (not shown) are provided in the course of the game.

[0033] The performance control RAM 74 has multiple storage areas. The performance control RAM 74 is provided with a command receiving buffer, a game status storage area, a performance mode storage area, a performance pattern storage area, a performance symbol storage area, a judgment storage area (0th storage area), a first reserved storage area, a second reserved storage area, etc. The above-mentioned storage areas are merely examples, and many other storage areas are provided. In addition, the performance control board 95 is equipped with an RTC (real-time clock) 79 that outputs the current time. The performance control CPU 71 inputs a date signal indicating the current date and a time signal indicating the current time from the RTC 79, and executes various processes based on the current date and time. The RTC 79 normally operates on power from the gaming machine when power is supplied to the gaming machine, and operates on power supplied from a backup power supply mounted on the power supply board PS when the power to the gaming machine is turned off. Therefore, the RTC 79 can measure the current date and time even when the power to the gaming machine is turned off. The RTC 79 may be operated by a battery provided on the performance control board 95.

[0034] The payout control board 60 controls the launch of game balls and the payout of prize balls. The payout control board 60 is equipped with a payout CPU 60a, a payout ROM 60b, and a payout RAM 60c, and is connected to the main control board 50 so as to be able to communicate in both directions. The payout CPU 60a reads out a program stored in the payout ROM 60b and performs arithmetic processing based on input signals from a payout ball counting switch 251 and an opening detection switch 252, which detect whether game balls have been paid out or not, and transmits corresponding data to the main control board 50 based on the processing.

[0035] Also, the output side of the payout control board 60 is connected to a payout motor 250 of a prize ball payout device for paying out a predetermined number of prize balls from a game ball storage section to a player. The payout CPU 60a reads out a predetermined program from the payout ROM 60b and performs arithmetic processing based on a payout number designation command transmitted from the main control board 50, and controls the payout motor 250 of the prize ball payout device to pay out a predetermined number of prize balls to a player. At this time, the payout RAM 60c functions as a data work area during the arithmetic processing of the payout CPU 60a. It also checks whether a game ball lending device (card unit) not shown is connected to the payout control board 60, and if the game ball lending device (card unit) is connected, it transmits launch control data to the launch control board 75 to allow the game balls to be launched. In addition, a tray full detection switch 51 and a ball jam detection switch 52 are connected to the dispensing control board 60.

[0036] The launch control board 75 permits launch when it receives launch control data from the payout control board 60. Then, it reads out the touch signal from the touch sensor 11a and the input signal from the launch volume 11b, controls the energization of the launch solenoid 12a and the ball feed solenoid 12b, and launches the game ball. The firing solenoid 12a is a rotary solenoid. A firing member (not shown) is directly connected to the firing solenoid 12a, and the firing solenoid 12a rotates to rotate the firing member. Here, the rotation speed of the launch solenoid 12a is set to about 99.9 (times / minute) based on the frequency based on the output cycle of the crystal oscillator provided on the launch control board 75. As a result, the number of launched game balls per minute is about 99.9 (balls / minute), since one ball is launched per rotation of the launch solenoid. In other words, a game ball is launched approximately every 0.6 seconds. The ball-sending solenoid 12b is composed of a linear solenoid, and sends out the game balls on the upper tray 6a (see FIG. 1) one by one toward a striking member directly connected to the launch solenoid 12a.

[0037] The input side of the performance control board 95 is connected to the performance button detection switch 8a provided on the performance button 8, and a detection signal is input from the performance button detection switch 8a. The performance control board 95 is also connected to the performance accessory device 32 and the performance lighting device 33 provided on the game board 10, and the performance control CPU 71 controls the lighting of the performance lighting device 33 and controls the drive of a motor for changing the direction of light irradiation. It also controls the supply of electricity to drive sources such as solenoids and motors that operate the performance accessory device 32. In this embodiment, the performance button 8 is configured to protrude, so the performance accessory device 32 includes the performance button 8. The performance control board 95 has an output side connected to the image display unit 31 and the audio output device 34. The performance control board 95 is also provided with a volume changeover switch 36 for changing the volume of the sound output from the audio output device 34.

[0038] Next, the performance button 8 is incorporated in the center part of the plate unit 7. The effect button 8 is configured to be movable between a normal operation position (not shown), a depressed position retracted below the normal operation position, and a protruding operation position protruding above the normal operation position. The effect button 8 is also configured to be capable of being depressed from any position including the normal operation position and the protruding operation position to the depressed position. In addition, in this specification, the detailed structure of the effect button 8 is disclosed in, for example, JP 2013-116168 A, so description thereof will be omitted.

[0039] <Configuration of the performance control CPU> Here, the configuration of the performance control CPU will be explained using FIG. FIG. 4 is a block diagram showing the configuration of the performance control CPU. The performance control CPU 71 is a SoC (System On Chip) that integrates a host CPU 151, host RAM 152, host ROM 153, CGROM 154, crystal oscillator 155, VRAM 156, VDP (Video Display Processor) 157, and an overall control CPU 76 to control the image display of the image display unit 31 (first liquid crystal module 31a, second liquid crystal module 31b). 4, VDP 157, host CPU 151, and overall control CPU 76 are shown separately, but VDP 157 may include host CPU 151. Also, overall control CPU 76 and host CPU 151 may be combined into one CPU. In that case, the contents stored in host ROM 153 and host RAM 151 may be stored in performance control ROM 73 and performance control RAM 74. As will be described later, the VDP 157 also includes a sound control circuit 300 for controlling sound output in the gaming machine.

[0040] Based on a later-described effect pattern designation command received from the overall control CPU 76, the host CPU 151 instructs the VDP 157 to display image data stored in the CGROM 154 on the image display unit 31. Such instructions are made by setting data in the control register 201 of the VDP 157 and outputting a display list made up of a group of drawing control commands. Furthermore, when the host CPU 151 receives a V blank interrupt signal or a drawing end signal from the VDP 157, it performs appropriate interrupt processing.

[0041] Furthermore, the host CPU 151 instructs the audio control circuit 300 included in the VDP 157 to output predetermined audio data to the audio output device 34 based on the performance pattern designation command received from the performance control board 95. The host RAM 152 is built in the host CPU 151, and functions as a work area for data during arithmetic processing by the host CPU 151, and temporarily stores data read from the host ROM 153.

[0042] In addition, the host ROM 153 is composed of a mask ROM, and stores a control processing program for the host CPU 151, pattern arrangement information that corresponds the pattern numbers of the performance patterns to the types of performance patterns 35, a display list generation program for generating a display list, animation patterns for displaying animations of performance patterns, animation scene information, etc. This animation pattern is referenced when displaying the animation of the production pattern, and stores the combination of animation scene information included in the production pattern, the display order of each animation scene information, etc. Also, the animation scene information stores information such as wait frame (display time), target data (sprite identification number, transfer source address, etc.), parameters (sprite display position, transfer destination address, etc.), drawing method, etc.

[0043] The CGROM 154 is made up of flash memory, EEPROM, EPROM, mask ROM, etc., and stores compressed image data (sprites, movies) etc., which are a collection of pixel information for a given range of pixels (e.g., 32 x 32 pixels). The pixel information is made up of color number information that specifies a color number for each pixel, and an α value that indicates the transparency of the image. Furthermore, the CGROM 154 stores uncompressed palette data in which color number information for specifying a color number is associated with display color information for actually displaying the color. The CGROM 154 may be configured to compress only a portion of the image data instead of compressing all of the image data. As a compression method for movies, various known compression methods such as MPEG4 can be used. The CGROM 154 also stores a large amount of voice data, as will be described later.

[0044] The crystal oscillator 155 outputs a pulse signal to a clock generation circuit 205 of the VDP 157, and by dividing the frequency of this pulse signal, the clock generation circuit 205 generates a system clock for the VDP 157 to perform control, a synchronization signal for synchronizing with the image display unit 31, and the like. The clock generation circuit 205 will be described in detail later.

[0045] The VRAM 156 is composed of an SRAM that allows high-speed writing and reading of image data. The VRAM 156 also has a display list storage area 156a for temporarily storing a display list output from the host CPU 151, a development storage area 156b for storing image data expanded by the expansion circuit 206, and a first frame buffer 156c and a second frame buffer 156d for the first liquid crystal module 31a, and a first frame buffer 156e and a second frame buffer 156f for the second liquid crystal module 31b, for drawing or displaying images. The VRAM 156 also stores palette data. The two sets of frame buffers (156c and 156d, and 156e and 156f) are alternately switched between a "drawing frame buffer" and a "display frame buffer" every time drawing starts.

[0046] The VDP 157 is a so-called image processor, which reads image data from one of the frame buffers (display frame buffers) based on instructions from the host CPU 151, generates video signals (R (red), G (green), B (blue) signals, etc.) based on the read image data, and outputs them to the image display unit 31. However, in the gaming machine of this embodiment, the VDP 157 is not merely an image processor, but also has a sound output function. The VDP 157 also includes a control register 201 , a CG bus I / F 202 , a CPU I / F 203 , a clock generation circuit 205 , an expansion circuit 206 , a drawing circuit 207 , a display circuit 208 , a memory controller 209 , and an audio control circuit 300 .

[0047] The control register 201 is a register used by the VDP 157 to control drawing and display, and drawing control and display control are performed by writing and reading data to and from the control register 201. The host CPU 151 can write and read data to and from the control register 201 via the CPU I / F 203. This control register 201 has six types of registers: a system control register for making basic settings necessary for the operation of the VDP 157; a data transfer register for making settings necessary for data transfer; a drawing register for making settings to control drawing; a bus interface register for making settings necessary for bus access; an decompression register for making settings necessary for decompressing compressed images; and a display register for making settings to control the display.

[0048] The CG bus I / F 202 is an interface circuit for communication with the CGROM 154 , and image data from the CGROM 154 is input to the VDP 157 via the CG bus I / F 202 . In addition, the CPU I / F 203 is an interface circuit for communication with the host CPU 151, and via the CPU I / F 203, the host CPU 151 outputs a display list to the VDP 157, accesses control registers, and inputs various interrupt signals from the VDP 157.

[0049] The data transfer circuit 204 transfers data between various devices. Specifically, it transfers data between the host CPU 151 and the VRAM 156, between the CGROM 154 and the VRAM 156, and between various storage areas of the VRAM 156 (including the frame buffer). The clock generation circuit 205 receives a pulse signal from the crystal oscillator 155 and generates a system clock that determines the arithmetic processing speed of the VDP 157. It also generates a clock for generating a synchronization signal and outputs the synchronization signal to the image display unit 31 via the display circuit.

[0050] The decompression circuit 206 is a circuit for decompressing the image data compressed in the CGROM 154, and stores the decompressed image data in the development memory area 153b. The drawing circuit 207 is a circuit that performs sequence control according to a display list that is made up of a group of drawing control commands.

[0051] The display circuit 208 is a circuit that generates R (red), G (green), and B (blue) signals (analog signals) that indicate color data of an image as a video signal from image data (digital signals) stored in a "display frame buffer" in the VRAM 156, and outputs the generated video signals (R (red), G (green), and B (blue) signals) to the first liquid crystal module 31a and the second liquid crystal module 31b. Furthermore, the display circuit 208 also outputs synchronization signals (vertical synchronization signal, horizontal synchronization signal, etc.) for synchronizing with the first liquid crystal module 31a and the second liquid crystal module 31b to the first liquid crystal module 31a and the second liquid crystal module 31b. In this embodiment, R (red), G (green), and B (blue) signals obtained by converting digital signals into analog signals are output to the first liquid crystal module 31a and the second liquid crystal module 31b as video signals, but the video signals may also be output as digital signals.

[0052] When the host CPU 151 instructs the memory controller 209 to switch the frame buffer, the memory controller 209 controls switching between the "drawing frame buffer" and the "display frame buffer." The audio control circuit 300 reads out a predetermined program based on a command sent from the performance control board 95 and controls the audio output in the audio output device 34 . The audio control circuit 300 outputs audio using audio data stored in the CGROM 154. In this case, the CGROM 154 includes a sound source ROM for storing audio data.

[0053] Note that instead of storing the audio data in CGROM 154, a sound source ROM may be provided separately in VDP 157. In this case, since a larger amount of image data can be stored instead of audio data being stored in the CGROM 154, which has a fixed capacity, the presentation using video can be made more diverse and impressive.

[0054] Also, the sound control circuit 300 may not be included in the VDP 157, but may be provided independently on the performance control board 95. In that case, the sound source ROM may be included in the sound control circuit 300. The first liquid crystal module 31a and the second liquid crystal module 31b constituting the image display unit 31 are provided with an LCD driver 36a and an LCD driver 36b for driving the liquid crystal, respectively, and control signals from the VDP 157 are input to these LCD drivers. Either the LCD driver 36a or the LCD driver 36b controls a plurality of LED light sources that emit light as a backlight.

[0055] <Configuration of the back of the game board> Next, the configuration of the back side of the game board will be described. FIG. 5 is a rear view showing a state in which each unit is assembled to the base frame, and FIG. 6 is a partially exploded perspective view of FIG. 2, 5, 6, etc., a base frame (liquid crystal base frame) 130 having an opening penetrating in the front-rear direction is attached to the rear (rear surface) of the game board 10, and an image unit (image display unit 31, and image display cover 165) 160 is attached to the rear (rear side) of the base frame so as to cover the opening. A lamp relay board 166 is attached to the rear (rear surface) of the image display cover (liquid crystal cover) 165, and a board protection case (board case) 200 accommodating a main control board is attached to the lower rear part of the image display cover 165 below the lamp relay board 166.

[0056] The base frame (liquid crystal base) 130 is a substantially rectangular ring-shaped body having openings penetrating in the front, rear and side directions, and its ring-shaped front surface 131 is attached and fixed to the rear surface of the game board 10. There is space on the rear surface of the base frame for arranging various circuit boards and components. A first performance board 55 and a second performance board 70 that constitute a performance control board 95 stored in a performance board case 700 are arranged on the rear side of the image unit (liquid crystal unit) 160 fixed to the rear side of the base frame 130. The image unit 160 is configured so that it can be freely slidably attached to the base frame from the side (left and right direction), up and down direction, or diagonally within a gap (storage space) for storing an image display unit provided on the front side of the first performance board. The various circuit boards arranged on the rear surface of the base frame are covered with a cover member 170 (FIGS. 5 and 6).

[0057] The gaming machine of this embodiment is characterized by a performance board case that houses a performance control board 95. The performance control board 95 is, for example, configured by combining a first performance board 55 and a second performance board 70. The first performance board 55 and the second performance board 70 are housed in a performance board case 700 in an integrated state by being connected via a connector. In the present embodiment described below, the side of the gaming machine 1 facing the player is referred to as the front side, and the rear side not facing the player is referred to as the rear side.

[0058] Figure 7 is a diagram explaining the performance control board (first performance board) stored in the performance board case of this embodiment, where (a) is a diagram of the first performance board seen from the rear, and (b) is a diagram of the first performance board seen from the front. As shown in Figure 7, the first performance board 55 is equipped with, on its rear surface, a battery holder 80 in which a button battery for operating, for example, an RTC 79 can be attached, a connector 81 which is connected to a connector provided on a ROM cassette 40 described later, an equal number of connectors 82 (second connectors) which are connected to two connectors 72 (Figure 8) on the second performance board 70, a connector 83 (third connector) to which a harness for the main control board 50 is connected, a segmented LCD 85 which displays errors, an FeRAM 77 described later, and other electronic components such as capacitors, ICs, etc.

[0059] The segment LCD 85 can be configured by one 7-segment LCD or 7-segment LED. The 7-segment LCD is a liquid crystal display device that is configured by seven segments that can be individually turned on / off to represent one character of a number. A 7-segment LED is an LED display device consisting of seven segments that can be turned on and off individually to represent one digit. The segmented liquid crystal 85 may further include a segment for displaying dots in addition to the seven segments for displaying numbers. When an error occurs and the door of the gaming machine is opened, the player may mistake the error number displayed on the segment LCD 85 for a setting value. For this reason, the error may be displayed on the segment LCD 85 using symbols such as alphabets instead of numbers.

[0060] Figure 8 is a diagram explaining the performance control board (second performance board) stored in the performance board case of this embodiment, where (a) is a diagram of the second performance board seen from the front, and (b) is a diagram of the second performance board seen from the rear. As shown in Figure 8, the second performance board 70 has a performance control CPU 71 on its front surface, and an equal number of connectors 72 on its back surface that are connected to the two connectors 82 of the first performance board 55. The performance control CPU 71 integrates (combines) the functions of the performance control CPU, image control CPU, lamp control CPU, and VDP, and has built-in ROM and RAM. In this embodiment, the program used for the performance control by the performance control CPU 71 and the image data displayed by the performance control CPU 71 are stored in an integrated data ROM 92 contained in a removable ROM cassette 40. The image data in the integrated data ROM 92 can be supplied to the second performance board 70 via the first performance board 55.

[0061] Fig. 9 is a schematic front view illustrating the performance board case of this embodiment. Fig. 10 is a schematic perspective view illustrating the performance board case of this embodiment. Figs. 11 and 12 are exploded perspective views of the performance board case. Fig. 13 is a diagram illustrating parts to be attached to the performance board case. An overview of the performance board case of this embodiment will be described with reference to Figures 9 to 12. As shown in Figs. 9 to 12, the performance board case 700 includes a board base 700B (front case piece) and a board cover 700A (rear case piece). By combining the board cover 700A and the board base 700B, a performance board case 700 (base member) is formed as a box that contains the performance board. The board cover 700A constituting the performance board case 700 further includes a ROM cassette 40 (mounting member), a heat sink 730, a heat sink cover 740, etc., at its rear side.

[0062] As shown in Figures 11 and 12, the board base 700B and the board cover 700A respectively have a base-side board accommodating section 701 and a cover-side board accommodating section 702 for accommodating the first performance board 55 and the second performance board 70. The performance board case 700 configures an inner section (board storage section) with a base side board storage section 701 (FIG. 11) provided on the board base 700B and a cover side board storage section 702 (FIG. 12) provided on the board cover 700A, and stores the first performance board 55 and the second performance board 70 in the inner section. The first performance board 55 and the second performance board 70 are connected via a connector and stored in the performance board case 700 in an integrated state. As will be described in detail later, the first performance board 55 is screwed to the board cover 700A. In reality, the first performance board 55 has four openings. The first performance board 55 is fixed to the board cover 700A by passing a screw through each opening of the first performance board 55 and screwing the screw into the screw hole of the board cover 700A. As an example, the screw 741 screws into the screw hole 745 of the board cover 700A. In the board cover 700A, openings 715, 716 (Figure 11) are provided at locations corresponding to the positions of the connector 83 and segmented LCD 85 on the first performance board 55, and the connector 83 and segmented LCD 85 are exposed on the rear side of the board cover 700A (Figures 9 and 10). Since the connector 83 is exposed, it is easy to connect to the main control board 50 using a harness, and the display on the segmented LCD 85 can be checked through the board cover 700A, which is very convenient.

[0063] In addition, the base side substrate accommodating portion 701 and the cover side substrate accommodating portion 702 each have a plate portion formed in an approximately rectangular shape and a flange portion protruding from the peripheral edge of each plate portion and surrounding one side surface of each plate portion (Figures 11 and 12). The flange portion constituting the base side substrate accommodating portion 701 of the substrate base 700B has five L-shaped hook pieces 701a formed on each of the portions protruding along the two long sides of the substrate base 700B (Figure 11). On the other hand, among the flanges constituting the cover-side substrate accommodating portion 702 of the substrate cover 700A, the portions protruding along the two long sides of the substrate cover 700A are formed into a double-wall shape, and an insertion groove portion 702a into which the hook piece 701a of the substrate base 700B can be inserted is provided between the walls forming the double wall. Also, a hook piece is formed in each insertion groove portion 702a (FIG. 12).

[0064] When the board cover 700A and the board base 700B are assembled together, the hook pieces 701a of the board base 700B are inserted into the insertion grooves 702a of the board cover 700A. Then, the board base 700B is slid in the direction of the arrow α in FIG. 11 and FIG. 12 along the left-right direction relative to the board cover 700A. Then, the hook piece of the board cover 700A and the hook piece of the board base 700B engage with each other, so that the board base 700B and the board cover 700A are combined so that they will not come off unless they move each other in the opposite direction to the arrow α. When combined in this way, the board cover 700A and the board base 700B form a box-shaped inner container part (board container part) that is shielded from the outside by the base side board container part 701 and the cover side board container part 702, and the first performance board 55 and the second performance board 70 are stored in the inner container part. This can suppress the possibility of the first performance board 55, the second performance board 70, etc. being illegally replaced.

[0065] In this embodiment, the board base 700B and the board cover 700A are sealed by a fastening seal portion 750A with the first performance board 55 and the second performance board 70 sandwiched between them. As shown in Figures 8 and 9, at appropriate positions along the edges of the performance board case 700, there are provided fastening seal parts 750A for closing (sealing) the board base 700B and the board cover 700A.

[0066] As shown in FIG. 11, the board base 700B and the board cover 700A each include locked portions 720, 721 that form a fastening seal portion 750A. As described below, the fastening sealing portion 750A locks the board base 700B and the board cover 700A in a closed (sealed) state by driving a locking member (rivet pin) into the fastening holes of the locked portions 720 and 721 to lock the locked portions 720 and 721. By removing the locking member (rivet pin) driven into the fastening holes of the locked portions 720 and 721, the performance board case 700 consisting of the board base 700B and the board cover 700A becomes openable. Sealing or closing the performance board case 700 means making the performance board case 700 in an unopenable state unless the sealing member driven into the sealed portion is removed or the fastening (seal) is destroyed.

[0067] On the other hand, as shown in FIG. 9 and FIG. 10, the attachment portion of the ROM cassette 40 on the performance board case 700 is provided with a fastening locking portion 750B for fastening (locking) the ROM cassette 40 to the performance board case 700. The fastening locking portion 750B is a fastening locking portion for further fixing (locking) the ROM cassette 40 to the performance board case 700 in a state in which the board base 700B and the board cover 700A are closed (sealed) by the fastening sealing portion 750A. The fastening locking portion 750B locks (fixes) the ROM cassette 40 to the performance board case 700 (board cover 700A) by driving a locking member (rivet pin) into a fastening hole provided in the locked portion 42, 709 as described below to lock the locked portion 42, 709. The ROM cassette 40 can be removed from the board cover 700A by removing the locking member (rivet pin) driven into the fastening hole of the locked portion 42, 709. When removing the ROM cassette 40, it is necessary to release the lock by the fastening locking portion 750B, but it is not necessary to release the seal by the fastening sealing portion 750A. Furthermore, when opening the performance board case 700, it is necessary to release the seal by the fastening sealing portion 750A, but it is not necessary to release the lock by the fastening locking portion 750B. The different fastening modes of the fastening seal portion 750A and the fastening lock portion 750B will be described in detail later.

[0068] As shown in FIG. 13, the board cover 700A has an opening 703 on the rear side at a position corresponding to the second performance board 70, and further on the rear side is provided with a heat sink 730 to cover the opening 703. Furthermore, the board cover 700A includes a heat sink cover 740 that covers the heat sink 730 on the rear side of the board cover 700A. The board cover 700A also has a cassette attachment portion 704 on the rear side for attaching the ROM cassette 40 thereto. The cassette attachment portion 704 is provided with a positioning pin 705 that protrudes from the surface of the board cover 700A. The positioning pin 705 is used to position the ROM cassette 40 when a worker attaches it to the performance board case 700 (board cover 700A), and also fits into an insertion hole 45 (described later) provided in the ROM cassette 40 to secure the ROM cassette 40 to the performance board case 700 (board cover 700A).

[0069] In addition, the cassette mounting portion 704 has an opening 706 at a position corresponding to a connector 81 (first connector) protruding from the first performance board 55 contained within the performance board case 700, and the connector 81 is exposed from the opening 706. When the ROM cassette 40 is attached to the cassette mounting portion 704 of the performance board case 700 (board cover 700A), the connector 81 of the first performance board 55 is connected to a connector 91 (fourth connector) provided on the integrated ROM board 90 contained in the ROM cassette 40. Further, the cassette attachment portion 704 is provided with a multi-purpose claw portion 710 in the vicinity of the positioning pin 705 in the figure. The characteristics of the claw portion 710 will be described in detail later. Furthermore, the cassette mounting portion 704 is provided with an opening 707 provided at a position corresponding to a button battery that is detachably attached to the first performance board 55 contained within the performance board case 700, and a detachable cover 708 that covers the opening 707. When it is necessary to install or replace a button battery in the battery holder 80 provided on the first performance board 55, the interior of the performance board case 700 can be accessed simply by removing the removable cover 708. There is no need to open the performance board case 700.

[0070] The cassette attachment portion 704 is provided with a locked portion 709 which, when the ROM cassette 40 is normally attached, forms a fastening locking portion 750B together with the locked portion 42 of the cassette case 40A and into which a locking member (rivet pin) is driven. When the ROM cassette 40 is fastened to the board cover 700A (performance board case 700), the detachable cover 708 provided on the cassette mounting portion 704 cannot be removed, and the detachable cover 708 can be removed only after the ROM cassette 40 is removed from the board cover 700A (performance board case 700), thereby preventing unauthorized access to the inside of the performance board case 700. Fastening the ROM cassette 40 to the board cover 700A (performance board case 700) not only secures the ROM cassette 40 (prevents it from being taken away), but also makes it possible to easily control whether or not access is possible to the inside of the performance board case 700.

[0071] Furthermore, as shown in FIG. 13, the side wall portion 104a of the cassette mounting portion 704 is provided with a first fixing portion 711 that fixes the first fixed portion 43 (described later) of the ROM cassette 40 when the ROM cassette 40 is attached to the board cover 700A, and a claw portion 710 that protrudes downward leaving a space 710a between itself and the surface of the cassette mounting portion 704 and fixes the second fixed portion 44 between itself and the surface of the cassette mounting portion 704.

[0072] As shown in Figures 9 and 10, slide locks 550 for closing (sealing) board base 700B and board cover 700A are provided at appropriate locations along the edges of performance board case 700. By operating knob 551 downward (in the direction of arrow 552) from the state shown in Figures 9 and 10 and pushing it down to the position marked LOCK, it is possible to lock the performance board case 700 from being opened. Conversely, by sliding knob 551 upward (opposite the direction of arrow 552) to return it to the state shown in Figures 9 and 10, the lock on performance board case 700 can be released, making it possible to open it, provided that the seal by fastening sealing portion 750A has been released.

[0073] <ROMカセット> FIG. 14 shows a ROM board equipped with an integrated data ROM, where (a) is a rear view of the ROM board, and (b) is a front view of the ROM board. As shown in FIG. 14, the integrated ROM board 90 has a connector 91 on its front surface for connecting to the connector of the first performance board 55, and an integrated data ROM 92 on its rear surface. Figure 15 is a schematic diagram of a ROM cassette, where (a) is a schematic perspective view of the ROM cassette seen from the rear, and (b) is a view of the ROM cassette seen from the front. Figures 16 and 17 are exploded perspective views of the ROM cassette.

[0074] The configuration of the ROM cassette of this embodiment will be described with reference to FIGS. As described above, the ROM cassette 40 is removably attached to the cassette mounting portion 704 of the board cover 700A in the performance board case 700. The ROM cassette 40 includes a cassette body 40B that houses an integrated ROM board 90 therein, and a cassette case 40A that houses the cassette body 40B therein. The cassette case 40A comprises an engaging portion 42 which constitutes the fastening engaging portion 750B together with an engaging portion 709 provided on the performance board case 700 (board cover 700A), a first fixed portion 43 which is fixed to the performance board case 700 (board cover 700A), and a second fixed portion 44. The cassette body 40B has an insertion hole 45 into which a positioning pin 705 protruding from the cassette mounting portion 704 on the surface of the board cover 700A is inserted, and a connector 91 which is connected to the connector 81 of the first performance board 55 contained within the performance board case 700.

[0075] The connector 91 is provided on the integrated ROM board 90 housed in the cassette body 40B and protrudes from the opening 41 of the cassette body 40B. As shown in FIGS. 16 and 17, the cassette body 40B is accommodated in a cassette body accommodating portion 46 of the cassette case 40A, and the cassette body 40B accommodates the integrated ROM board 90 in a ROM board accommodating portion 47 thereof.

[0076] The display mode and display control of the image display unit 31, which is a characteristic component of the gaming machine of this embodiment, will be described below. As described above, the image display unit 31 of this embodiment is a display device that combines a first liquid crystal module 31a that performs color display by a first method using color filters, and a second liquid crystal module 31b that performs color display by a second method not using color filters. In the image display unit 31, from the rear side as viewed from the player, a backlight 100, a first liquid crystal module 31a, and a second liquid crystal module 31b are arranged. In this specification, the term "backlight" refers to a light guide plate or light emitting plate such as an acrylic plate that emits light from a surface by guiding incident light from an LED as a light source to the front side.

[0077] Before describing the characteristic configuration of the image display unit 31 of this embodiment, the basic configurations of the first liquid crystal module 31a and the second liquid crystal module 31b will be described. <Basic configuration of the first liquid crystal module> FIG. 18 is a schematic cross-sectional view illustrating the basic configuration of the first liquid crystal module. Generally, a liquid crystal display device includes white LEDs 115W as a light source, a backlight (light guide plate) 100 that emits light using the light emitted from the LEDs 115W, and a first liquid crystal module 31a arranged on the front side of the backlight 100. The white LEDs 115W emit white light, and white light is emitted from the backlight 100. The white light emitted from the backlight 100 enters the first liquid crystal module 31a. In the image display unit 31 of this embodiment, which will be described later in detail, the light incident on the first liquid crystal module 31a is not white backlight light from the white LED 115W, but backlight light of multiple colors that are sequentially switched based on the color display of the second method. However, the function as a liquid crystal module is the same, and the case where the white LED 115W is used will be described. In summary, the first liquid crystal module 31a includes a layer in which liquid crystal molecules are arranged (liquid crystal molecular layer), a color filter laminated on the front side thereof, and a polarizing filter. The color filter configures one pixel with sub-pixels of three colors, R (red), G (green), and B (blue).

[0078] In this specification, a liquid crystal molecular layer in which liquid crystal molecules are aligned may be simply called liquid crystal molecules or liquid crystal for the sake of simplicity. The function of the liquid crystal molecules will be described in detail later, but the liquid crystal molecules of the first liquid crystal module 31a are driven by a drive signal (drive voltage) applied from the LCD driver 36a based on a video signal from the VDP 157. The liquid crystal molecules driven based on the drive signal perform polarization control on the light that has entered the liquid crystal molecular layer so that the light can or cannot exit from the polarizing filter after passing through the color filter of each sub-pixel.

[0079] In FIG. 18, for example, for one pixel of the first liquid crystal module 31a, when the liquid crystal molecules are controlled so that light emitted from the R sub-pixel (color filter) can pass through the polarizing filter, light emitted from the G sub-pixel (color filter) cannot pass through the polarizing filter, and light emitted from the B sub-pixel (color filter) cannot pass through the polarizing filter, the pixel emits R (red). For another pixel, if the liquid crystal molecules are controlled so that the light emitted from the G sub-pixel (color filter) can pass through the polarizing filter, the light emitted from the R sub-pixel (color filter) can pass through the polarizing filter, and the light emitted from the B sub-pixel (color filter) cannot pass through the polarizing filter, then that pixel will emit G (green) light. When expressing an intermediate color in one pixel, the liquid crystal molecules are controlled so that light emitted from all sub-pixels (color filters) can pass through the polarizing filter, while the liquid crystal molecules are controlled so as to adjust the amount of light entering each sub-pixel (the amount of light emitted from the liquid crystal molecular layer). By controlling the driving of the liquid crystal molecules corresponding to the sub-pixels for all pixels, an image can be displayed on the entire screen.

[0080] The display control of the first liquid crystal module will be described in detail with reference to FIGS. FIG. 19 is a schematic diagram showing a layered structure of elements constituting the first liquid crystal module. As shown in Figure 19, the first liquid crystal module 31a is configured by stacking, from the backlight 100 side, an incident-side polarizing filter 101a, a glass substrate 102a, an incident-side transparent electrode 103a, an incident-side light distribution film 104a, liquid crystal molecules 105a, an exit-side light distribution film 106a, an exit-side transparent electrode 107a, a color filter 108, and an exit-side polarizing filter 109a. A current is applied to the incident-side transparent electrode 103a and the exit-side transparent electrode 107a to apply a voltage to the liquid crystal molecules 105a. That is, a drive voltage is applied between the incident-side transparent electrode 103a and the exit-side transparent electrode 107a to drive the liquid crystal molecules 105a.

[0081] The operation of the liquid crystal module in a typical driving method will be described below. The operation of the first liquid crystal module will be described, but the second liquid crystal module (described later) also operates in a similar manner. As described later, the second liquid crystal module 31b is configured by stacking, from the backlight 100 side, an incident side polarizing filter 101b, a glass substrate 102b, an incident side transparent electrode 103b, an incident side light distribution film 104b, liquid crystal molecules 105b, an exit side light distribution film 106b, an exit side transparent electrode 107b, and an exit side polarizing filter 109b. In the following description of the operation of the liquid crystal module in a typical driving method, elements common to the first liquid crystal module 31a and the second liquid crystal module 31b will not be marked with the symbols a and b and will not be distinguished from one another.

[0082] FIG. 20 is a diagram for explaining the basic operation of a TN type liquid crystal module. In a liquid crystal module that employs the TN (Twisted Nematic) method, when the voltage applied to the liquid crystal molecules is OFF, the liquid crystal molecules 105 align themselves horizontally, allowing the light incident from the entrance side polarizing filter 101 to pass through the exit side polarizing filter 109. When the voltage is ON, the liquid crystal molecules stand up and block the light at the exit side polarizing filter 109, thereby controlling the light exiting from the color filter 108 and producing a color display. 20(a), liquid crystal molecules 105 have the property of aligning along the grooves of the light distribution film. When liquid crystal molecules 105 are sandwiched between two light distribution films (incident-side light distribution film 104 and exit-side light distribution film 106) that have grooves in mutually perpendicular directions (directions a and b), the liquid crystal molecules 105 are aligned with a 90-degree twist.

[0083] As shown in Figure 20(b), when no voltage is applied to the liquid crystal molecules 105, the light L from the backlight 100 that enters the incident side light distribution film 104 has its polarization plane rotated 90 degrees in accordance with the twist direction of the liquid crystal molecules 105, exits from the exit side light distribution film 106, and enters the color filter 108 (not shown). 20(c), when a voltage is applied to the liquid crystal molecules 105 by the transparent electrode 103, the liquid crystal molecules 105 are aligned along the electric field in a direction perpendicular to the main surfaces of the light distribution films 104 and 106. As a result, the light L from the backlight 100 that is incident on the incident-side light distribution film 104 exits from the exit-side light distribution film 106 without rotating its polarization plane, and enters the color filter 108 (not shown).

[0084] FIG. 21 is a diagram explaining in more detail the operation of a TN type liquid crystal module. As explained with reference to FIG. 19 for the first liquid crystal module 31a, the liquid crystal molecules 105, the light distribution films 104 and 106, and the transparent electrode 103 in FIG. The polarization direction of incident-side polarizing filter 101 is direction a, and the polarization direction of exit-side polarizing filter 109 is direction b, the directions a and b being perpendicular to each other. That is, the polarization directions of incident-side polarizing filter 101 and exit-side polarizing filter 109 are perpendicular to each other. The polarization direction of the incident-side polarizing filter 101 and the groove direction of the incident-side light distribution film 104 are parallel to each other in the a direction, and the polarization direction of the exit-side polarizing filter 109 and the groove direction of the exit-side light distribution film 106 are parallel to each other in the b direction.

[0085] The light L from the backlight 100 is a mixture of various lights with different polarization plane directions, but when the light L enters the incident-side polarizing filter 101, the action of the polarizing filter causes only the light La whose polarization plane is oriented in the a direction to be emitted and extracted. In its current state, the extracted light La does not exit from the exit-side polarizing filter 109, whose polarization direction is in the b direction. However, as explained in Figure 20, the liquid crystal molecules twist the polarization plane to the b direction (becoming light Lb), and the light can exit from the exit-side polarizing filter 109. The liquid crystal molecules perform control to switch the plane of polarization of the light from the backlight 100 between a state in which the light can pass through the output side polarizing filter 109 and a state in which the light cannot pass through.

[0086] As shown in FIG. 21, when light L from backlight 100 enters incident-side polarizing filter 101, light La is emitted from incident-side polarizing filter 101 with the polarization plane oriented in the a direction. Light La passes through a glass substrate 102 and an incident-side transparent electrode 103 (neither of which are shown), and then passes through an incident-side light distribution film 104 . As shown in Figure 21(a), when no voltage is applied to the liquid crystal molecules 105 by the incident side transparent electrode 103 and the exit side transparent electrode 107 and the liquid crystal molecules 105 are twisted (corresponding to Figure 20(b) above), the light La becomes light Lb, whose plane of polarization is rotated 90 degrees by the liquid crystal molecules 105 and aligned in the b direction. The light Lb passes through an output-side light distribution film 106 and a color filter 108 (not shown), and is output from an output-side polarizing filter 109 whose polarization direction is the b-direction. As a result, light corresponding to the color of the color filter 108 that has passed through is emitted from the liquid crystal module, causing the sub-pixel to emit light.

[0087] 21(b), when a voltage is applied to the liquid crystal molecules 105 by the incident-side transparent electrode 103 and the exit-side transparent electrode 107 and the liquid crystal molecules 105 are aligned (corresponding to the above FIG. 20(c)), the light La passes through the exit-side light distribution film 106 and color filter 108 (not shown) with the polarization plane remaining in direction a without rotating, and is blocked by the exit-side polarizing filter 109, whose polarization direction is direction b. As a result, the subpixel does not emit light. In this manner, in the first liquid crystal module 31a, the voltage applied to the liquid crystal molecules 105 for each color (each sub-pixel) of the color filter 108 is controlled, and the light emission and emitted color for each pixel can be controlled by switching between passing and blocking the light that has passed through the color filter 108 from the exit-side light distribution film 106.

[0088] FIG. 22 is a diagram for explaining drive control of a liquid crystal module according to the VA method. The basic concept is the same as that of the TN type described above, and the layered structure of the elements that make up the liquid crystal module is also the same as the structure shown in FIG. In the VA mode, as in the TN mode, the voltage applied to the liquid crystal molecules 105 for each color (sub-pixel) of the color filter is controlled to switch between passing and blocking the light that has passed through the color filter from the exit-side light distribution film 106, thereby controlling the light emission and emitted color for each pixel. The liquid crystal molecules 105 used in the VA (Vertical Alignment) mode are aligned in a direction perpendicular to the light distribution film when the voltage applied to the liquid crystal molecules 105 is OFF, as shown in Fig. 22(a), which is opposite to the TN mode. The light La extracted from the entrance polarizing filter 101 is blocked by the exit polarizing filter 109 without having its polarization plane twisted by the liquid crystal molecules 105. As a result, the sub-pixel does not emit light.

[0089] Conversely, as shown in FIG. 22(b), when a voltage is applied to the liquid crystal molecules 105, the aligned liquid crystal molecules 105 tilt, and the tilted liquid crystal molecules 105 cause birefringence. Thereby, the light La becomes light Lb whose plane of polarization is rotated 90 degrees to direction b, and is emitted from the emission-side polarizing filter 109. As a result, light corresponding to the color of the color filter 108 (not shown) that it passed through is emitted from the liquid crystal module, causing the sub-pixels to emit light.

[0090] FIG. 23 is a timing chart illustrating the display control of the first liquid crystal module. The display of the first liquid crystal module 31a is controlled by a display control signal shown in FIG. Within the vertical synchronization period controlled by the vertical synchronization signal, one frame is displayed during an image effective period (pixel effective period, display period) excluding the blanking period. The gaming machine 1 of this embodiment displays 60 frames of images per second, so the image validity period per frame is 1 / 60 seconds. In addition, if the video (image) data that is the source of the image to be displayed on the first liquid crystal module 31a is created at 30 frames per second (30 fps), it is possible to display the same image twice in a pseudo 30 fps manner. In the first liquid crystal module 31a, during the image effective period, a liquid crystal drive signal for driving the liquid crystal molecules 105a of the first liquid crystal module 31a so that the light emitted from the color filter 108 corresponding to the color to be emitted by each pixel is emitted from the exit side polarizing filter 109a of the first liquid crystal module 31a is input from the LCD driver 36a of the first liquid crystal module 31a to the liquid crystal drive circuit. The liquid crystal drive signal is a signal that is generated by the LCD driver 36a based on a video signal input to the LCD driver 36a from the VDP 157. This causes each pixel to emit light in a desired color to display one frame of an image.

[0091] The LCD driver 36a inputs a liquid crystal drive signal that constitutes one frame image based on the video signal from the VDP 157 to the liquid crystal drive circuit. The liquid crystal drive circuit of the first liquid crystal module 31a applies a drive voltage to the liquid crystal molecules 105a provided between the incident side transparent electrode 103a and the exit side transparent electrode 107a of the first liquid crystal module 31a in order to drive the liquid crystal molecules 105a. That is, the liquid crystal drive circuit applies a current to the incident side transparent electrode 103a and the exit side transparent electrode 107a based on the input liquid crystal drive signal. In this example, the LED 115, which is the light source of the backlight 100, emits white light during the image active period, and the backlight 100 emits white light.

[0092] Next, the configuration of the second liquid crystal module 31b will be described. The first liquid crystal module 31a described above displays a color image by continuously illuminating one pixel with a color corresponding to the displayed image using backlight light during the image effective period (1 / 60 seconds) during which one frame of image is displayed. Color display for each pixel is achieved by controlling the drive of the liquid crystal molecules for each sub-pixel (R (red), G (green), B (blue) color filter) that makes up the pixel, switching whether or not to emit light. In contrast, the second liquid crystal module 31b described below does not have the concept of sub-pixels, since it performs color display for each pixel.

[0093] Although a detailed description will be given later, the second liquid crystal module 31b differs from the first liquid crystal module 31a in that it does not use color filters but instead performs color display in the following manner. Three LED light sources capable of emitting R (red), G (green), and B (blue) are provided as light sources for the backlight provided on the rear surface of the second liquid crystal module 31b. During the image effective period (1 / 60 seconds) during which one frame of image is displayed, the LED light source that emits light is switched every 1 / 180 seconds, which is one third of the period. As a result, the backlight changes color every 1 / 180th of a second.

[0094] In the second liquid crystal module 31b, the driving of the liquid crystal molecules is controlled in accordance with the switching timing of the backlight every 1 / 180 seconds, and the passage or blocking of light in each pixel of the second liquid crystal module 31b is switched. As a result, in each pixel of the second liquid crystal module 31b, either R (red), G (green), or B (blue) is displayed at ultra-high speed every 180 seconds, or no color is displayed because the backlight light is blocked. A person viewing the second liquid crystal module 31b sees a color as shown in Fig. 13 below, which is a combination of one or more of the colors R (red), G (green), and B (blue). This allows color display in the second liquid crystal module 31b. In addition, if the video (image) data that is the source of the image to be displayed on the second liquid crystal module 31b is created at 30 frames per second (30 fps), the same image can be displayed twice to simulate 30 fps.

[0095] <Basic configuration of the second liquid crystal module> FIG. 24 is a schematic diagram showing a layered structure of elements constituting the second liquid crystal module. The second liquid crystal module 31b can basically have the same configuration as the first liquid crystal module 31a. Here, the second liquid crystal module 31b does not have a color filter 108, and is configured, for example, by stacking, from the backlight side, an incident side polarizing filter 101b, a glass substrate 102b, an incident side transparent electrode 103b, an incident side light distribution film 104b, liquid crystal molecules 105b, an exit side light distribution film 106b, an exit side transparent electrode 107b, and an exit side polarizing filter 109b. In the second liquid crystal module 31b, during the image effective period, a liquid crystal driving signal for driving the liquid crystal molecules 105b of the second liquid crystal module 31b so that the emitted light corresponding to each pixel is emitted from the exit side polarizing filter 109b of the second liquid crystal module 31b is input from the LCD driver 36b of the second liquid crystal module 31b to the liquid crystal driving circuit. The liquid crystal drive signal is a signal that is generated by the LCD driver 36b based on a video signal input to the LCD driver 36b from the VDP 157. This causes each pixel to emit light in a desired color to display one frame of an image. The LCD driver 36b inputs a liquid crystal drive signal that constitutes one frame image based on the video signal from the VDP 157 to the liquid crystal drive circuit. The liquid crystal drive circuit of the second liquid crystal module 31b applies a drive voltage to the liquid crystal molecules 105b provided between the incident side transparent electrode 103b and the exit side transparent electrode 107b of the second liquid crystal module 31b in order to drive the liquid crystal molecules 105b. That is, the liquid crystal drive circuit of the second liquid crystal module 31b applies a current to the incident side transparent electrode 103b and the exit side transparent electrode 107b of the second liquid crystal module 31b based on the input liquid crystal drive signal.

[0096] FIG. 25 is a schematic cross-sectional view illustrating the basic configuration of the second liquid crystal module. The second liquid crystal module 31b, like the first liquid crystal module 31a, controls whether or not backlight is allowed to exit from the exit-side polarizing filter 109 by driving the liquid crystal molecules 105, thereby displaying an image. In other words, the liquid crystal molecules 105 of the second liquid crystal module 31b can switch the polarization plane of the backlight light by a mechanism similar to that described in Figures 7 to 9, and control whether or not the backlight light is emitted from the exit-side polarizing filter 109b.

[0097] The backlight 100 provided on the back surface of the second liquid crystal module 31b has red LED 115R, green LED 115G, and blue LED 115B as light sources, and can emit light in any of the colors R (red), G (green), and B (blue) by switching the LEDs that emit light. When backlight of any of the colors R (red), G (green), and B (blue) enters the second liquid crystal module 31b, the liquid crystal molecules 105 are driven based on a liquid crystal drive signal generated by the LCD driver 36b to switch between passing and blocking the backlight on a pixel-by-pixel basis. Since the mechanism for color display is different from that of the first liquid crystal module 31a, the concept of sub-pixels does not exist.

[0098] The liquid crystal molecules 105b used in the second liquid crystal module 31b require a response speed (driving speed) that is at least three times faster than that used in the first liquid crystal module 31a. Red LED 115R, green LED 115G, and blue LED 115B are arranged on the side or back of backlight 100 (light guide plate, light emitting plate, lens), and the LEDs that emit light into backlight 100 are switched sequentially every predetermined time (1 / 180 seconds). This allows backlight 100 to switch its emission color to R (red), G (green), and B (blue) every 1 / 180 seconds.

[0099] 25(a), in a period in which the backlight 100 emits R (red), the liquid crystal molecules 105b of the corresponding second liquid crystal module 31b are controlled so that R (red) backlight is emitted from the exit-side polarizing filter 109b of the second liquid crystal module 31b at a particular pixel that is to emit a color including an R component (to display a color including an R component) and the pixel emits R (red). For the other pixels, the liquid crystal molecules 105b are controlled so that the backlight light is blocked. As described above, the liquid crystal molecules 105b are controlled based on a liquid crystal drive signal (R component drive signal) corresponding to the R component of one frame image generated by the LCD driver 36b of the second liquid crystal module 31b based on the video signal from the VDP 157.

[0100] 25(b), the liquid crystal molecules 105b of the second liquid crystal module 31b are controlled so that at a particular pixel in the second liquid crystal module 31b that is to emit a color including a G component (a color including a G component is to be displayed), the G (green) backlight light is emitted from the exit-side polarizing filter 109b of the second liquid crystal module 31b, causing the pixel to emit G (green). For the other pixels, the liquid crystal molecules 105b are controlled so that the backlight light is blocked. As described above, the liquid crystal molecules 105b are controlled based on a liquid crystal drive signal (G component drive signal) corresponding to the G component of one frame image generated by the LCD driver 36b of the second liquid crystal module 31b based on a video signal from the VDP 157.

[0101] 25(c), in the period in which the backlight 100 emits light in B (blue), the B (blue) backlight light is emitted from the exit-side polarizing filter 109b of the second liquid crystal module 31b at a particular pixel that is to emit light in a color including the B component (to display a color including the B component), and the corresponding liquid crystal molecules 105b are controlled so that the pixel emits light in B (blue). For the other pixels, the liquid crystal molecules 105b are controlled so that the backlight light is blocked. As described above, the liquid crystal molecules 105b are controlled based on a liquid crystal drive signal (B component drive signal) corresponding to the B component of one frame image generated by the LCD driver 36b of the second liquid crystal module 31b based on a video signal from the VDP 157. In Figure 25, by controlling the liquid crystal molecules 105b of the second liquid crystal module 31b from (a) to (b) to (c), the pixel on the left side of the figure appears to be "red," the pixel in the center of the figure appears to be "green," and the pixel on the right side of the figure appears to be "blue."

[0102] This control enables one frame of color display in the second liquid crystal module 31b, which is based on the concept explained below. For each pixel of the second liquid crystal module 31b, R (red), G (green), and B (blue) are displayed at an ultra-high speed of every 1 / 180 seconds. Alternatively, light is blocked, resulting in no light emission. As a result, a person viewing the second liquid crystal module 31b sees a color, as shown in FIG. 26 below, which is a combination of one or more colors. The second liquid crystal module 31b can achieve color display without using a color filter.

[0103] FIG. 26 is a diagram illustrating the concept of a second type of color display in the second liquid crystal module. For example, if you want to make a pixel in the second liquid crystal module 31b transparent in an image of one frame (1 / 60 seconds), you can switch the light emission color from R (red) to G (green) to B (blue) every 1 / 180 seconds, so that all light is transmitted and the pixel becomes transparent. In addition, if you want to make a specific pixel in the second liquid crystal module 31b emit yellow light in an image of one frame (1 / 60 seconds), the pixel will be perceived as "yellow" to the human eye by switching between R (red) emission → G (green) emission → no emission due to light blocking every 1 / 180 seconds. If you want a specific pixel in the second liquid crystal module 31b to emit magenta light in an image of one frame (1 / 60 seconds), the light emission is switched from R (red) light emission → no light emission due to light blocking → B (blue) light emission every 1 / 180 seconds, and the human eye will perceive that pixel as "magenta."

[0104] If you want to make a specific pixel in the second liquid crystal module 31b emit cyan light in an image of one frame (1 / 60 seconds), the light emission is switched from no light emission due to light blocking to G (green) light emission to B (blue) light emission every 1 / 180 seconds, and the human eye will perceive that pixel as "cyan." If it is desired to make a specific pixel of the second liquid crystal module 31b emit R (red) light in an image of one frame (1 / 60 seconds), the pixel will be visually recognized as "R (red)" by switching the emission between R (red) light emission → no light emission due to light blocking → no light emission due to light blocking every 1 / 180 seconds. If you want a specific pixel in the second liquid crystal module 31b to emit G (green) light in an image of one frame (1 / 60 seconds), the pixel will be perceived as "magenta" by the human eye by switching between no emission due to light blocking → G (green) emission → no emission due to light blocking every 1 / 180 seconds. If it is desired to make a specific pixel of the second liquid crystal module 31b emit B (blue) light in an image of one frame (1 / 60 seconds), the light emission is switched every 1 / 180 seconds from no light emission due to light blocking to no light emission due to light blocking to B (blue) light emission, so that the human eye perceives "B (blue)" for that pixel. If you want to express black with a specific pixel of the second liquid crystal module 31b in an image of one frame (1 / 60 seconds), you can make that pixel emit no light by blocking light for one frame (1 / 60 seconds), and the human eye will perceive the pixel as "black."

[0105] FIG. 27 is a timing chart illustrating the display control signals of the second liquid crystal module. Within the vertical synchronization period, one frame is displayed during the image effective period excluding the blanking period. During the image effective period, the LCD driver 36b of the second liquid crystal module 31b inputs current to the red LED 115R, the green LED 115G, and the blue LED 115B every 1 / 180 seconds, and as a result, the emitting LEDs are switched. The backlight 100 switches the emission color from R (red) to G (green) to B (blue) in sequence every 1 / 180 seconds. The LCD driver 36b of the second liquid crystal module 31b generates a liquid crystal drive signal for the R component (R component drive signal), a liquid crystal drive signal for the G component (G component drive signal), and a liquid crystal drive signal for the B component (B component drive signal) that make up one frame image in response to changes in the emission color of the backlight 100.

[0106] As will be described later, the R component drive signal is a signal for driving and controlling the liquid crystal molecules 105b of the second liquid crystal module 31b so that light is emitted from the corresponding exit side polarizing filter 109b of the second liquid crystal module 31b at the timing when the backlight 100 emits R (red) light for pixels of the second liquid crystal module 31b that are to be made to emit light in a color including an R component during the display period of one frame (1 / 60 seconds). In addition, the G component drive signal is a signal for driving and controlling the liquid crystal molecules 105b of the corresponding pixels of the second liquid crystal module 31b that are to emit light in a color including the G component during the display period of one frame (1 / 60 seconds) so that light is emitted from the exit side polarizing filter 109b of the second liquid crystal module 31b at the timing when the backlight 100 emits light in G (green). In addition, the B component drive signal is a signal for driving and controlling the liquid crystal molecules 105b of the corresponding pixels of the second liquid crystal module 31b that are to emit light in a color including the B component during the display period of one frame (1 / 60 seconds) at the timing when the backlight 100 emits light in R (red).

[0107] FIG. 28 is a timing chart illustrating display control focusing on one pixel of the second liquid crystal module. During the image effective period, the LCD driver 36b inputs current to the red LED 115R, the green LED 115G, and the blue LED 115B every 1 / 180 seconds, and as a result, the emitting LEDs are switched. In all cases shown in FIG. 28, the backlight 100 switches the emission color from R (red) to G (green) to B (blue) in sequence every 1 / 180 seconds.

[0108] (1) When it is desired to put a specific pixel of the second liquid crystal module 31b into a transparent state, based on the R component drive signal, G component drive signal, and B component drive signal for that pixel, the corresponding liquid crystal molecule 105b is controlled at the timing when the backlight 100 emits R (red) light to emit R (red) light from the exit side polarizing filter 109b of the second liquid crystal module 31b, the corresponding liquid crystal molecule 105b is controlled at the timing when the backlight 100 emits G (green) light to emit G (green) light from the exit side polarizing filter 109b, and the corresponding liquid crystal molecule 105b is controlled at the timing when the backlight 100 emits B (blue) light to emit B (blue) light from the exit side polarizing filter 109b. As a result, the pixel emits R (red) light for the first 1 / 180 seconds in one frame (1 / 60 seconds), emits G (green) light for the next 1 / 180 seconds, and emits B (blue) light for the last 1 / 180 seconds. As a result, the pixel is visually recognized as being in a transparent state for one frame at a time, as shown in Figure 26.

[0109] (2) When it is desired to make a specific pixel of the second liquid crystal module 31b emit yellow light consisting of R and G components, based on the R component drive signal, G component drive signal, and B component drive signal for that pixel, at the timing when the backlight 100 emits R (red) light, the corresponding liquid crystal molecule 105b is controlled to emit R (red) light from the exit side polarizing filter 109b of the second liquid crystal module 31b, at the timing when the backlight 100 emits G (green) light, the corresponding liquid crystal molecule 105b is controlled to emit G (green) light from the exit side polarizing filter 109b, and at the timing when the backlight 100 emits B (blue) light, the corresponding liquid crystal molecule 105b is controlled to not emit light from the exit side polarizing filter 109b. As a result, the pixel emits R (red) light for the first 1 / 180 seconds in one frame (1 / 60 seconds), emits G (green) light for the next 1 / 180 seconds, and blocks light for the last 1 / 180 seconds. As a result, the pixel is visually recognized as yellow for one frame at a time, as shown in Figure 26.

[0110] (3) When it is desired to make a specific pixel of the second liquid crystal module 31b emit magenta light consisting of R and B components, based on the R component drive signal, G component drive signal, and B component drive signal for that pixel, the corresponding liquid crystal molecule 105b is controlled at the timing when the backlight 100 emits R (red) light to emit R (red) light from the exit side polarizing filter 109b of the second liquid crystal module 31b, the corresponding liquid crystal molecule 105b is controlled at the timing when the backlight 100 emits G (green) light to not emit light from the exit side polarizing filter 109b, and the corresponding liquid crystal molecule 105b is controlled at the timing when the backlight 100 emits B (blue) light to emit B (blue) light from the exit side polarizing filter 109b. As a result, the pixel emits R (red) light for the first 1 / 180 seconds in one frame (1 / 60 seconds), the light is blocked for the next 1 / 180 seconds, and the pixel emits B (blue) light for the last 1 / 180 seconds. As a result, the pixel is visually recognized as magenta for one frame at a time, as shown in Figure 26.

[0111] (4) When it is desired to make a specific pixel of the second liquid crystal module 31b emit cyan light consisting of G and B components, based on the R component drive signal, G component drive signal, and B component drive signal for that pixel, at the timing when the backlight 100 emits R (red) light, the corresponding liquid crystal molecule 105b is controlled to not emit light from the exit side polarizing filter 109b of the second liquid crystal module 31b, at the timing when the backlight 100 emits G (green) light, the corresponding liquid crystal molecule 105b is controlled to emit G (green) light from the exit side polarizing filter 109b, and at the timing when the backlight 100 emits B (blue) light, the corresponding liquid crystal molecule 105b is controlled to emit B (blue) light from the exit side polarizing filter 109b. As a result, the pixel is blocked from light for the first 1 / 180 seconds in one frame (1 / 60 seconds), emits G (green) light for the next 1 / 180 seconds, and emits B (blue) light for the last 1 / 180 seconds. As a result, as described above, the pixel is visually recognized as cyan in one frame unit.

[0112] (5) When it is desired to express black at a specific pixel of the second liquid crystal module 31b, based on the R component drive signal, G component drive signal, and B component drive signal for that pixel, when the backlight emits R (red) light, the corresponding liquid crystal molecules 105b are controlled to prevent light from emitting from the exit side polarizing filter 109b of the second liquid crystal module 31b, when the backlight emits G (green) light, the corresponding liquid crystal molecules 105b are controlled to prevent light from emitting from the exit side polarizing filter 109b, and when the backlight emits B (blue) light, the corresponding liquid crystal molecules 105b are controlled to prevent light from emitting from the exit side polarizing filter 109b. As a result, no light is emitted from the pixel during one frame (1 / 60 seconds), and as a result, as described above, the pixel is visually recognized as black for one frame at a time.

[0113] The basic configuration and display principle of the first liquid crystal module 31a and the second liquid crystal module 31b used in the image display unit 31 of this embodiment have been described above. The configuration of the image display unit 31 of this embodiment will be described in detail below. The image display unit 31 of this embodiment has two liquid crystal modules arranged in the depth direction to create a powerful presentation. However, as described above, when two first liquid crystal modules 31a are arranged in front of the backlight, the amount of light emitted from the first liquid crystal module 31a on the front side is about 5% of the amount of light from the backlight. On the other hand, increasing the light intensity of the backlight increases power consumption, and in gaming machines with limited power capacity, it is necessary to reduce the number of bonus points, which causes inconvenience in terms of presentation. This is also undesirable from the viewpoint of energy conservation. Furthermore, increasing the amount of light from the backlight causes the temperature of the LCD unit to rise. The heat resistance of a normal LCD module is around 0 to 50 degrees, and exceeding this temperature can cause malfunctions. This can be solved by adopting an LCD module with a high heat resistance, but this would result in increased costs.

[0114] These problems can be solved by changing the display method of the liquid crystal module arranged on the front side to the second method (by arranging the second liquid crystal module 31b in front of the first liquid crystal module 31a). This is because the second method, in which the amount of light per pixel is not divided among sub-pixels, is clearly more efficient with respect to light than the first method, in which the amount of light per pixel is divided by color filters for every three sub-pixels. Since the second method does not require as much light as the first method, there is no need to significantly increase the amount of light compared to when two first liquid crystal modules 31a are arranged side by side, and the above-mentioned problems related to heat resistance and power consumption can be solved.

[0115] However, simply placing a second liquid crystal module 31b in front of a first liquid crystal module 31a in the configuration of FIG. 18 using white LEDs as the backlight light source cannot produce a color display in the second liquid crystal module 31b. As explained above, in order for the second liquid crystal module 31b to display color, the backlight emission color needs to be completely switched between R (red), G (green), and B (blue) every 1 / 180 seconds, but such switching cannot be performed for the light emitted from the first liquid crystal module 31a, which uses color filters.

[0116] That is, in the first liquid crystal module 31a, the 1 / 60 second image display period is not divided like in the second liquid crystal module 31b, but instead color display is performed by switching whether or not light is emitted from the color filters (sub-pixels) over the entire image display period. Therefore, during an image display period of 1 / 60 seconds, each pixel of the first liquid crystal module 31a constantly emits light of three colors, R (red), G (green), and B (blue), and R (red), G (green), and B (blue) are mixed together. If such light in which R (red), G (green), and B (blue) are mixed is used, the second liquid crystal module 31b cannot perform a good color display. Therefore, in the image display unit of this embodiment, instead of placing the second liquid crystal module 31b in front of the first liquid crystal module 31a which uses a backlight that emits white light as described in FIG. 18, color display of the first liquid crystal module 31a and the second liquid crystal module 31b is performed using a backlight that emits light in sequence from R (red) to G (green) to B (blue) using red LEDs 115R, green LEDs 115G, and blue LEDs 115B which can be switched to emit light every 1 / 180 seconds as described in FIG. 25.

[0117] FIG. 29 is a diagram showing the configuration of an image display unit of this embodiment. As shown in FIG. 29(a), the image display unit 31 of this embodiment has a backlight 100, a first liquid crystal module 31a, and a second liquid crystal module 31b arranged in that order from the rear side in the depth direction, and images are displayed simultaneously on both display elements. The first liquid crystal module 31a and the second liquid crystal module 31b share the backlight 100.

[0118] As shown in FIG. 29(b), red LEDs 115R, green LEDs 115G, and blue LEDs 115B are arranged on the side surface of the backlight 100. The red LED 115R, the green LED 115G, and the blue LED 115B may be provided on the rear surface of the backlight 100. The red LED 115R, the green LED 115G, and the blue LED 115B are connected to the LCD driver 36b of the second liquid crystal module 31b, and their light emission is controlled. The red LED 115R, the green LED 115G, and the blue LED 115B may be connected to the LCD driver 36a of the first liquid crystal module 31a to control light emission. In this case, the LCD driver 36a also controls switching of the light emission of the red LED 115R, the green LED 115G, and the blue LED 115B every 1 / 180 seconds.

[0119] The LCD driver 36b applies current to the red LED 115R, the green LED 115G, and the blue LED 115B to cause them to emit light in synchronization with the R component drive signal, the G component drive signal, and the B component drive signal that are generated based on the image input from the VDP 157 and output to the liquid crystal drive circuit. Alternatively, the LCD driver 36b outputs an R component drive signal, a G component drive signal, and a B component drive signal to the liquid crystal drive circuit in synchronization with the timing at which a current is applied to the red LED 115R, the green LED 115G, and the blue LED 115B to cause them to emit light. In either case, the timing at which current is applied to the red LED 115R, the green LED 115G, and the blue LED 115B (the light emission timing of each LED) is synchronized with the R component drive signal, the G component drive signal, and the B component drive signal, respectively.

[0120] By sequentially switching between the light sources that emit light among the red LED 115R, the green LED 115G, and the blue LED 115B, the backlight 100 switches the emitted color from R (red) to G (green) to B (blue) every 1 / 180 seconds to provide a second-type color display by the second liquid crystal module 31b. Only when the light emission timing of the red LED 115R, the green LED 115G, and the blue LED 115B is synchronized with the drive signals for each color component can an appropriate second-type color display be achieved.

[0121] In addition, in the image display unit 31 of this embodiment, the emission color of the backlight 100 is switched sequentially between R (red), G (green), and B (blue), and the first liquid crystal module 31a displays the desired color by passing each emission color sequentially emitted from the backlight 100 through a color filter 108. Note that, due to the interaction between the change in the emission color of the backlight 100 and the color filter 108, only one color of light, the same as the emission color of the backlight 100, can be emitted from the color filter 108 of each pixel. This is due to the following characteristics of the color filters: R (red), G (green), and B (blue) light from the backlight 100 can pass through the color filter 10 of the same color as the light, but are blocked by the color filter 108 of a different color.

[0122] As a result of each pixel's color filter 108 emitting only one color of light that is the same as the emission color of the backlight 100, the first liquid crystal module 31a displays in a similar manner to the second liquid crystal module 31b by changing the emission color of each pixel in response to the change in the emission color of the backlight 100 during one frame period. The second liquid crystal module 31b performs color display in the same manner as described in Figures 25 to 28, using R (red) light, G (green) light, and B (blue) light that pass through the first liquid crystal module 31a sequentially in accordance with changes in the emission color of the backlight 100. In order for the first liquid crystal module 31a to display in the same manner as the second liquid crystal module 31b, the first liquid crystal module 31a needs to input a liquid crystal drive signal to a liquid crystal drive circuit in synchronization with changes in the emission color of the backlight 100 to control the pixels.

[0123] For this purpose, the LCD driver 36b of the second liquid crystal module 31b, which controls the emission of the backlight 100 (lighting control of the red LED 115R, the green LED 115G, and the blue LED 115B), inputs RGB signals to the LCD driver 36a via the VDP 157 at the timing when each LED is to be emitted. The LCD driver 36a outputs a liquid crystal drive signal generated based on the video signal input from the VDP 157 to the liquid crystal drive circuit in synchronization with the RGB signal. As a result, in the first liquid crystal module 31a, a liquid crystal drive signal synchronized with the change in the emission color of the backlight 100 is input to the liquid crystal drive circuit to control the pixels, and display can be performed in a similar manner to the second liquid crystal module 31b. Since the light emission time of each color of the backlight 100 becomes 1 / 3 and the amount of light decreases, the amount of light emitted by the red LED 115R, the green LED 115G, and the blue LED 115B is controlled to increase.

[0124] FIG. 30 is a timing chart illustrating display control in the image display unit of this embodiment. The image display by the image display unit of this embodiment is controlled by the control signals shown in FIG. Within the vertical synchronization period, one frame is displayed during the image effective period excluding the blanking period. During the image effective period, the LCD driver 36b inputs current to the red LED 115R, the green LED 115G, and the blue LED 115B every 1 / 180 seconds, and as a result, the emitting LEDs are switched. In all cases shown in FIG. 28, the backlight 100 switches the emission color from R (red) to G (green) to B (blue) in sequence every 1 / 180 seconds.

[0125] The second liquid crystal module 31b has the same basic configuration as described above. In response to the emission of each color by the backlight 100, whose emission color changes from R (red) → G (green) → B (blue), the LCD driver 36b of the second liquid crystal module 31b inputs a liquid crystal drive signal for the R component, a liquid crystal drive signal for the G component, and a liquid crystal drive signal for the B component that make up one frame image to the liquid crystal drive circuit. The liquid crystal driving circuit of the second liquid crystal module 31b inputs a current based on this liquid crystal driving signal to the incident side transparent electrode 103b and the exit side transparent electrode 107b of the second liquid crystal module 31b, and applies a driving voltage to the liquid crystal molecules 105b of the second liquid crystal module 31b arranged between the incident side transparent electrode 103b and the exit side transparent electrode 107b to drive the liquid crystal molecules 105b.

[0126] That is, the LCD driver 36b of the second liquid crystal module 31b generates a liquid crystal drive signal for the R component (R component drive signal), a liquid crystal drive signal for the G component (G component drive signal), and a liquid crystal drive signal for the B component (G component drive signal) that make up one frame image based on the video signal from the VDP 157, and inputs them to a liquid crystal drive circuit (not shown) in response to the light emission of the backlight 100. The liquid crystal driving circuit of the second liquid crystal module 31b applies a driving voltage between the incident side transparent electrode 103b and the exit side transparent electrode 107b of the second liquid crystal module 31b based on the input R component driving signal, G component driving signal, and B component driving signal to drive the liquid crystal molecules 105b.

[0127] The R component drive signal generated by the LCD driver 36b is input to the liquid crystal drive circuit of the second liquid crystal module 31b to drive and control the liquid crystal molecules 105b of the second liquid crystal module 31b so that light is emitted from the corresponding exit side polarizing filter 109b at the timing when the backlight 100 emits R (red) light for pixels of the second liquid crystal module 31b that are to emit light in a color including the R component during the display period of one frame (1 / 60 seconds). The G component drive signal generated by the LCD driver 36b is input to the liquid crystal drive circuit of the second liquid crystal module 31b to drive and control the liquid crystal molecules 105b of the second liquid crystal module 31b so that light is emitted from the corresponding exit side polarizing filter 109b at the timing when the backlight 100 emits G (green) for pixels of the second liquid crystal module 31b that are to be illuminated in a color including the G component during the display period of one frame (1 / 60 seconds).

[0128] The B component drive signal generated by the LCD driver 36b is input to the liquid crystal drive circuit of the second liquid crystal module 31b in order to drive and control the liquid crystal molecules 105b of the second liquid crystal module 31b so that light is emitted from the corresponding exit side polarizing filter 109b at the timing when the backlight 100 emits R (red) light for pixels of the second liquid crystal module 31b that are to be illuminated in a color including the B component during the display period of one frame (1 / 60 seconds).

[0129] While the backlight 100 is emitting R (red) light, the liquid crystal drive circuit of the second liquid crystal module 31b controls the liquid crystal molecules 105b of the second liquid crystal module 31b based on the R component drive signal so as to allow R (red) light to pass through the exit-side polarizing filter 109b corresponding to the pixel that is to emit light in a color including the R component. When the backlight 100 emits G (green) light, the liquid crystal driving circuit of the second liquid crystal module 31b controls the liquid crystal molecules 105b of the second liquid crystal module 31b based on the G component driving signal so as to allow G (green) light to pass through the exit side polarizing filter 109b corresponding to the pixel desired to emit light in a color including the G component. When the backlight 100 emits B (blue) light, the liquid crystal drive circuit of the second liquid crystal module 31b controls the liquid crystal molecules 105b of the second liquid crystal module 31b so that the B (blue) light can pass through the output side polarizing filter 109b corresponding to the pixel to be emitted with the B component drive signal and light containing the B component. By displaying R (red), G (green), and B (blue) at ultra-high speed for each pixel of the second liquid crystal module 31b (switching the light emitted from each pixel of the second liquid crystal module 31b to R (red), G (green), and B (blue) at ultra-high speed), or by blocking the light and making it non-emitting, a color that is a combination of one or more colors is visible to the human eye.

[0130] On the other hand, in the first liquid crystal module 31a, a process different from that of the basic configuration described above is carried out. The first liquid crystal module 31a is equipped with color filters, and R (red) light, G (green) light, and B (blue) light from the backlight 100 can pass through sub-pixels of the same color (color filters 108) but are cut by sub-pixels of a different color (color filters 108). Therefore, in a particular pixel of the first liquid crystal module 31a, the sub-pixel (color filter 108) that does not correspond to the emission color of the backlight 100 has light cut and does not emit light, but if the light that passes through the sub-pixel (color filter 108) that corresponds to the emission color of the backlight 100 can further pass through the exit side polarizing filter 109a of the first liquid crystal module 31a, the pixel in question will emit light in the emission color of the emitting sub-pixel (the emission color of the backlight 100).

[0131] On the other hand, in a particular pixel of the first liquid crystal module 31a, the sub-pixels (color filters 108) that do not correspond to the emission color of the backlight 100 have their light cut and do not emit light, and if the light that passes through the sub-pixels (color filters 108) that correspond to the emission color of the backlight 100 cannot pass through the exit-side polarizing filter 109a of the first liquid crystal module 31a, then none of the sub-pixels emit light and the pixel does not emit light. In this way, the pixel can emit light only when the backlight 100 emits light of the same color as the sub-pixel (color filter 108) that is controlled to be able to emit light, and the emitted color is the emission color of the sub-pixel (backlight color). Since only sub-pixels of the same color as the emission color of backlight 100 can emit light, R, G, and B light cannot be emitted simultaneously from each sub-pixel that makes up one pixel, and color display for each pixel in the normal manner as described in Figure 5 cannot be performed. Therefore, as described below, the first liquid crystal module 31a of this embodiment performs color display using a display method similar to that of the second liquid crystal module 31b, which performs drive control of the liquid crystal molecules 105a (control of whether or not light can be emitted from the sub-pixels) in response to changes in the emission color of the backlight.

[0132] The LCD driver 36a of the first liquid crystal module 31a generates a liquid crystal drive signal for the R component (R component drive signal), a liquid crystal drive signal for the G component (G component drive signal), and a liquid crystal drive signal for the B component (B component drive signal) that make up one frame image based on the video signal from the VDP 157, and inputs them to a liquid crystal drive circuit (not shown) in response to the light emission of the backlight 100. The liquid crystal driving circuit of the first liquid crystal module 31a applies a driving voltage between the incident side transparent electrode 103a and the exit side transparent electrode 107a of the first liquid crystal module 31a based on the input R component driving signal, G component driving signal, and B component driving signal to drive the liquid crystal molecules 105a of the first liquid crystal module 31a. That is, the liquid crystal driving circuit of the first liquid crystal module 31a inputs a current based on the liquid crystal driving signal to the incident side transparent electrode 103a and the exit side transparent electrode 107a of the first liquid crystal module 31a, and applies a driving voltage to the liquid crystal molecules 105a of the first liquid crystal module 31a arranged between the incident side transparent electrode 103a and the exit side transparent electrode 107a, for driving the liquid crystal molecules 105a.

[0133] The R component drive signal generated by the LCD driver 36a is input to a liquid crystal drive circuit to drive and control the liquid crystal molecules 105a of the first liquid crystal module 31a so that R (red) light is emitted from the corresponding exit-side polarizing filter 109 at the timing when the backlight 100 emits R (red) light for pixels of the first liquid crystal module 31a that are to be illuminated in a color including the R component during the display period of one frame (1 / 60 seconds). The G component drive signal generated by the LCD driver 36a is input to the liquid crystal drive circuit to drive and control the liquid crystal molecules 105a of the first liquid crystal module 31a so that G (green) light is emitted from the corresponding exit side polarizing filter 109 at the timing when the backlight 100 emits G (green) light for pixels of the first liquid crystal module 31a that are to be illuminated in a color including the G component during the display period of one frame (1 / 60 seconds). The B component drive signal generated by the LCD driver 36a is input to a liquid crystal drive circuit to drive and control the liquid crystal molecules 105a of the first liquid crystal module 31a so that B (blue) light is emitted from the corresponding exit side polarizing filter 109 at the timing when the backlight 100 emits B (blue) light for pixels of the first liquid crystal module 31a that are to be illuminated in a color including the B component during the display period of one frame (1 / 60 seconds).

[0134] Specifically, while the backlight 100 is emitting R (red), the liquid crystal drive circuit of the first liquid crystal module 31a controls the liquid crystal molecules 105a of the first liquid crystal module 31a based on the R component drive signal so as to allow R (red) light to pass through the exit-side polarizing filter 109 corresponding to the pixel that is to emit light in a color including the R component. When the backlight 100 emits G (green) light, the liquid crystal driving circuit of the first liquid crystal module 31a controls the liquid crystal molecules 105a of the first liquid crystal module 31a based on the G component driving signal so as to allow G (green) light to pass through the output side polarizing filter 109 corresponding to the pixel desired to emit light in a color including the G component. When the backlight 100 emits B (blue) light, the liquid crystal driving circuit of the first liquid crystal module 31a controls the liquid crystal molecules 105a of the first liquid crystal module 31a based on the B component driving signal so as to allow B (blue) light to pass through the exit side polarizing filter 109 corresponding to the pixel desired to emit light with light including the B component. For each pixel of the first liquid crystal module 31a, R (red), G (green), and B (blue) are displayed at ultra-high speed (the light emitted from each pixel of the first liquid crystal module 31a is switched to R (red), G (green), and B (blue) at ultra-high speed), or the light is blocked to prevent emission of light, and as in the case of the second liquid crystal module 31b, a color that is a combination of one or more colors is perceived by the human eye.

[0135] The light emission mode of the first liquid crystal module in the image display unit 31 of this embodiment will be described with attention focused on one pixel. 31 and 32 are timing charts illustrating a control signal for each pixel of the first liquid crystal module 31a in the image display unit of this embodiment. During the image effective period, the LCD driver 36b inputs current to the red LED 115R, the green LED 115G, and the blue LED 115B every 1 / 180 seconds, and as a result, the emitting LEDs are switched. In all cases shown in Figs. 31 and 32, the backlight 100 switches the emission color from R (red) to G (green) to B (blue) in sequence every 1 / 180 seconds.

[0136] As shown in Figure 31(a), when specific pixels of the first liquid crystal module 31a are to be displayed transparently, the LCD driver 36a of the first liquid crystal module 31a inputs drive signals (R component drive signal, G component drive signal, B component drive signal) that drive the liquid crystal molecules 105a to allow light to pass through the output side polarizing filter 109a of the first liquid crystal module 31a corresponding to all of the R sub-pixels, G sub-pixels, and B sub-pixels over one frame. In this way, the R sub-pixel emits light during the 1 / 180 second period when the backlight 100 emits R (red light), the G sub-pixel emits light during the 1 / 180 second period when the backlight 100 emits G (green light), and the B sub-pixel emits B (blue light) during the 1 / 180 second period when the backlight 100 emits B (blue light). By emitting light successively in the order of R (red) → G (green) → B (blue) over one frame, the pixel is perceived as being in a transmissive state, just like in the second method.

[0137] As shown in Figure 31(b), in order to cause a specific pixel of the first liquid crystal module 31a to emit yellow light, drive signals (R component drive signal, G component drive signal, B component drive signal) are input that drive the liquid crystal molecules 105 so that light can pass through the output side polarizing filter 109 corresponding to the R subpixel and G subpixel, but cannot pass through the output side polarizing filter 109 corresponding to the B subpixel, over one frame. In this way, the R sub-pixel emits light during the 1 / 180 second period when the backlight 100 emits R (red) light, and the G sub-pixel emits light during the 1 / 180 second period when the backlight 100 emits G (green) light. On the other hand, during the 1 / 180 second period when the backlight 100 emits B (blue) light, neither sub-pixel emits light. By continuously switching between R (red) emission → G (green) emission → no emission due to light blocking over the course of one frame, the pixel emits yellow light (is perceived as yellow) just like in the second method.

[0138] Furthermore, as shown in FIG. 32(a), in order to cause a specific pixel of the first liquid crystal module 31a to emit cyan light, drive signals (R component drive signal, G component drive signal, B component drive signal) are input to drive the liquid crystal molecules 105a of the first liquid crystal module 31a so that light can pass through the output-side polarizing filter 109a of the first liquid crystal module 31a corresponding to the G subpixel and B subpixel, but cannot pass through the output-side polarizing filter 109a corresponding to the R subpixel, over one frame. During the 1 / 180 second period when the backlight 100 emits R (red) light, none of the sub-pixels emit light. During the 1 / 180 second period when the backlight 100 emits G (green) light, the G sub-pixel emits light, and during the 1 / 180 second period when the backlight 100 emits B (blue) light, the B sub-pixel emits light. By successively blocking light and emitting the following light in the order of no light, G (green) light, and B (blue) light over one frame, the pixel emits cyan light (is perceived as cyan), just like in the second method.

[0139] As shown in Figure 32(b), when black is to be expressed by a specific pixel of the first liquid crystal module 31a, drive signals (R component drive signal, G component drive signal, B component drive signal) are input to drive the liquid crystal molecules 105a of the first liquid crystal module 31a so that no light can pass through the output-side polarizing filter 109 corresponding to any of the R sub-pixels, G sub-pixels, and B sub-pixels over one frame. During a 1 / 180 second period when the backlight 100 emits R (red), during a 1 / 180 second period when the backlight 100 emits G (green), and during a 1 / 180 second period when the backlight 100 emits B (blue), none of the sub-pixels emit light. A pixel does not emit light over one frame, and is viewed as black.

[0140] An example of the light emission mode of the display device of this embodiment as a result of the above-mentioned control will be described below. FIG. 33 is a diagram illustrating an example of an image display mode of the image display unit of this embodiment. For the sake of simplicity, Fig. 33 shows only liquid crystal molecules 105 and color filters 108 for the first liquid crystal module 31a, but in reality, the first liquid crystal module 31a includes all the elements shown in Fig. 19. Light emitted from the sub-pixels of the first liquid crystal module 31a is polarized by liquid crystal molecules 105a so as to be able to pass through the exit-side polarizing filter 109a of the first liquid crystal module 31a. For simplicity of explanation, only liquid crystal molecules 105b are shown for the second liquid crystal module 31b, but in reality, the second liquid crystal module 31b has all the elements shown in Fig. 24. The light emitted from the second liquid crystal module 31b is polarized by the liquid crystal molecules 105b so as to be able to pass through the exit-side polarizing filter 109b of the second liquid crystal module 31b. The displays of both liquid crystal modules constituting the image display unit 31 can be simultaneously viewed from the front side. In addition, in the explanation of Figure 33, the pixels of the first liquid crystal module 31a and the second liquid crystal module 31b are shown to have a one-to-one correspondence for the sake of convenience, but since light is diffused, light does not enter or exit between only one pixel in the first liquid crystal module 31a and the second liquid crystal module 31b.

[0141] In FIG. 33, even if the light output from the color filter 108 of the first liquid crystal module 31a appears to be blocked by the blocking portion of the second liquid crystal module 31b, the light output from the color filter 108 is emitted to the outside via some path. As an example, in the case of Figure 33, all sub-pixels of the first pixel, second pixel, and third pixel of the first liquid crystal module 31a are controlled to allow light to pass through from the exit-side polarizing filter 109a of the first liquid crystal module 31a over one frame. 33(a), during the period of 1 / 180 seconds during which the backlight 100 emits R (red), light is emitted from the exit-side polarizing filters 109a corresponding to the R sub-pixels of the first, second, and third pixels of the first liquid crystal module 31a, and no light is emitted from the exit-side polarizing filters 109a corresponding to the G and B sub-pixels.

[0142] 33(b), during a period of 1 / 180 seconds during which the backlight 100 emits G (green), light is emitted from the exit-side polarizing filters 109a corresponding to the G sub-pixels of the first, second, and third pixels of the first liquid crystal module 31a, and no light is emitted from the exit-side polarizing filters 109a corresponding to the R and B sub-pixels. 33(c), during a period when the backlight 100 emits B (blue) light, light is emitted from the exit-side polarizing filters 109a corresponding to the B sub-pixels of the first, second, and third pixels of the first liquid crystal module 31a, and no light is emitted from the exit-side polarizing filters 109a corresponding to the R and G sub-pixels. In this case, the first, second, and third pixels of the first liquid crystal module 31a all change their light emission from R (red) light → G (green) light → B (blue) light, so that each pixel is perceived as “transparent” on a frame-by-frame basis.

[0143] Of course, this is not the only option, and various colors can be expressed according to the principle of Fig. 26 by controlling the first, second, third and other pixels so that light does not exit from the exit-side polarizing filters 109 corresponding to the R, G and B sub-pixels, as described above. For example, in the first pixel in FIG. 33, control is performed so that light does not exit from the exit-side polarizing filter 109a of the first liquid crystal module 31a corresponding to the R subpixel. In this case, the first pixel of the first liquid crystal module 31a does not emit light due to light blocking in Fig. 33(a). Therefore, the light emission of the first pixel changes from no light emission due to light blocking → G (green) light emission → B (blue) light emission, and the first pixel is visually recognized as cyan in one frame unit.

[0144] Similarly, in the first pixel of the first liquid crystal module 31a, control is performed so that light does not exit from the exit-side polarizing filter 109a of the first liquid crystal module 31a corresponding to the G subpixel. In this case, the first pixel of the first liquid crystal module 31a emits no light due to light blocking as shown in Fig. 33(b). Therefore, the first pixel of the first liquid crystal module 31a changes its light emission from R (red) light emission → no light emission due to light blocking → B (blue) light emission, and each pixel is visually recognized as magenta in one frame unit. Furthermore, in the first pixel of the first liquid crystal module 31a, control is performed so that light is not emitted from the exit-side polarizing filter 109a of the first liquid crystal module 31a corresponding to the B subpixel. In this case, the first pixel of the first liquid crystal module 31a emits no light due to light blocking as shown in Fig. 33(c). Therefore, the first pixel of the first liquid crystal module 31a changes its light emission from R (red) light emission to G (green) light emission to no light emission due to light blocking, and each pixel is visually recognized as yellow in one frame unit.

[0145] Next, the second liquid crystal module 31b will be described. During the emission periods of each color of the backlight 100 shown in Figures 33(a) to 33(c), as described above, only light of the emission color of the backlight 100 is emitted from the first liquid crystal module 31a, and the space between the first liquid crystal module 31a and the second liquid crystal module 31b is filled with diffused light of the emission color of the backlight 100. In FIG. 33(a) where the backlight 100 emits R (red) light, the space between the first liquid crystal module 31a and the second liquid crystal module 31b is filled with diffused R (red) light. In FIG. 33(b) where the backlight 100 emits G (green) light, the space between the first liquid crystal module 31a and the second liquid crystal module 31b is filled with diffused G (green) light. In FIG. 33(c) where the backlight 100 emits B (blue) light, the space between the first liquid crystal module 31a and the second liquid crystal module 31b is filled with diffused B (blue) light.

[0146] The second liquid crystal module 31b uses these diffused lights to perform the second type color display described with reference to FIGS. As a result, in the case shown in FIG. 33, the three pixels of the second liquid crystal module 31b are perceived as follows. The first pixel of the second liquid crystal module 31b switches between R (red) emission, G (green) emission, and no emission due to light blocking, and is therefore visually recognized as yellow. Also, the second pixel of the second liquid crystal module 31b switches from no emission due to light blocking to G (green) emission to B (blue) emission, and is therefore visually recognized as cyan. Furthermore, the third pixel of the second liquid crystal module 31b switches from R (red) emission to no emission due to light blocking to B (blue) emission, and is therefore visually recognized as magenta. As configured as described above, the image display unit 31 of this embodiment saves energy by reducing power consumption without increasing the light output of the backlight, avoiding high costs, while also increasing the interest of the game by providing a new, deep presentation using multiple liquid crystal modules.

[0147] In addition, by lighting the backlight 100 behind the color filters in R (red), G (green), and B (blue), the first liquid crystal module 31a and the second liquid crystal module 31b can display images with approximately the same colors. The wavelength (color width) of the light that passes through the color filter is narrower than that of the light emitted from the LED, so the color difference between the first liquid crystal module 31a and the second liquid crystal module 31b is reduced by passing the light through the color filter.

[0148] Furthermore, a feature of the image display unit of this embodiment is that in the second liquid crystal module 31b, by controlling the amount of light passing through the pixels of the second liquid crystal module 31b for each color component, it is possible to change the light intensity ratio for each color component and realize intermediate colors. As described in detail below, in order to vary the light intensity for each color component, the LCD driver 36b may vary the light intensity of the backlight 100 by the red LED 115R, the green LED 115G, and the blue LED 115B for each color. In this case, the current values ​​applied to the red LED 115R, the green LED 115G, and the blue LED 115B may be different. By adjusting the applied current value to adjust the light intensity of red LED 115R, green LED 115G, and blue LED 115B, it is possible to control so as to eliminate unevenness in the light intensity for each color of light emitted from backlight 101. 29(b), a plurality of red LEDs 115R, green LEDs 115G, and blue LEDs 115B may be provided and the number of LEDs may be changed for each color, thereby varying the light intensity ratio for each color component of the backlight 100. Alternatively, the number of red LEDs 115R, green LEDs 115G, and blue LEDs 115B may be changed to equalize the light intensity for each color component of the backlight 100, thereby eliminating unevenness in the light intensity.

[0149] Incidentally, the speed and time (excitation time, response speed, response time) from when the LCD driver 36b applies a current to an LED element until light is emitted differs depending on the emitted color. That is, there is a problem in that the time from when the LCD driver 36b applies a current to the red LED 115R, the green LED 115G, and the blue LED 115B until light is emitted differs for each LED 115. The time from when a current is applied to the LED until light is actually emitted is the longest for the red LED 115R, the next longest for the green LED 115G, and the shortest for the blue LED 115B. When current is applied at the same timing, blue LED 115B starts emitting light the earliest, green LED 115G starts emitting light the next earliest, and red LED 115R starts emitting light the latest.

[0150] In the second type of image display described in Figures 25 to 28, accurate color expression is not possible unless the drive timing of the liquid crystal module based on the drive signal for each color component is synchronized with (at least) the emission start timing of the LED, i.e., the backlight. Assume that a current is applied to any one of the LEDs, for example, red LED 115R, at a timing that matches the timing at which the red LED 115R starts to emit light and the driving timing of the liquid crystal molecules, and the same timing is applied to green LED 115G and blue LED 115B. In this case, problems may occur in which the green LED 115G emits light too early, causing green to be mixed into the light emitted by the backlight 100, which should be emitting red light, or the blue LED 115B starts emitting light too late, causing the backlight 100 to not be able to emit B (blue) light in time to drive the liquid crystal molecules based on the B component drive signal.

[0151] Therefore, the LCD driver 36b adjusts the timing of current application so that light can be emitted in synchronization with the drive signal of each color component according to the response characteristics of the LEDs 115 of each color, and controls the backlight 100 so that it starts emitting light at the desired timing. Therefore, the LCD driver 36b defines the timing at which the backlight 100 should start emitting light as t0, the timing at which a current is applied to the red LED 115R to cause the backlight 100 to emit red light at time t0 as t1, the timing at which a current is applied to the green LED 115G to cause the backlight 100 to emit green light at time t0 as t2, and the timing at which a current is applied to the blue LED 115B to cause the backlight 100 to emit blue light at time t0 as t3. As described above, the time from when a current is applied to an LED until light is actually emitted is longer for the red LED 115R, followed by the green LED 115G and the blue LED 115B. Therefore, the LCD driver 36b determines whether the time from each of the timings t1, t2, and t3 to the timing t0 is |t0-t1|>|t0-t2|>|t0-t3| The timing of current application to the LEDs 115 of each color is controlled so as to satisfy the relationship. As described above, the LCD driver 36b applies current to the red LED 115R at the earliest timing before the backlight is turned on for each color, applies current to the green LED 115G at the next earliest timing, and applies current to the blue LED 115B at the latest timing.

[0152] The same applies to red LED 116R, green LED 116G, and blue LED 116B in the modified example of FIG. 21, whose light emission timings are synchronized with red LED 115R, green LED 115G, and blue LED 115B. The LCD driver 36b applies current to the same colors (red LED 115R and red LED 116R, green LED 115G and green LED 116G, and blue LED 115B and blue LED 116G) at the same timing.

[0153] In the image display unit 31 of this embodiment, the first liquid crystal module 31a is disposed on the back side (rear side), and the second liquid crystal module 31 is disposed on the front side (front side). Alternatively, a backlight 100 capable of emitting light in three colors, R (red), G (green), and B (blue), may be used, and multiple second liquid crystal modules 31b may be arranged in front and behind each other, so that each second liquid crystal module 31b can perform color display using the second method.

[0154] Also, in the image display unit 31 of this embodiment, the amount of light output from the color filter 108 of the liquid crystal module 31a is substantially ⅓ or less of the amount of light incident on each sub-pixel. On the other hand, the red LED 115R, green LED 115G, and blue LED 115B of the backlight 100 can be made of LEDs with higher power and increased light output. In the image display unit 31 of this embodiment, in which the second liquid crystal module 31b that does not use a color filter is arranged on the front side of the first liquid crystal module 31a that uses a color filter, the light loss of the entire unit is small compared to when the first liquid crystal module is used on the front side (transmittance 5%), and the required light amount of the LED is relatively small, about three times that of a normal one. Compared to when the first liquid crystal modules 31a are arranged in front and behind, it is possible to reduce concerns about economy, heat resistance, etc.

[0155] FIG. 34 is a diagram showing a modification of the image display unit of this embodiment. The modified example shown in FIG. 34 has a configuration in which a light-emitting feature 500 is disposed between the first liquid crystal module 31a and the second liquid crystal module 31b in FIG. The light-emitting device 500 comprises a third liquid crystal module 31c having a similar configuration to the first liquid crystal module 31a arranged on the front side thereof, and a backlight 501 arranged on the rear side of the third liquid crystal module 31c.

[0156] A backlight (light-emitting plate, light guide plate, lens) 501 provided in the light-emitting device 500 has red LEDs 116R, green LEDs 116G, and blue LEDs 116 arranged on its side or back. By switching the LEDs that emit light into the backlight 501, the backlight 501 can switch the light emission color from R (red) to G (green) to B (blue). Furthermore, the light-emitting feature 500 includes an LED driver 37 that controls the light emission of the red LED 116R, the green LED 116G, and the blue LED 116. The LED driver 38 switches the LEDs that emit light every predetermined time (1 / 180 seconds) at the same timing as the LCD driver 36b, thereby switching the emission color of the backlight 501.

[0157] Further, the third liquid crystal module 31c receives drive signals from the VDP 157 that are synchronized with the drive signals for each color component that are supplied to the first liquid crystal module 31a. As described above, the LCD driver 36b of the second liquid crystal module 31b outputs RGB signals for synchronization to the outside when turning on the red LED 115R, the green LED 115G, and the blue LED 115B. The RGB signals of the second liquid crystal module 31b are input to the LED driver 38 via the VDP 157 and the host CPU 151. When the second liquid crystal module is to cause the red LED 116R, green LED 116G, and blue LED 116 to emit light in synchronization with the red LED 115R, green LED 115G, and blue LED 115B, it inputs a lighting signal to the LED driver 38 to light up the red LED 116R, green LED 116G, and blue LED 116 in accordance with the RGB signal. Normally, the LED driver 38 passes the RGB signal through, and when a turn-on signal is input, it controls the color LED 116R, the green LED 116G, and the blue LED 116 to light up.

[0158] Note that the LED driver 38 does not always output RGB signals, but rather, an RGB signal may be input to the LED driver 38 as a lighting signal to cause the red LED 116R, green LED 116G, and blue LED 116 to emit light in synchronization with the red LED 115R, green LED 115G, and blue LED 115B. As a result, the image display unit is capable of displaying images as described below.

[0159] FIG. 35 is a schematic cross-sectional view illustrating an image display by the image display unit of FIG. As shown in FIG. 35, the light emitted from the first liquid crystal module 31a by the display method described in FIG. 30 to FIG. 33 is partially blocked by the light-emitting device 500 and cannot be seen by the player. However, the backlight 501 of the light-emitting prop 500 can emit R (red), G (green), and B (blue) in synchronization with the backlight 100 by using a red LED 115R, a green LED 115G, a blue LED 115B, and a red LED 116R, a green LED 116G, and a blue LED 116B that emit light in synchronization with the above-mentioned control. Further, the first liquid crystal module 31c of the light-emitting role object 500 receives a drive signal synchronized with the drive signal input to the first liquid crystal module 31a. In the first liquid crystal module 31c, images are displayed in the same manner as in the first liquid crystal module 31a, using a drive signal synchronized with that of the first liquid crystal module 31a and sequentially switched RGB backlight lights in the manner described with reference to Figures 30 to 33. As a result, the display contents of the first liquid crystal module 31a hidden by the light-emitting character object 500 are displayed on the first liquid crystal module 31c of the light-emitting character object 500. Therefore, by viewing the display by first liquid crystal module 31a and first liquid crystal module 31c, the player can visually recognize the content that should originally be displayed on first liquid crystal module 31a.

[0160] Even more distinctive is the display on the second liquid crystal module 31b. The second liquid crystal module 31b has no light-emitting feature 500 behind it, and in an area 600 where the R (red), G (green), and B (blue) lights from the first liquid crystal module 31a directly reach, the second type of image display is performed mainly using the R (red), G (green), and B (blue) lights from the first liquid crystal module 31a. On the other hand, the second liquid crystal module 31b has an illuminating feature 500 behind it, and in an area 601 where the R (red), G (green), and B (blue) lights from the first liquid crystal module 31a do not directly reach, the second type of image display is performed mainly using the R (red), G (green), and B (blue) lights from the first liquid crystal module 31c of the illuminating feature 500. In this way, the image display unit of this embodiment can save energy by suppressing power consumption without increasing the light intensity of the backlight, while avoiding high costs, and can enhance the entertainment value of the game by providing a new depth of effect with multiple liquid crystal modules. Furthermore, the entertainment value of the game can be further enhanced by arranging accessories between the multiple liquid crystal modules without sacrificing the display content.

[0161] Incidentally, when the orientation of the polarization plane of light explained in Figure 21 is taken into consideration, the light that exits the exit-side polarizing filter 109a of the first liquid crystal module 31a and the exit-side polarizing filter 109c (not shown) of the third liquid crystal module 31c cannot pass through the entrance-side polarizing filter 101b of the second liquid crystal module 31b as it is. This is because the direction of the polarization plane of the light emitted from the first liquid crystal module 31a and the third liquid crystal module 31c (direction b in FIG. 21) does not match the polarization direction (direction a) of the incident-side polarizing filter 101b of the second liquid crystal module. Therefore, in the image display unit 31 of this embodiment configured as shown in FIGS. 29 and 34, a problem may occur in which an image cannot be displayed on the second liquid crystal module 31b. Therefore, in the image display unit 31 of this embodiment, it is necessary to provide a retardation film (1 / 2 wavelength plate) between the exit side polarizing filter 109a of the first liquid crystal module 31a and the entrance side polarizing filter 101b of the second liquid crystal module 31b, and between the exit side polarizing filter 109c of the third liquid crystal module 31c and the entrance side polarizing filter 101b of the second liquid crystal module 31b. Specifically, in the configuration of Figure 29 which has only the first liquid crystal module 31a and the second liquid crystal module 31b, the retardation film may be attached to the front side of the exit side polarizing filter 109a of the first liquid crystal module 31a, or to the rear side of the entrance side polarizing filter 101b of the second liquid crystal module 31b.

[0162] In the configuration of Figure 34, which has the third liquid crystal module 31c between the first liquid crystal module 31a and the second liquid crystal module 31b, it is desirable to attach a retardation film to the rear side of the incident side polarizing filter 101b of the second liquid crystal module 31b, or to attach retardation films to the front side of the exit side polarizing filter 109a of the first liquid crystal module 31a and the front side of the exit side polarizing filter 109c of the third liquid crystal module 31c. The retardation film as a half-wave plate can impart a phase difference of λ / 2 (180°) to the light emitted from the exit-side polarizing filter 109a of the first liquid crystal module 31a and the exit-side polarizing filter 109c of the third liquid crystal module 31c, and rotate the polarization plane by 90 degrees to direction a. This allows the emitted light from the first liquid crystal module 31a and the third liquid crystal module 31c to pass through the incident side polarizing filter 101b of the second liquid crystal module 31b, allowing an image to be displayed on the second liquid crystal module 31b without any problems.

[0163] In the example of Figure 35, a light-emitting device 500 including a third liquid crystal module 31c and a backlight 116 is provided between the first liquid crystal module 31a and the second liquid crystal module 31b, but instead of the light-emitting device 500, a movable device imitating a predetermined shape may be provided between the first liquid crystal module 31a and the second liquid crystal module 31b. The movable part may be provided with only a red LED 116R, a green LED 116G, and a blue LED 116 on its front side. Then, the LED driver 37 controls the red LED 116R, the green LED 116G, and the blue LED 116 in the same manner as in FIG. 35 to emit R (red) light, G (green) light, and B (blue) light toward the second liquid crystal module 31b every 1 / 180 seconds. In the second liquid crystal module 31b, the R (red), G (green), and B (blue) lights from the first liquid crystal module 31a are blocked by the light-emitting part 500, but color display by the second method can be performed using the R (red), G (green), and B (blue) lights from the red LED 116R, green LED 116G, and blue LED 116B provided on the movable part.

[0164] In the second liquid crystal module 31b, in areas where the R (red), G (green), and B (blue) light from the first liquid crystal module 31a is not blocked by the movable parts, color display is performed using a second method using the R (red), G (green), and B (blue) light from the first liquid crystal module 31a. The light emitted from the LED has low diffusibility and emits a point-like light without diffusing, so it is not suitable for the second liquid crystal module 31b to display color according to the second method as it is, because the light does not reach the pixels of the second liquid crystal module 31b evenly. On the other hand, since the light emitted from the backlight 100 is diffused in the backlight serving as a light guide plate (the backlight emits light from a surface), the second liquid crystal module 31b can be suitably used for the second type of color display. The red LED 116R, green LED 116G, and blue LED 116 provided on the front of the movable parts do not naturally emit light as backlight, so it is desirable to attach a diffusion film to the front side of the movable parts to prevent these from emitting point light.

[0165] As described above, the emission timing of the red LED 116R, green LED 116G, and blue LED 116 is completely synchronized with the emission timing of the red LED 115R, green LED 115G, and blue LED 115B, which are the light sources of the backlight 100, so that the second liquid crystal module 31b as a whole can perform color display using the second method without any problems. It should be noted that the retardation film does not need to be attached to a movable component, and may be attached to the front side of the exit polarizing filter 109a of the first liquid crystal module 31a, or to the rear side of the entrance polarizing filter 101b of the second liquid crystal module 31b.

[0166] In the configuration shown in Figures 34 and 35, a light guide plate such as an acrylic plate engraved with a predetermined pattern may be placed between the first liquid crystal module 31a and the second liquid crystal module 31b instead of the light-emitting element 500. By illuminating the light guide plate with light from the red LED 116R, the green LED 116G, and the blue LED 116, an image according to the pattern can be displayed. By displaying using the light guide plate, the effect patterns 35 and the like displayed on the first liquid crystal module 31a and the second liquid crystal module 31b can be displayed in an emphasized and reinforced manner. The red LED 116R, the green LED 116G, and the blue LED 116 emit light from the side of the light guide plate, not from the back, so that the visibility of the display in the first liquid crystal module 31a is not impaired. Then, the LED driver 37 controls the red LED 116R, the green LED 116G, and the blue LED 116 in the same manner as in FIG. 35 to emit R (red) light, G (green) light, and B (blue) light toward the light guide plate every 1 / 180 seconds. The light emission timings of the red LED 116R, green LED 116G, and blue LED 116 are completely synchronized with the light emission timings of the red LED 115R, green LED 115G, and blue LED 115B which are the light sources of the backlight 100. Therefore, an image can be displayed on the light guide plate, and color display can be performed by the second method by using the light from the light guide plate as a light source for the second liquid crystal module 31b.

[0167] If the frame start timing (vertical synchronization timing, VSYNC) of the first liquid crystal module 31a and the second liquid crystal module 31b is out of sync, color misalignment may occur in either the first liquid crystal module 31a or the second liquid crystal module 31b. The emission timing of the red LED 115R, green LED 115G, and blue LED 115B is synchronized with the drive signals of the first liquid crystal module 31a and the second liquid crystal module 31b. However, if the vertical synchronization timing of the two liquid crystal modules is misaligned, a problem may occur in which, for example, in the second liquid crystal module 31b, the backlight 100 does not emit R (red) light when the liquid crystal molecules should be driven by the liquid crystal drive signal for the R component (when the pixels should be displayed in red). Therefore, it is necessary to synchronize the vertical synchronization signal (VSYNC) between the first liquid crystal module 31a and the second liquid crystal module 31b. A method for synchronizing the vertical synchronization signals of the first liquid crystal module 31a and the second liquid crystal module 31b in the image display unit 31 of this embodiment will be described below.

[0168] FIG. 36 is a diagram for explaining the basic configuration of a liquid crystal screen. An LCD screen is made up of a large number of pixels arranged in a matrix, with the pixels arranged in the horizontal direction forming one scanning line (horizontal line). An image is then displayed by scanning (driving pixels) the scanning lines (horizontal lines) one line at a time (for example, from left to right) in the up and down direction (vertical direction) in accordance with a (VGA) input signal. Furthermore, on the liquid crystal screen, non-display areas (=blank areas) can be set in the horizontal and vertical directions around a display area (effective pixel area) 50 made up of effective pixels where an image is actually displayed.

[0169] In the example shown in FIG. 36( a ), the blank areas set in the horizontal and vertical directions of the effective pixel area 50 include a horizontal front porch 51 , a horizontal back porch 52 , a vertical front porch 53 , and a vertical back porch 54 . By adjusting the sizes of the back porch and front porch, it is possible to change the position of the display area (effective pixel area) 50 within the liquid crystal screen. The blank area set above the effective pixel area 50 is a vertical front porch 53 , and the blank area set below the effective pixel area 50 is a vertical back porch 54 . In addition, in a horizontal line including effective pixel area 50, the blank area set on the left side (scanning start side) is horizontal front porch 51, and the blank area on the right side (scanning end side) is horizontal back porch 52. It should be noted that the blank areas do not necessarily have to be set separately above and below, or in front and behind, the effective pixel area 50. As shown in FIG. 36(b), they may be set as horizontal blank areas 55 in front or behind the effective pixel area 50, or may be set together as vertical blank areas 56 on the top or bottom.

[0170] As described above, the image display unit (liquid crystal screen) includes an LCD driver that drives pixels (liquid crystals) based on signals input from the VDP 157. The first liquid crystal module 31a includes an LCD driver 36a, and the second liquid crystal module 31b includes an LCD driver 36b. The liquid crystal screen has different operation modes (drive modes) according to the state of the signal input from the VDP 157 to the LCD driver, and these are roughly divided into DE mode and fixed mode. 4, the display circuit 208 outputs a video signal and a sync signal, but these are signals in a fixed mode, which will be described later, and in the DE mode, a data enable signal (DE signal) is used. The fixed mode will be described below.

[0171] In the fixed mode, the input signals input from the VDP 157 mainly include a drive clock, a luminance signal and a color signal (video signal) conforming to the video, and synchronization signals (H-SYNC signal, V-SYNC signal, blank signal). FIG. 37 is a diagram showing a synchronization signal of the liquid crystal module. When the V-SYNC signal is input from the VDP 157, the driver scans (drives) one line at a time from the first dot on the liquid crystal screen according to the state of the V-BLANK signal. The period during which the V-BLANK signal is invalid after the V-SYNC signal is input corresponds to a vertical blank area 56 (vertical front porch 53+vertical back porch 54). During the effective period of the V-BLANK signal, drawing in the effective pixel area 50 is performed. An inactive period of the H-BLANK signal (not shown) during the active period of the V-BLANK signal corresponds to a horizontal blank area 55 (horizontal front porch 51+horizontal back porch 52). When the H-BLANK signal is active, actual drawing (driving of pixels) is performed by the active pixels. When the H-SYNC signal is input during scanning of one line, the next line is scanned.

[0172] When the V-SYNC signal is input after the vertical back porch period, it is time to refresh the screen and start scanning the next screen. Moreover, the vertical blanking period (vertical front porch period+vertical back porch period) is defined by the V-BLANK signal. 37(b), when the blank area is set collectively either before or after the effective pixel area, the V-SYNC signal is input at the end of the blanking period consisting of the vertical front porch 53 and the vertical back porch 54, and the display returns to the first pixel of the next screen. This timing is the screen refresh timing.

[0173] In the image display unit 31 of this embodiment, the following control is performed to match the vertical synchronization timing of the first liquid crystal module 31a and the second liquid crystal module 31b. Basically, this involves controlling the vertical synchronization timing of one liquid crystal module to match the vertical synchronization timing of another liquid crystal module. In the following, a case will be described in which the vertical synchronization timing of the first liquid crystal module 31a is slower than that of the second liquid crystal module 31b, although this is of course only one example and the opposite is also possible. When the LCD driver 36a finishes scanning the last pixel of the second liquid crystal module 31b and returns to the first pixel, it forcibly returns the first liquid crystal module 31a whose pixels are still being driven to the first pixel. This synchronizes the vertical synchronization timing of the first liquid crystal module 31a and the second liquid crystal module 31b. This can be achieved by using the following configuration.

[0174] FIG. 38 is a diagram (part 1) for explaining a synchronization signal for adjusting the vertical synchronization timing of two liquid crystal screens included in the image display unit of this embodiment. (i) indicates a synchronizing signal input to the second liquid crystal module 31b, and (ii) indicates a synchronizing signal input to the first liquid crystal module 31a. In the gaming machine of this embodiment, as shown in Figure 38(b), for the first liquid crystal module 31a having a smaller refresh rate value, the timing of the V-SYNC signal is made earlier than the actual timing (the vertical back porch period is shortened) and made the same timing as the V-SYNC signal of the second liquid crystal module 31b shown in Figure 38(a). The VDP 157 outputs a V-SYNC signal, the timing of which is synchronized with that of the second liquid crystal module 31b, to the LCD driver 36a of the first liquid crystal module 31a.

[0175] Furthermore, the difference in refresh rate between the first liquid crystal module 31a and the second liquid crystal module 31b is very slight, and at the time when the vertical back porch period ends for the second liquid crystal module 31b, it is highly likely that the first liquid crystal module 31a will also have finished driving the effective pixel area 50a and entered the vertical back porch period. When the vertical back porch period ends and the vertical front porch period starts for the second liquid crystal module 31b, even if the vertical front porch period is also forcibly entered for the first liquid crystal module 31a, no problem occurs with the image display of the first liquid crystal module 31a.

[0176] In such a case, V-SYNC is input after the vertical blank area 56, but by inputting the V-SYNC input to the second liquid crystal module 31b and also inputting a V-SYNC signal to the first liquid crystal module 31a at the same time, it is possible to match the vertical synchronization timing of the first liquid crystal module 31a and the second liquid crystal module 31b.

[0177] As another method, after the LCD driver 36b finishes scanning the last pixel of the second liquid crystal module 31b, it waits until the first liquid crystal module 31a, which is still driving the intermediate pixels, finishes scanning the last pixel and returns to the first pixel, and then returns to the first pixel. This synchronizes the vertical synchronization timing of the first liquid crystal module 31a and the second liquid crystal module 31b. This can be achieved by the following configuration.

[0178] FIG. 39 is a diagram (part 2) for explaining a synchronization signal for adjusting the vertical synchronization timing of two liquid crystal screens included in the image display unit of this embodiment. 13(a) shows the vertical synchronizing signal of the second liquid crystal module 31b, and (b) shows the vertical synchronizing signal of the first liquid crystal module 31a. In the gaming machine of this embodiment, as shown in Figure 39(a), for the second liquid crystal module 31b, the second liquid crystal module 31b waits even after a specified period corresponding to the vertical back porch 54b has elapsed, and the input timing of the original V-SYNC signal is delayed from the actual timing, so that it is the same timing as the vertical synchronization signal of the first liquid crystal module 31a. The VDP 157 transmits a vertical synchronization signal as shown in FIG. 39(a) in synchronization with the vertical synchronization timing (input timing of the V-SYNC signal) of the first liquid crystal module 31a. A V-SYNC signal is input after the vertical blank area 56. By inputting the V-SYNC signal to the LCD driver 36a of the first liquid crystal module 31a and also to the LCD driver 36b of the second liquid crystal module 31b at the same time, it is possible to match the vertical synchronization timing of the first liquid crystal module 31a and the second liquid crystal module 31b.

[0179] The same is true for the third liquid crystal module 31c; by inputting a V-SYNC signal to the LCD driver 36a of the first liquid crystal module 31a and also to the LCD driver of the third liquid crystal module 31b at the same time, the vertical synchronization timing of the first liquid crystal module 31a and the third liquid crystal module 31b can be aligned. As a result, the vertical synchronization timing can be aligned in all of the first liquid crystal module 31a, the second liquid crystal module 31b, and the third liquid crystal module 31c. In this embodiment, the red LED 115R, the green LED 115G, and the blue LED 115B may be configured to emit R (red) light, G (green) light, and B (blue) light, respectively, by converting the wavelength of ultraviolet light emitted from an LED capable of emitting invisible light (ultraviolet light) using a fluorescent tube.

[0180] In addition to the above, the configuration of the image display unit of this embodiment will be further described. FIG. 40 is a diagram illustrating an LED module provided in the gaming machine. As shown in FIG. 40(a), the LED module 115 includes a red LED 115R, a green LED 115G, and a blue LED 115B on a substrate 115S. In the gaming machine 1, the LED module 115 shown in FIG. 40(a) is disposed above and below at least one of the left and right sides of the backlight 100 as shown in FIG. 40(b), and light from the LED module 115 is caused to enter the backlight 100. The LED module arranged on the upper side surface of the backlight 100 is LED module 115-U, and the LED module arranged on the lower side surface of the backlight 100 is LED module 115-D. The LED modules 115-U and 115-D may be arranged on the upper and lower side surfaces of the backlight 100.

[0181] A plurality of LED modules 115 each having a minimum unit LED as shown in FIG. 40(a) may be provided, or one LED module having a large number of LEDs may be provided. The backlight 100 has an uneven portion on its bottom surface for reflecting light to the front side. The uneven portion allows the backlight 100 to function as a light guide. The uneven portion of the backlight 100 has a pattern that guides the light incident from the LED module 115-U from the upper side to the center of the backlight 100, and the light incident from the LED module 115-D from the lower side to the center of the backlight 100.

[0182] The driving method of the red LED 115R, the green LED 115G, and the blue LED 115B provided in the gaming machine 1 of this embodiment can be switched between "DC (direct current) driving" and "PWM (Pulse Width Modulation) driving". In general, "DC drive" is a drive method that lights up a light source (LED) continuously over time, while "PWM drive" is a drive method that repeatedly turns the light source on and off. The gaming machine 1 of this embodiment switches the LED drive method for each of the multiple LED modules 115. For example, in order to change the light emission mode in the upper and lower regions of the backlight 100, the gaming machine 1 can change the drive method of the mounted LEDs in the LED module 115-U arranged on the upper side of the backlight 100 and the LED module 115-D arranged on the lower side of the backlight 100. As described above, the terms "DC drive" and "PWM drive" refer to the drive method for one light source (LED), but in this specification they particularly refer to the drive method for an LED module 115 containing multiple LEDs.

[0183] In the "DC driving" of this embodiment, as described with reference to Fig. 10 etc., the red LEDs 115R, green LEDs 115G, and blue LEDs 115B on the LED module 115 are caused to emit light simultaneously. During the display period of the image display unit 31, the red LEDs 115R, green LEDs 115G, and blue LEDs 115B are caused to light up continuously. During the display period, the R light, G light, and B light emitted from the red LEDs 115R, green LEDs 115G, and blue LEDs 115B are simultaneously incident, causing the backlight (light guide plate) 100 to emit white light.

[0184] On the other hand, in the "PWM drive" of this embodiment, as described with reference to Fig. 12 etc., the red LED 115R, green LED 115G, and blue LED 115B on the LED module 115 are switched to emit light. During the display period of the image display unit, the red LED 115R, green LED 115G, and blue LED 115B are switched on and off in sequence. The R (red) light, G (green) light, and B (blue) light emitted sequentially from the red LED 115R, green LED 115G, and blue LED 115B enter the backlight (light guide plate) 100, causing it to emit red, green, and blue lights in that order.

[0185] When all the LED modules 115 are PWM driven, the LCD driver 36 applies, for example, a current value of 142 mA to the red LED 115 R, 163 mA to the green LED 115 G, and 142 mA to the blue LED 115 B. The light emission time of each LED is 3.8 ms. In this case, the measured luminance of the second liquid crystal module 31b on the front side is 220 cd / m 2 It was. In order to improve the luminance, the current values ​​applied to the red LED 115R, the green LED 115G, and the blue LED 115B are increased to 160 mA, 180 mA, and 170 mA, respectively. The measured luminance of the second liquid crystal module 31b is 254 cd / m 2 It became. However, the increase in brightness is not visually noticeable, and considering the increase in temperature of the LED, it cannot be said that increasing the applied current value is desirable.

[0186] If, instead of increasing the current value applied to the LEDs, the lighting period of the green LEDs 115G and the blue LEDs 115B were made longer than that of the red LEDs 115R, there was a problem that the white balance of the backlight 100 would be disrupted if the number of red LEDs 115R, green LEDs 115G, and blue LEDs 115 remained the same (1:1:1 ratio). If the white balance of the backlight 100 is disturbed, the color of the display in the liquid crystal display module 31 is also affected. In contrast, in this embodiment, the ratio of the number of red LEDs 115R, green LEDs 115G, and blue LEDs 115B provided in the LED module is, for example, 2:1:1. For example, as shown in Fig. 40, the LED module 115 includes two red LEDs 115R, one green LED 115G, and one blue LED 115B. Similarly to the above, currents of 142 mA, 163 mA, and 142 mA are applied to the red LED 115R, green LED 115G, and blue LED 115B, respectively. With this configuration, it is possible to achieve both high brightness and white balance.

[0187] On the other hand, when all the LED modules 115 are DC driven (to emit white light), the gaming machine 1 (LCD driver 36) applies, for example, a current value of 41 mA to the red LED 115R, 47 mA to the green LED 115G, and 41 mA to the blue LED 115B. The measured luminance of the second liquid crystal module 31b on the front side is 345cd / m 2 It is. 40, the LEDs in the LED module 115 are arranged in BRGR (or RGRB) rather than in BGRR or RRGB. By arranging the LEDs in this way and causing them to emit light, it is possible to reduce unevenness in the light emission of the backlight 100 when driven by DC.

[0188] In the gaming machine of this embodiment, the red LED 115R, the green LED 115G, and the blue LED 115B are basically configured to be PWM driven. Also, the same configuration of the red LED 115R, the green LED 115G, and the blue LED 115B as described above can be DC driven to make the backlight 100 emit white light. It is desirable to realize image display for the first liquid crystal module 31a and the second liquid crystal module 31b not by DC driving alone or PWM driving alone, but by combining both depending on the characteristics of the image to be displayed, thereby realizing image display that is easy for the player to view.

[0189] FIG. 41 is a diagram for explaining a display mode using light emission by DC driving and light emission by PWM driving of an LED module. The gaming machine 1 can switch between the drive methods of the multiple LED modules 115, which are capable of DC drive and PWM drive as described above, to cause one of the upper and lower areas of the backlight (light guide plate) 100 to emit light (white light) through DC drive of the LED modules, and the other area to emit light (RGB sequential light) through PWM drive. For example, the gaming machine 1 may display an image only on the lower side of the second liquid crystal module 31b on a standby screen, etc. In that case, as shown in Fig. 41, the gaming machine 1 causes the upper half of the backlight 100 to emit light by DC driving the upper LED module 115-U, and causes the lower half to emit light by PWM driving the lower LED module 115-D.

[0190] As shown in FIG. 41, in the lower half of the image display unit 31, a color image 800 is displayed in the first liquid crystal module 31a using a display method similar to the field sequential method, by using sequential RGB illumination of the backlight 100 with RGB light incident from the PWM-driven LED module 115-D. Furthermore, using the light emitted from the first liquid crystal module 31a, a color image is displayed 801 by the field sequential method in the lower half of the second liquid crystal module 31b. This is the same as the aspect described with reference to FIG.

[0191] Meanwhile, in the upper half of the image display unit 31, the first liquid crystal module 31a performs normal color image display 802 using color filters by using white emission of the backlight 100 due to white light incident from the DC-driven LED module 115-U. In this case, since the light emitted from the first liquid crystal module 31a includes all elements of R light, G light, and B light, it is basically impossible to perform color image display by the field sequential method in the upper half of the second liquid crystal module 31b. By directly emitting the color image light emitted from the first liquid crystal module 31a through the second liquid crystal module 31b, the player can only view the display image (such as the performance pattern 35) of the first liquid crystal module 31a in the upper half of the image display unit 31.

[0192] However, the RGB light that enters the lower half of the backlight 100 from the PMW-driven LED module 115-D does not remain in the lower half, but part of it propagates to the upper half of the backlight 100. As a result, a color image display 803 can be performed by the field sequential method using propagating light of RGM, using at least some of the pixels in the upper half of the first liquid crystal module 31a. When the first liquid crystal module 31a does not display a color image in the normal mode, it is possible to display a color image in the field sequential mode using all the pixels in the upper half of the first liquid crystal module 31a. Furthermore, by using the light emitted from the first liquid crystal module 31a, a color image display 804 can be performed by the field sequential method in the upper half of the second liquid crystal module 31b. Since the RGB light by the FS color display 800 in the lower half of the first liquid crystal module 31a also propagates to the upper half side of the second liquid crystal module 31b, this can also be used. Since the white light entering from the DC-driven LED module 115 is mixed with the propagating light (RGB light), the color development of the color image may be worse than in the lower half or in the case of Figure 20, but an image that is sufficiently visible as a color image can be displayed in the upper half of the second liquid crystal module 31b.

[0193] The measured luminance on the upper side of the second liquid crystal module 31b is 283 cd / m 2 , the measured brightness at the bottom is 233cd / m 2 , with a measured brightness of 281cd / m 2 It became. With this configuration, the screen becomes brighter than when only PWM drive is used, and the display, limited to the upper side that is illuminated by DC drive, becomes less tiring to the eyes. In the above description, the upper half of the backlight 100 is illuminated by DC driving of the LED module, and the lower half is illuminated by PWM driving of the LED module, but the configuration may be reversed. That is, the lower half of the backlight 100 may be illuminated by DC driving of the LED module 115, and the upper half of the backlight 100 may be illuminated by PWM driving of the LED module 115.

[0194] The image display unit 31 of the gaming machine 1 can turn off the dual liquid crystal display that displays images on the first liquid crystal module 31a and the second liquid crystal module 31b. When the dual LCD display is turned off, an image obtained by combining the image displayed on the second LCD module 31b with the image displayed on the first LCD module 31a is displayed on the first LCD module 31a as a performance image, except for the small pattern 35A described later.

[0195] FIG. 42 is a diagram for explaining a display mode when dual liquid crystal display is not performed. As shown in FIG. 42, when the dual liquid crystal display is turned off, the gaming machine 1 drives both of the LED modules 115-U and 115-D with DC, and causes the backlight 100 to emit white light by the incident white light. Then, in the first liquid crystal module 31a, a normal color image display 805 using a color filter is performed. The second liquid crystal module 31b is basically controlled so that the entire surface is in a transmissive state, allowing the image displayed in the first liquid crystal module 31a to be visible to the player. Furthermore, the gaming machine 1 is provided with an additional red LED module 117R, a green LED module 117G, and a blue LED module 117B on the side of the second liquid crystal module 31b, which are different from those used for the backlight 100, and these are driven by PWM. The LED module 117 may have the same configuration as the LED module 115 for the backlight 100. The gaming machine 1 causes the R light, G light, and B light emitted from the additional LED to enter the second liquid crystal module 31b, and displays at least the small symbol 35A on the second liquid crystal module 31b by a field sequential display. Even when a blackout effect is performed on the first display module 31a on the rear side, where the effect pattern 35 is not displayed and the effect screen is darkened, the small pattern 35A is displayed on the second display module 31b, so there is no need to display it on the first display module 31a. The effect of the effect can be enhanced by completely darkening the first display module 31a.

[0196] Furthermore, in the gaming machine 1, a role-playing object, whether movable or non-movable, can be disposed between the first liquid crystal module 31a and the second liquid crystal module 31b. For example, it is envisaged that a movable device that is in a waiting position above the image display unit 31 and out of the player's field of vision will protrude to a protruding position between the first liquid crystal module 31a and the second liquid crystal module 31b when a jackpot confirmation effect is triggered by, for example, the operation of the effect button 8.

[0197] Fig. 43 is a diagram for explaining a display mode according to the configuration shown in Fig. 33. The configuration in Fig. 43 is a mode according to the configuration shown in Fig. 33, and both of the LED modules 115-D and 115-U are PWM driven to cause the entire backlight 100 to emit RGM sequential light. The first liquid crystal module 31a performs FS color image display 802 using RGB light, and the second liquid crystal module 31a performs FS color image display 807 using the RGB light from the first liquid crystal module 31a. FIG. 43 shows a case where a special object is placed between first liquid crystal module 31a and second liquid crystal module 31b, but the present invention can also be applied to a case where no special object is placed.

[0198] As shown in Fig. 43, when a role object 450 exists between the first liquid crystal module 31a and the second liquid crystal module 31b, or when a movable role object protrudes, the display of the first liquid crystal module 31a becomes partially invisible to the player. For example, when a role object exists in front of the performance pattern 35 displayed on the first liquid crystal module 31a, the player cannot see the performance pattern 35. 42, additional LED modules 117 (red LED module 117R, green LED module 117G, blue LED module 117B) different from those for the backlight 100 are provided on the side surface of the second liquid crystal module 31b and are driven by PWM. The LED modules 117 may have the same configuration as the LED modules 115 for the backlight 100.

[0199] The gaming machine 1 causes the R light, G light, and B light emitted from the additional LED module 117 to enter the second liquid crystal module 31b, and displays the small symbol 35A on the second liquid crystal module 31b by a field sequential display. When an object such as a prop is present between the first liquid crystal module 31a and the second liquid crystal module 31b, the configuration in which an additional LED module 117 is used to display on the second liquid crystal module 31b can also be applied to the configurations of Figures 41 and 42.

[0200] Even if there is no object between the first liquid crystal module 31a and the second liquid crystal module 31b, the amount of light can be increased by an additional LED module 117 so that the image displayed in field sequential color on the second liquid crystal module 31b can be seen more clearly. When a blackout effect in which the effect pattern 35 is hidden and the effect screen is darkened is performed on the first display module 31a on the rear side, the small pattern 35A can be displayed on the second display module 31b using RGB light from the LED module 117. Since there is no need to display the small pattern 35A on the first display module 31a, the first display module 31a can be completely darkened to enhance the effect of the effect. It should be noted that the small symbol 35A itself cannot be displayed only by the additional LED module 117, but can also be displayed normally by field sequential display using light from the first liquid crystal module 31a.

[0201] [Startup control of the performance control CPU] The performance control CPU 71 starts up by executing a startup program stored in a boot ROM (FeRAM 77) that serves as an external storage area provided on the performance control board 95. Although the FeRAM 77 is implemented on the performance control board 95, unlike the performance control ROM 73 built into the performance control CPU 71, the performance control CPU 71 treats the FeRAM 77 as an external memory area. The performance control CPU 71 integrates the functions of the VDP that controls image display, and at startup, also starts up the VDP section. Therefore, the performance control CPU 71 also performs PLL control for generating a drive clock that depends on the resolution of the liquid crystal display device of the gaming machine. Therefore, it was basically necessary to store setting information such as the drive clock of the liquid crystal display device and a setting program (startup program) in the FeRAM 77 of the performance control board 95. However, if the size of the liquid crystal display device changes in a new model, the setting information will also change. In that case, it is necessary to rewrite the setting information on the FeRAM 77, making it difficult to completely reuse the performance control board 95. This runs counter to the trend toward reuse of performance control boards, including performance control CPUs, from environmental and economical standpoints. Therefore, in the gaming machine of this embodiment, the setting information and the start-up program for each model are stored in the integrated data ROM 92 (external storage area different from the FeRAM 77) in the replaceable ROM cassette 40. By replacing the ROM cassette 40 without storing setting information etc. in the performance control board 95, the performance control CPU can be started based on the specifications of each model. Therefore, it is possible to provide a gaming machine that facilitates reuse of the performance control board 95 and is environmentally friendly and economical.

[0202] This is explained in detail below. FIG. 44 is a diagram for explaining the configuration of the control program of the performance control board in the gaming machine of this embodiment. As described above, the performance control CPU 71 is a single chip that integrates the image processor (VDP), the overall control CPU 76, and the image control CPU (host CPU) 151. The performance control ROM and the performance control RAM may also be built in. The overall control CPU 76 and the host CPU 151 may be a single CPU, and in that case, the overall control CPU 76 may integrate the functions of the host CPU 151 . If not, the control of the VDP 157 included in the performance control CPU is executed by the overall control CPU 76 via the host CPU 151. Here, the explanation will be given on the assumption that the overall control CPU 76 and the host CPU 151 are integrated. The FeRAM 77 provided on the performance control board 95, which is used in common by each model, stores the boot program of the performance control CPU 71 (overall control CPU 76). The integrated data ROM 92 on the integrated ROM board 90 housed in the ROM cassette 40 stores a model-specific control program and setting information (control information) for the performance control CPU 71 based on specifications that differ for each model.

[0203] As shown in FIG. 44, the boot program stored in the FeRAM 77 is the FRAM (registered trademark)_BOOT program. The FRAM (registered trademark)_BOOT program is a microprogram that has the minimum functions required for the performance control CPU 71 (overall control CPU 76) to start up and recognize the ROM cassette 40. The setting information stored in the integrated data ROM 92 includes a drive clock corresponding to the resolution of the liquid crystal module included in the image display unit 31, and the like. The control programs stored in the integrated data ROM 92 are a SATA_BOOT program and a SATA_PRG program. The SATA_BOOT program is a program that controls the drive clock in accordance with specifications that differ for each model, such as the resolution of the image display unit 31, based on the setting information. The SATA_PRG program is a user program that causes the overall control CPU 76 to carry out performance control, such as determining and executing a performance based on a variation pattern designation command after the system is started.

[0204] The startup sequence of the performance control CPU 71 is explained below. FIG. 45 is a diagram explaining the startup sequence of the performance control CPU. In step 101, the performance control CPU 71 (overall control CPU 76) transfers (calls) the FRAM (registered trademark)_BOOT program from the FeRAM 77 to the performance control RAM 74, and executes the transferred FRAM (registered trademark)_BOOT program. This FRAM (registered trademark)_BOOT program is a simple program for calling SATA_BOOT. After executing the FRAM (registered trademark)_BOOT program, the performance control CPU 71 recognizes the ROM cassette 40 connected to the performance control board 95 in step S102, and transfers (calls) the SATA_BOOT program stored in the integrated data ROM 92 on the integrated ROM board 90 to the performance control RAM 74 in step S103.

[0205] In step S104, the performance control CPU 71 executes the transferred SATA_BOOT program, and in step S105, executes PLL (Phase Locked Loop) settings using the control information on the integrated data ROM 92. In the PLL settings, the reference clock (the base clock) is divided to generate a driving clock in the image unit 31. Specifically, the performance control CPU 71 (overall control CPU 76) controls the PLL circuit provided in the clock generation circuit 205, divides the pulse signal (for example, 1 GHz) generated by the crystal oscillator 155, and repeats feedback control until the clock determined by the control information is obtained, thereby generating a drive clock. This PLL setting can be performed only once at startup, and the PLL setting cannot be changed thereafter. Through the above processing, the performance control CPU 71 including the VDP 157 completes the start-up (boot), and thereafter, the overall control CPU 76 executes the SATA_PRG program, which is a user program. The SATA_PRG program becomes operable after SATA_BOOT.

[0206] [Audio / Volume Control] Here, the voice control and the volume control in the gaming machine of this embodiment will be described. First, the volume setting process in the gaming machine will be outlined. In the pachinko machine 1 of this embodiment, the initial value of the master volume value is set by the volume switch 280. This is a task that can basically only be performed by the game store staff, and the volume switch 280 is often installed in a position where the player cannot operate it, such as on the back of the game machine. The volume switch 280 is often composed of a dip switch or a knob. Furthermore, the player can adjust the master volume value from the initial value set by using, for example, the left and right keys (volume adjustment buttons) of the cross key 78 according to his own convenience and preference. This operation can be performed when the gaming machine is in a waiting state. The operating means is not limited to the cross key as long as it allows the volume adjustment operation. The adjustment of the master volume value using the volume control button may be performed while the special symbols are changing, but the adjustment cannot be performed within 15 frames after the change starts or when the change stops.

[0207] The master volume value can be changed in one step from "1" to "10" using the volume switch 280 or the volume adjustment button, and four volume levels within that range - "large," "medium," "small," and "eco" - can be set as the initial value for the master volume value using the volume switch 280.

[0208] When the volume switch 280 is switched to "large", the master volume value is set to "10", when it is switched to "medium", the master volume value is set to "7", when it is switched to "small" or "eco", the master volume value is set to "4". When the volume switch 280 is set to "Eco," the performance lighting device 33 is turned off while the gaming machine 1 is in a customer waiting state, and the brightness of the image display unit 31 is set low when not in operation. When the volume switch SW 280 is operated while the gaming machine 1 is not energized, the host CPU 151 sets the master volume value according to the output value of the volume switch SW 280 at the time of starting up the gaming machine. The set master volume value is stored in the host RAM 152, for example.

[0209] In addition, when waiting for customers or when the special symbols change, the "master volume value (initial value)" set by the volume switch SW280 is adjusted between "1" and "10" using the volume adjustment button so that the volume suits the player's preference. If the initial value of the volume switch 280 is "ECO", the player may not be able to adjust the volume using the cross key 78. The master volume value adjusted using the volume adjustment button is stored in the host RAM 152, for example.

[0210] In the gaming machine of this embodiment, under the control of the sound control circuit 300, sound is output from the speaker at a volume based on the master volume value described above. Outputting sounds at an excessively loud volume from the sound output device 34 in a gaming machine installed in a gaming establishment can be a burden on the employees of the gaming establishment and the players. Such problems can be solved to a certain extent by appropriately setting the master volume value of the gaming machine 1 and keeping the output volume from the audio output device 34 below a certain level. However, if the output volumes of all ranges are uniformly lowered in order to reduce the overall output volume from the audio output device 34 in response to lowering the master volume value, sounds in specific ranges may become difficult to hear. As a result, the audio (performance sound) may become difficult to hear overall. Therefore, in order to make the sound (performance sound) easier to hear even when the output volume from the sound output device 34 is lowered overall, the gaming machine 1 corrects the volume balance using a coefficient that changes the volume for each range of sound according to the master volume value, resulting in an overall volume balance as shown in Figure 46.

[0211] FIG. 46 is a conceptual diagram illustrating the volume balance for each range in accordance with a change in the master volume value. This is merely a conceptual diagram, but it shows the percentage of each range's volume in the overall volume, which is indicated by the height of the bar graph. The overall volume of the gaming machine is the combined volume of all speakers equipped in the audio output device 34, namely, the upper left speaker SL0, the upper right speaker SR0, the lower left speaker SL1, the lower right speaker SR1, the subwoofer SSUB0, and the subwoofer SSUB1. In this embodiment, by appropriately balancing the volume of the sounds output from the speakers, it is possible to make sounds in a desired range easier to hear while suppressing the overall volume.

[0212] In the gaming machine 1, the volume of the mid-range is relatively lowered (its proportion to the overall volume is reduced) as the master volume value transitions from a high master volume value of "10" to a low master volume value of "1". Naturally, the volume of the treble and bass range sounds also decreases as the master volume value changes, but the "reduction range" of the mid-range volume is made larger than the "reduction range" of the treble and bass range volumes. The volume balance can be changed so that the volumes of the treble and bass ranges are relatively louder than the mid-range. Even at a low volume with a low master volume value that does not burden players or game arcade employees, the volume of high and low range sounds can be made relatively loud, making high and low range sounds easier to hear and audio (performance sounds) easier to hear.

[0213] The sound control circuit of the gaming machine 1 has the following configuration in order to achieve the volume balance as shown in FIG. FIG. 47 is a schematic diagram illustrating a sound control circuit provided in the gaming machine. As described above, the audio output device 34 includes the upper left speaker SL0, the upper right speaker SR0, the lower left speaker SL1, the lower right speaker SR1, the subwoofer SSUB0, and the subwoofer SSUB1. The flow of signals in the audio control circuit 300 will be described with reference to FIG. 47, the audio control circuit 300 includes an audio channel (track) 301. The audio control circuit 300 can input audio data read from the CGROM 154 or the above-mentioned sound source ROM to the audio channel 301 and perform processing such as volume control, muting, and fading.

[0214] The audio control circuit 300 includes, for example, 32 audio channels 301 (301-1 to 301-32), and simultaneously inputs and processes up to 32 pieces of audio data, and inputs audio signals to the respective output speakers. Therefore, audio based on the multiple pieces of audio data can be synthesized and output from each speaker. The audio channel 301 includes a first mixer circuit (MIXER1) 302 and a second mixer circuit (MIXER2) 303. The first mixer circuit 302 includes a mute circuit 302a that mutes the audio input to the audio channel 300, and a first volume (V1) circuit 302b that gives a volume value specific to the input audio. The specific volume value is the volume given to the audio data that is specified by the creator of the audio data.

[0215] The second mixer circuit 303 mainly includes a second volume (V2) circuit 303a, a third volume (V3) circuit 303b, and a fourth volume (V4) circuit 303c, which control fade in the audio channel 300. The audio signal output from the first volume circuit 302b and input to the second mixer circuit 303 is input to the second volume circuit 303a, the third volume circuit 303b, or the fourth volume circuit 303c depending on the output speaker set for the audio.

[0216] When audio is set to be output from either the upper left speaker, the upper right speaker, the lower left speaker, or the lower right speaker, the audio signal is branched as a signal directed to the upper speaker or the right speaker depending on the speaker to which it is output, and is further branched at each of the upper and lower sides to either the left or right speaker. The signal for the upper speaker is branched into signals for the upper left speaker SL0 and the upper right speaker SR0, and these are input to signal lines L0 and R0, respectively. The signal for the lower speaker is branched into a signal for the lower left speaker SL1 and a signal for the lower right speaker SR1, and these are input to a signal line L1 and a signal line R1, respectively. In the case of an audio set to be output from one of the subwoofers, the signals output from the third volume circuit V3 and the fourth volume circuit V4 are input to the signal line SUB0 or ​​the signal line SUB1 as signals for the subwoofers SSUB0 and SSUB1. All the audio channels 301 have the same configuration.

[0217] Signal lines L0, R0, L1, R1, SUB0, and SUB1 to which the audio channels 301 are connected are connected to a return mixer circuit 304. Signals from all of the audio channels 301 are input to the return mixer circuit 304 for each signal line (i.e., for each speaker) and mixed for each speaker. The signals from each speaker are input to a volume equalizer 310 . For reasons explained below, the volume equalizer 310 sets the overall output volume to a volume that corresponds to the master volume value, while changing the volume for each range (low range, mid range, low range) according to the master volume value, thereby adjusting the volume balance for each range. Such control is performed based on a control program executed by the processing core of the volume equalizer 310, and on preset parameters and a master volume value. The control program and parameters can be read from, for example, the integrated data ROM 92 when the system is started.

[0218] The volume equalizer 310 has, for example, two processing cores A and B. Core A receives signals from, for example, signal lines L0, R0, L1, and R1. Core A performs equalizer processing on the input signals. That is, core A determines coefficients for the signals based on the current master volume value and the parameter table so that the volume balance for each range of the sound output from each speaker is the desired balance. Core A applies the determined coefficients to the signals from signal lines L0, R0, L1, and R1, respectively, and outputs the applied signals to speakers SL0, SR1, SL1, and SR1.

[0219] Core B receives signals from, for example, signal lines L0, R0, SUB0, and SUB1. Core B performs equalizer processing on the input signals. That is, based on the current master volume value and the parameter table, core B determines a coefficient for each signal so that the volume balance for each range in the sound output from each speaker is the desired balance. Core B applies the determined coefficients to signal lines SUB0 and SUB1, and outputs the resulting signals to subwoofers SSUB0 and SSUB1. It is not necessary to have a plurality of processing cores, and equalizer processing may be performed by a single core. It is not necessary that all the signals from the signal lines L0, R0, L1, R1, SUB0, and SUB1 are the target of the equalizer. For example, the speaker SSUB1 may be used to notify the player by vibration caused by sound pressure, instead of outputting a performance sound (music) as a speaker. In that case, even if the signal from the signal line SUB1 is input to the volume equalizer 310, it is not necessary to adjust the volume balance for each range.

[0220] In the parameter table, a frequency band (range) in an audio signal and a coefficient to be multiplied by the signal can be stored in association with each master volume value. The correspondence between frequencies and coefficients can be stored for each audio signal (from signal line L0, signal line R0, signal line L1, signal line R1, signal line SUB0, signal line SUB1) for speakers SL0, SR0, SL0, SL1, SSUB0, SSUB1. Speakers have specifications that suit them best; some are better suited to producing low-frequency sounds, some to mid-frequency sounds, and some to high-frequency sounds. Therefore, since the same audio signal is input but sounds different, it is desirable to adjust the coefficient applied to the audio signal depending on the speaker. The parameters (T, F, Q) of EQ0 and EQ1, which will be described later, may be varied for each audio signal (target speaker) to vary the ranges of the low, mid, and high frequencies.

[0221] FIG. 48 is a diagram illustrating the change in volume for each range at each master volume value. Using Fig. 48, the settings of the volume equalizer for achieving the volume balance shown in Fig. 47 will be described. In Fig. 48, the range (frequency) is low on the left side, and the range (frequency) is high on the right side. The graph shows the volume for each frequency range from low to mid to high for each master volume for an audio signal based on the same audio data output from either signal line L0, signal line R0, signal line L1, or signal line R1. What is shown in FIG. 48 is the audio signal after the coefficients stored in the parameter table above have been applied, not the coefficients themselves.

[0222] The volume equalizer 310 controls the volume of the input signal from the return mixer circuit 304 based on two frequency bands (EQ0, EQ1). Generally, an equalizer is a device that increases or decreases the volume for each frequency band, and the volume equalizer 310 is the same. In the example shown in Fig. 48, the equalizer type (T) in EQ0 is LSF, and the signal of a frequency lower than a specific frequency is increased or decreased. Here, the specific frequency (F) is, for example, 300Hz, and Q, which sets the frequency width for adjusting the volume based on this specific frequency (F), is, for example, 0.7071. The gain (G), which is the adjustment value, is 12.0dB. The equalizer type (T) in EQ1 is PEQ, which increases or decreases the signal near a specific frequency. Here, the specific frequency (F) is 7.94 kHz, and the Q, which sets the frequency range for adjusting the volume based on this specific frequency band (F), is, for example, 0.4071.

[0223] The frequency band centered on the frequency (F) of 7.94 kHz in EQ1 corresponds to the "treble range" in this embodiment, and the frequency band lower than the frequency (F) of 300 Hz in EQ0 corresponds to the "bass range." Therefore, the "midrange" in this embodiment corresponds to the frequency band higher than the frequency band (F) of 300 Hz in EQ0 and lower than the lower limit of the frequency band centered on the frequency band (F) of 7.94 kHz in EQ1. The volume equalizer 310 can be adjusted to control the volume of high and low range sounds, as well as the volume of mid-range sounds. The volume equalizer 310 applies a coefficient to the signal so that the reduction in volume between the bass range defined by EQ1 and the treble range defined by EQ2 is smaller than the midrange range volume in response to the reduction in overall volume caused by lowering the master volume value.

[0224] FIG. 48(a) shows the case where the master volume value is "10." The volume when this master volume value is "10" is taken as the reference volume of 0 dB. Sound is output without applying any coefficient to the volume of the entire range. Figure 48(b) shows the case where the master volume value is "5". The volume is -7.5 dB lower than the volume of a master volume value of "10". As a result of adding gain with EQ0 and EQ1, the signal is multiplied with a coefficient so that there is almost no drop in volume from a master volume value of "10" in the low and high ranges, and in the mid range, the signal is multiplied with a coefficient so that the volume is reduced by a maximum of approximately -5 dB. Compared to Figure 48(a) where the master volume value is "10", the volume of the mid-range has decreased slightly, while there is no significant change in the volume of the low and high ranges. As a result, the low and high range sounds are easier to hear with the overall volume reduced by -7.5 dB.

[0225] Fig. 48(c) shows the case where the master volume value is "1". The volume is -15.0 dB lower than the volume based on a master volume value of "10". As a result of adding gain with EQ0 and EQ1, a coefficient is applied to the signal so that the volume is reduced by about -2 dB from the master volume value of "10" in the low and high ranges, and a coefficient is applied to the signal so that the volume is reduced by a maximum of about -12 dB in the mid-range. Compared to Figure 48(b) where the master volume value is "5", the volume of the mid-range has decreased significantly, while there is no significant change in the volume of the low and high ranges. As a result, with the overall volume reduced by -15.0 dB, low and high range sounds are easier to hear.

[0226] As described above, the volume equalizer 310 reduces the volume of the mid-range sounds by a larger amount, while reducing the volume reduction in the low and high range sounds, so that the overall volume corresponds to the master volume value. Even if the master volume value is set to "1," while the overall volume is lowered, the volume of high and low frequency sounds is less likely to decrease compared to the mid-frequency sounds, making it easier to hear the range of sounds you want to hear (high and low frequency sounds).

[0227] Note that the configuration for emphasizing high and low range sounds is just one example, and the parameters and coefficients of EQ0 and EQ1 may be set to emphasize either the high and mid ranges, the mid and low ranges, or the high, mid or low ranges. In the case shown in FIG. 48, no correction is made to change the volume balance at the master volume value "10", but correction to change the volume balance may be made for all master volume values ​​including "10".

[0228] Incidentally, the master volume value can be said to be a comprehensive volume setting value given to all of the multiple audio channels 301 included in the audio control circuit 300. On the other hand, the audio control circuit 300 can also give a sub-volume value that is a volume adjustment for the master volume value to the first volume circuit V1 included in each audio channel 301 (inputting a different volume value only to a specific audio channel). By providing different coefficients to the audio channel 301 depending on the master volume according to the speaker (signal line) to which the audio data is output, the volume balance for each range can be changed.

[0229] Furthermore, there are cases where you want to ensure the volume of a specific sound (loan sound, winning sound, hold change sound) relative to the volume of other sounds. For example, depending on the type of sound, it may be undesirable for the volume of a master volume value of "1" for the high and low ranges to be louder than the volume of a master volume value of "3" for a specific sound in the mid-range. A specific sound is not output at the same volume for all master volume values, but for a specific sound that you want to emphasize, a coefficient is set to adjust the reduction in volume of the specific sound so that the reduction in volume of the specific sound is smaller than the reduction in the master volume value. This adjustment may be performed only within a specific volume setting range.

[0230] As the image display device of the gaming machine 1, a liquid crystal display device, a rear projector, or any other arbitrary display device can be adopted. Furthermore, the display mode of the image display device of the present invention can be applied not only to pachinko machines, but also to slot machines and other amusement machines and game machines in general that have display devices. [Explanation of symbols]

[0231] 1 gaming machine, 10 gaming board, 13 first start port, 14 second start port, 31 image display unit, 34 sound output device, 35 performance pattern, 50 main control board, 50a main CPU, 50b main ROM, 50c main RAM, 71 performance control CPU, 73 performance control ROM, 74 performance control RAM, 77 FeRAM, 90 integrated ROM board, 95 performance control board

Claims

[Claim 1] A control unit, a first storage area, and a second storage area different from the first storage area, The control unit is A boot program is transferred from the first storage area, and the transferred boot program is executable; By executing the startup program, setting information can be transferred from the second storage area, and settings related to the control by the control unit are performed based on the transferred setting information. A gaming machine characterized by:

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