Multilayer ceramic capacitor

Abstract

To inhibit deterioration of moisture resistance of a multilayer ceramic capacitor.SOLUTION: A laminate 110 further includes extended dielectric body parts S1E and S2E that extend from at least one of a first side margin part S1 and a second side margin part S2 so as to cover only a part of an inner layer part C on at least one of a first end surface and a second end surface.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2019-110158 (Patent Document 1) is a prior art document that discloses the configuration of a multilayer ceramic capacitor. The multilayer ceramic capacitor described in Patent Document 1 includes a capacitance forming portion and a protective portion. The capacitance forming portion has a plurality of internal electrodes that are laminated in a first direction and whose end positions in a second direction perpendicular to the first direction are aligned to within 0.5 μm in the second direction. The protective portion covers the capacitance forming portion from the first and second directions. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-110158 A Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, multilayer ceramic capacitors have become smaller and larger in capacitance. As a result, the external dimensions of multilayer ceramic capacitors are becoming smaller, while the area occupied by the internal electrode layers relative to the external dimensions is becoming larger. As a result, the dielectrics sandwiching the stacked internal electrode layers from the sides become thinner, so that moisture that penetrates through the interfaces between the dielectrics and the external electrodes can easily reach the internal electrode layers, thereby reducing the moisture resistance of the multilayer ceramic capacitor.

[0005] The present invention has been made in consideration of the above problems, and an object of the present invention is to provide a multilayer ceramic capacitor in which the deterioration of moisture resistance is suppressed. [Means for solving the problem]

[0006] A multilayer ceramic capacitor according to the present invention includes a laminate, a first external electrode, and a second external electrode. The laminate includes a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked along a lamination direction. The laminate includes a first main surface and a second main surface opposing each other in the lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to both the lamination direction and the width direction. The first external electrode is provided on the first end surface. The second external electrode is provided on the second end surface. The multiple internal electrode layers include a first internal electrode layer connected to the first external electrode and a second internal electrode layer connected to the second external electrode. The laminate includes an inner layer portion, a first outer layer portion, a second outer layer portion, a first side margin portion, and a second side margin portion. In the inner layer portion, opposing portions of the first internal electrode layer and the second internal electrode layer that face each other are stacked in the stacking direction to have a capacitance. The first outer layer portion is located on the first main surface side of the inner layer portion in the stacking direction. The second outer layer portion is located on the second main surface side of the inner layer portion in the stacking direction. The first side margin portion is located on the first side surface side of the inner layer portion in the width direction. The second side margin portion is located on the second side surface side of the inner layer portion in the width direction. The laminate further includes an extended dielectric portion extending from at least one of the first side margin portion and the second side margin portion so as to cover only a portion of the inner layer portion at at least one of the first end face and the second end face. Effect of the Invention

[0007] According to the present invention, it is possible to suppress the deterioration of the moisture resistance of the multilayer ceramic capacitor. [Brief description of the drawings]

[0008] [Figure 1] 1 is a perspective view showing the appearance of a multilayer ceramic capacitor according to an embodiment of the present invention; [Diagram 2] 2 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1, taken along the line II-II. [Diagram 3]3 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1, taken along the line III-III. [Figure 4] 4 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1, taken along the line IV-IV. [Diagram 5] 3 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 2, as viewed from the direction of the VV line arrow. [Figure 6] 6 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 2, taken along the line VI-VI. [Figure 7] 10 is a schematic view showing a first attaching step of collectively attaching side ceramic green sheets to a first side surface of each of a plurality of laminate chips. FIG. [Figure 8] 10 is a schematic diagram showing a state in which a plurality of laminate chips are pressed collectively against a side ceramic green sheet. FIG. [Figure 9] 10 is a schematic diagram showing a state of a plurality of stacked chips after a first bonding step has been performed. FIG. [Figure 10] 13 is a schematic diagram showing a state of the plurality of laminate chips after a second bonding step has been performed in which side ceramic green sheets are collectively bonded to second side surfaces of each of the plurality of laminate chips. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, a multilayer ceramic capacitor according to an embodiment of the present invention will be described with reference to the drawings. In the following description of the embodiment, the same or corresponding parts in the drawings are designated by the same reference characters, and description thereof will not be repeated.

[0010] Fig. 1 is a perspective view showing the appearance of a multilayer ceramic capacitor according to one embodiment of the present invention. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 1, seen from the direction of the arrows along line II-II. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 1, seen from the direction of the arrows along line III-III. Fig. 4 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 1, seen from the direction of the arrows along line IV-IV. Fig. 5 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 2, seen from the direction of the arrows along line VV. Fig. 6 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 2, seen from the direction of the arrows along line VI-VI. Figs. 1 to 6 show a length direction L of the laminate, a width direction W of the laminate, and a lamination direction T of the laminate, which will be described later.

[0011] 1 to 6, a multilayer ceramic capacitor 100 according to one embodiment of the present invention includes a laminate 110, a first external electrode 120, and a second external electrode 130. The laminate 110 includes a plurality of dielectric layers 140 and a plurality of internal electrode layers 150 alternately laminated along a lamination direction T.

[0012] The laminate 110 includes a first main surface 111 and a second main surface 112 facing each other in a stacking direction T, a first side surface 113 and a second side surface 114 facing each other in a width direction W perpendicular to the stacking direction T, and a first end surface 115 and a second end surface 116 facing each other in a length direction L perpendicular to both the stacking direction T and the width direction W. The first external electrode 120 is provided on the first end surface 115. The second external electrode 130 is provided on the second end surface 116.

[0013] The multiple internal electrode layers 150 include multiple first internal electrode layers 151 connected to the first external electrode 120, and multiple second internal electrode layers 152 connected to the second external electrode 130. Although an example in which five each of the first internal electrode layers 151 and the second internal electrode layers 152 are provided is shown in Figs. 2 to 4, the number of each of the first internal electrode layers 151 and the second internal electrode layers 152 is not limited to five.

[0014] 5, the first internal electrode layer 151 includes a facing portion 151C facing the second internal electrode layer 152, and a lead portion 151X drawn to the first end surface 115. As shown in Fig. 6, the second internal electrode layer 152 includes a facing portion 152C facing the first internal electrode layer 151, and a lead portion 152X drawn to the second end surface 116.

[0015] As shown in FIGS. 2 to 6, the laminate 110 is partitioned into an inner layer portion C, a first outer layer portion X1, a second outer layer portion X2, a first side margin portion S1, a second side margin portion S2, a first end margin portion E1, and a second end margin portion E2.

[0016] The inner layer portion C has a capacitance due to the opposing portion 151C of the first internal electrode layer 151 and the opposing portion 152C of the second internal electrode layer 152 being stacked in the stacking direction T. The first outer layer portion X1 is located on the first main surface 111 side of the inner layer portion C in the stacking direction T. The second outer layer portion X2 is located on the second main surface 112 side of the inner layer portion C in the stacking direction T.

[0017] The first side margin S1 is located on the first side surface 113 side of the inner layer portion C in the width direction W. The second side margin S2 is located on the second side surface 114 side of the inner layer portion C in the width direction W. The first end margin E1 is located on the first end surface 115 side of the inner layer portion C in the length direction L. The second end margin E2 is located on the second end surface 116 side of the inner layer portion C in the length direction L.

[0018] It is preferable that the corners and ridges of the laminate 110 are rounded. Here, a corner is a portion where three faces of the laminate 110 intersect, and a ridge is a portion where two faces of the laminate 110 intersect.

[0019] The thickness of the dielectric layer 140 located in the inner layer portion C is preferably 0.4 μm or more and 0.8 μm or less. The thickness of the first outer layer portion X1 and the thickness of the second outer layer portion X2 are each preferably 10 μm or more and 30 μm or less. The thickness of the dielectric layer 140 located in the inner layer portion C, the thickness of the first outer layer portion X1, and the thickness of the second outer layer portion X2 are each a dimension at the center position in the width direction W of the laminate 110.

[0020] Each of the dielectric layers 140 is, for example, BaTiO 3 , CaTiO 3 , SrTiO 3 or CaZrO 3 Each of the plurality of dielectric layers 140 may contain, in addition to the above-mentioned main component, a subcomponent of at least one of a Si compound, an Mg compound, an Mn compound, an Fe compound, a Cr compound, an Ni compound, and a Co compound, the content of which is less than that of the main component.

[0021] The first side margin portion S1 and the second side margin portion S2 are made of a dielectric ceramic material mainly composed of a perovskite compound containing Ba and Ti. The first side margin portion S1 and the second side margin portion S2 may be made of the same dielectric ceramic material as the multiple dielectric layers 140, or may be made of a dielectric ceramic material different from that of the multiple dielectric layers 140.

[0022] The first side margin portion S1 and the second side margin portion S2 may contain at least one of Si and Mg. Also, the first side margin portion S1 and the second side margin portion S2 may contain Mn.

[0023] Each of the first internal electrode layer 151 and the second internal electrode layer 152 contains one metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au, or an alloy containing the metal. Each of the first internal electrode layer 151 and the second internal electrode layer 152 may further contain dielectric particles having the same composition as the ceramic contained in the dielectric layer 140. In addition, Sn may be present at the interface between each of the first internal electrode layer 151 and the second internal electrode layer 152 and the dielectric layer 140.

[0024] The thickness of each of the first internal electrode layer 151 and the second internal electrode layer 152 is preferably 0.4 μm or more and 0.8 μm or less. The number of the internal electrode layers 150 including the first internal electrode layer 151 and the second internal electrode layer 152 is preferably 90 sheets or more and 900 sheets or less.

[0025] Here, the thickness of each of the dielectric layer 140, the first internal electrode layer 151 and the second internal electrode layer 152 can be measured by the following method.

[0026] First, a surface defined by the stacking direction T and width direction W of the laminate 110, i.e., a surface perpendicular to the length direction L of the laminate 110, is exposed by grinding, and the exposed cross section is observed with a scanning electron microscope. Next, the thickness of the dielectric layer 140 is measured on a total of five lines, including a center line along the stacking direction T that passes through the center of the exposed cross section, and two lines drawn equally spaced on each side of the center line. The average of these five measured values ​​is defined as the thickness of the dielectric layer 140.

[0027] The thickness of each of the first internal electrode layer 151 and the second internal electrode layer 152 can also be measured using a scanning electron microscope in a manner similar to that used to measure the thickness of the dielectric layer 140, on the same cross section as the cross section in which the thickness of the dielectric layer 140 was measured.

[0028] The first external electrode 120 is formed over the entire first end face 115 of the laminate 110, and is formed so as to extend from the first end face 115 to the first main face 111, the second main face 112, the first side face 113, and the second side face 114. The first external electrode 120 is electrically connected to the first internal electrode layer 151.

[0029] The second external electrode 130 is formed over the entire second end face 116 of the laminate 110, and is formed so as to extend from the second end face 116 to the first main face 111, the second main face 112, the first side face 113, and the second side face 114. The second external electrode 130 is electrically connected to the second internal electrode layer 152.

[0030] The first external electrode 120 and the second external electrode 130 each include, for example, an underlying electrode layer and a plating layer disposed on the underlying electrode layer. The underlying electrode layer includes at least one layer selected from the group consisting of a baked electrode layer, a resin electrode layer, and a thin-film electrode layer.

[0031] The baked electrode layer is a layer containing glass and metal, and may be one layer or multiple layers. The baked electrode layer is composed of, for example, one metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au, or an alloy containing this metal, such as an alloy of Ag and Pd.

[0032] The baked electrode layer is formed by applying and baking a conductive paste containing glass and metal to the laminate 110. The baking may be performed simultaneously with the firing of the laminate 110, or may be performed after the firing of the laminate 110.

[0033] The resin electrode layer can be formed, for example, as a layer containing conductive particles and a thermosetting resin. When forming the resin electrode layer, the resin electrode layer may be formed directly on the laminate without forming a baked electrode layer. The resin electrode layer may be a single layer or multiple layers.

[0034] The thin-film electrode layer is, for example, a layer of 1 μm or less in thickness in which metal particles are deposited, and can be formed by a known thin-film formation method such as sputtering or vapor deposition.

[0035] The plating layer disposed on the base electrode layer is composed of, for example, one metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au, or an alloy containing this metal, such as an alloy of Ag and Pd. The plating layer may be a single layer or multiple layers. However, the plating layer is preferably a two-layer structure in which a Sn plating layer is formed on a Ni plating layer. The Ni plating layer has a function of preventing the base electrode layer from being eroded by solder when mounting the multilayer ceramic capacitor 100. The Sn plating layer has a function of improving the wettability of the solder when mounting the multilayer ceramic capacitor 100.

[0036] As shown in Fig. 3, at the center in the length direction L, the width of the multiple internal electrode layers 150 increases from the end in the stacking direction T toward the center. As shown in Fig. 4, even at the end in the length direction L, the width of the multiple internal electrode layers 150 increases from the end in the stacking direction T toward the center.

[0037] This change in width of the internal electrode layer 150 is due to the difference in thermal shrinkage rate during firing between each of the first outer layer portion X1 and the second outer layer portion X2 and the internal layer portion C. Specifically, the thermal shrinkage rate during firing of the internal layer portion C is smaller than that of each of the first outer layer portion X1 and the second outer layer portion X2, so that the width of the internal electrode layer 150 located at the center of the stacking direction T is wider than the width of the internal electrode layer 150 located at the end portion of the stacking direction T.

[0038] 3, in a cross section of the laminate 110 parallel to the stacking direction T and the width direction W at the center of the laminate 110 in the length direction L, the maximum deviation D in the width direction W of the multiple internal electrode layers 150 is 5 μm or less. Specifically, the maximum deviation D in the width direction W between the internal electrode layer 150 located closest to the first side surface 113 and the internal electrode layer 150 located closest to the second side surface 114 among the multiple internal electrode layers 150 is 5 μm or less.

[0039] As shown in Figures 4 to 6, the laminate 110 further includes an extended dielectric portion extending from at least one of the first side margin portion S1 and the second side margin portion S2 so as to cover only a portion of the inner layer portion C at at least one of the first end face 115 and the second end face 116.

[0040] Specifically, the extending dielectric portion S1E extends from the first side margin portion S1 so as to cover only a portion of the inner layer portion C on at least one of the first end face 115 and the second end face 116. The extending dielectric portion S2E extends from the second side margin portion S2 so as to cover only a portion of the inner layer portion C on at least one of the first end face 115 and the second end face 116.

[0041] In this embodiment, the extending dielectric portion S1E extends from the first side margin portion S1 so as to cover only a portion of the inner layer portion C at both the first end face 115 and the second end face 116. The extending dielectric portion S2E extends from the second side margin portion S2 so as to cover only a portion of the inner layer portion C at both the first end face 115 and the second end face 116. The shapes of the extending dielectric portion S1E and the extending dielectric portion S2E do not have to be symmetrical to each other.

[0042] The extended dielectric parts S1E and S2E are located at least in the center of the stacking direction T. As a result, the end of the internal electrode layer 150 in the width direction W located in the center of the stacking direction T is covered by the extended dielectric parts S1E and S2E. In this embodiment, the end of the internal electrode layer 150 in the width direction W located in a range of 30% to 70% near the center of the stacking direction T in the inner layer part C is covered by the extended dielectric parts S1E and S2E. The extended dielectric parts S1E and S2E can be confirmed by exposing a surface defined by the length direction L and width direction W of the laminate 110, i.e., a surface perpendicular to the stacking direction T of the laminate 110, by grinding and observing the exposed cross section. Alternatively, the extended dielectric parts S1E and S2E can be confirmed by grinding the multilayer ceramic capacitor 100 from the external electrode side toward the length direction L.

[0043] 4, the extended dielectric portions S1E, S2E extend into the inner layer portion C within a range not exceeding a line LV connecting an end portion in the width direction W of the internal electrode layer 150 arranged closest to the first principal surface 111 and an end portion in the width direction W of the internal electrode layer 150 arranged closest to the second principal surface 112. This makes it possible to prevent the connection between the first internal electrode layer 151 and the first external electrode 120, and the connection between the second internal electrode layer 152 and the second external electrode 130 from becoming insufficient.

[0044] At least one of Si and Mg is segregated in the portions of the multiple internal electrode layers 150 covered with the extended dielectric portions S1E, S2E in at least one of the first end face 115 and the second end face 116. In this embodiment, at least one of Si and Mg is segregated also in both ends in the width direction W of each of the multiple internal electrode layers 150. The segregation of Si and Mg can be confirmed, for example, by observing the cross section by SEM / EDX.

[0045] Since the insulating properties are improved in the portion where at least one of Si and Mg is segregated, even if the ends in the width direction W of the internal electrode layers 150 adjacent to each other in the stacking direction T are close to each other, the occurrence of a short circuit can be suppressed. As a result, the reliability of the multilayer ceramic capacitor 100 can be improved.

[0046] The dimension of the multilayer ceramic capacitor 100 in the length direction L is, for example, not less than 0.1 mm and not more than 1.0 mm. The dimension of the multilayer ceramic capacitor 100 in the lamination direction T is not less than 0.05 mm and not more than 0.5 mm. The dimension of the multilayer ceramic capacitor 100 in the width direction W is, for example, not less than 0.05 mm and not more than 0.5 mm. The above dimensions include tolerances.

[0047] A method for manufacturing the multilayer ceramic capacitor 100 according to this embodiment will now be described.

[0048] In the manufacturing method of the multilayer ceramic capacitor 100, first, a ceramic slurry containing ceramic powder, a binder, and a solvent is prepared. This ceramic slurry is formed into a sheet shape on a carrier film using a die coater, a gravure coater, a microgravure coater, or the like, to produce inner layer ceramic green sheets, outer layer ceramic green sheets, and side ceramic green sheets, which will be described later.

[0049] Each of the outer layer ceramic green sheets and the side ceramic green sheets may be made of the same material as the inner layer ceramic green sheets, or may be made of a material containing a component different from that of the inner layer ceramic green sheets. In this embodiment, at least one of Si and Mg is added when the side ceramic green sheets are prepared.

[0050] Next, a conductive paste is printed in a stripe pattern on the inner layer ceramic green sheets by screen printing, inkjet printing, gravure printing, etc. The conductive paste contains Ni powder, an organic solvent, a binder, etc.

[0051] A material sheet is prepared, in which a conductive pattern that becomes the internal electrode layer 150 is printed on the surface of a ceramic green sheet for an inner layer that becomes the dielectric layer 140 located in the inner layer portion C.

[0052] A plurality of material sheets and outer layer ceramic green sheets are laminated. Specifically, the plurality of material sheets are laminated such that the strip-shaped conductive patterns formed on the inner layer ceramic green sheets face in the same direction and are shifted by half a pitch in the width direction between adjacent material sheets. A plurality of outer layer ceramic green sheets are laminated on both sides of the laminated plurality of material sheets in the lamination direction.

[0053] The stacked outer layer ceramic green sheets and material sheets are thermocompression bonded to produce a mother block, which is then cut into a plurality of laminated chips using a cutting blade or the like.

[0054] FIG. 7 is a schematic view showing a first attaching step of collectively attaching side ceramic green sheets to the first side surfaces of each of a plurality of laminate chips.

[0055] As shown in FIG. 7, each of the multiple laminate chips 10 has a first main surface 11, a second main surface 12, a first side surface 13, a second side surface 14, a first end surface 15, and a second end surface 16. The first main surface 11 is a portion corresponding to the first main surface 111 of the laminate 110, and the second main surface 12 is a portion corresponding to the second main surface 112 of the laminate 110. The first side surface 13 is a portion corresponding to the first side surface 113 of the laminate 110, and the second side surface 14 is a portion corresponding to the second side surface 114 of the laminate 110. The first end surface 15 is a portion corresponding to the first end surface 115 of the laminate 110, and the second end surface 16 is a portion corresponding to the second end surface 116 of the laminate 110.

[0056] In the first attachment process in which side ceramic green sheets are collectively attached to the first side surface 13 of each of the multiple laminate chips 10, a side ceramic green sheet 20 that will become a first side margin portion S1 is attached to the first side surface 13 of each of the multiple laminate chips 10.

[0057] Specifically, as shown in FIG. 7, the support plate 32 is positioned so that the first side 13 of the multiple laminate chips 10 adhesively held by the expand sheet 31 faces downward, and the side ceramic green sheet 20 is positioned below the multiple laminate chips 10 so as to face the multiple laminate chips 10.

[0058] Here, the side ceramic green sheet 20 is placed in an expanded state on an elastic body 41, and the elastic body 41 is placed on a stage 42. Then, the support plate 32 is lowered in the direction of arrow E shown in FIG.

[0059] Fig. 8 is a schematic diagram showing a state in which a plurality of laminate chips are pressed collectively against a side ceramic green sheet. As shown in Fig. 8, a plurality of laminate chips 10 are pressed collectively against a side ceramic green sheet 20. At this time, each of the plurality of laminate chips 10 is pressed against the side ceramic green sheet 20 with such a pressing force that the elastic body 41 in the portion in contact with the plurality of laminate chips 10 via the side ceramic green sheet 20 is elastically deformed in the vicinity thereof.

[0060] As a result, the side ceramic green sheet 20 in the portion sandwiched between the multiple laminate chips 10 and the elastic body 41 is pressed against the first side surfaces 13 of the multiple laminate chips 10, respectively, and a shear force acts on the side ceramic green sheet 20 at the edges of the first side surfaces 13 of the multiple laminate chips 10, thereby punching out the side ceramic green sheet 20.

[0061] The physical properties of the side ceramic green sheet 20 are adjusted so that the shear force generated by the corners of the first side surface 13 is stronger than the shear force generated by the ridges of the first side surface 13. For example, an additive that increases the viscosity of the side ceramic green sheet 20 is added, so that burrs are generated in the portions sheared by the ridges, where the shear force is weaker than that of the corners. As a result, burrs 23 that become extended dielectric portions are generated in the portions of the side ceramic green sheet 20 sheared by the ridges of the first side surface 13.

[0062] That is, the side ceramic green sheet 20 is divided into punched portions 21 which are punched out by each of the multiple laminate chips 10 to become side margins, burr portions 23 extending from the center portions of the edges of the punched portions 21, and remaining portions 22 after punching. After that, the support plate 32 is raised.

[0063] Fig. 9 is a schematic diagram showing the state of the multiple laminate chips after the first attachment step has been performed. As shown in Fig. 9, the first side surface 13 of each of the multiple laminate chips 10 adhesively held by the expand sheet 31 is covered by the punched portion 21. Furthermore, the portions of the first end surface 15 and the second end surface 16 near the first side surface 13 are covered by the burr portion 23.

[0064] In addition, when attaching the side ceramic green sheet 20 to the multiple laminate chips 10, an adhesive (not shown) may be applied in advance to at least one of the first side surface 13 of the multiple laminate chips 10 and the main surface of the side ceramic green sheet, if necessary. Examples of adhesives that can be used here include those containing various resin components as the main component, those in which the resin components are dissolved in a solvent, and pastes in which ceramic particles are dispersed. In addition, the method of applying the adhesive is not particularly limited, and various methods can be used.

[0065] Next, a second attachment step is performed in which side ceramic green sheets 20 are collectively attached to the second side surface 14 of each of the multiple laminate chips 10. Fig. 10 is a schematic diagram showing the state of the multiple laminate chips after the second attachment step is performed in which side ceramic green sheets are collectively attached to the second side surface of each of the multiple laminate chips.

[0066] The second bonding process in which the side ceramic green sheets 20 are bonded collectively to the second side surface 14 of each of the multiple laminate chips 10 is similar to the first bonding process in which the side ceramic green sheets 20 are bonded collectively to the first side surface 13 of each of the multiple laminate chips 10 described above, in that the side ceramic green sheets 20, which will become the second side margin portion S2, are bonded collectively to the second side surface 14 of each of the multiple laminate chips 10 after the side ceramic green sheets 20 have been bonded to the first side surface 13, and therefore will not be described here.

[0067] 10, the side ceramic green sheet 20 (more precisely, the punched portion 21 of the side ceramic green sheet 20) is attached to each of the second side surfaces 14 of the multiple laminate chips 10 while the multiple laminate chips 10 are adhesively held by the expand sheet 31. Furthermore, the portions of the first end surface 15 and the second end surface 16 near the second side surface 14 are covered with the burrs 23.

[0068] The laminate chip 10 with the side ceramic green sheets 20 attached thereto is heated to sinter the ceramic material, and then barrel polished to form the laminate 110.

[0069] A conductive paste is applied to each of the first end surface 115 and the second end surface 116 of the laminate 110 to form a metal layer, the formed metal layer is subjected to a baking process, and then Ni plating and Sn plating are applied in sequence on the baked metal layer to form the first external electrode 120 and the second external electrode 130.

[0070] Through the series of steps described above, the multilayer ceramic capacitor 100 in accordance with this embodiment can be manufactured.

[0071] In the multilayer ceramic capacitor 100 according to this embodiment, the multilayer body 110 further includes extended dielectric portions S1E, S2E extending from at least one of the first side margin portion S1 and the second side margin portion S2 so as to cover only a part of the inner layer portion C on at least one of the first end face 115 and the second end face 116. This lengthens the shortest path that moisture that has infiltrated from the interfaces between the first side margin portion S1 and the second side margin portion S2, which are dielectrics sandwiching the multiple internal electrode layers 150 from the sides, and the first external electrode 120 and the second external electrode 130, takes to reach the internal electrode layer 150, thereby suppressing a decrease in the moisture resistance of the multilayer ceramic capacitor 100.

[0072] In the multilayer ceramic capacitor 100 according to this embodiment, the maximum deviation in the width direction W of the multiple internal electrode layers 150 is 5 μm or less. This ensures a wide space between the opposing portions 151C of the first internal electrode layer 151 and the opposing portions 152C of the second internal electrode layer 152, thereby increasing the capacitance.

[0073] In the multilayer ceramic capacitor 100 according to this embodiment, at the ends in the length direction L, the widths of the multiple internal electrode layers 150 become wider from the ends toward the center in the stacking direction T. This lengthens the shortest path that moisture that has infiltrated from the interfaces between the first side margin portion S1 and the second side margin portion S2 and the first external electrode 120 and the second external electrode 130 takes to reach the internal electrode layer 150 located at the ends in the stacking direction T, thereby suppressing a decrease in the moisture resistance of the multilayer ceramic capacitor 100.

[0074] In the multilayer ceramic capacitor 100 according to this embodiment, the extended dielectric portions S1E, S2E are located at least in the center in the stacking direction T. This makes it possible to lengthen the shortest path that moisture that has infiltrated from the interfaces between the first and second side margin portions S1, S2 and the first and second external electrodes 120, 130 travels to reach the wide internal electrode layer 150 located in the center in the stacking direction T, thereby suppressing a decrease in the moisture resistance of the multilayer ceramic capacitor 100.

[0075] In the multilayer ceramic capacitor 100 according to this embodiment, at least one of Si and Mg is segregated in the portions of the internal electrode layers 150 that are covered with the extended dielectric portions S1E, S2E in at least one of the first end face 115 and the second end face 116. As a result, if the portions covered with the extended dielectric portions S1E, S2E at the ends in the width direction W of the internal electrode layers 150 adjacent to each other in the stacking direction T are close to each other, the portions where at least one of Si and Mg is segregated have improved insulation, so that it is possible to suppress the occurrence of a short circuit due to contact between the ends. As a result, it is possible to improve the reliability of the multilayer ceramic capacitor 100.

[0076] (Additional Note) It will be appreciated by those skilled in the art that the exemplary embodiments described above are examples of the following aspects.

[0077] <1> a laminate including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked along a stacking direction, the laminate including a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to both the stacking direction and the width direction; a first external electrode provided on the first end surface; a second external electrode provided on the second end surface, the plurality of internal electrode layers include a first internal electrode layer connected to the first external electrode and a second internal electrode layer connected to the second external electrode, the laminate includes an inner layer portion having a capacitance in which opposing portions of the first internal electrode layer and the second internal electrode layer are stacked in the stacking direction, a first outer layer portion located on a first main surface side of the inner layer portion in the stacking direction, a second outer layer portion located on a second main surface side of the inner layer portion in the stacking direction, a first side margin portion located on a first side surface side of the inner layer portion in the width direction, and a second side margin portion located on a second side surface side of the inner layer portion in the width direction, The laminate further includes an extended dielectric portion extending from at least one of a first side margin portion and a second side margin portion so as to cover only a portion of the inner layer portion at at least one of the first end face and the second end face.

[0078] <2> The maximum deviation in the width direction of the plurality of internal electrode layers is 5 μm or less. <1> The multilayer ceramic capacitor according to claim 1 .

[0079] <3> At the end portions in the length direction, the widths of the plurality of internal electrode layers become wider from the end portions toward the center portion in the stacking direction. <1> or <2> The multilayer ceramic capacitor according to claim 1 .

[0080] <4> The extended dielectric portion is located at least in the center in the stacking direction. <3> The multilayer ceramic capacitor according to claim 1 .

[0081] <5> At least one of Si and Mg is segregated in a portion of the plurality of internal electrode layers that is covered with the extended dielectric portion in at least one of the first end face and the second end face. <1> from <4> 13. The multilayer ceramic capacitor according to claim 12,

[0082] In the above description of the embodiments, configurations that can be combined may be combined with each other.

[0083] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present invention is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0084] 10 laminated chip, 11,111 first main surface, 12,112 second main surface, 13,113 first side surface, 14,114 second side surface, 15,115 first end surface, 16,116 second end surface, 20 side ceramic green sheet, 21 punched portion, 22 remaining portion, 23 burr portion, 31 expanded sheet, 32 support plate, 41 elastic body, 42 stage, 100 laminated ceramic capacitor, 110 laminate, 120 first external electrode, 130 second external electrode, 140 dielectric layer, 150 internal electrode layer, 151 first internal electrode layer, 151C,152C facing portion, 151X,152X lead portion, 152 second internal electrode layer, C internal layer portion, D maximum displacement amount, E1 first end margin portion, E2 Second end margin portion, L length direction, S1 first side margin portion, S1E, S2E extended dielectric portion, S2 second side margin portion, T stacking direction, W width direction, X1 first outer layer portion, X2 second outer layer portion.

Claims

1. a laminate including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked along a stacking direction, the laminate including a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to both the stacking direction and the width direction; a first external electrode provided on the first end surface; a second external electrode provided on the second end surface, the plurality of internal electrode layers include a first internal electrode layer connected to the first external electrode and a second internal electrode layer connected to the second external electrode, the laminate includes an inner layer portion having a capacitance formed by stacking mutually opposing opposing portions of the first internal electrode layer and the second internal electrode layer in the stacking direction, a first outer layer portion located on a first main surface side of the inner layer portion in the stacking direction, a second outer layer portion located on a second main surface side of the inner layer portion in the stacking direction, a first side margin portion located on a first side surface side of the inner layer portion in the width direction, and a second side margin portion located on a second side surface side of the inner layer portion in the width direction, the laminate further includes an extended dielectric portion extending from at least one of the first side margin portion and the second side margin portion so as to cover only a portion of the inner layer portion at at least one of the first end face and the second end face.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein a maximum amount of deviation in the width direction among the plurality of internal electrode layers is 5 μm or less.

3. 3. The multilayer ceramic capacitor according to claim 1, wherein at ends in the length direction, widths of the plurality of internal electrode layers increase from the ends toward a center in the stacking direction.

4. 4. The multilayer ceramic capacitor according to claim 3, wherein the extended dielectric portion is located at least in a central portion in the lamination direction.

5. 2. The multilayer ceramic capacitor according to claim 1, wherein at least one of Si and Mg is segregated in a portion of the plurality of internal electrode layers that is covered by the extended dielectric portion in at least one of the first end face and the second end face.

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