Contraction header signal information examination system and method

Abstract

To provide a method for facilitating effective and efficient soft mounting of an examination order of a different type in an examination system, and provide a signal processing examination system.SOLUTION: A signal processing examination method comprises the steps of: selecting a signal processing mode among a header conclusion mode, a contraction header training mode, and a contraction header mode; executing signal processing information determination processing in accordance with a selection result of the signal processing mode; and executing modulation / demodulation related processing in accordance with a result of the signal processing information determination processing. In the contraction header mode, processing is executed to a communication signal. Header information cannot be easily used at first in the communication signal itself. Demodulation parameter information is advantageously derived / developed / inserted from the other information in the communication signal.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] [Related Applications] This application claims the benefit of and priority to Provisional Application No. 63 / 512,605, entitled "TECHNIQUES FOR HEADERLESS DEMODULATION OF A SIGNAL," filed July 7, 2023 (Attorney Docket No. ATSY-0138-00.00US), which is incorporated herein by reference in its entirety.

[0002] TECHNICAL FIELD Embodiments of the present disclosure relate to the fields of signal processing and electronic testing. [Background technology]

[0003] Electronic systems and devices have contributed greatly towards the development of modern society and have facilitated increased productivity and reduced costs in the analysis and communication of information in a variety of business, scientific, educational and entertainment applications. New communication devices and protocols have been implemented to address the ever-increasing demand to communicate more information. Proper transmission and processing (e.g., modulation, demodulation, etc.) of signals that carry information is essential for accurate information communication between electronic devices. As larger amounts of information are communicated and new communication protocols are developed, more time and resources are required to test the ability of components to properly participate in information communication, making test systems and the overall test operation less productive and more costly.

[0004] Also, as communication components and protocols evolve and change, testing to ensure accurate signal transmission and processing tends to become complex and problematic. Addressing changing communication protocol requirements in a traditional manner often leads to more complex test patterns (e.g., individually, larger patterns, collectively, more of these patterns are required, etc.), resulting in undesirable increases in test time. To address the increasing amount of information and new communication protocol requirements, more electronic resources associated with testing (e.g., test scan chain components, wave generation components, additional information storage capacity, etc.) are also traditionally required. However, memory space and other resources in integrated circuits are typically limited, which results in a concentration of resource allocations toward normal operations (e.g., mission mode operations, non-test operations, end use operations, etc.) and functions. However, allocating and dedicating this limited space to test resources for relatively infrequent test operations tends to be costly, inefficient, and / or an undesirable allocation of resources. It is traditionally impractical and / or impossible to provide adequate time and resources to adequately test an implementation of a new communications protocol within a device under test (DUT), such as by an automatic test system (ATE). Summary of the Invention

[0005] The presented embodiments of the present disclosure facilitate flexible implementation of different types of test procedures in a test system. The embodiments described herein enable efficient and effective component-based testing of communication systems and methods that have limited resources to support the components. In fact, the embodiments of the present disclosure enable communication devices to be fully tested without adding additional electronic resources that are not required by the communication device for normal operation, thereby providing cost savings for device manufacturers.

[0006] In some embodiments, a reduced header communication signal processing test method comprises: performing an autocorrelation of a cyclic prefix in a signal, the signal being configured according to a communication protocol; identifying start timings of symbols in the signal based on results of the autocorrelation, the symbols being defined by the communication protocol and including Orthogonal Frequency Division Modulation (OFDM) symbols. The method further comprises: determining an initial coarse frequency error correction based on results of the autocorrelation; setting a set of bins for the signal, the set of bins including pilot bins and data bins, further wherein the set of bins corresponds to a set of subcarriers associated with the signal, the pilot bins including corresponding pilot subcarriers in the set of subcarriers, and the data bins corresponding to data subcarriers in the set of subcarriers. The method further comprises extracting identities of the pilot bins according to a definition of the pilot subcarriers defined by the communication protocol; setting ideal constellation values ​​and ideal symbol values ​​for the pilot bins and the data bins; and determining other demodulation parameter values ​​based on results of the ideal constellation values ​​and ideal symbol values ​​for the pilot bins and the data bins.

[0007] In another embodiment, a signal processing test system includes a load board configured to couple to a plurality of devices under test (DUTs); a controller configured to direct testing of the plurality of DUTs, the controller having a test mode selection module operable to select between a plurality of test modes, where one of the plurality of test modes is associated with reduced header communication signal test processing applied to a signal; and test electronics configured to test the plurality of DUTs under control of the controller. The test electronics are coupled to the load board, the test electronics having a demodulation information determination module operable to gather information associated with a demodulation operation, where the demodulation operation includes determining signal processing information based on information in a payload portion of the signal; and a demodulation module operable to perform a demodulation operation based on information received from the demodulation information determination module.

[0008] In another embodiment, a signal processing test method includes the steps of selecting a signal processing mode among a header including mode, a reduced header training mode, and a reduced header mode; performing a signal processing information decision process according to a result of the signal processing mode selection step; and performing a modulation / demodulation related process according to a result of the signal processing information decision process. [Brief description of the drawings]

[0009] The accompanying drawings, which are incorporated in and form a part of this specification, are included for illustrative purposes of the principles of the disclosure and are not intended to limit the disclosure to the specific implementations shown in the drawings. The drawings are not drawn to scale unless specifically indicated otherwise.

[0010] [Figure 1A] FIG. 1 is a block diagram of an exemplary testing environment or system according to an embodiment of the present disclosure.

[0011] [Figure 1B]1 is a block diagram of an exemplary radio frequency (RF) integrated circuit device or DUT in accordance with an embodiment of the present disclosure.

[0012] [Figure 1C] FIG. 1 is a block diagram of an exemplary testing environment or system according to an embodiment of the present disclosure.

[0013] [Figure 2A] FIG. 2 is a block diagram of an example DUT in accordance with an embodiment of the present disclosure.

[0014] [Figure 2B] FIG. 1 is a block diagram of an exemplary automatic test system (ATE) in accordance with an embodiment of the present disclosure.

[0015] [Figure 3A] 4 is a flowchart of an exemplary multi-mode modulation / demodulation parameter determination method including novel reduced header processing, in accordance with an embodiment of the present disclosure.

[0016] [Figure 3B] 1 is a block diagram of an exemplary multi-mode modulation / demodulation parameter determination system according to an embodiment of the present disclosure.

[0017] [Figure 4A] 1 is a block diagram of an example PDU communication frame or packet according to an embodiment of the present disclosure.

[0018] [Figure 4B] 1 is a block diagram of an example PDU communication frame or packet at different communication protocol / model layers according to an embodiment of the present disclosure.

[0019] [Figure 4C] 1 includes various exemplary data packets including organization and configuration of information within a PPDU, according to embodiments of the present disclosure.

[0020] [Figure 4D]1A-1C are data packet diagrams including various example organizations and configurations of information ("packets") according to embodiments of the present disclosure.

[0021] [Figure 4E] 1 is a block diagram of different exemplary signal physical layer protocol data unit (PPDU) organizations / configurations for each IEEE 802.11-based wireless network protocol / standard, according to an embodiment of the present disclosure.

[0022] [Figure 5A] FIG. 2 is a block diagram of an example signal configuration according to an embodiment of the present disclosure.

[0023] [Figure 5B] FIG. 2 is a block diagram of an example frequency spectrum of subcarriers and corresponding bins according to an embodiment of the present disclosure.

[0024] [Figure 5C] FIG. 2 is a graphical block diagram of an example transmission scheme of OFDM symbol tones / signals according to an embodiment of the present disclosure.

[0025] [Figure 5D] 1 is a block diagram of an example OFDM symbol payload portion transmission with reduced header information according to an embodiment of the present disclosure.

[0026] [Figure 5E] 5A-5C are block diagrams of various example subcarrier configuration allocations according to embodiments of the present disclosure.

[0027] [Figure 6A] 1 is a block diagram of several example constellation maps associated with signal communication, according to an embodiment of the present disclosure.

[0028] [Figure 6B] 1 is a block diagram of several example constellation map errors associated with signal communication, according to an embodiment of the present disclosure.

[0029] [Figure 7] 4 is a logic flow diagram of an exemplary test mode selection process according to an embodiment of the present disclosure.

[0030] [Figure 8] FIG. 4 is a block diagram of an example reduced header mode test process according to an embodiment of the present disclosure.

[0031] [Figure 9A] 1 is a block diagram of an exemplary autocorrelation graph result according to an embodiment of the present disclosure.

[0032] [Figure 9B] FIG. 2 is a block diagram of an example autocorrelation process according to an embodiment of the present disclosure.

[0033] [Figure 10] 4 is a flowchart of an exemplary equalizer value determination process according to an embodiment of the present disclosure.

[0034] [Figure 11A] 4 is a flow chart of an exemplary ideal pilot tone determination process according to an embodiment of the present disclosure.

[0035] [Figure 11B] 11 is a graph of an example simulated channel response in the presence of a signal with a full header or a signal with a non-blind known stimulus, in accordance with an embodiment of the present disclosure.

[0036] [Figure 11C] 11 is a graph illustrating the location of several example pilot bin frequency responses according to an embodiment of the present disclosure.

[0037] [Figure 12A] 1 is a flowchart of an exemplary interpolation process including iterative updating / re-determination of equalization values ​​within a bin, in accordance with an embodiment of the present disclosure.

[0038] [Figure 12B] 11 is an example graph of the results of an interpolation process including iterative updating / re-determination of equalization values ​​within a bin, according to an embodiment of the present disclosure.

[0039] [Figure 12C] 1 is a flowchart of an exemplary interpolation process including iterative updating / re-determination of equalization values ​​within a bin, in accordance with an embodiment of the present disclosure. [Figure 12D] 1 is a flowchart of an exemplary interpolation process including iterative updating / re-determination of equalization values ​​within a bin, in accordance with an embodiment of the present disclosure.

[0040] [Figure 12E] FIG. 12 is a block diagram of an example subcarrier bin configuration 1291 according to an embodiment of the present disclosure.

[0041] [Figure 12F] 1 is a block diagram of an exemplary signal information processing operation according to an embodiment of the present disclosure.

[0042] [Figure 12G] 1 is a block diagram of an exemplary signal information processing operation according to an embodiment of the present disclosure.

[0043] [Figure 12H] 1 is a block diagram of an exemplary signal information processing operation according to an embodiment of the present disclosure.

[0044] [Figure 12I] FIG. 12 is a block diagram of an equalizer value list 1293 associated with bins of OFDM values ​​within a burst or frame.

[0045] [Figure 12J] 15 is a flow chart of an average equalizer process 1500 according to some embodiments of the present disclosure.

[0046] [Figure 13A]1 is an example graph of a frequency response of a bandwidth including multiple bins / subcarriers, according to an embodiment of the present disclosure.

[0047] [Figure 13B] 1 is an example graph of a frequency response of a bandwidth including multiple bins / subcarriers, according to an embodiment of the present disclosure.

[0048] [Figure 14A] 4 is a flowchart of an exemplary enhanced equalizer process according to an embodiment of the present disclosure.

[0049] [Figure 14B] 1 is a block diagram of some example signal information processing operations according to embodiments of the present disclosure.

[0050] [Figure 15] 11 is a flow chart of an exemplary current data bin label reassignment process according to an embodiment of the present disclosure.

[0051] [Figure 16] 11 is a flow chart of an example reduced-header reference signal training mode testing process according to an embodiment of the present disclosure.

[0052] [Figure 17] FIG. 1 is a block diagram of an example 802.11ax 20 MHz ideal waveform in accordance with an embodiment of the present disclosure.

[0053] [Figure 18] 1 is a graph of an exemplary payload-only ideal IQ waveform when the input parameter HeaderlessDemod is set to a training mode (eg, HeaderlessDemodTraining and Execute, etc.) in accordance with an embodiment of the present disclosure.

[0054] [Figure 19] 4 is a graph of an exemplary extracted payload-only ideal signal in accordance with an embodiment of the present disclosure.

[0055] [Figure 20] 4 is a graph of a demodulated payload-only signal according to an embodiment of the present disclosure.

[0056] [Figure 21] 11 is a flow chart of an exemplary header mode test process according to an embodiment of the present disclosure.

[0057] [Figure 22] FIG. 1 is a block diagram of an exemplary electronic system that may be used as a platform for implementing and controlling methods according to embodiments of the present disclosure.

[0058] [Figure 23] 23 is a block diagram of an exemplary algorithmic reduced header processing module 2300, in accordance with an embodiment of the present disclosure.

[0059] [Figure 24] FIG. 2 is a block diagram of an example algorithmic interpolation module according to an embodiment of the present disclosure.

[0060] [Diagram 25] 1 is an extension of the exemplary algorithms Enhanced Equalizer and Reassignment modules.

[0061] [Figure 26] FIG. 2 is a block diagram of an exemplary algorithmic training module processing module according to an embodiment of the present disclosure.

[0062] [Figure 27] FIG. 2 is a block diagram of an exemplary algorithm pilot bin ideal value module, in accordance with an embodiment of the present disclosure.

[0063] [Figure 28] FIG. 2 is a block diagram of an exemplary algorithmic iterative interpolation module, in accordance with an embodiment of the present disclosure.

[0064] [Figure 29] FIG. 2 is a block diagram of an exemplary testing method according to an embodiment of the present disclosure.

[0065] [Diagram 30] FIG. 4 is a block diagram of an example reduced header mode test process according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0066] Reference will now be made in detail to preferred embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. While the present disclosure will be described in conjunction with the preferred embodiments, it will be understood that this is not intended to limit the present disclosure to these embodiments. On the contrary, the present disclosure is intended to encompass alternatives, modifications, and equivalents that may be included within the spirit and scope of the present disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present disclosure.

[0067] The presented systems and methods include efficient and effective approaches for handling modulation / demodulation in various scenarios, including situations where it would otherwise be difficult to properly handle signal modulation / demodulation (e.g., due to limited capabilities / resources in a device, economical, etc.). In some embodiments, a communication signal is demodulated without relying on some demodulation parameters contained within the signal that would otherwise be utilized in conventional approaches. In some exemplary implementations, a "reduced header information demodulation decision" process is performed on a communication signal in which header information (e.g., preamble information, channel estimation related information, reference information, etc.) is not initially readily available in the communication signal itself, and demodulation parameter information is advantageously derived / developed / extrapolated from other information in the communication signal. By reducing the header size, a device under test (DUT) with limited resources is efficiently tested, thereby reducing the cost and complexity of testing.

[0068] In view of the above, embodiments of the present disclosure enable efficient and effective signal processing component testing. In some embodiments, a "reduced header information demodulation" process is performed by an automatic test equipment (ATE) system in response to a signal being transmitted to or by a device under test (DUT). This process is performed within the test environment on a payload portion of information for which demodulation parameter information would normally be included within other parts of a communication protocol. The demodulation parameter information would not otherwise be readily available to the DUT. Results of up-converting and down-converting the signal within the DUT are captured and conveyed to the ATE for post-processing according to the "reduced header information demodulation" process. In some exemplary implementations, the reduced header information demodulation process is implemented by a computer algorithm running on a workstation associated with the ATE. The payload portion is communicated in compliance with the payload specification of a communication protocol, and information and data related to demodulation parameters specified by other parts of the protocol are not included within the signal. In some exemplary implementations, the signal specifically includes less header / preamble information associated with the communication protocol than would otherwise be included within the signal.

[0069] 1A is a block diagram of an exemplary test environment or test system 100A according to an embodiment of the present disclosure. The test system 100A is included in some embodiments of a signal processing test system. The test environment or test system 100A includes an automatic test equipment (ATE) 110A and a device under test (DUT) (e.g., 120A, 130A, etc.). The ATE 110A includes a controller 111A, test electronics 114A, a test or load board 119A, and a user interface (not shown). In some embodiments, the controller 111A is configured to direct testing of multiple DUTs (e.g., DUTs 120A, 130A, etc.). The test electronics 114A is configured to test multiple DUTs. The controller 111A is coupled to the test electronics 114A and the test or load board 119A. The load board 119A is configured to communicatively couple to the test electronics 114A and a number of devices under test (eg, DUT 120A, DUT 130A, etc.).

[0070] In some example implementations, the controller 111A includes a test mode selection module 112A. The test mode selection module selects between 1) reduced header signal processing test mode processing, 2) reduced header with reference signal training mode test processing, and 3) header test mode processing. Additional characteristics / features and operations of these modes are presented elsewhere herein. The test electronics 114A is communicatively coupled to the controller 111A. It is understood that various factors may be utilized in making the mode selection. For example, some portions of the testing of the DUT are performed in one mode, and other portions of the testing of the DUT are performed in another mode. In some embodiments, for one burst (e.g., a burst with few OFDM symbols in the payload, etc.), the header test mode is selected, and for another burst (e.g., a burst with many OFDM symbols in the payload, etc.), the reduced header signal processing test mode is selected.

[0071] The test electronics 114A includes a demodulation information determination module 115A and a demodulation module 117A communicatively coupled to each other. The demodulation information determination module 115A collects information associated with demodulation operations, including determining signal processing information not otherwise included in the reduced header information. The demodulation module 117A performs demodulation operations based on information received from the demodulation information determination module 115A. In some embodiments, the test electronics 114A directs testing of the DUTs and includes resources assigned to each DUT. In some implementations, the test electronics 114A may include a field programmable gate array (FPGA). Additional characteristics / features and operations of the test mode selection module 112A and the demodulation information determination module 115A are presented elsewhere herein.

[0072] In some embodiments, the test mode selection module 112A selects a reduced header signal processing test operation, and the demodulation information determination module 115A determines signal processing information associated with the demodulation operation, where the signal processing information is not otherwise included within the header portion of the signal associated with the demodulation operation.

[0073] Various information associated with testing the DUT (e.g., test mode selection, test results, preliminary analysis results, reconfiguration test information, test instructions, etc.) is communicated between the test equipment 110A and a user test interface. In some example implementations, the user test interface includes a processing unit, a memory, and user input / output components (e.g., a display, a keyboard, etc.). The memory can store test-related information, the processing unit can process the information, and the user input / output components can communicate information to and from a user.

[0074] In some embodiments, the DUTs (e.g., 120A, 130A, etc.) are considered signal processing components. The DUT 120A may be configured for final implementation in an end-use device 190A. In some embodiments, the DUT 120A is configured for final end-use implementation in a communications device or system (e.g., a mobile phone, an Internet of Things (IoT) device, or a device conforming to the Institute of Electronics and Electrical Engineers (IEEE) 802.11 wireless networking protocol / standard, etc.). The device 190A includes a transceiver 191A, a signal processing core 192A, a processor / microcontroller 193A, a memory storage 195A (e.g., ROM / RAM, etc.) and an I / O interface 194A (e.g., digital interface pins, etc.). The signal processing core 192A includes an analog signal processing component 172A, a baseband component 172A, a register 173A, and a cache 174A. When integrated within device 190A, DUT 120A may have access to other resources and functionality (e.g., memory / storage 195, processor / microcontroller 193A, etc.), but these resources are typically not available to DUT 120A during testing before DUT 120A is integrated within device 190A.

[0075] The DUT 120A is primarily associated with performing analog operations. In some exemplary implementations, the DUT 120 is a radio frequency (RF) integrated circuit chip. In some embodiments, the DUT 120A is associated with performing communications operations. The DUT 120A may be configured to perform transceiver operations, analog signal processing, and the like.

[0076] In some embodiments, the DUT is an RF component that performs various aspects of communication signal transmission and reception operations (including performing up-conversion and down-conversion operations on the signals). In a transmission activity, modulated information (e.g., in the form of modulated signals, I and Q signals, etc.) is combined and up-converted to an RF signal by multiplying a carrier frequency generated by a local oscillator by a baseband modulated signal. In a transmission activity, modulated information (e.g., in the form of modulated signals, I and Q signals, etc.) is combined and up-converted to an RF signal by multiplying a carrier frequency generated by a local oscillator by a baseband modulated signal. It is understood that the DUT may have various interface configurations (e.g., analog, digital, etc.) for coupling with the baseband component. The RF component supports filtering (e.g., may perform portions of interpolation in the analog and digital domains, etc.) to meet spectral mask requirements. In some embodiments, the novel test system and method presented herein receives information based on captured samples of the up-converted transmitted communication signal and the down-converted received communication signal. The novel ability to accurately process payload symbols containing reduced header information makes it possible to test DUTs with limited memory resources to store captured samples that would otherwise be overloaded with samples from the large header portion.

[0077] 1B is a block diagram of two exemplary radio frequency (RF) integrated circuit DUTs according to an embodiment of the present disclosure. DUT 150A includes mixer 151A, mixer 152A, amplifier 153A, amplifier 154A, mixer 181A, mixer 182A, summer component 183A, amplifier 184A, and local oscillator 155A. Mixer 151A is coupled to amplifier 153A, and mixer 152A is coupled to amplifier 154A. Mixer 181A and mixer 182A are coupled to summer component 183A, which is coupled to amplifier 184A. Local oscillator 155A is coupled to mixer 151A, mixer 152A, mixer 181A, and mixer 182A. A local oscillator provides an in-phase signal to mixers 151A and 181A, but also provides a 90 degree phase shifted quadrature signal to mixers 152A and 182A. A radio frequency (RF) input signal 157A is provided to mixers 151A and 152A. Amplifiers 153A and 154A provide an analog output signal 158A to the baseband component. An analog input signal 188A from the baseband component is provided to mixers 181A and 182A, which in turn provide an input to summer component 183A. Summer component 183A combines the in-phase portion of the signal and the quadrature portion of the signal and forwards the result to amplifier 184A. Amplifier 184A provides an RF output signal 187A.

[0078] DUT 150B includes mixer 151B, mixer 152B, amplifier 153B, amplifier 154B, mixer 181B, mixer 182B, summer component 183B, amplifier 184B, local oscillator 155B, and digital RF data component 159B. Mixer 151B is coupled to amplifier 153B, and mixer 152B is coupled to amplifier 154B. Local oscillator 155B is coupled to mixer 151B, mixer 152B, mixer 181B, and mixer 182B. The local oscillator provides an in-phase signal to mixers 151B and 181B, but also provides a 90 degree phase shifted quadrature signal to mixers 152B and 182B. A radio frequency (RF) input signal 157B is provided to mixers 151B and 152B. The outputs of amplifier 153B and amplifier 154B are coupled to digital RF data component 159B. Digital RF data component 159B provides digital output signal 158B to the baseband component. Digital input signal 188B from the baseband component is fed to mixers 181B and 182B which in turn provide inputs to summer component 183B. Summer component 183B combines the in-phase portion of the signal and the quadrature portion of the signal and forwards the result to amplifier 184B. Amplifier 184B provides RF output signal 187B.

[0079] It is understood that there are various testing approaches. There may be different types of DUTs with various configurations. In some embodiments, the DUT may be configured as a more complete device / system (e.g., integrated system, circuit board level, etc.) closer to the final end-use configuration. FIG. 1C is a block diagram of an exemplary test environment or test system 100C according to some embodiments. The exemplary test environment or test system 100C is similar to the exemplary test environment or test system 100A, except that a device circuit board 190C is being tested as a DUT similar to DUT 190A.

[0080] The test environment or test system 100C of FIG. 1C includes an automatic test equipment (ATE) 110C and a device under test (DUT) (e.g., 190C, 199C, etc.). The ATE 110C includes a controller 111C, a test mode selection module 112C, a test electronics 114C, a demodulation information module 115C, a demodulation module 117C, a test or load board 119C, and a user interface (not shown). In some exemplary implementations, the device 190C includes a transceiver 191C, a signal processing core 192C, a processor / microcontroller 193C, a memory storage 195C (e.g., ROM / RAM, etc.), and an I / O interface 194C (e.g., ATE digital interface pins, etc.). In some embodiments, the DUT 199C is an end-use product (e.g., a mobile phone, a device conforming to an IEEE 802.11 wireless network protocol / standard, etc.). Part of the testing of a DUT (eg, DUT 190C, DUT 199C, etc.) relates to testing analog components (eg, RF chips, RF processors, etc.) within the DUT.

[0081] As the DUT configuration approaches the end-use device level, utilizing the presented approach (e.g., reduced header demodulation, etc.) provides several advantages. Selection between modes (e.g., full header mode, reduced header mode, etc.) allows for flexible testing and potential reduction in overall test time. As the DUT configuration approaches the end-use level, reduced header demodulation provides several further benefits. If the goal is to directly test analog components within the DUT, a reduced length test pattern stream that is more relevant to the analog components can be utilized. By allowing testing to be isolated to the analog components, the risk of other components corrupting the test results is reduced. This ability to isolate testing also makes it easier to "split" the test, or target different parts of the DUT for testing at different times, which in turn helps simplify debugging challenges, etc.

[0082] In some embodiments, a DUT may include multiple test functions. Figure 2A is a block diagram of an example DUT 200 according to an embodiment of the present disclosure. It is understood that DUT 200 is similar to DUT 120A. DUT 200 includes a boundary scan register 210, a core 220, and a test access port 270. Boundary scan register 210 includes multiple boundary scan cells (BSCs). The boundary scan cells are similar to boundary scan cells 215. Boundary scan cells 215 include multiplexers (MUXs) 211 and 214, and flip-flops 212 and 213. MUX 211 is coupled to flip-flop 212, which is coupled to flip-flop 213, which in turn is coupled to MUX 214. Based on the SHIFT DR signal, MUX 211 can select and forward either the normal operation data input or forward the scan test data input as a scan out signal and in response to the clock DR to flip-flop 212 for latching. In response to the UPDATE DR signal, flip-flop 212 is updated with information.

[0083] MUX 214 selects and transfers either the data in flip-flop 213 or the information from flip-flop 213 based on the mode control signal. Core 220 includes scan chain area A, scan chain area B, and scan chain area C. Scan chain area A includes a combinational circuit and a number of scan cells (SCs) coupled together in a scan chain manner. The combinational circuit performs normal functions during mission mode operation. The scan cells can function as both sequential circuits during mission mode operation and also support test operations (e.g., scan in, capture, scan out, etc.) during test mode operation. Test information can be communicated from one scan cell to another in the scan chain. It is understood that the DUT can also include flip-flops that are not part of the scan chain and flip-flops dedicated to scan chain operations. Scan cell (SC) 270 includes multiplexer 271 and flip-flop 272. Based on the scan enable signal, MUX 271, in response to the clock and reset signals, can select and forward either the mission mode operation data input or the scan test data input to flip-flop 272. Flip-flop 272 outputs information to other mission mode operation circuits and other scan chain components.

[0084] Test Access Port (TAP) 230 includes a TAP controller coupled to a test reset input, a test clock input, a test mode input, MUX 233, an instruction register, a bypass register, and an identification information register coupled to MUX 232. MUX 232 is also coupled to MUX 225, additional capture memory 231, the test block, and the boundary scan register. MUX 233 is also coupled to the instruction register, MUX 232, and a test data output. A test data input is coupled to the boundary scan registers, the debug block, the test block, scan chain A, scan chain B, and scan chain C. DUT 200 may be compatible with various standards (e.g., JTAG, IEEE 1149.1, etc.).

[0085] Typically, there are not enough memory resources (e.g., scan test chain resources, capture memory resources, and waveguide generation resources, etc.) in the DUT to conveniently support testing of various functions (e.g., communication functions, demodulation operations, etc.) without the novel approach presented herein. There are significant problems and challenges in including a large amount of dedicated circuitry and other components for testing in analog signal processing components (e.g., relatively expensive because chip space is limited and components can be tested only a limited number of times, etc.). In some embodiments, for DUTs that primarily perform analog signal processing during normal non-test operations, signals are processed and forwarded to other components in the system without the need to "store" intermediate or end results in the analog DUT. Analog processing components do not include the much larger number of normal operation components (e.g., storage capacity, flip-flops in scan chains, etc.) available for dual normal / test operations. Issues and challenges related to the "lack" of available storage capacity for test operations (e.g., capture, scan chains, etc.) are exacerbated as technology and communication protocols evolve.

[0086] 2B is a block diagram of an exemplary automatic test system (ATE) 250 according to an embodiment of the present disclosure. Automatic test system 250 includes digital test function module 251, arbitrary waveform generation module 252, arbitrary waveform digitization (AWD) sequencer 253, DC resources 254, and time measurement resources 255, all of which are coupled to master clock 257. Digital test function module 251 includes vector memory coupled to real-time comparator (coupled to full memory), and drive formatter and edge timing components. Edge timing components are coupled to receive formatter coupled to digital capture memory. Pin electronics are coupled to drive formatter, receive formatter, MUX time measurement and DC test unit.

[0087] The arbitrary waveform generation module 252 includes an arbitrary waveguide generation (AWG) component coupled to an AWG sequencer component, a waveform source memory, and an amplifier / filter coupled to the resulting SFG and a MUX. The MUX is coupled to a DC offset component, test head #1, and test head #2. The arbitrary waveform digitization (AWD) sequencer 253 includes a waveguide digitizer coupled to a multimode modulation / demodulation parameter determination module, a digitizer sequencer, a waveform capture memory, and an amplifier / filter coupled to the MUX. The MUX is coupled to test head #1, and test head #2. The DC resources 254 include a DC data memory, and a time measurement resource module 255 including a time measurement unit / time interval analyzer.

[0088] In some embodiments, there are not enough memory resources (e.g., capture memory resources, waveguide generation resources, etc.) to conveniently support testing of various functions (e.g., communication functions, demodulation operations, etc.). As more functions are integrated and DUTs and communication protocols become more complex, the testing of the DUTs becomes more complex as a result, increasing the demand for more capable test systems. Testing is further complicated by the requirement to test many DUTs simultaneously in parallel. Test resources in ATE can be substantial, but are not infinite, and allocating resources for all of the different test activities becomes costly and impractical, thereby complicating the allocation of test resources. As a result, in conventional test systems, there is not enough memory available for some activities (e.g., any waveguide generation, etc.) on an individual DUT basis.

[0089] The novel systems and methods described herein enable ATE systems to perform testing of modulation and demodulation performance of DUTs that would otherwise be impractical or impossible. The novel systems and methods also increase the performance of ATE systems. Test efficiency is improved through the reduction of the need for large test patterns associated with long header information (e.g., that would otherwise be time consuming, inefficient, error prone, etc.). The amount of ATE resources (e.g., memory resources, etc.) required to handle the otherwise large test patterns is also reduced.

[0090] 3A is a flow chart of an exemplary multi-mode modulation / demodulation parameter determination method 300 including reduced header processing, according to an embodiment of the present disclosure. The multi-mode modulation / demodulation parameter determination method 300 is included in some embodiments of a signal processing test method. In one exemplary implementation, the multi-mode modulation / demodulation parameter determination method 300 relates to testing operations (e.g., up-conversion operations, down-conversion operations, initial front-end transmit operations, initial front-end receive operations, etc.) within a radio frequency (RF) component. The multi-mode modulation / demodulation parameter determination method 300 readily accommodates efficient testing of the RF component's performance in modulating and demodulating communication signals using reduced header information.

[0091] At block 310, a test mode selection process is performed. The test mode selection process allows for a flexible and efficient response to various test scenarios. Multiple test modes are available with the ability to effectively address different demodulation challenges, such as communication bursts with very long header portions. Additional descriptions of the test mode selection process operation are provided elsewhere herein (e.g., the description of the test mode selection process shown in FIG. 7).

[0092] At block 320 of FIG. 3A, a demodulation information determination process is performed. In some embodiments, various types of demodulation information (e.g., timing information, frequency error, equalization values, etc.) are determined based on reduced header mode operation. In some exemplary implementations, the demodulation information is determined without traditional reliance on header information. Additional descriptions of the demodulation information determination process operations are provided elsewhere herein (e.g., blocks 730, 740, 750, 800, 1600, etc.). At block 330, full demodulation is performed. In some embodiments, full demodulation includes determining various parameters associated with demodulation. These parameters may include full equalizer values, frequency error values ​​and sampling clock errors, error vector magnitude (EVM), among others. Additional descriptions of full demodulation operations are provided elsewhere herein.

[0093] In some embodiments, the full demodulation is performed from the perspective of the DUT. In some exemplary implementations, the DUT is a radio frequency (RF) integrated circuit (e.g., similar to DUTs 150A and 150B), and the full demodulation is the demodulation that generates the output signal of the DUT (158A, 158B). It is understood that additional demodulation may be performed on the output signal of the DUT that is not considered part of the full demodulation. In some exemplary implementations, additional demodulation operations (e.g., FFT, data bit decode, etc.) may be performed on the communication signal by back-end baseband digital signal processing, but are not considered part of the full demodulation from the perspective of the radio frequency (RF) integrated circuit DUT. In other embodiments, additional demodulation operations (e.g., FFT, data bit decode, etc.) may be performed on the communication signal by back-end baseband digital signal processing, but are considered part of the full demodulation (e.g., from the perspective of a different DUT (e.g., 190C, 199C, etc.)).

[0094] 3B is a block diagram of an exemplary multimode modulation / demodulation parameter determination test environment. The multimode modulation / demodulation parameter determination test environment includes a test system 390 (e.g., similar to ATE 110A, 110C, etc.) and a DUT 391 (e.g., similar to DUT 120A, 150A, 150B, etc.). The test system 390 directs testing of the DUT 391, in which various types of signal processing tests are performed. In some embodiments, the test system 390 provides simulated test information to the DUT 391 and receives captured test information (e.g., associated with a real in-phase (I) signal, a virtual quadrature-phase (Q) signal, etc.). It is understood that for EVM, the test system 390 can direct testing of both transmitter RF output characteristics and receiver RF input characteristics. The DUT 391 performs operations associated with a receiving module 341A, a carrier demodulation module 342A, a transmitting module 341B, and a carrier modulation module 342B. The test system 390 includes a multi-mode modulation / demodulation parameter determination module 370 and a control module 371. The test system 390 performs operations associated with the cyclic prefix removal module 344, the fast Fourier transform (FFT) module 345, the equalization module 346, and the message decoder module 347. In some embodiments, portions of the operations of the carrier demodulation module 342A are performed within the test system 390. The receive module 341 performs various activities associated with the initial reception of a communication (e.g., carrier bandpass filters, synchronization operations, automatic gain control, etc.).

[0095] The carrier demodulation module 342A performs various operations associated with demodulating a carrier frequency (e.g., local oscillator based demodulation, 90 degree tuned demodulation into in-phase (I) / "real" signal component and quadrature (Q) / "imaginary" component, etc.). Similarly, the carrier modulation module 341B performs various operations associated with modulating a carrier frequency. In some embodiments, operations associated with the receive module 341A, carrier demodulation module 342A, transmit module 341B, and carrier modulation module 341B are performed by transceiver components and analog processing components (e.g., 191A, 172A, etc.).

[0096] The multimode modulation / demodulation parameter determination module 370 of FIG. 3B ascertains various modulation / demodulation parameters. In some embodiments, the multimode modulation / demodulation parameter determination module 370 performs a multimode modulation / demodulation parameter determination method. In some exemplary implementations, the multimode modulation / demodulation parameter determination method is similar to method 300. The multimode modulation / demodulation parameter determination module 370 receives an input from a test system 390. In some embodiments, the input indicates a selection of a test mode. Operations by the multimode modulation / demodulation parameter determination module 370 may be performed within the test system 390.

[0097] A cyclic prefix removal module 344 removes cyclic prefixes added to these signals (e.g., at the transmission source, etc.). A fast Fourier transform (FFT) module 345 converts these signals into signals corresponding to a discrete Fourier series configuration. An equalization module 346 performs an equalization operation on these signals based on information received from (e.g., inverse estimates, etc.). A multi-mode modulation / demodulation parameter determination module 370 performs data decoding operations (e.g., QAM demodulation / desampling operations, parallel-to-serial conversion and MUX operations, etc.).

[0098] The message decoder module 347 performs various demodulation operations. In some embodiments, the message decoder module 347 outputs a stream of data corresponding to the raw transmitted data. In some example implementations, the message decoder module 347 decodes data symbols (e.g., QAM demodulation / desampling of the data constellation point information, parallel-to-serial multiplexing (MUX) to concatenate logical bits corresponding to the constellation point information, etc.).

[0099] The communicated information is organized into "blocks" of information that correspond to portions of a signal communication (e.g., a header portion, a payload or a body portion, etc.). In some exemplary implementations, the blocks of information are communicated according to a protocol (e.g., a communications protocol, a network protocol, a storage protocol, etc.) that includes a definition of the organization and configuration of the blocks and the information. In some embodiments, this information includes a header portion and a data / payload portion. In some embodiments, the communications protocol organizes the information according to a communications protocol layer, with the header portion including supplemental information associated with the protocol layer (e.g., signal processing related parameters, constants, metadata, etc.) and the data payload portion including data / information from another protocol layer.

[0100] The communication protocol layers are also organized into a communication protocol layer hierarchy. It is understood that there may be several layers in the communication protocol layer hierarchy. In some exemplary implementations, the protocol layers are organized from layers related to the organization of user / host application information / data to layers related to the organization of information for actual transmission / reception on the physical communication medium, with multiple layers in between. In some embodiments, these layers are referred to as higher or lower relative to their relative positions in the hierarchy. The layers related to the organization of user / host application information / data are referred to as upper layers, and the layers related to the organization of information for actual transmission / reception on the physical communication medium are referred to as lower layers. In some exemplary implementations, the layers related to the organization of user / host application information / data are referred to as lower layers, and the layers related to the organization of information for actual transmission / reception on the physical communication medium are referred to as upper layers.

[0101] The header portion is information transmitted before the payload portion. It is understood that some protocols have different designations for information transmitted before the data / payload portion (e.g., preamble, header, etc.). In an effort to avoid confusion, as referred to herein, header information includes information received in the preamble portion of the signal, information received in the header portion of the signal, and combinations of information received in both the preamble and header portions of the signal.

[0102] In some embodiments, the signal is configured according to a protocol data unit (PDU) of a communication protocol. In some exemplary implementations, a PDU is a single unit of information communicated (e.g., transmitted, received, etc.) between similar entities (e.g., entities considered at a similar protocol level, peer entities of a network, etc.). The PDU includes information associated with a header portion / section and a portion of information associated with a data / payload portion or section. The data / payload portion may be considered a service data unit (SDU). In some exemplary implementations, a service data unit is a unit of information passed between a higher communication protocol level (e.g., a level closer to a user / host application level, etc.) and a lower communication protocol level (e.g., a level closer to a physical communication level, etc.) to be served / encapsulated by the lower communication protocol level. It is understood that a payload portion of a first communication protocol layer may include information configured within the second communication protocol layer as header information of the second communication protocol layer and payload information of the second communication protocol layer (e.g., from the perspective of the first communication protocol layer, etc.). The first communication protocol layer is a higher communication protocol layer and the second communication protocol layer is a lower communication protocol layer.

[0103] It is understood that the described novel approach is flexible in that it is configurable for implementation with various communication protocols. In some embodiments, the described novel approach is compatible with IEEE 802.11-based wireless network protocol standards (e.g., 802.11 a / b / g / n / ac / ax / be, etc.). In other embodiments, the described novel approach is compatible with Wi-Fi-based wireless network protocols / standards (e.g., Wi-Fi 4, 5, 6, 7, etc.). The described novel approach may also be compatible with communication layer models / suites (e.g., Open Systems Interconnection (OSI), Internet communication suite, Transmission Control Protocol / Internet Protocol (TCP / IP), etc.). The basic frame organization / structure of an 802.11-based burst includes a header portion followed by a data / payload portion (including OFDM symbols).

[0104] 4A is a block diagram of an exemplary PDU 401A frame or packet according to some embodiments. PDU 401A is structured according to a communication protocol. PDU 401A includes a header portion / section 402A and a data / payload portion / section 403A. Header portion / section 402A and data / payload portion / section 403A include information organized in fields. It is understood that PDU 401A may be considered a communication frame, communication packet, and the like. It is understood that communication information may be structured using other fields not shown (e.g., tail / tailer portions / sections at the ends of the PDU, etc.).

[0105] 4B is a block diagram of an example PDU frame or packet at different communication protocol / model layers according to an embodiment of the present disclosure. PDU 401B is a block diagram of an example frame at a second communication protocol layer 409A. In some example implementations, the communication configuration (or "frame") 401B includes a header portion / section 402B and a data / payload portion 403B. PDU 401C is a block diagram of an example frame at a first communication protocol layer 409B. In some example implementations, the communication configuration (or "frame") 401C includes a header portion / section 402C and a data / payload portion 403C.

[0106] As information "passes" from layer to layer in the communications protocol hierarchy, it is processed according to the requirements of each layer. This processing often involves adding or removing header information associated with the layer. Whether header information is added or removed typically depends on whether the overall direction is higher or lower in the communications protocol hierarchy. In some embodiments, when a PDU from a higher level passes to a lower level to create a "new" PDU at the lower level, header information associated with the lower level is added. In some embodiments, the upper layer PDU is considered a lower level service data unit (SDU) that is encapsulated (e.g., wrapped inside) by the lower level PDU. Payload section 403C includes SDU 404C (also known as PDU 401B from layer 409A) and is encapsulated with header section 402C to form the "new" PDU 401C.

[0107] Whether a communication / signal includes reduced header information or does not include header information is related / dependent on the perspective of a communication protocol layer. From the perspective of one communication protocol layer, a communication / signal may be considered reduced-header / headerless if it lacks some or substantially all header information; whereas, from the perspective of another communication protocol layer, the communication may be considered to include header information or to have a header. In some exemplary implementations, the payload section 403C including SDU 404C (also known as PDU 401B) is considered to be headerless even though SDU 404C includes the header information in the header section 402B from PDU 401B. In some embodiments, if the header section 402C is absent (e.g., no additions have been made to this information), the communication is also considered to be headerless. In some embodiments, the data / payload portion 403C includes the communication configuration PPDU 401B (and thus includes the header portion / section 402B and the data / payload portion 403B).

[0108] The reduced header information demodulation process according to the present disclosure operates on the payload portion of the PDU. In some example implementations, the payload portion of the PDU is considered a "headerless" process from the perspective of the communication protocol layer associated with the PDU. In some example implementations, the reduced header information demodulation process operates on information that is headerless from the perspective of the first communication protocol layer 409B (this information includes data payload section 303C information, but not information from header section 402C). Although the payload information (e.g., 403C, etc.) is considered "headerless" from the perspective of the protocol layer (e.g., 409B, etc.), the payload information includes "header" (e.g., 402B) information from another protocol layer.

[0109] It is understood that a communication protocol layer may have multiple sub-layers, which have different functions and perform different operations associated with the respective communication protocol layers. Figure 4C includes various example organizations and configurations of information within a PPDU (also referred to as "frames"), according to some embodiments.

[0110] Communication configuration 410A is a block diagram of an exemplary frame according to some embodiments. Communication configuration 410A is compatible with a physical protocol data unit (PDU) frame. Frame 410A includes a header portion / section 420A and a data / payload portion / section 430A. Header portion / section 420A and data / payload portion / section 430A include information organized in fields.

[0111] Communication configuration 410B is a block diagram of an exemplary frame according to some embodiments. Frame 410B is compatible with a physical layer protocol data unit (PPDU). Frame 410B includes a header portion / section 420B and a data / payload portion / section 430B. In some embodiments, header portion / section 420B includes a preamble field 421B and a signal field 422B.

[0112] Frame 410C is a block diagram of an exemplary communication information organization and configuration (also referred to as a "frame") according to some embodiments. Frame 410C is compatible with a physical layer protocol data unit (PPDU). Frame 410C includes a header portion / section 420C and a data / payload portion / section 430C. In some embodiments, data / payload portion / section 430C includes packet 430C and packet 450C. Packet 440C includes a packet header portion / section 441C and a packet data / payload portion / section 442C. Packet 450C includes a packet header portion / section 451C and a packet data / payload portion / section 452C.

[0113] Frame 410D is a block diagram of an exemplary communication information organization and configuration (also referred to as a "frame") according to some embodiments. Frame 410D is compatible with a physical layer protocol data unit (PPDU). Frame 410D includes a header portion / section 420D and a data / payload portion / section 430D. In some embodiments, header section 420D includes a preamble field 421D and a physical header 422D.

[0114] In some example implementations, data / payload portion / section 430D includes physical layer service data unit (SDU) 440D (also known as MPDU) and physical layer service data unit (SDU) 450D (also known as MPDU). Physical layer service data unit (SDU) 440D includes a MAC layer PDU (MPDU). MPDU 440D includes a MAC header portion / section 441DD and a MAC data / payload portion / section 442D. MPDU 450D includes a MAC header portion / section 451DD and a MAC data / payload portion / section 452D. In some embodiments, the medium access control (MAC) layer protocol data unit (PDU) is a physical layer service data unit (SDU).

[0115] 4D includes an exemplary organization and configuration of information according to some embodiments. Communication configuration or frame 410F is a block diagram of an exemplary frame according to some embodiments. Frame 410F is compatible with a frame configuration or physical layer protocol data unit (PPDU) configuration. Frame 410F includes a header portion / section 420F and a data / payload portion / section 430F. In some embodiments, header portion / section 420F includes a preamble field 421F and a signal field 422F. Data / payload portion / section 430F includes orthogonal frequency division multiplexing OFDM symbols 441F, 442F to 448F. It is understood that modulated forms of OFDM symbols at lower protocol levels may include header information associated with multiple higher protocol levels. OFDM symbols are configured for communication within a communication protocol physical layer, and some of the OFDM symbols include header information from a protocol layer (e.g., link layer, transport layer, etc.) even though they are considered headerless payload data from the physical layer perspective.

[0116] 4E is a block diagram of different exemplary signal physical layer protocol data unit (PPDU) organizations / structures (also called "frames") for each IEEE 802.11-based wireless network protocol / standard, according to some embodiments. The PPDU includes a respective physical layer header portion and a physical layer data portion. The header portion includes various training fields including reference training symbols, and the signal field (SIG) includes rate, length and parity information. It is understood that the size of the header portion increases significantly when new communication protocol organizations / structures of the IEEE 802.11-based change (e.g., when a new version is released, etc.).

[0117] The PPDU 451 complies with the IEEE 802.11a / g communication protocol, and the header includes a legacy short training field (L-STF), a legacy long training field (L-LTF), and a legacy signal field (L-SIG). On the other hand, the PPDU 452 complies with the IEEE 802.11n high-throughput (HT) communication protocol, and the header includes a legacy short training field (L-STF), a legacy long training field (L-LTF), a legacy signal field (L-SIG), a high-throughput signal field (SIG), a high-throughput short training field (STF), and one to four high-throughput long training fields (HT LTF). The PPDU453 complies with the IEEE 802.11ac Very High Throughput (VHT) communication protocol, and the header includes a legacy short training field (L-STF), a legacy long training field (L-LTF), a legacy signal field (L-SIG), a very high throughput signal field A (SIG-A), a very high throughput short training field (STF), 1 to 8 very high throughput long training fields (VHT LTF) and a very high throughput signal field B (SIG-B).

[0118] Additionally, the PPDU 454 complies with the IEEE 802.11ax high-efficiency (HE) communications protocol, where the header includes a legacy short training field (L-STF), a legacy long training field (L-LTF), a legacy signal field (L-SIG), a repeating non-HT signal field (RL-SIG), a high-efficiency signal field A (SIG-A), a high-efficiency short training field (STF), and 1 to 8 high-efficiency long training fields (VHT LTF). Finally, PPDU455 is compliant with IEEE 802.11be (HET), an extremely high throughput communication protocol, and the header includes a Legacy Short Training Field (L-STF), a Legacy Long Training Field (L-LTF), a Legacy Signal Field (L-SIG), a Repeated Legacy Signal Field (RL-SIG), a Universal Signal Field (U-SIG), a High Efficiency Signal Field (EHT-SIG), a High Efficiency Short Training Field (EHT-STF) and a High Efficiency Long Training Field (EHT-LFT). The duration of an EHT-LFT symbol is determined by the GI+LFT size.

[0119] In some embodiments, the reduced header information demodulation test system and method according to the present disclosure is compatible with a subcarrier communication approach. In some exemplary implementations, the subcarrier communication approach includes multiple tones organized within a communication channel. These tones may be organized and configured according to the IEEE 802.11 wireless network protocol / standard.

[0120] There are at least two aspects of the changing communication protocol standards that pose significant challenges to test operations. The first aspect is that the header portion and corresponding header information increases with the new protocol standards, which means that more information is required for sampling and capture during testing. The second aspect is that the bandwidth becomes larger, resulting in increased sampling rates. In some exemplary implementations, the DUT requires 400 samples to test signals compliant with OFDM 802.11a and between 15360 and 24320 samples to test signals compliant with OFDM 802.11be. As previously indicated, many communication DUTs have limited resources (e.g., memory, scan test cells, etc.) for test operations, and the increased information required for testing (e.g., associated with sampling capture, etc.) overloads the limited resources. The limited resources become saturated with information about the header portion and therefore cannot handle proper testing of the payload portion. The reduced header information demodulation test system and method according to the present disclosure overcomes these challenges and advantageously enables proper testing of the payload portion. Also, storing information associated with the waveform (eg, the output of the AWG components, etc.) places a smaller burden on the memory of the DUT and the ATE system.

[0121] It is understood that different power levels can be assigned to different RUs and that RUs can be assigned across various carrier bandwidths. There are more tones / subcarriers in a layer than there are tones assigned to user data communications. Some tones / subcarriers may be utilized for control operations (e.g., pilots, guard / null space, etc.). It is understood that the RUs and tones may be organized and configured according to IEEE 802.11 wireless network protocols / standards.

[0122] 5A is a block diagram of an exemplary signal configuration according to some embodiments. The tones are arranged in different levels based on the number of tones included in a resource unit (RU). In some exemplary implementations, a resource unit is used to indicate a group of subcarriers (e.g., tones, etc.) used in a communication (e.g., downlink transmission, uplink transmission, etc.). For example, level 510 includes 37 RUs (1A to 37A) with each RU including 26 tones, level 520 includes 16 RUs (1B to 16B) with each RU including 52 tones, level 530 includes 8 RUs (1C to 8C) with each RU including 106 tones, level 540 includes 4 RUs (1D to 4D) with each RU including 242 tones, level 550 includes 2 RUs (1E and 2E) with each RU including 484 tones, and level 570 includes 1 RU (1F) with 996 tones.

[0123] In some embodiments, the subcarriers are associated with a frequency bandwidth or range. The frequency bandwidth is defined by a communication protocol (e.g., IEEE 802.11 wireless network protocol / standard, etc.). In other embodiments, the reference signals are associated with predefined, known characteristics. Each received reference signal characteristic is determined and compared to the corresponding predefined characteristic.

[0124] FIG. 5B is a block diagram of an example frequency spectrum of subcarriers and corresponding bins according to an embodiment of the disclosure. Each frequency bin corresponds to a subcarrier. User subcarriers and corresponding bins are distributed throughout the spectrum (e.g., User 1 subcarriers, User 2 subcarriers, etc.). The block diagram also shows the location / spacing of subcarriers for reference tones / signals (e.g., pilot tones, etc.) according to some embodiments. Between the pilot bins, there are data bins. At both ends of the spectrum, there are subcarriers / bins that act as guard subcarriers (e.g., to help mitigate interference from other spectrums). In some example implementations, there are non-pilot tone null subcarriers at the center carrier frequency value.

[0125] 5C is a graph block diagram of an example transmission of OFDM symbol tones / signals according to an embodiment of the present disclosure. The transmission includes OFDM symbols 0, 1 and 2 concatenated in a "burst" frame sequence across the time domain. One OFDM burst includes an OFDM symbol. The OFDM symbol includes data bit streams 1 to n, each assigned to subcarrier 1 through N bins. One modulated subcarrier is equivalent to one point in frequency and time. The IFFT creates an OFDM waveform from the OFDM subcarriers. One OFDM symbol includes the IFFT OFDM waveform plus a guard interval.

[0126] The novel presented approach allows for determining the start of each of OFDM symbols 0, 1, and 2 based on information in the OFDM symbols in the payload portion of a "burst" frame, without relying on information from the header portion of the "burst" frame. It will be appreciated that the novel approach described herein is compatible with implementation in a variety of communication protocols (e.g., OFDM protocols, OFDMA protocols, etc.).

[0127] 5D is a block diagram of an exemplary OFDM symbol payload portion transmission using reduced header information according to an embodiment of the present disclosure. As previously indicated, header information (e.g., preamble information, reference information, etc.) is often used to correct (e.g., equalize, etc.) problems with communication. OFDM symbol payload portion transmission 505 includes OFDM symbols 501, 502, and 503. OFDM symbols 501, 502, and 503 are arranged in a loop pattern. In some embodiments, the payload data is arranged without preamble training. For example, the start of OFDM symbol 501 loops around to the end of OFDM symbol 503 reference symbol. This pattern is considered continuous (e.g., no start, no end, etc.). OFDM symbol 502 includes a cyclic prefix portion 502A at the start of OFDM symbol 502 and an end portion 502B. Cyclic prefix portion 502A is a copy of end portion 502B. OFDM symbol 501 includes a cyclic prefix portion and an end portion 501B. OFDM symbol 503 includes a cyclic prefix portion 503A at the beginning of the OFDM symbol 503, and an end portion.

[0128] FIG. 5E is a block diagram of various exemplary subcarrier configuration allocations according to an embodiment of the present disclosure. Dots or circles indicate various subcarriers within a communication bandwidth. Filled dark circles indicate pilot subcarrier signals, and unfilled circles indicate other subcarrier signals (e.g., data subcarriers, null subcarriers, etc.). The Y-axis corresponds to the frequency values ​​of the various subcarriers, and the X-axis indicates the transmission of the subcarriers over time. Different pilot subcarrier configurations (e.g., block, comb, scattered, etc.) may be implemented to address different conditions or concerns. While pilot signals provide valuable information regarding the performance of the DUT, designating all subcarriers as pilots at all times does not enable communication of other data. Thus, the configuration of pilot subcarriers is often a trade-off that balances different objectives. In configuration 591, all subcarriers within the bandwidth are intermittently utilized as pilot subcarriers to provide an indication of all subchannel conditions. In configuration 592, intermittent subcarriers within the bandwidth are utilized as pilot subcarriers that continuously provide an indication of the subchannel conditions of those subcarriers. In configuration 593, one pilot subcarrier information is transmitted continuously and the other pilot subcarrier information is intermittent in frequency and time. The pilot subcarrier signals are reference signals that have properties (e.g., BPSK modulation, etc.) that are resistant to misinterpretation due to communication conditions (e.g., channel conditions, equipment vibration differences, etc.).

[0129] The various subcarrier configurations are predefined (e.g., known by the ATE, etc.). The subcarrier configuration protocol may be publicly known (e.g., according to a published industry standard, IEEE 802-11 family of protocols, etc.) or privately known (e.g., private interpretation of an industry standard, confidential configuration, trade secret, etc.). The subcarrier configuration information is accessible to the ATE and can be utilized to implement the various novel reduced header systems and methods presented elsewhere herein. In some embodiments, the subcarrier configuration is utilized to extract information (e.g., related to timing, frequency error, ideal values, equalizer, etc.) from the payload portion of the communication. In some exemplary implementations, this information is extracted from the complex payload portion without relying on the availability of header information.

[0130] It is intended to accurately transmit the information in the original data stream. In some embodiments, an exemplary data stream is shown in FIG. 5C. The data is modulated according to several constellation maps in the process of being communicated. Errors or deviations from the ideal values ​​in each constellation map are often associated with communication challenges (e.g., improper channel characteristics, frequency response characteristics, scattering, fading, power loss over distance, etc.). FIG. 6A is a block diagram of several exemplary constellation maps associated with signal communication, according to an embodiment of the present disclosure. Block dots indicate symbols in ideal positions (e.g., ideal I and Q maps). Constellation map 610 is a BPSK map with two possible symbols and one information bit / symbol. Constellation map 620 is a QPSK map with four possible symbols and two information bits / symbol. Constellation map 630 is a 16QAM map with 16 possible symbols and four information bits / symbol. It will be appreciated that various other QAM configurations may exist (eg, 64QAM, 256QAM, 1024QAM, etc.).

[0131] 6B is a block diagram of some example constellation map errors associated with signal communication according to some embodiments. The constellation map includes ideal symbol positions shown as solid black dots (e.g., 640, 650, 670, 680, etc.) and symbol positions associated with the transmitted signal shown as hollow dots (e.g., 641, 642, 674, etc.). The constellation map shows an ideal or reference vector 690 and effort vectors 671 and 672.

[0132] 7 is a flow chart of an example test mode selection process 700 according to an embodiment of the present disclosure. The test mode selection process 700 provides flexible and adaptable selection between test modes (e.g., header inclusion mode, reduced header training mode, reduced header mode; etc.). The test mode selection process 700 enables the ATE to execute a variety of test scenarios having different test characteristics and capabilities. In some embodiments, this selection enables "backwards" compatibility with legacy test approaches and also enables implementation of novel test approaches described herein that would otherwise be impractical or impossible in legacy test approaches.

[0133] At block 710, a selection trigger is received. The selection trigger may be based on a communication protocol or an overall test approach, etc. There may be a desire to perform some tests of the DUT with a signal having a full header, then with another signal having a reduced header. There may be a desire to obtain a statistical sampling of the full header processing capabilities of the DUT, and then increase the overall throughput with reduced headers. For example, first test whether the header information portion is properly processed / stored in the limited chip memory, then in a second "run" verify whether the payload is correctly processed / stored.

[0134] At block 720, a test mode is determined based on the received trigger information. The capabilities of the different available test modes are considered at 720 in response to a selection trigger. In some embodiments, the selection trigger may indicate that the first DUT does not include sufficient memory to handle testing of a communication burst that includes larger header information. In some embodiments, if the DUT fails the first test run, the failure indication serves as a trigger to perform a second test run using a different test mode.

[0135] A reduced header mode test process is selected at block 730. In some embodiments, the DUT does not include sufficient resources (e.g., memory, etc.) to efficiently perform demodulation tests. If the communication protocol specifies relatively large header information that exceeds the ability of the DUT to respond adequately to the test scenario, a reduced header mode test process may be selected at 730 to overcome challenges associated with large amounts of header information.

[0136] At block 740, a reduced-header reference signal mode test process is selected. In some embodiments, the reduced-header reference signal mode test process is selected as the secondary test. In some exemplary implementations, the reduced-header mode test process is selected for a first test run on the DUT and the reduced-leader reference signal mode test process is selected for a second test run. By performing a second test run using a different test mode, any anomalies not captured by the first test run may be identified. The anomalies may be due to test characteristics of the first test mode that the second test mode may not be affected by.

[0137] In block 750, a header mode test process is selected. In some embodiments, the header mode test process may produce more reliable results for certain complex test scenarios. For test scenarios that require very high QAM demodulation, the results of the header mode test process may be more reliable than the reduced header mode test process and the reduced header with reference signal mode test process. The reduced header mode test process 800 is included in a demodulation decision process (e.g., similar to block 320, etc.).

[0138] FIG. 8 is a block diagram of an exemplary reduced header mode test process 800 according to an embodiment of the present disclosure. In some embodiments, the reduced header mode test process 800 is included in a reduced header communication signal processing test method. The reduced header mode test process is utilized when reference signal information is reduced / not available. In some exemplary implementations, there is no reference signal to compare against the capture (e.g., to determine / calculate impairments, etc.). The reduced header mode test process is utilized when a receiving component (e.g., DUT, etc.) reduces information about the received signal (e.g., reduced modulation related information, header information, preamble information, signal configuration information, etc.). In some exemplary implementations, the reduced header does not include various fields of information (e.g., short training field, long training field, sync field, header field, signal field, service field, modulation selection bit / field, rate field, etc.). In other exemplary implementations, a portion of these fields is included in the reduced header. The received information is less than would otherwise be available in a normal field / non-test situation.

[0139] At block 810, a reduced header mode test processing instruction is accessed (e.g., headerless without a reference signal, etc.). In some example implementations, the reduced header mode test processing instruction is based on a selection of reduced header mode test processing (e.g., similar to the selection at block 710, etc.). The selection may be made based on various conditions (e.g., the DUT does not have sufficient resources to handle testing of communications with full header information, it is desirable to have a smaller test pattern for testing payloads that include reduced header information, it is desirable to have multiple test runs with different test characteristics, etc.).

[0140] In block 820, a reduced header demodulation information determination process is performed. In some embodiments, the reduced header demodulation information determination process determines information utilized in testing modulation / demodulation operations (e.g., signal processing operations, etc.). In some exemplary implementations, the reduced header demodulation information determination process includes blocks 821, 822, 823, 824, 825, and 826.

[0141] At block 821, an autocorrelation of the cyclic prefix in the signal is performed. In some embodiments, the signal is a loop signal (such as similar to the signal in FIG. 5D). The signal is configured according to a communication protocol. In some exemplary implementations, the communication protocol corresponds to a communication protocol standard in the IEEE 802.11 family of wireless network protocols / standards. In some embodiments, a peak search function is performed on the results of the autocorrelation.

[0142] At block 822, the start timing of symbols in the signal are identified based on the autocorrelation results from block 821. These symbols are defined by a communication protocol. These symbols may include Orthogonal Frequency Division Modulation (OFDM) symbols. In some example implementations, the start and end positions / timing of the symbols relative to each other (e.g., where one OFDM symbol starts and ends relative to the start and end of another OFDM symbol, etc.) are identified.

[0143] At block 823, an initial coarse frequency error correction is determined based on the autocorrelation results from block 821. The phase and coarse frequency error difference may also be determined from an analysis of the peaks in the autocorrelation results. In some embodiments, the difference in the peak location from the expected peak location may indicate the phase difference and corresponding frequency error. In some exemplary implementations, the initial coarse frequency error correction is determined by the process described with reference to Figures 9A and 9B. As described elsewhere herein, the initial coarse frequency error correction may be an average of each individual frequency error correction.

[0144] At block 824, a set of bins for the signal is established, the set of bins including pilot bins and data bins. The set of bins corresponds to a set of subcarriers associated with the signal, the pilot bins correspond to pilot subcarriers within the set of subcarriers, and the data bins correspond to data subcarriers within the set of subcarriers. In some example implementations, a Fast Fourier Transform (FFT) operation is performed on a portion of the signal associated with the OFDM symbol, and the results are used to establish the set of bins.

[0145] At block 825, identities of pilot bins are extracted according to the definition of pilot subcarriers defined by the communication protocol. In some embodiments, identifying the pilot bins includes identifying the positions of the pilot bins relative to each other and relative to other bins in the set of bins. It is understood that the identities and definitions of subcarrier (e.g., pilot subcarriers, data subcarriers, null subcarriers, etc.) configurations and positions relative to each other may vary (e.g., as presented in the description of Figures 5A-5E, elsewhere herein, etc.).

[0146] At block 826, ideal constellation values ​​and ideal symbol values ​​are set for the pilot bins and data bins. In some embodiments, interpolation is used to set the ideal constellation values ​​and ideal symbols for the data bins. It will be appreciated that various types of interpolation (e.g., linear, least squares regression, iterative update / re-determination, etc.) are compatible with and readily implemented in the reduced header mode test process 800. Additional descriptions of the interpolation process operations are provided elsewhere herein (e.g., in the description of processes 1200A, 1200B, etc.).

[0147] In block 827, other demodulation parameter values ​​are determined based on the results of the ideal constellation values ​​and ideal symbol values ​​for the pilot bins and data bins (e.g., based on the results of block 826, etc.). In some embodiments, the equalizer value from the first bin is first applied to the second bin and then updated based on the results of block 826. In some example implementations, the first bin and the second bin are adjacent or next to each other. The configuration of the first bin and the second bin with respect to their proximity to each other may be defined by a communication protocol (e.g., an industry standard, an IEEE 802.11-based communication protocol, etc.).

[0148] In some embodiments, after the reduced header demodulation information determination process from block 820 is performed, operation proceeds to block 830 where an exemplary full demodulation is performed. This full demodulation is similar to block 330. In some embodiments, the full demodulation is similar to some aspects of a conventional demodulation analysis. After the information from block 820 is available, processing may proceed with full demodulation determination information similar to conventional information that would not otherwise be conventionally available from the reduced header signal.

[0149] 9A is a block diagram of an example autocorrelation graph result according to some embodiments. In some example implementations, the autocorrelation is related to a cyclic prefix in an OFDM symbol (such as similar to that shown in FIG. 5D). The peaks in the graph are the resulting autocorrelation of a signal including the cyclic prefix and the position of a delayed version of this signal. The Y-axis is normalized correlation (unitless) in increments of 0.1, and the X-axis is samples (unitless) with increments of 1000 samples per grid width.

[0150] In some exemplary implementations, a reduced header demodulation information determination process (e.g., similar to block 820) is performed. Autocorrelation is performed on the looped signal to generate peak indications at the locations of OFDM symbols in the signal (e.g., results similar to those in FIG. 9A, FIG. 9B, etc.). The autocorrelation provides timing related information and coarse frequency error information. The timing of the concatenation boundaries of the OFDM symbols in the looped signal is determined based on the peaks in the autocorrelation result. Portions of the signal associated with different OFDM symbols are identified (e.g., the start and end of the OFDM symbol, etc.) based on a peak search of the autocorrelation result. The start and end of the OFDM symbol are similar to the start and end of OFDM symbols 0, 1, and 2 in FIG. 5C. The phase and coarse frequency error differences may also be determined from an analysis of the peaks in the autocorrelation result.

[0151] 9B is a block diagram of an example autocorrelation process according to an embodiment of the disclosure. OFDM symbol 910A includes cyclic prefix 911A and corresponding end portion 912A. Copy OFDM symbol 920B includes cyclic prefix 921B and corresponding end portion 922B. Copy OFDM symbol 920B is a copy of OFDM symbol 910A. The copy of OFDM symbol 920B is shifted in the time domain by an amount of time corresponding to a Fast Fourier Transform or FFT size, or the like. During the shift, autocorrelation is performed so that an autocorrelation peak 930 is found when cyclic prefix 921B aligns with end portion 912A in the time domain. Autocorrelation peak 930 has both an amplitude and a phase. If there is no coarse frequency error, the phase is zero. If there is a non-zero phase, there is a coarse frequency error. The coarse frequency error is defined as D theta divided by dt, where D theta is equal to the phase. dt is the amount of time from the start of the OFDM symbol to the end of the OFDM symbol (not counting the cyclic prefix).

[0152] The bottom of FIG. 9B includes a block diagram of a frequency domain spectrum (e.g., frequency response, digitizer, due to other components that introduce other out-of-band spectrum, etc.), including a local oscillator spectrum, a signal spectrum, and other spectra. In some exemplary implementations, a local oscillator is present, and in other exemplary implementations, a local oscillator may not be present or may be present elsewhere. In some embodiments, a response close to the true frequency error may be obtained by coarse frequency error correction. In some exemplary implementations, the coarse frequency error correction avoids substantial EVM rise (e.g., below the EVM associated with any residual frequency error in cases where the spectrum is not clean). Timing information associated with the OFDM symbol and the coarse frequency error correction allows for subsequent reliable extraction of the ideal symbol. Extraction of the ideal symbol value and retrieval of the capture value provide information for the frequency domain analysis (e.g., post-FFT, etc.) described elsewhere herein. Equalizer values ​​are described elsewhere herein (e.g., in processes 1200A, 1200B).

[0153] 9A and 9B, in some embodiments, a coarse frequency error for each individual peak in FIG. 9A (e.g., corresponding to peaks for OFDM symbol 0, OFDM symbol 1, OFDM symbol 2, etc.) is determined similar to the error frequency determination for OFDM symbol 910A. Each resulting individual frequency error is averaged over multiple peaks (e.g., peaks in FIG. 9A). In some embodiments, each resulting individual frequency error is averaged over multiple peaks within a payload portion of a burst or frame. Based on the average frequency error value, an average frequency error correction is determined. The average frequency error correction is applied to the waveform (e.g., the payload portion of a burst or frame, etc.).

[0154] An FFT operation is performed on each portion of the signal associated with OFDM symbols 0, 1, and 2 to generate respective channel bandwidth subcarriers (e.g., similar to subcarrier bin 1 through subcarrier N in FIG. 5C). Although the values ​​of the subcarriers within each bin may change over time (e.g., with different OFDM symbols, etc.), the location of each of the bins within the bandwidth is defined by the communication protocol and remains fixed. Because the locations of the pilot bins are set by the communication protocol, the subcarriers associated with each pilot bin are easily identified. The communication protocol also specifies that BPSK modulation is used for the pilot subcarriers, and that BPSK analysis described elsewhere herein is used to determine ideal values ​​for the pilot subcarriers within each pilot bin.

[0155] For the pilot and data bins, ideal constellation values ​​and ideal symbol values ​​are set (e.g., at block 826, etc.), which includes determining equalizer values. In some example implementations, equalizers are set for pilot and data subcarriers associated with the respective pilot and data bins.

[0156] FIG. 10 is a flow chart of an exemplary equalizer value determination process 1000 according to an embodiment of the present disclosure. In some embodiments, the equalizer values ​​are obtained from analyzing the frequency response within the pilot bins and data bins. The equalizer values ​​(e.g., for the pilot bins, data bins, etc.) are the inverse of the respective frequency response values. In some embodiments, this is for the OFDM symbols available in the capture and then averaged. It is understood that the equalizer value determination and interpolation process described herein is applicable to both magnitude and phase correction. The interpolation process 1000 is included in some embodiments of the reduced header mode test process (e.g., process 800, etc.).

[0157] At block 1010, equalizer values ​​are determined for pilot subcarriers at pilot bin locations based on the ideal pilot tone constellation values. In some embodiments, the frequency response is based on the difference between the ideal pilot tone constellation values ​​and the received / captured pilot tone values. Additional description of the determination of equalization values ​​is provided elsewhere herein (e.g., such as the description of process 1100 shown in FIG. 11).

[0158] Based on the ideal data tone constellation values, equalizer values ​​are determined for the data subcarriers at the data bin locations in block 1020. The determination of the equalizer values ​​at the data bin locations is based on the results of the equalizer values ​​of the step of determining equalizer values ​​at pilot bin locations. In some example implementations, the equalizer values ​​determined for the data subcarriers at the data bin locations are based on an interpolation between the equalizer values ​​from block 1010 of the pilot subcarriers at the pilot bin locations.

[0159] In some embodiments, setting the ideal constellation values ​​and ideal symbol values ​​for the pilot bins (e.g., at block 826, etc.) includes performing an ideal pilot tone determination process. The ideal pilot tone determination process sets the ideal constellation values ​​and ideal symbol values ​​for the pilot bins. Other processes (e.g., interpolation, etc.) are used to set the ideal constellation values ​​and ideal symbol values ​​for the data bins.

[0160] 11A is a flow chart of an example ideal pilot tone determination process 1100 according to an embodiment of the present disclosure. In some example implementations, an ideal pilot tone value is obtained for an ideal pilot tone constellation point and an ideal symbol. At block 1110, a coarse frequency error determination is completed. In some embodiments, the result of an autocorrelation peak search function process is utilized in determining the coarse frequency error. The compensation value is the difference between the expected frequency of the pilot bin defined by the communication protocol standard and the received or captured frequency of the pilot bin.

[0161] At block 1120, the coarse frequency error is compensated. In some embodiments, compensating for the coarse frequency error includes adjusting the captured pilot bin subcarrier signal value by a compensation value. The compensation value is equal in magnitude and the negative of the coarse error value. For example, if the captured pilot bin subcarrier signal is 2.4499 GHz, which has a frequency error 100 kHz below the expected value, the compensation is to add 100 kHz to 2.4499 GHz for a value of 2.45 GHz. If the captured pilot bin subcarrier signal is 2.4501 GHz, which has a frequency error 100 kHz above the expected value, the compensation is to subtract 100 kHz from 2.4501 GHz for a value of 2.45 GHz.

[0162] In block 1130, pilot tone values ​​of the signal are obtained. In some embodiments, the pilot tones are modulated according to a binary phase shift keying BPSK protocol. In some exemplary implementations, the pilot tones are relatively immune to noise. BPSK signals are more susceptible to noise due to the low constellation density in the IQ plane. A small amount of noise may cause a symbol error in, for example, a 1024QAM constellation type, while the same amount of noise does not cause a symbol error in the BPSK constellation plane. There is an increasing inverse exponential relationship between the logarithmic bit error rate value and the signal-to-noise ratio decibel value. As the QAM value increases, the probability that the error will focus on a different constellation type relative to the signal-to-noise ratio (BPSK error probability is the same as QPSK) increases. In some exemplary implementations, to have a symbol error rate of 10e-6 for a BPSK / QPSK signal, an SNR of about 13 dB is required, while to achieve the same for a 256QAM signal, for example, an SNR of about 28 dB must be achieved.

[0163] In block 1140, a determination is made whether a re-estimation of the frequency error is appropriate / necessary, and if so, a fine-tuning frequency error estimation is performed in block 1145, otherwise, block 1150 is executed. If the user selected "LowSNR" for the FrequencyEstimationMethod, processing moves to block 1145. If "HighSNR" was selected for the FrequencyEstimationMethod, processing skips to block 1050.

[0164] At block 1145, if the result of the determination at block 1040 is positive, a frequency error re-estimation process is optionally performed using the ideal pilot tone and / or data bin values ​​from block 1130. In some embodiments, the re-estimation provides a more accurate frequency error estimate by also using the ideal pilot tone and / or data bin values.

[0165] In block 1050, an ideal pilot tone value is returned. In some embodiments, the ideal pilot tone value is associated with an ideal pilot bin value and an ideal pilot subcarrier value (e.g., an ideal pilot subcarrier symbol value, etc.). With the returned ideal pilot tone value, a more accurate estimation of the frequency error can be achieved.

[0166] The new presented approach overcomes many challenges for demodulation with reduced header information. Figure 11B is an example graph of simulated channel response in the presence of a signal with full header or a signal with a non-blind known stimulus, according to some embodiments. This non-blind known stimulus can be similar to PayloadOnlyIdealIQWaveform discussed elsewhere herein. As shown in Figure 11B, in some embodiments, the system can easily obtain known channel responses for all of the subcarriers used. However, traditionally, challenges arise when the system only has pilot tones to obtain an initial frequency response. The Y-axis is magnitude (dB) from 7.0 dB to 1.0 dB in 1.0 dB increments, and the X-axis is subcarrier frequency from 1000.0 Hz to 1000.0 Hz in 50 Hz increments.

[0167] FIG. 11C is a graph showing an example pilot bin frequency response location according to some embodiments. The known pilot bin frequency response is not highly populated compared to the otherwise unknown data bin frequency response. In some embodiments, interpolation is performed to set frequency response values ​​for data bins intermediate the pilot bins. It is understood that the frequency responses for the data bins shown in FIG. 11C are not known until the interpolation is performed. The Y-axis is magnitude (dB) from 7.0 dB to 1.0 dB in 1.0 dB increments, and the X-axis is subcarrier frequency from 1000.0 Hz to 1000.0 Hz in 50 Hz increments.

[0168] FIG. 12A is a flow chart of an exemplary interpolation process 1200A including iterative updating / re-determination of equalization values ​​within bins, according to an embodiment of the present disclosure. The interpolation process 1200A is included in some embodiments of a reduced-header communication signal processing test method. The exemplary interpolation process 1200A with iterative updating / re-determination of equalization values ​​provides more accurate interpolation of equalization values ​​than interpolation processes with less iterative updates, such as traditional linear and traditional least-squares interpolation. Having a more accurate equalization rate allows more accurate demodulation operations for the DUT, and corresponding test operations of those operations. This approach allows testing of DUTs that otherwise cannot easily handle / demodulate full frames or packets with full header information in a test environment. It is understood that the interpolation process 1200A with iterative updating / re-determination of equalization values ​​within bins is applicable to both magnitude and phase correction.

[0169] In block 1201 of FIG. 12A, new equalizer values ​​for pilot tones are determined. In some embodiments, the equalizer values ​​are based on pilot binary phase shift keying (BPSK) such as ideal / known or easily extracted pilot signal values. The BPSK analysis of this signal has only two constellation points as opposite parts of the X-axis shown in the exemplary constellation map 610. Given that there is a relatively large distance between constellation points in BPSK compared to other constellation maps (e.g., 620, 630, etc.), there is little chance of erroneously associating the received signal value with the wrong ideal constellation point. In addition, there is little chance that the noise is so large that it would add confusion to the decision regarding the appropriate constellation point. Thus, the difference between the received or captured signal value and the ideal constellation point provides a reliable indication of the channel response. The inverse of the channel response is equal to the equalizer value.

[0170] At block 1202, a determination is made whether the next bin is a data bin. In some embodiments, the next bin is assumed to be a data bin if it does not have the characteristics of a pilot bin or a null bin. The next bin is assumed to be a data bin if it is not one of the previously identified pilot bins and has some transmitted signal characteristics (e.g., as opposed to a null bin, which is not expected to have the transmitted signal characteristics).

[0171] In block 1203, new equalizer values ​​are applied to the data bins. In some embodiments, applying new equalizers from adjacent bins provides a more accurate estimate of preliminary equalizer values ​​for the current data bin. Applying preliminary new equalizers from adjacent bins to the current data bin provides a reasonable initial correction for the corresponding subcarrier values ​​of the current bin.

[0172] In block 1204, data subcarrier ideal signal values ​​are extracted for the data bins. In some embodiments, the data subcarrier ideal signal values ​​are based on a relationship between the results of block 1203 to known expected values ​​according to the communication protocol standard. By using these results of block 1203, the likelihood of misidentifying the appropriate corresponding ideal constellation point value is significantly reduced compared to other conventional approaches.

[0173] New equalizer values ​​are set based on the data subcarrier ideal signal values ​​in block 1205. Setting new equalizer values ​​for the current data bin based on the data subcarrier ideal signal values ​​from block 1204 provides a more accurate interpolation result. This more accurate estimation of the appropriate equalization values ​​allows for avoidance, and in many cases reversal, of problems related to frequency response errors.

[0174] 12B is a graph of the results of an interpolation process including iterative updating / re-determination of equalization values ​​within bins, according to an embodiment of the present disclosure. The graph includes a representation of the relationship between the various bins and associated subcarriers within the communication bandwidth. The graph also provides an illustration of the manner in which the described novel iterative interpolation approach allows precise adjustment to utilize efficient testing of DUT demodulation performance. The Y-axis is magnitude (dB) from 7.5 dB to 4.0 dB in 0.5 dB increments, and the X-axis is subcarrier frequency from 1012.0 Hz to 975.0 Hz in 1.0 Hz increments.

[0175] 12C and 12D are flow charts of an exemplary interpolation process 1200B with iterative updating / re-determination of equalization values ​​within bins, according to an embodiment of the present disclosure. The interpolation process 1200B is included in some embodiments of the reduced header communication signal processing test method. In some embodiments, the interpolation process 1200B is similar to the interpolation process 1200A. Also, the iterative updating / re-determination of the equalization value interpolation process 1200B provides more accurate interpolation of the equalization values ​​than an interpolation process with fewer iterative updates, such as, for example, a conventional linear or conventional least squares interpolation. It will be appreciated that the interpolation process 1200B with iterative updating / re-determination of equalization values ​​within bins is applicable to both magnitude and phase correction.

[0176] Process 1200B performs functions related to the analysis of the pilot bins. In block 1207, one of the pilot bins is selected and assigned to the label of the current pilot bin. In block 1210, an ideal value is extracted for the current pilot bin, where the extracting of the ideal value for the current pilot bin is based on binary phase shift keying (BPSK) analysis. In block 1215, a pilot equalizer value based on the ideal value for the current pilot bin from block 1210 and the known captured value for the current pilot bin is extracted. In block 1217, the pilot equalizer is inserted into a list of equalizers associated with bins in the burst or frame package.

[0177] This process performs functions related to the analysis of the next data bin. In block 1220, one of the data bins adjacent to the current pilot bin is selected, and the label of the current data bin is assigned to this one of the data bins. In block 1221, the label of the current equalizer is assigned to the pilot equalizer value. In block 1225, the current equalizer value is applied to the current data bin. In block 1230, an ideal constellation value is extracted for the current data bin. In block 1235, a new equalizer value is extracted based on the ideal constellation value from block 1230 and the known captured value of the current data bin. In block 1237, the new equalizer is inserted into the list of equalizers associated with the bins in the burst or frame package.

[0178] The process includes checking for subsequent bins that are not data bins (e.g., pilot bins, null bins, etc.). At block 1240, a determination is made whether the next bin in the set of bins is another one of the pilot bins. At block 1241, the label of the current pilot bin is reassigned to another one of the pilot bins. At block 1242, a determination is made whether the next bin in the set of bins is another one of the data bins. At block 1243, the next bin is skipped (e.g., the results in the block indicate that the next bin is not a data bin, etc.). In some embodiments, if there is a null bin between the pilot bin and the data bin, the process "skips" the null bin and analyzes the next data bin or pilot.

[0179] This process also includes the possibility of handling special situations (e.g., handling data bins at the edge of the bandwidth, restarting the analysis at a subsequent pilot bin, etc.). In block 1245, if the next bin in the set of bins is another one of the data bins, it is checked whether the next bin is a bandwidth edge bin. When proceeding to block 1250 and block 1270, it is understood that the null bin is skipped. In block 1250, if the check is negative, a new equalizer is applied to the next bin in the data bins. In block 1270, if the check is positive, an enhanced equalizer process is performed. In block 1261, a determination is made whether the repetition of the current bin corresponds to the last bin (e.g., in a burst or frame package, etc.). If the current bin is the last bin, the process proceeds to block 1262, and if the current bin is not the last bin, the process proceeds to block 1290. In block 1290, a current pilot bin label reassignment process is performed. In block 1262, an averaging equalization process is performed.

[0180] In some embodiments, process 1200B proceeds until all bins in the bandwidth have been processed. The process may proceed in a frequency bin / subcarrier up direction, a frequency bin / subcarrier down direction, or both. In some embodiments, a pilot is selected as an initial pilot and the process proceeds in a frequency bin / subcarrier down direction. When the pilot reaches the lowest frequency bin / subcarrier in the bandwidth, it returns to the initial pilot and the process proceeds in a frequency bin / subcarrier up direction until the pilot reaches the highest frequency bin / subcarrier in the bandwidth. In some embodiments, a full demodulation process (e.g., similar to blocks 230, 830, etc.) is performed based on the results of the interpolation process 1200B.

[0181] 12E is a block diagram of an example subcarrier bin configuration 1291 according to an embodiment of the present disclosure. The dots or circles indicate various subcarriers (also known as transmission spectrum within a communication bandwidth). The filled dark circles indicate pilot subcarrier bins, also known as pilot bins, and the unfilled circles indicate data subcarrier bins (also known as data bins). It is understood that the subcarrier bin configuration may include other subcarriers (not shown). The Y-axis corresponds to the frequency values ​​of the various subcarriers, and the X-axis indicates the transmission of the subcarriers over time.

[0182] It will be appreciated that the subcarrier bin configuration 1291 illustrates a communication burst or frame of subcarriers and corresponding OFDM symbols according to some embodiments of the present disclosure. The columns of bins correspond to bins within the respective OFDM symbols. The bins are also tracked in rows of bins (e.g., bin row 0, bin row 4, bin row 9, bin row 14, etc.). It will be appreciated that the organization of OFDM symbols included in the subcarrier bin configuration 1291 may vary. In some embodiments, each column is associated with a different OFDM symbol. In some exemplary implementations, the OFDM symbols are in a loop (e.g., similar to the payload portion 505) that repeats within the subcarrier bin configuration (e.g., OFDM symbol 4501 repeats as 501A, 501B, 501C, 501D, etc.). Subcarrier bin configuration 1291 is associated with a subcarrier bin configuration, but there is also an equalization value associated with each bin (e.g., an equalizer associated with the bin in column 0, an equalizer associated with the bin in column 9, an equalizer associated with the bin in column 19, etc.). These bins include 1274D, 1274H, 1271J, and in the expanded view section 1271A, 1272A, 1273A, 1274A, 1271B, 1272B, 1273B, 1274B, 1271C, 1271E, 1272E, 1273E, 1274E, 1271F, 1272F, 1273F, 1274F, and 1271G.

[0183] In some embodiments, the equalizer values ​​associated with the bins are determined according to an interpolation process 1200B. Figures 12F, 12G, and 12H are flowcharts illustrating an example implementation of the interpolation process 1200B according to some embodiments of the present disclosure. It is understood that the blocks in Figures 12F, 12G, and 12H (e.g., 1210B in Figure 12F, block 1210E in Figure 12G, block 1210K in Figure 12H, etc.) are different iterations of the respective processing blocks in Figures 12C and 12D (e.g., block 1210 in Figure 12C, etc.).

[0184] FIG. 12F is a block diagram of an exemplary signal information processing operation according to an embodiment of the present disclosure. There are several bins including pilot bin 1271A, data bin 1272A, data bin 1273A, and pilot bin 1271B. The process starts with pilot bin 1271A in block 1210A, where an ideal constellation value associated with pilot bin value 1281A (also called pilot bin ideal value) is extracted for pilot bin 1271A. In block 1215A, pilot equalizer 1282A is extracted. In block 1220A, pilot equalizer 1282A is applied to data bin 1272A. In block 1230A, ideal constellation value 1283A of the data in data bin 1272A is extracted. In block 1235A, new equalizer 1284A is extracted. In block 1250A, a new equalizer 1284A is applied to data bin 1273A. In block 1230AA (e.g., the process returns to another iteration of block 1230, etc.), an ideal constellation value 1285A for the data in data bin 1273A is extracted. In block 1235AA, a new equalizer 1287A is extracted. The process proceeds to other blocks (not shown) and continues (e.g., a new equalizer is applied to the next data bin, etc.). In block 1240A, a determination is made whether the next bin is a pilot bin. If the process encounters another pilot (e.g., pilot bin 1271B, etc.), the process returns and performs another iteration of block 1210 (e.g., in FIG. 12G, etc.).

[0185] FIG. 12G is a block diagram of an exemplary signal information processing operation according to an embodiment of the present disclosure. There are several bins, including pilot bin 1271B, data bin 1272B, data bin 1273B, and pilot bin 1271C. The process starts with pilot bin 1271B in block 1210B, where an ideal constellation value associated with pilot bin value 1281B (also called pilot bin ideal value) is extracted for pilot bin 1271B. In block 1215B, pilot equalizer 1282B is extracted. In block 1220B, pilot equalizer 1282B is applied to data bin 1272B. In block 1230B, ideal constellation value 1283B of the data in data bin 1272B is extracted. In block 1235B, new equalizer 1284B is extracted. At block 1250B, a new equalizer 1284B is applied to data bin 1273B. At block 1230BB (e.g., the process returns to another iteration of block 1230, etc.), an ideal constellation value 1285B for the data in data bin 1273B is extracted. At block 1235BB, a new equalizer 1287B is extracted. The process proceeds to other blocks (not shown) and continues (e.g., a new equalizer is applied to the next data bin, etc.). At block 1240B, a determination is made whether the next bin is a pilot bin. If the process encounters another pilot (e.g., pilot bin 1271C, etc.), the process returns and performs another iteration of block 1210.

[0186] The process continues in a similar manner from Figures 12F and 12G for other bins in the OFDM symbol. With reference to Figure 12E, the process continues to find the equalizer associated with bin 1274D. Thus, the process determines the equalizer value for each bin in equalizer column 0 of Figure 12E. The process returns to the next column and begins again with bin 1271E.

[0187] 12H is a block diagram of an exemplary signal information processing operation according to an embodiment of the present disclosure. There are several bins, including pilot bin 1271E, data bin 1272E, data bin 1273E, and pilot bin 1271F. The process starts with pilot bin 1271E in block 1210E, where an ideal constellation value associated with pilot bin value 1281E (also known as pilot bin ideal value) is extracted for pilot bin 1271E. In block 1215E, pilot equalizer 1282E is extracted. In block 1220E, pilot equalizer 1282E is applied to data bin 1272E. In block 1230E, ideal constellation value 1283E of the data in data bin 1272E is extracted. In block 1235E, new equalizer 1284E is extracted. In block 1250E, a new equalizer 1284E is applied to data bin 1273E. In block 1230EE (e.g., the process returns to another iteration of block 1230, etc.), an ideal constellation value 1285E for the data in data bin 1273E is extracted. In block 1235EE, a new equalizer 1287E is extracted. The process proceeds to other blocks (not shown) and continues (e.g., a new equalizer is applied to the next data bin, etc.). In block 1240E, a determination is made whether the next bin is a pilot bin. If the process encounters another pilot (e.g., pilot bin 1271F, etc.), the process returns and performs another iteration of block 1210.

[0188] The process continues in a similar manner for the other bins of the OFDM symbol (e.g., in a burst, frame, etc.). With reference to FIG. 12E, we move up bin 1274H of the second column and back to bin 1271J of the next column. Once the equalization value for the burst has been extracted, the process proceeds to an averaging process. With reference again to FIG. 12D, in block 1290, an averaging process is performed. The averaging process is performed based on the equalization values ​​in the list of equalizers (e.g., developed in blocks 1217, 1237, etc.). FIG. 12I is a block diagram of an equalizer value list 1293 associated with the bins of OFDM values ​​in a burst or frame. These bins correspond to the bins in FIG. 12E, and the equalizer values ​​correspond to an exemplary implementation of the interpolation process 1200B (e.g., shown in FIG. 12F, FIG. 12G, FIG. 12H, etc.). 12F, in block 1215A, an equalizer 1282A is extracted from pilot bin 1271A. According to the interpolation process 1200B, in block 1217, the equalizer 1282A is inserted into a list (e.g., equalizer value list 1293, etc.). It is understood that the equalizer values ​​may be inserted into a list stored in memory.

[0189] 12J is a flowchart of an average equalizer process 1500 according to some embodiments of the present disclosure. The average equalizer process 1500 provides an opportunity for an overall improved handling of frequency errors and equalization corrections. In some embodiments, this averaging can help to avoid over-correction due to outliers or aberrations in certain bins. In some exemplary implementations, this averaging can help to smooth results over time (e.g., in the lateral direction, etc.) and across multiple subcarrier frequencies (e.g., in the vertical OFDM symbol direction, etc.). In some exemplary implementations, the average equalizer process 1500 is included in block 1262.

[0190] At block 1510, an equalizer value is accessed. In some embodiments, the equalizer value list 1293 is accessed. In some exemplary implementations, the accessed equalizer value is associated with an OFDM symbol within a communication burst or frame. The equalizer value may be accessed from a memory or other mechanism.

[0191] At block 1520, an average equalization value is determined. It is understood that the average equalization value may be associated with different averaging objectives. With reference to both FIG. 12J and FIG. 12I together, the average equalization value may correspond to an average of the equalization values ​​in a row (e.g., bin row 0, bin row 5, etc.) of the equalizer value list 1293. The average equalization value may correspond to an average of the equalization values ​​in a column (e.g., equalizer column 0, equalizer column 9, etc.) of the equalizer value list 1293. The average equalization value may correspond to an average of the equalization values ​​in a burst or frame (e.g., burst or frame 1291, etc.).

[0192] At block 1530, an average equalizer value is applied to subcarriers within a bin of an OFDM symbol. In some embodiments, applying an average equalizer to the subcarriers leads to a residual error mitigation capability. It is understood that the average equalizer value may be applied in various configurations. A first average equalizer value of a first row of subcarriers may be applied to corresponding subcarriers of the first row, and a second average equalizer value of a second row of subcarriers may be applied to corresponding subcarriers of the second row. A first average equalizer value of a first column of subcarriers may be applied to corresponding subcarriers of the first column, and a second average equalizer value of a second column of subcarriers may be applied to corresponding subcarriers of the second column. The average equalizer values ​​may be applied to subcarriers within a bin of an OFDM symbol in a burst, frame, etc.

[0193] It is understood that various forms of interpolation are compatible with the proposed novel approach. In some embodiments, the accuracy of the interpolation approach may vary. FIG. 13A is an example graph of a frequency response of a bandwidth including multiple bins / subcarriers according to an embodiment of the present disclosure. Different bin / subcarrier values ​​are indicated by filled dots (e.g., 5071A, 5072, 5073, 5074, 5075, 5076, 5077, 5078, 5079, etc.). In FIG. 13A, pilot bins are associated with dots 5071A, 5073, 5075, 5077, and 5079, and data bins are associated with the remaining dots (e.g., 5072, 5074, 5076, 5078, etc.), and a linear interpolation process is utilized to estimate the frequency response and the corresponding equalizer. The estimate is reasonable, but there is a deviation from the true value.

[0194] FIG. 13B is an exemplary graph of a frequency response of a bandwidth including multiple bins / subcarriers according to an embodiment of the present disclosure. The frequency response, bandwidth, multiple bins / subcarriers, and corresponding signals in FIG. 13B are similar to those in FIG. 13A. In FIG. 13B, pilot bins are associated with dots 5071A, 5073, 5075, 5077, and 5079, and data bins are associated with the remaining dots (e.g., 5072, 5074, 5076, 5078, etc.) and an iterative interpolation process (e.g., similar to that of 1200B, which is utilized to estimate the frequency response and corresponding equalizer). In some embodiments, the iterative interpolation process is similar to the interpolation process with iterative updating / re-determination of the equalization value in the bin (e.g., as shown in FIG. 12A, FIG. 12C, FIG. 12D, etc.). The iterative interpolation process results in values ​​that are very close to the true value. For example, the deviation between the interpolated value and the true value in FIG. 13B is much smaller than in FIG. 13A. In some exemplary implementations, there is no symbol error when extracting the constellation information, and the iterative interpolation process value is the same as the true value.

[0195] In some implementations, the frequency lines are flat or fairly close to straight for most of the bins / subcarriers in the large central portion of the bandwidth, but begin to have issues toward the edges (e.g., due to filter performance / limitations, etc.). In the central portion (solid dots between 5073 and 5077), the frequency is fairly flat or just a small ripple in the range 5091. Assuming the bin / subcarrier frequency responses are relatively flat or close to each other (e.g., 5073 is relatively close to 5074, etc.), the equalizer values ​​from one serve as relatively good initial equalization values ​​for the other. As the frequency reaches the lower and upper boundaries or edges of the bandwidth (e.g., 5071A, 5072, 5078, 5079, etc.), the frequency response range (e.g., 5092A, 5093, etc.) begins to drop off rapidly. In some embodiments, as the frequency drops, the magnitude of the change in response increases in the downward direction. In some embodiments, this difference is added to the estimated equalizer value as the process traverses bins / subcarriers closer to the edge. The estimated equalizer used for bin / subcarrier 5071B includes the equalizer from bin / subcarrier 5072 added to adjustment value 5092B (equal to the difference 5092A between the equalizers of bin / subcarrier 5073 and bin / subcarrier 5072) to provide an initial estimate of 5071B. For graphical purposes, estimate 5071B is shown associated with virtual bin / subcarrier 5071B which is relatively close to bin subcarrier 5071A (e.g., in the same way that bin / subcarrier 5073 is relatively close to bin / subcarrier 5074) and serves as a relatively good initial equalizer value for the other.

[0196] 14A is a flow chart of an exemplary enhanced equalizer process according to an embodiment of the present disclosure. The enhanced equalizer process can be implemented to handle special or unique data bin scenarios. In some exemplary implementations, the data bins are located at the edge of the bandwidth, and as a result, the difference between the equalization values ​​may vary more significantly between bins. Therefore, only relying on the equalizer values ​​from previous bins may not be reliable enough. In some embodiments, the adjustments made by the enhanced equalizer process provide more reliable interpolation and estimation of the appropriate equalizer values.

[0197] In block 1470, if the result of checking whether the next bin (e.g., from block 1245, etc.) is a bandwidth edge bin is positive, an enhanced equalizer process is performed. The enhanced equalizer process is similar to the enhanced equalizer process performed in block 1270. In block 1471, a delta equalizer value is set based on the current equalizer value and the new equalizer value. The delta equalizer value is the difference between the current equalizer value and the new equalizer value. In block 1472, the new equalizer value is added to the delta equalizer value, and the label of the enhanced equalizer value is assigned to this addition result. Adding the new equalizer value to the delta equalizer value provides a result that is much closer to the true equalizer value of the next bin. In block 1447, the enhanced equalizer is applied to the next data bin. Using the enhanced equalizer value provides a more reliable estimate of the appropriate equalizer value of the next data bin. Therefore, when the enhanced equalizer is applied to the demodulation of the next data bin,

[0198] 14B is a block diagram of an exemplary signal information processing operation according to an embodiment of the present disclosure. There are several bins, including data bin 7071, data bin 7072, and data bin 7073. The process begins with data bin 7071, and in block 1430R, an ideal constellation value 7081 is extracted for data bin 7071. In block 1435T, a new equalizer 7082 is extracted and applied to data bin 7071. In block 1445U, data equalizer 7082 is applied to data bin 7072. In block 1430V, an ideal constellation value 7083 of the data in data bin 7072 is extracted. In block 1435W, a new equalizer 7084 is extracted and the new equalizer 7084 is applied to data bin 7072. At block 1445X, a new / delta equalizer 7085 (e.g., new equalizer 7084 plus a delta equalizer value similar to 5092B in FIG. 13B, etc.) is applied to data bin 7073. At block 1430Y (e.g., the process returns to another iteration, such as block 1430R), an ideal constellation value 7087 for the data in data bin 7073 is extracted. At block 1435Z, a new equalizer 7089 is extracted and new equalizer 7089 is applied to data bin 7073.

[0199] 15 is a flow chart of an exemplary current data bin label reassignment process according to an embodiment of the present disclosure. The block diagram of the current data bin label reassignment process is similar to the block diagram of the current data bin label reassignment process of block 1290. In block 1590, the current data bin label reassignment process is performed. The current data bin label reassignment process 1590 includes the following operations: In block 1591, the next data bin is reassigned to the label of the current data bin, and the next data bin becomes known as the current bin. In block 1592, if the confirmation is negative, the new equalizer value is reassigned to the label of the current equalizer value, and the new equalizer value becomes known as the current equalizer value. In block 1595, if the confirmation is positive, the enhanced equalizer value is reassigned to the label of the current equalizer value, and the enhanced equalizer value becomes known as the current equalizer value.

[0200] In some embodiments, a full demodulation process (e.g., similar to blocks 230, 830, etc.) is performed based on the results of the interpolation process (e.g., 1200A, 1200B, etc.). In some embodiments, the full demodulation is performed in the same way as in a normal manner (e.g., similar to a non-test environment, similar to using full header information, etc.). The full demodulation is similar to demodulation in a real-world field environment. The full modulation is similar to modulation when associated header / preamble information is available in the signal transmission. In some exemplary implementations, performing the full modulation includes determining the full equalizer value, accurately setting the frequency error and sampling the clock error, etc. In some embodiments, all the result parameters required to test the RF WiFi component / device are determined.

[0201] It is understood that other interpolation processes may be implemented. In some embodiments, a linear or polynomial adaptive response or interpretation is implemented. In some example implementations, an iterative interpolation process (e.g., 1200A, 1200B, etc.) is selected and implemented instead of linear or polynomial interpolation if capture by the device potentially gives larger erroneous values ​​for some interpolated bins than expected (e.g., which may result in larger channel response interpolation errors, etc.). In some embodiments, the interpolated pilot positions are not heavily populated.

[0202] FIG. 16 is a flow chart of an example reduced-header reference signal training mode test process 1600 according to an embodiment of the present disclosure. In the reduced-header reference signal training mode test process: A known ideal payload signal is extracted from a full Wi-Fi signal. The ideal payload signal (e.g., PayloadOnlyIdealIQWaveform, etc.) has no header information or reduced header information. The ideal payload signal is played back to the DUT. In some embodiments, a demodulator may be trained with an ideal waveform to provide an ideal payload portion (e.g., mostly data, only data, etc.) of a packet with reduced or no header information. A clean capture with low EVM is used to train the modulator to generate the ideal payload portion. This approach also enables testing of DUTs that otherwise cannot easily handle / demodulate full frames or packets with full header information.

[0203] The process includes developing an ideal waveform based on information in a header portion of the signal. At block 1610, a reduced header reference signal mode test process indication is accessed. At block 1620, a reduced header demodulation information determination process is performed based on the reference signal training. At block 1630, a training process is performed. At block 1640, an ideal waveform including a training sequence is demodulated. At block 1641, a complete packet of the ideal waveform is accessed. At block 1642, the complete packet of the ideal waveform is demodulated. At block 1643, a payload portion of the ideal waveform is generated based on the demodulation of the complete packet ideal waveform. In some embodiments, the payload waveform is a payload-specific ideal waveform (e.g., an IQ waveform, etc.).

[0204] The process includes demodulation testing based on the use of an ideal waveform. In block 1650, a reduced header demodulation is performed using the payload portion of the ideal waveform. The reduced header demodulation can be a headerless demodulation performed using a headerless payload only portion of the ideal waveform. In block 1651, the ideal waveform of the payload portion is used as a reference and loaded into the tester stimulus and used as a source for the DUT. In block 1652, an ideal reference trace process is performed. In some embodiments, the ideal reference trace process includes defining the constellation points of an ideal demodulated signal. In block 1653, an ideal subcarrier type per symbol process is performed. In some embodiments, an input parameter IdealReferenceTrace defines the constellation points of an ideal demodulated signal, and a parameter IdealSubcarrierTypePerSymbol defines the subcarrier type of each element of the ideal reference trace. In some exemplary implementations, IdealReferenceTrace is a complex array whose length is twice the length of IdealSubcarrierTypePerSymbol.

[0205] At block 1680, full demodulation is performed. In some embodiments, full demodulation is similar to some aspects of conventional demodulation analysis. After the information from block 1650 is available, processing may proceed with full demodulation decision information similar to conventional information that would not otherwise be conventionally available from the reduced header signal.

[0206] 17 is a screenshot of an example 802.11ax 20MHz ideal waveform graphical user interface (GUI) according to an embodiment of the present disclosure. The waveform in the GUI is a complete packet including a header portion and a data portion. In some embodiments, the training includes a complete burst to generate a payload-only ideal signal. The Y-axis is amplitude (unitless) in increments of 0.2 and the X-axis is time (uS) in increments of 2000.

[0207] FIG. 18 is a screenshot of an exemplary payload-only ideal IQ waveform graphical user interface (GUI) when the input parameter HeaderlessDemod is set to training, according to some embodiments. The HeaderlessDemodTraining and Execute options are used to implement the development and creation of a payload-only ideal IQ waveform. The graph is provided by the PayloadOnlyIdealIQWaveform operation. Waveform 1810 is a waveform of a complete packet including the header and data payload portions of a communication, and waveform 1820 is a waveform of the data payload only portion of the communication. In waveform 1810, the Y-axis is amplitude (Volts) in increments of 0.5 and the X-axis is time (uS) in increments of 2000. In waveform 1820, the Y-axis is amplitude (Volts) in increments of 2.0 and the X-axis is time (uS) in increments of 2000.

[0208] Figure 19 is a screenshot of a graph of an example extracted payload-only ideal signal according to an embodiment of the disclosure. Figure 19 illustrates some of the characteristics of the operation of block 1653, such as the input parameter IdealReferenceTrace, which defines the constellation points of the ideal demodulated signal, and the parameter IdealSubcarrierTypePerSymbol, which defines the subcarrier type of each element of the ideal reference trace. In some example implementations, IdealReferenceTrace is a complex array whose length is twice the length of IdealSubcarrierTypePerSymbol. The Y-axis is amplitude (Volts) in increments of 0.5, and the X-axis is time (uS) in increments of 2000.

[0209] 20 is a screenshot of a graph of a demodulated payload-only signal in a GUI according to an embodiment of the present disclosure. To perform headerless demodulation with an ideal payload-only waveform, the input parameters to the headerless demodulation are based on training (e.g., DoHeaderlessDemod and BurstSearchEnable set to false, etc.). The Y-axis is amplitude (Volts) in increments of 0.5 and the X-axis is time (uS) in increments of 2000.

[0210] FIG. 21 is a flow chart of an exemplary header mode test process 2100 according to an embodiment of the present disclosure. At block 2110, a header mode test process instruction is accessed. In some embodiments, the header mode test instruction is accessed from a memory included in the ATE system. At block 2120, a parameter information determination process is performed. These parameters are related to frequency offset, timing information, equalization, etc. These parameters are utilized in the demodulation communication system. At block 2125, demodulation parameter information is extracted from the header. The composition of this information is defined by the communication protocol. This information is extracted from fields in the header (e.g., short training field, long training field, signal field, etc.). At block 2130, full demodulation is performed.

[0211] Much of the description is presented with reference to public communication protocols. It is understood that the novel presented systems and methods are readily applicable to protocols that are not publicly known (e.g., not privately established by a test entity, not established by a DUT manufacturer, not confidentially communicated to an ATE entity, etc.). Multiple types of modulation (e.g., BPSK, QPSK, etc.) may be assigned to subcarriers and ideal values ​​may be set and, as a result, become "known" by the ATE. Signals and corresponding information may be configured according to various types of protocols (e.g., public, private, etc.). Various values ​​(e.g., timing, frequency error, equalizer, EVM, performance values, modulation values, demodulation values, etc.) may be set based on captured information compared to ideal values. These values ​​may be applied to other signals (e.g., adjacent subcarriers, etc.). The configuration or organization of subcarriers within a bandwidth may be set (e.g., relative to each other, within frequency bins, etc.) and become known to the ATE. The presented novel iterative interpolation systems and methods may be utilized to determine information about various signals (e.g., pilot subcarriers, data subcarriers, etc.). It will thus be appreciated that the novel presented systems and methods are applicable to a wide variety of different test scenarios and conditions. In some exemplary implementations, the novel presented systems and methods are readily applicable to protocols having predefined characteristics and definitions (e.g., modulation definitions, configuration definitions, etc.).

[0212] 22 is a block diagram of an exemplary electronic system 2200 that may be used as a platform for implementing and controlling methods according to some embodiments. In some embodiments, the electronic system 2200 is a workstation that executes algorithms associated with the novel systems and methods presented herein. The electronic system 2200 may be included within an ATE system (e.g., ATE110A, ATE110C, etc.). The electronic system 2200 may be a "server" computer system. The electronic system 2200 includes a central processing unit 2210, a system memory 2215, a bulk memory 2225 (e.g., hard drive, external memory, etc.), an input / output (I / O) device 2230, a communication component / port 2240, and a bus 2250. It will be understood that one or more non-transitory computer-readable media (e.g., system memory 2215, bulk memory 2225, etc.) store instructions that, when executed by one or more processors (e.g., central processing units, etc.), cause the one or more processors to perform operations of the methods and processes described elsewhere herein (e.g., methods 300, 700, 1000, 1100, 1200A, 1200B, 1590, 1600, etc.).

[0213] The bus 2250 is configured to couple other components (e.g., central processing unit 2210, system memory 2215, bulk memory 2225, input / output (I / O) devices 2230, communication components / ports 2240, etc.) and to communicatively communicate information among these components. The central processing unit 2210 is configured to process information and instructions. The system memory 2221 (e.g., read only memory (ROM), random access memory (RAM), etc.) and the bulk memory 2225 are configured to store information and instructions for the central processing unit complex 2215. The I / O devices 2230 can communicate information to the system (e.g., central processing unit 2210, memory 2225, etc.). The I / O devices 2230 may be any suitable device for communicating information and / or commands to an electronic system (e.g., keyboard, buttons, joystick, microphone, touch sensor digitizer panel, display component, light emitting diodes (LEDs), display, etc.). The communication port 2240 is configured to exchange / communicate information with an external device / network (not shown). The communication port 940 may have various configurations (e.g., RS-232 port, Universal Asynchronous Receiver Transmitter (UART), USB port, infrared optical transceiver, Ethernet port, IEEE 13394, synchronous port, etc.) and may communicate with an external network.

[0214] In some embodiments, the methods and processes described elsewhere herein are implemented by algorithms executed on a workstation (e.g., electronic system 2200, etc.). Algorithms for accessing information (e.g., retrieving from memory, downloading from a network, etc.) are easily implemented for some of the operations of the methods and processes (e.g., 810, block 1610, etc.). Aspects of performing full demodulation blocks (e.g., 330, 830, 1680, etc.), which may be similar to conventional demodulation methods and processes, may be implemented using algorithms similar to conventional algorithms. It is understood that the algorithmic modules described herein are expressed in pseudocode, which may be easily converted for implementation in various programming languages.

[0215] FIG. 23 is a block diagram of an exemplary algorithm, a reduced header processing module 2300, according to an embodiment of the present disclosure. The reduced header processing module 2300 is associated with implementing block 820 of the method 800. The reduced header processing module 2300 includes an autocorrelation module 2310 (block 821), a coarse frequency error estimation module 2320 (block 823), a timing module 2330 (block 822), a set of bins configuration module 2350 (block 824), a pilot bin identification module 2360 (block 825), and an ideal pilot bin configuration module 2370 (block 826). The autocorrelation module 2310 is associated with implementing block 821. The coarse frequency error estimation module 2320 is associated with implementing block 823. The timing module 2330 is associated with implementing block 822. The set of bins configuration module 2350 is associated with implementing block 824. The pilot bin identification module 2360 is associated with implementing block 825. The ideal pilot bin setting module 2370 is associated with implementing block 826. The other demodulation parameters determination module 2380 is associated with implementing block 827.

[0216] Fig. 24 is a block diagram of an exemplary algorithm, an interpolation module 2400, according to an embodiment of the present disclosure. The interpolation module 2400 is related to the implementation of the iterative interpolation process 1200B. The interpolation module 2400 includes a pilot bin identification module 2410, an ideal pilot bin value extraction module 2420, an adjacent data bin selection module 2430, a current equalizer to data bin application module 2430, an ideal value extraction module 2440 for the current data bin, a new equalizer value determination and application module 2450, a subsequent bin is a data bin or not determination module 2460, a next bin is an edge data bin or not check module 2480, a normal new equalizer application module 2485, an enhanced equalizer module 2490, and a reallocation module 2495. Fig. 25 is an expanded version of the exemplary enhanced equalizer module 2490 and reallocation module 2495.

[0217] These modules in the interpolation module 2400 are associated with implementing the blocks in the interpolation process 1200B. The pilot bin identification module 2410 is associated with implementing the block 1207. The ideal pilot bin value extraction module 2420 is associated with implementing the blocks 1210 and 1215. The adjacent data bin selection module 2430 is associated with implementing the block 1220. The current equalizer to data bins application module 2430 is associated with implementing the block 1225. The current data bin ideal value extraction module 2440 is associated with implementing the block 1230. The new equalizer value determination and application module 2450 is associated with implementing the blocks 1235 and 1237. The subsequent bin is a data bin determination module 2460 is associated with implementing the blocks 1240-1243. The next bin is an edge data bin determination module 2480 is associated with implementing the block 1245. The apply normal new equalizer module 2485 is associated with the implementation of block 1250. The enhanced equalizer module 2490 is associated with the implementation of block 1270. The average equalization module 2941 is associated with the implementation of blocks 1262 and 1500. The reallocation module 2495 is associated with the implementation of blocks 1290 and 1590.

[0218] 26 is a block diagram of an exemplary algorithm, a training module processing module 2600, according to an embodiment of the present disclosure. The training module processing module 2600 includes a module 2610 for completing an ideal waveform demodulation training sequence and a reduced header ideal payload reference demodulation module 2620. The training module processing module 2600 is associated with implementing block 1620. The module 2610 for completing an ideal waveform demodulation training sequence is associated with implementing block 1630.

[0219] 27 is a block diagram of an exemplary algorithm, pilot bin ideal value module 2700, according to an embodiment of the present disclosure. The pilot bin ideal value module 2700 is associated with the implementation of block 1100. The pilot bin ideal value module 2700 includes a coarse frequency error estimation module 2710, a frequency error compensation module, an ideal pilot bin value extraction module 2730, a decision re-estimation module 2740, a re-estimation module 2745, and a return module 2750. The coarse frequency error estimation module 2710 is associated with the implementation of block 1110. The frequency error compensation module 2720 is associated with the implementation of block 1120. The ideal pilot bin value extraction module 2730 is associated with the implementation of block 1130. The decision re-estimation module 2740 is associated with the implementation of block 1140. The re-estimation module 2745 is associated with the implementation of block 1145. The return module 2750 is associated with the implementation of block 1150.

[0220] 28 is a block diagram of an exemplary algorithm, iterative interpolation module 2800, according to an embodiment of the present disclosure. The iterative interpolation module 2800 is associated with the implementation of process 1200A. The iterative interpolation module 2800 includes an ideal pilot bin setting module 2810, a module 2820 for determining whether a subsequent bin is a data bin, a module 2830 for applying a new equalizer to the data bin, a module 2840 for extracting an ideal value for the data bin, and a module 2850 for setting a new equalizer value. The ideal pilot bin setting module 2810 is associated with the implementation of block 1201. The module 2820 for determining whether a subsequent bin is a data bin is associated with the implementation of block 1202. The module 2830 for applying a new equalizer to the data bin is associated with the implementation of block 1203. The module 2840 for extracting an ideal value for the data bin is associated with the implementation of block 1204. The module 2850 for setting a new equalizer value is associated with the implementation of block 1205.

[0221] 29 is a block diagram of a test method 2900 according to an embodiment of the present disclosure. At block 2910, a reduced header payload test pattern is communicated to a DUT. At block 2910, the DUT is instructed to perform a modulation / demodulation operation on the reduced header payload test pattern and capture the results. Capture information is received and a multi-mode modulation / demodulation parameter determination process is performed. Capture information is received and a multi-mode modulation / demodulation parameter determination process is performed.

[0222] FIG. 30 is a block diagram of an example reduced header mode test process 3000 according to an embodiment of the present disclosure. The reduced header mode test process 3000 is included in a reduced header communication signal processing method. The reduced header mode test process is utilized when reference signal information is reduced / not available. In some example implementations, reference signal information (e.g., reference symbols, etc.) that would otherwise be included in the header or preamble portion (e.g., included in the short training field, long training field, etc.) is not available. The reduced header mode test process is utilized when a receiving component (e.g., DUT, etc.) reduces information about the received signal (e.g., reduced modulation related information, header information, preamble information, signal configuration information, etc.). The received information is less than would otherwise be available in a normal field / non-test situation.

[0223] In block 3010, a reduced header mode test processing instruction is accessed (e.g., headerless without a reference signal, etc.). In some example implementations, the reduced header mode test processing instruction is based on a selection of reduced header mode test processing (e.g., similar to the selection in block 710, etc.). The selection may be made based on various conditions (e.g., the DUT does not have enough resources to handle testing of communications with full header information, it is desirable to have a smaller test pattern for testing payloads that include reduced header information, it is desirable to have multiple test runs with different test characteristics, etc.).

[0224] In block 3020, a reduced header demodulation information determination process is performed. In some embodiments, the reduced header demodulation information determination process determines information utilized in testing modulation / demodulation operations (e.g., signal processing operations, etc.). In some exemplary implementations, the reduced header demodulation information determination process includes blocks 3021, 3022, 3023, 3024, 3025, and 3026.

[0225] In block 3021, a characteristic or feature of a signal associated with a payload portion of information is identified. The characteristic or feature provides an indication of (e.g., correlates with, has an association with, etc.) timing information (e.g., start time, end time, etc.). The characteristic or feature may be included in the payload portion within the signal (e.g., cyclic prefix, other structure, etc.). In some exemplary implementations, analysis of the characteristic or feature (e.g., autocorrelation analysis, comparative analysis, etc.) provides results from which timing information is derived (e.g., identifiable correlation peaks, identifiable magnitude structures in these results, identifiable phase structures in these results, etc.). In some embodiments, the timing information is associated with a symbol included in the payload portion. In some embodiments, the symbol is detectable in a physical layer channel communication after modulation and before demodulation (e.g., after data encoding and IFFT in a modulation operation, before FFT and data decoding in a demodulation operation, etc.). The symbol may be an OFDM symbol, an OFDMA symbol, etc. In some embodiments, the signal is a loop signal (e.g., similar to the signal in FIG. 5D, etc.). The signals are configured according to a communications protocol (eg, publicly known, privately predefined, etc.).

[0226] In block 3022, the start timing of symbols in the signal is identified based on the results from block 3021. The symbols are defined by the communication protocol. In other implementations, the start and end positions / timing of symbols relative to each other (e.g., where one symbol starts and ends relative to the start and end of another symbol, etc.) are identified.

[0227] At block 3023, an initial coarse frequency error correction is determined based on the results from block 3021. The difference between the phase and coarse frequency error may also be determined from an analysis of characteristics or features of the signal associated with the payload portion of the information. In some embodiments, the difference between the expected value and the analyzed result value may indicate the phase difference and the corresponding frequency error. The expected value may be defined by or derived from a definition in the communication protocol.

[0228] At block 3024, a set of bins for the signal is established, the set of bins including pilot bins and data bins. The set of bins corresponds to a set of subcarriers associated with the signal, the pilot bins correspond to pilot subcarriers within the set of subcarriers, and the data bins correspond to data subcarriers within the set of subcarriers. In some example implementations, a Fast Fourier Transform (FFT) operation is performed on a portion of the signal associated with the symbol, and the results are utilized to establish the set of bins.

[0229] In block 3025, identities of pilot bins are extracted according to the definition of pilot subcarriers defined by the communication protocol. In some embodiments, identifying the pilot bins includes identifying the positions of the pilot bins relative to each other and to other bins in the set of bins. It is understood that the identities and definitions of the subcarrier (e.g., pilot subcarriers, data subcarriers, null subcarriers, etc.) configurations and positions relative to each other may vary (e.g., as presented in the description of Figures 5A-5E, elsewhere herein, etc.). In some embodiments, pilot signals are special BPSK subcarrier signals that are more susceptible to symbol errors than transmitted data symbols, and this relative immunity allows for reliable determination of impairments (e.g., symbol errors, frequency errors, etc.) in the pilot symbols, and reliable determination of equalizer values.

[0230] In block 3026, ideal constellation values ​​and ideal symbol values ​​are set for the pilot bins and the data bins. In some embodiments, interpolation is used to set the ideal constellation values ​​and ideal symbols for the data bins. It will be appreciated that various types of interpolation (e.g., linear, least squares regression, iterative update / re-determination, etc.) are compatible with and readily implemented in the reduced header mode test process 3000.

[0231] In block 3010, other demodulation parameter values ​​are determined based on the results of the ideal constellation values ​​and ideal symbol values ​​for the pilot bins and data bins (e.g., based on the results of block 826, etc.). In some embodiments, the equalizer value from the first bin is first applied to the second bin and then updated based on the results of block 826. In some example implementations, the first bin and the second bin are adjacent or next to each other. The configuration of the first and second bins with respect to their proximity to each other may be defined by a communication protocol (e.g., an industry standard, an IEEE 802.11-based communication protocol, etc.).

[0232] In some embodiments, after the reduced header demodulation information determination process from block 3020 is performed, operation proceeds to block 3030 where an exemplary full demodulation is performed. This full demodulation is similar to block 330. The full demodulation is similar in some aspects to conventional demodulation analysis. After the information from block 3020 is available, processing may proceed with full demodulation determination information similar to conventional information that would not otherwise be conventionally available from the reduced header signal.

[0233] The header mode test process (e.g., blocks 750, 2100, etc.) performs modulation and demodulation tests using information in the header portion of a communication burst or frame. The header mode test process uses information in the header portion to set timing and reference values ​​for comparison with pilot values. In some embodiments, the header test process performs conventional tests of the communication information and implements the header test process using conventional algorithms.

[0234] While the present disclosure has been described in conjunction with preferred embodiments, it will be understood that this is not intended to limit the disclosure to those embodiments. On the contrary, the present disclosure is intended to cover alternatives, modifications, and equivalents. This specification is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed, and obviously, many modifications and variations are possible.

[0235] The novel testing approach presented herein provides flexible and adaptable selection between test modes (e.g., header-included mode, reduced-header training mode, reduced-header mode; etc.). Additionally, the novel modes disclosed herein support efficient and effective testing of the demodulation performance of a communications DUT without relying on header information to perform the demodulation. In some embodiments, the reduced-header mode enables demodulation of communications signals that are configured (e.g., in bursts, packets, etc.) with less header information than would otherwise typically be included according to a communications protocol.

[0236] The presented novel approach facilitates flexible determination of timing, frequency offset, channel response and clock error, fine tuning frequency error, sampling clock error, IQ gain and phase imbalance and error vector magnitude (EVM), etc., based on varying amounts of physical layer communication protocol header information (e.g., from full header information to no header information attached only to the data / payload portion, etc.). The presented novel approach enables efficient and effective testing of demodulation components and functions, including improved overall test performance (e.g., reduced time, cost, etc.). The presented novel approach facilitates significant savings in test time and financial resources. 1. In some embodiments, a reduced header communication signal processing test method includes: performing an autocorrelation of a cyclic prefix in a signal, said signal being configured according to a communication protocol; identifying start timings of symbols within the signal based on results of the autocorrelation, where the symbols are defined by the communication protocol and include Orthogonal Frequency Division Modulation (OFDM) symbols. determining an initial coarse frequency error correction based on the results of the autocorrelation. setting a set of bins for the signal, where the set of bins includes pilot bins and data bins, where the set of bins corresponds to a set of subcarriers associated with the signal, the pilot bins correspond to pilot subcarriers within the set of subcarriers, and the data bins correspond to data subcarriers within the set of subcarriers. extracting identification information of the pilot bins according to a definition of the pilot subcarriers defined by the communication protocol; setting ideal constellation values ​​and ideal symbol values ​​for the pilot bins and the data bins; and determining other demodulation parameter values ​​based on the results of the ideal constellation values ​​and the ideal symbol values ​​of the pilot bins and the data bins. Equipped with. 2. 2. The method of claim 1, wherein the signal is a loop signal including payload data without preamble training reference symbols. 3. The step of identifying comprises: performing a peak search function on the results of the autocorrelation; and associating a result of the peak search function with an indication of the starting timing of the symbol. having The method according to item 1 or 2. 4. 4. The method according to any one of items 1 to 3, wherein the communication protocol corresponds to one of the IEEE 802.11 series wireless network communication protocols / standards. 5. 5. The method according to any one of items 1 to 4, wherein the signal includes a physical layer payload portion of a protocol data unit that is devoid of physical layer header information, and wherein a configuration of the physical layer payload portion of the protocol data unit otherwise complies with a configuration specification of a communications protocol standard corresponding to one of the IEEE 802.11 family of wireless network protocols / standards. 6. The step of setting ideal constellation values ​​and ideal symbol values ​​for the pilot bins comprises: Completing the determination of the coarse frequency error Compensating for the coarse frequency error obtaining ideal pilot tone values ​​in the signal, where the ideal pilot tone values ​​include the ideal constellation values ​​and the ideal symbol values ​​of the pilot bins and corresponding pilot subcarriers; determining whether a user selected "LowSNR" for the FrequencyEstimationMethod; if so, re-estimating the frequency error is appropriate; performing said re-estimation of said fine-tuning frequency error using pilot tones and / or data bin values ​​in said signal if said determination is positive. applying the fine tune frequency error to the signal; and returning the ideal pilot tone values, where the ideal pilot tone values ​​include the ideal constellation values ​​and the ideal symbol values ​​of the pilot bins and corresponding pilot subcarriers. having 6. The method according to any one of items 1 to 5. 7. The step of setting ideal constellation values ​​and ideal symbol values ​​for the pilot bins and the data bins comprises: determining equalizer values ​​for the pilot subcarriers within the pilot bins based on ideal pilot tone constellation values; and determining equalizer values ​​for the data subcarriers at the data bin locations based on ideal data tone constellation values; having The method according to items 1 to 7. 8. 8. The method of claim 7, wherein the equalizer values ​​for the pilot bins and the equalizer values ​​for the data bins are reciprocals of respective channel response values. 9. 9. The method of claim 7 or 8, wherein the determining of equalizer values ​​for the data bins comprises interpolation between the equalizer values ​​for the pilot bins. 10. The step of setting ideal constellation values ​​and ideal symbol values ​​for the pilot bins and the data bins comprises: selecting one of the pilot bins and assigning a label of a current pilot bin to the one of the pilot bins. extracting an ideal value for the current pilot bin, where the extracting the ideal value for the current pilot bin is based on a binary phase shift keying (BPSK) analysis. deriving a pilot equalizer value based on the ideal value of the current pilot bin and a known captured value of the current pilot bin; Inserting the pilot equalizer into an equalizer list. selecting one of the data bins adjacent to the current pilot bin and assigning the one of the data bins to a label of a current data bin; assigning a label of a current equalizer value to said pilot equalizer value; applying the current equalizer value to the current data bin. Extracting an ideal constellation value for the current data bin. deriving new equalizer values ​​based on the ideal constellation values ​​and known captured values ​​of the current data bin; Inserting the new equalizer into the equalizer list. determining whether a next bin in the set of bins is another one of the pilot bins. if said determination is affirmative, reassigning said label of the current pilot bin to said another one of said pilot bins. determining whether a next bin in the set of bins is another one of the data bins. if the next bin in the set of bins is another one of the data bins, determining whether the next bin is a bandwidth edge bin. if the determination is negative, applying the new equalizer value to the next bin. if said determination is positive, performing an enhanced equalizer process. determining whether the current bin iteration corresponds to the last bin; performing an averaging equalization process; and Executing a current databin label reassignment process having 10. The method according to any one of items 1 to 9. 11. The enhanced equalizer process includes: setting a delta equalizer value based on the current equalizer value and the new equalizer value; adding the new equalizer value to the delta equalizer value and assigning a label of enhanced equalizer value to the result of the addition; and applying the enhanced equalizer value to the next bin. Including, 11. The method according to any one of items 1 to 10. 12. The current data bin label reassignment process includes: reassigning the next data bin to the label of the current data bin, where the next data bin becomes known as the current bin. if the verification is negative, reassigning the new equalizer value to the label of the current equalizer value, where the new equalizer value becomes known as the current equalizer value; and if the determination is positive, reassigning the enhanced equalizer value to the label of the current equalizer value, where the enhanced equalizer value becomes known as the current equalizer value. Including, 11. The method according to any one of items 1 to 10. 13. In some embodiments, the signal processing test system includes a load board configured to couple to a plurality of devices under test (DUTs). a controller configured to direct testing of the plurality of DUTs, the controller having a test mode selection module operable to select between a plurality of test modes, where one of the plurality of test modes is associated with a reduced header communications signal test process applied to a signal; and test electronics configured to test the plurality of DUTs under control of the controller, the test electronics coupled to the load board, the test electronics comprising: a demodulation information determination module operable to collect information associated with a demodulation operation, where the demodulation operation includes determining signal processing information based on information in a payload portion of the signal; and a demodulation module operable to perform a demodulation operation based on information received from the demodulation information determination module; having Equipped with. 14. 14. The signal processing test system of claim 13, wherein the test mode selection module is operable to select the mode associated with reduced header communication signal test processing, and further wherein the demodulation information determination module determines signal processing information associated with a demodulation operation of the signal, the signal processing information not otherwise included within a header portion of the signal. 15. 15. The signal processing test system of claim 13 or 14, wherein the demodulation information determination module is operable to determine signal processing information associated with a plurality of pilot tone subcarriers and a plurality of non-pilot tone subcarriers in the signal, and a configuration of the plurality of pilot tone subcarriers and the plurality of non-pilot tone subcarriers otherwise complies with a communications protocol standard corresponding to one of the IEEE 802.11 family of wireless network protocols / standards. 16. 16. A signal processing test system as described in any of items 13 to 15, wherein the demodulation information determination module is operable to perform a reduced header communication signal processing test method, the reduced header communication signal including a payload portion that is repeatedly transmitted in a loop, and the reduced header communication signal does not have a complete set of header training reference symbols specified in a communication protocol. 17. In some embodiments, the signal processing test method includes the steps of selecting a signal processing mode among a header including mode, a reduced header training mode and a reduced header mode, performing a signal processing information decision process according to a result of the signal processing mode selection step, and performing a modulation / demodulation related process according to a result of the signal processing information decision process. 18. The reduced header training mode includes: demodulating an ideal waveform including a training sequence; and performing ideal headerless demodulation using a payload-only portion of the ideal waveform; and performing a training process including: Utilizing the results of the ideal headerless demodulation to perform a full demodulation of another payload waveform. Including, Item 18. The signal processing test method according to item 17. 19. The reduced header mode includes: performing an autocorrelation of a cyclic prefix in a signal, the signal being configured according to a communication protocol; identifying start timings of symbols within the signal based on results of the autocorrelation, where the symbols are defined by the communication protocol and include orthogonal frequency division modulation (OFDM) symbols. determining an initial coarse frequency error correction based on results of said autocorrelation; setting a set of bins for the signal, where the set of bins includes pilot bins and data bins, where the set of bins corresponds to a set of subcarriers associated with the signal, the pilot bins correspond to pilot subcarriers within the set of subcarriers, and the data bins correspond to data subcarriers within the set of subcarriers. extracting identification information of the pilot bins according to a definition of the pilot subcarriers defined by the communication protocol; setting ideal constellation values ​​and ideal symbol values ​​for the pilot bins and the data bins; and determining other demodulation parameter values ​​based on the results of the ideal constellation values ​​and the ideal symbol values ​​for the pilot bins and the data bins; Including, 19. The signal processing test method according to item 17 or 18. 20. 20. The signal processing test method according to any one of items 17 to 19, wherein the header-including mode includes obtaining demodulation information from a header included in the signal.

[0237] In some embodiments, one or more non-transitory computer-readable media store instructions that, when executed by one or more processors of an ATE, cause the one or more processors to perform any of the operations of the methods in items 1 to 12 and 17 to 20.

[0238] In summary, the disclosed techniques overcome limitations of prior systems and methods by enabling accurate demodulation of the payload portion of a communication in accordance with a communication protocol without relying on header information otherwise specified for use by the communication protocol. In some embodiments, the reduced header implementation includes a training aspect in which an ideal demodulated payload waveform is extracted from the complete ideal waveform (e.g., including header information, etc.) and the ideal demodulated payload waveform is used for demodulation of a received or captured signal. In some embodiments, pilot bins / subcarriers are identified in the payload portion of the looped communication signal and ideal pilot bin values ​​are set. An autocorrelation of the cyclic prefix and performance of a peak search function is utilized to identify the start of a symbol (e.g., a transmission symbol, an OFDM symbol, etc.). Pilot bins / subcarriers within the symbol and the corresponding ideal pilot bin / subcarrier values ​​are identified (e.g., by performing BPSK analysis, etc.) and, as a result, utilized to set the equalizer value. The equalizer value is applied to adjacent data bins and a new interpolated equalizer value for this data bin is developed. This process iteratively applies the equalizer values ​​from the previous data bin equalizer to the subsequent data bin until another pilot bin is encountered, and develops a new equalizer for the subsequent data bin.

[0239] At least one technical advantage of the disclosed technology is the ability to perform demodulation testing on a DUT that would otherwise be impractical or impossible due to limited resources. The ability of memory-limited DUTs to handle newer communication protocols may be tested. The novel reduced header demodulation process presented provides efficient and effective demodulation of data payload portions of a communication signal (e.g., not previously available without full header information). The novel reduced header system and method presented enables demodulation testing of a DUT by appropriately implementing and analyzing demodulation of the payload portion of a communication signal, despite the DUT having limited test-related resources that would prevent demodulation testing operations. A number of demodulation-related parameters (e.g., timing, frequency offset, channel response, clock error, etc.) may be determined utilizing the payload portion of the signal without relying on the header information. Additionally, the smaller capture size associated with reduced-header payload signals and corresponding test patterns reduce ATE upload and demodulation processing times. Test efficiency is improved through the reduction of the need for large test patterns associated with long header information (eg, that would otherwise be time consuming, inefficient, error prone, etc.).

[0240] Any combination of claim elements recited in any manner in any claim and / or any elements described in this application are within the intended scope of the disclosure and protection.

[0241] The description of various embodiments has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

[0242] Aspects of the present embodiment may be embodied as a system, a method, or a computer program product. Thus, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects (all of which may be generally referred to herein as a "module," "system," or "computer"). In addition, any hardware and / or software technique, process, function, component, engine, module, or system described in this disclosure may be implemented as a circuit, or a set of multiple circuits. Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable medium(s) having computer-readable program code embodied therein.

[0243] Any combination of one or more computer readable media may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, apparatus or device, or any suitable combination of the foregoing. More specific examples (non-exhaustive list) of computer readable storage media would include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read only memory (ROM), an erasable programmable read only memory (EPROM or flash memory), an optical fiber, a portable compact disk read only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this specification, a computer readable storage medium may be any tangible medium that may contain or store a program for use by or in connection with an instruction execution system, apparatus or device.

[0244] Aspects of the present disclosure are described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It should be understood that each block of the illustrated block diagrams and / or flowcharts, and combinations of blocks illustrated in the block diagrams and / or flowcharts, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, a special purpose computer or other programmable data processing apparatus to generate a machine. These instructions, when executed via a processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams. Such a processor may be, but is not limited to, a general purpose processor, a special purpose processor, an application specific processor or a field programmable gate array.

[0245] The flowchart diagrams and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block of the flowchart or block diagram may represent a module, segment, or part of code, which includes one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or a combination of dedicated hardware and computer instructions. The foregoing description relates to embodiments of the present disclosure, but other and further embodiments of the present disclosure may be conceived without departing from the basic scope thereof, the scope of which is determined by the following claims.

[0246]

[0043] Although embodiments of the present disclosure have been thus described, it should be understood that while the present disclosure has been described in particular embodiments, the present disclosure should not be construed as limited by such embodiments, but rather should be construed according to the following claims.

Claims

1. A reduced header communication signal processing test method, comprising: performing an autocorrelation of a cyclic prefix in a signal, said signal being configured according to a communications protocol; identifying timing of beginnings of symbols within the signal based on results of the autocorrelation, where the symbols are defined by the communications protocol and include Orthogonal Frequency Division Modulation (OFDM) symbols; determining an initial coarse frequency error correction based on results of the autocorrelation; setting a set of bins for the signal, where the set of bins includes pilot bins and data bins, where the set of bins corresponds to a set of subcarriers associated with the signal, the pilot bins correspond to pilot subcarriers within the set of subcarriers, and the data bins correspond to data subcarriers within the set of subcarriers; extracting identification information of the pilot bins according to a definition of the pilot subcarriers defined by the communication protocol; setting ideal constellation values ​​and ideal symbol values ​​for the pilot bins and the data bins; and determining other demodulation parameter values ​​based on the results of the ideal constellation values ​​and the ideal symbol values ​​of the pilot bins and the data bins. A method comprising:

2. The method of claim 1 , wherein the signal is a loop signal including payload data without preamble training reference symbols.

3. The step of identifying comprises: performing a peak search function on the results of the autocorrelation; and associating a result of the peak search function with an indication of the starting timing of the symbol. having The method of claim 2.

4. The method of claim 1 , wherein the communication protocol corresponds to one of the IEEE 802.11 family of wireless network communication protocols / standards.

5. 2. The method of claim 1, wherein the signal includes a physical layer payload portion of a protocol data unit that is devoid of physical layer header information, and wherein a configuration of the physical layer payload portion of a protocol data unit otherwise conforms to a configuration specification of a communications protocol standard corresponding to one of the IEEE 802.11 family of wireless network protocols / standards.

6. The step of setting ideal constellation values ​​and ideal symbol values ​​for the pilot bins comprises: completing a coarse frequency error determination; compensating for the coarse frequency error; obtaining ideal pilot tone values ​​within the signal, where the ideal pilot tone values ​​include the ideal constellation values ​​and the ideal symbol values ​​of the pilot bins and corresponding pilot subcarriers; determining whether a user has selected “LowSNR” for aFrequencyEstimationMode, and if so, re-estimation of the frequency error is appropriate; if the result of said determining is positive, performing said re-estimation of the fine-tuning frequency error using pilot tones and / or data bin values ​​in said signal; applying the fine tune frequency error to the signal; and returning the ideal pilot tone values, where the ideal pilot tone values ​​include the ideal constellation values ​​and the ideal symbol values ​​of the pilot bins and corresponding pilot subcarriers. having The method of claim 1.

7. The step of setting ideal constellation values ​​and ideal symbol values ​​for the pilot bins and the data bins comprises: determining equalizer values ​​for the pilot subcarriers within the pilot bins based on ideal pilot tone constellation values; and determining equalizer values ​​for the data subcarriers at data bin locations based on ideal data tone constellation values; having The method of claim 1.

8. The method of claim 7 , wherein the equalizer values ​​for the pilot bins and the equalizer values ​​for the data bins are reciprocals of respective channel response values.

9. The method of claim 7 , wherein the determining of equalizer values ​​for the data bins comprises interpolating between the equalizer values ​​for the pilot bins.

10. The step of setting ideal constellation values ​​and ideal symbol values ​​for the pilot bins and the data bins comprises: selecting one of the pilot bins and assigning a label of a current pilot bin to the one of the pilot bins; extracting an ideal value for the current pilot bin, where the extracting the ideal value for the current pilot bin is based on a binary phase shift keying (BPSK) analysis; deriving a pilot equalizer value based on the ideal value of the current pilot bin and a known captured value of the current pilot bin; inserting the pilot equalizer value into an equalizer list; selecting one of the data bins adjacent to the current pilot bin and assigning the one of the data bins to a label of the current data bin; assigning a current equalizer value label to said pilot equalizer value; applying the current equalizer value to the current data bin; extracting an ideal constellation value for the current data bin; deriving new equalizer values ​​based on the ideal constellation values ​​and known captured values ​​for the current data bin; inserting the new equalizer value into the equalizer list; determining whether a next bin in said set of bins is another one of said pilot bins; if the determination is affirmative, reassigning the label of the current pilot bin to the other one of the pilot bins; determining whether a next bin in said set of bins is another one of said data bins; if the next bin in the set of bins is another one of the data bins, determining whether the next bin is a bandwidth edge bin; if the determination is negative, applying the new equalizer value to the next bin; if said determination is positive, performing an enhanced equalizer process; determining whether the current bin iteration corresponds to the last bin; performing an averaging equalization process; and Executing a current databin label reassignment process having The method of claim 1.

11. The enhanced equalizer process includes: setting a delta equalizer value based on the current equalizer value and the new equalizer value; adding the new equalizer value to the delta equalizer value and assigning a label of enhanced equalizer value to the result of the addition; and applying the enhanced equalizer value to the next bin. Including, The method of claim 10.

12. The current data bin label reassignment process includes: reassigning the next data bin to the label of the current data bin, where the next data bin becomes known as the current bin; if the verification is negative, reassigning the new equalizer value to the label of the current equalizer value, where the new equalizer value becomes known as the current equalizer value; and if the determination is positive, reassigning an enhanced equalizer value to the label of a current equalizer value, where the enhanced equalizer value becomes known as the current equalizer value. Including, The method of claim 10.

13. a load board configured to couple to a plurality of devices under test (DUTs); a controller configured to direct testing of the plurality of DUTs, the controller having a test mode selection module operable to select between a plurality of test modes, where one of the plurality of test modes is associated with a reduced header communications signal test process applied to a signal; and test electronics configured to test the plurality of DUTs under control of the controller, the test electronics coupled to the load board, the test electronics comprising: a demodulation information determination module operable to collect information associated with a demodulation operation, where the demodulation operation includes determining signal processing information based on information in a payload portion of the signal; and a demodulation module operable to perform a demodulation operation based on information received from the demodulation information determination module; having A signal processing test system comprising:

14. 14. The signal processing test system of claim 13, wherein the test mode selection module is operable to select the test mode associated with reduced header communication signal test processing, and further wherein the demodulation information determination module determines signal processing information associated with a demodulation operation of the signal, the signal processing information not otherwise included within a header portion of the signal.

15. 14. The signal processing test system of claim 13, wherein the demodulation information determination module is operable to determine signal processing information associated with a plurality of pilot tone subcarriers and a plurality of non-pilot tone subcarriers in the signal, the configuration of the plurality of pilot tone subcarriers and the plurality of non-pilot tone subcarriers otherwise conforming to a communications protocol standard corresponding to one of the IEEE 802.11 family of wireless network protocols / standards.

16. 14. The signal processing test system of claim 13, wherein the demodulation information determination module is operable to perform a reduced header communications signal processing test method, the reduced header communications signal including a payload portion that is repeatedly transmitted in a loop, and the reduced header communications signal does not have a complete set of header training reference symbols specified in a communications protocol.

17. selecting a signal processing mode among a header inclusion mode, a reduced header training mode and a reduced header mode; performing a signal processing information decision process according to the result of the step of selecting a signal processing mode; and performing modulation / demodulation related processing according to a result of the signal processing information determination processing. A signal processing test method comprising:

18. The reduced header training mode includes: demodulating an ideal waveform including a training sequence; and performing ideal headerless demodulation using a payload-only portion of the ideal waveform; performing a training process including: Utilizing the results of the ideal headerless demodulation to perform a full demodulation of another payload waveform. Including, 20. The signal processing test method of claim 17.

19. The reduced header mode includes: performing an autocorrelation of a cyclic prefix in a signal, the signal being configured according to a communications protocol; identifying timing of beginnings of symbols within the signal based on results of the autocorrelation, where the symbols are defined by the communication protocol and include orthogonal frequency division modulation (OFDM) symbols; determining an initial coarse frequency error correction based on results of the autocorrelation; setting a set of bins for the signal, where the set of bins includes pilot bins and data bins, where the set of bins corresponds to a set of subcarriers associated with the signal, the pilot bins correspond to pilot subcarriers within the set of subcarriers, and the data bins correspond to data subcarriers within the set of subcarriers; extracting identification information of the pilot bins according to a definition of the pilot subcarriers defined by the communication protocol; setting ideal constellation values ​​and ideal symbol values ​​for the pilot bins and the data bins; and determining other demodulation parameter values ​​based on the results of the ideal constellation values ​​and the ideal symbol values ​​for the pilot bins and the data bins; Including, 20. The signal processing test method of claim 17.

20. 20. The signal processing test method of claim 17, wherein the header-included mode includes obtaining demodulation information from a header included within the signal.

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